X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fevent%2Focteontx2%2Fotx2_evdev_adptr.c;h=d69f269df6c23f78d8085b3bcb15884eed7c2171;hb=8e6663b8c145a3dcbd7b298b93682814973c7fcd;hp=0a5d7924ada5de5e4925883d58897ffd619cc233;hpb=52f2fcb3e29adbe7f9deb3090df7436b1652c20d;p=dpdk.git

diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c
index 0a5d7924ad..d69f269df6 100644
--- a/drivers/event/octeontx2/otx2_evdev_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_adptr.c
@@ -453,9 +453,10 @@ sso_add_tx_queue_data(const struct rte_eventdev *event_dev,
 			struct otx2_ssogws_dual *dws;
 
 			old_dws = event_dev->data->ports[i];
-			dws = rte_realloc_socket(old_dws,
+			dws = rte_realloc_socket(ssogws_get_cookie(old_dws),
 						 sizeof(struct otx2_ssogws_dual)
-						 + (sizeof(uint64_t) *
+						 + RTE_CACHE_LINE_SIZE +
+						 (sizeof(uint64_t) *
 						    (dev->max_port_id + 1) *
 						    RTE_MAX_QUEUES_PER_PORT),
 						 RTE_CACHE_LINE_SIZE,
@@ -463,6 +464,10 @@ sso_add_tx_queue_data(const struct rte_eventdev *event_dev,
 			if (dws == NULL)
 				return -ENOMEM;
 
+			/* First cache line is reserved for cookie */
+			dws = (struct otx2_ssogws_dual *)
+				((uint8_t *)dws + RTE_CACHE_LINE_SIZE);
+
 			((uint64_t (*)[RTE_MAX_QUEUES_PER_PORT]
 			 )&dws->tx_adptr_data)[eth_port_id][tx_queue_id] =
 				(uint64_t)txq;
@@ -472,16 +477,21 @@ sso_add_tx_queue_data(const struct rte_eventdev *event_dev,
 			struct otx2_ssogws *ws;
 
 			old_ws = event_dev->data->ports[i];
-			ws = rte_realloc_socket(old_ws,
-						sizeof(struct otx2_ssogws_dual)
-						+ (sizeof(uint64_t) *
-						   (dev->max_port_id + 1) *
-						   RTE_MAX_QUEUES_PER_PORT),
+			ws = rte_realloc_socket(ssogws_get_cookie(old_ws),
+						sizeof(struct otx2_ssogws) +
+						RTE_CACHE_LINE_SIZE +
+						(sizeof(uint64_t) *
+						 (dev->max_port_id + 1) *
+						 RTE_MAX_QUEUES_PER_PORT),
 						RTE_CACHE_LINE_SIZE,
 						event_dev->data->socket_id);
 			if (ws == NULL)
 				return -ENOMEM;
 
+			/* First cache line is reserved for cookie */
+			ws = (struct otx2_ssogws *)
+				((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
+
 			((uint64_t (*)[RTE_MAX_QUEUES_PER_PORT]
 			 )&ws->tx_adptr_data)[eth_port_id][tx_queue_id] =
 				(uint64_t)txq;