X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faxgbe%2Faxgbe_ethdev.h;h=810ac4a749d7713d370402fc90461fe728842200;hb=6d13ea8e8e49ab957deae2bba5ecf4a4bfe747d1;hp=17e9e4146593b0755beb75479bc5ddd42382c8e0;hpb=4ac7516b8b390038a29481aacfb461565f177b29;p=dpdk.git

diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index 17e9e41465..810ac4a749 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -10,6 +10,16 @@
 #include <rte_lcore.h>
 #include "axgbe_common.h"
 
+#define IRQ				0xff
+#define VLAN_HLEN			4
+
+#define AXGBE_TX_MAX_BUF_SIZE		(0x3fff & ~(64 - 1))
+#define AXGBE_RX_MAX_BUF_SIZE		(0x3fff & ~(64 - 1))
+#define AXGBE_RX_MIN_BUF_SIZE		(ETHER_MAX_LEN + VLAN_HLEN)
+#define AXGBE_MAX_MAC_ADDRS		1
+
+#define AXGBE_RX_BUF_ALIGN		64
+
 #define AXGBE_MAX_DMA_CHANNELS		16
 #define AXGBE_MAX_QUEUES		16
 #define AXGBE_PRIORITY_QUEUES		8
@@ -25,6 +35,23 @@
 #define AXGBE_DMA_SYS_ARCACHE		0x0
 #define AXGBE_DMA_SYS_AWCACHE		0x0
 
+/* DMA channel interrupt modes */
+#define AXGBE_IRQ_MODE_EDGE		0
+#define AXGBE_IRQ_MODE_LEVEL		1
+
+#define AXGBE_DMA_INTERRUPT_MASK	0x31c7
+
+#define AXGMAC_MIN_PACKET		60
+#define AXGMAC_STD_PACKET_MTU		1500
+#define AXGMAC_MAX_STD_PACKET		1518
+#define AXGMAC_JUMBO_PACKET_MTU		9000
+#define AXGMAC_MAX_JUMBO_PACKET		9018
+/* Inter-frame gap + preamble */
+#define AXGMAC_ETH_PREAMBLE		(12 + 8)
+
+#define AXGMAC_PFC_DATA_LEN		46
+#define AXGMAC_PFC_DELAYS		14000
+
 /* PCI BAR mapping */
 #define AXGBE_AXGMAC_BAR		0
 #define AXGBE_XPCS_BAR			1
@@ -310,6 +337,10 @@ struct axgbe_phy_impl_if {
 	/* Process results of auto-negotiation */
 	enum axgbe_mode (*an_outcome)(struct axgbe_port *);
 
+	/* Pre/Post auto-negotiation support */
+	void (*an_pre)(struct axgbe_port *port);
+	void (*an_post)(struct axgbe_port *port);
+
 	/* Pre/Post KR training enablement support */
 	void (*kr_training_pre)(struct axgbe_port *);
 	void (*kr_training_post)(struct axgbe_port *);
@@ -404,6 +435,7 @@ struct axgbe_version_data {
 	unsigned int tx_tstamp_workaround;
 	unsigned int ecc_support;
 	unsigned int i2c_support;
+	unsigned int an_cdr_workaround;
 };
 
 /*
@@ -418,11 +450,12 @@ struct axgbe_port {
 	struct axgbe_version_data *vdata;
 
 	/* AXGMAC/XPCS related mmio registers */
-	uint64_t xgmac_regs;	/* AXGMAC CSRs */
-	uint64_t xpcs_regs;	/* XPCS MMD registers */
-	uint64_t xprop_regs;	/* AXGBE property registers */
-	uint64_t xi2c_regs;	/* AXGBE I2C CSRs */
+	void *xgmac_regs;	/* AXGMAC CSRs */
+	void *xpcs_regs;	/* XPCS MMD registers */
+	void *xprop_regs;	/* AXGBE property registers */
+	void *xi2c_regs;	/* AXGBE I2C CSRs */
 
+	bool cdr_track_early;
 	/* XPCS indirect addressing lock */
 	unsigned int xpcs_window_def_reg;
 	unsigned int xpcs_window_sel_reg;
@@ -506,7 +539,11 @@ struct axgbe_port {
 	/* Hardware features of the device */
 	struct axgbe_hw_features hw_feat;
 
-	struct ether_addr mac_addr;
+	struct rte_ether_addr mac_addr;
+
+	/* Software Tx/Rx structure pointers*/
+	void **rx_queues;
+	void **tx_queues;
 
 	/* MDIO/PHY related settings */
 	unsigned int phy_started;
@@ -534,6 +571,11 @@ struct axgbe_port {
 	/* I2C support */
 	struct axgbe_i2c i2c;
 	volatile int i2c_complete;
+
+	/* CRC stripping by H/w for Rx packet*/
+	int crc_strip_enable;
+	/* csum enable to hardware */
+	uint32_t rx_csum_enable;
 };
 
 void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if);