X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt.h;h=443d9fee46dc4eed176f082e7166857dddac3280;hb=6dc83230b43b1a69603f61e55ddc4e5905336365;hp=f6a45f47ea877a9b7c8557b182af8fb2bf30601e;hpb=51fbba03f732d418a4cd564f30e093c49e2076dd;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index f6a45f47ea..443d9fee46 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -22,6 +22,7 @@ #include "bnxt_util.h" #include "tf_core.h" +#include "bnxt_ulp.h" /* Vendor ID */ #define PCI_VENDOR_ID_BROADCOM 0x14E4 @@ -146,6 +147,7 @@ #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12 struct bnxt_led_info { + uint8_t num_leds; uint8_t led_id; uint8_t led_type; uint8_t led_group_id; @@ -217,11 +219,13 @@ struct bnxt_child_vf_info { struct bnxt_pf_info { #define BNXT_FIRST_PF_FID 1 -#define BNXT_MAX_VFS(bp) (bp->pf.max_vfs) -#define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs) +#define BNXT_MAX_VFS(bp) ((bp)->pf->max_vfs) +#define BNXT_MAX_VF_REPS 64 +#define BNXT_TOTAL_VFS(bp) ((bp)->pf->total_vfs) #define BNXT_FIRST_VF_FID 128 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp) -#define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp)) +#define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \ + BNXT_PF_RINGS_USED(bp)) uint16_t port_id; uint16_t first_vf_id; uint16_t active_vfs; @@ -361,7 +365,6 @@ struct bnxt_coal { #define BNXT_MAX_TC 8 #define BNXT_MAX_QUEUE 8 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) -#define BNXT_MAX_Q (bp->max_q + 1) #define BNXT_PAGE_SHFT 12 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) @@ -420,6 +423,7 @@ struct bnxt_ctx_mem_info { uint16_t tim_entry_size; uint32_t tim_max_entries; uint8_t tqm_entries_multiple; + uint8_t tqm_fp_rings_count; uint32_t flags; #define BNXT_CTX_FLAG_INITED 0x01 @@ -432,6 +436,13 @@ struct bnxt_ctx_mem_info { struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; }; +struct bnxt_ctx_mem_buf_info { + void *va; + rte_iova_t dma; + uint16_t ctx_id; + size_t size; +}; + /* Maximum Firmware Reset bail out value in milliseconds */ #define BNXT_MAX_FW_RESET_TIMEOUT 6000 /* Minimum time required for the firmware readiness in milliseconds */ @@ -472,11 +483,21 @@ struct bnxt_error_recovery_info { uint32_t last_reset_counter; }; +/* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */ +#define BNXT_IF_CHANGE_RETRY_INTERVAL 50 +/* Maximum retry count for FUNC_DRV_IF_CHANGE */ +#define BNXT_IF_CHANGE_RETRY_COUNT 40 + struct bnxt_mark_info { uint32_t mark_id; bool valid; }; +struct bnxt_rep_info { + struct rte_eth_dev *vfr_eth_dev; + pthread_mutex_t vfr_lock; +}; + /* address space location of register */ #define BNXT_FW_STATUS_REG_TYPE_MASK 3 /* register is located in PCIe config space */ @@ -494,14 +515,61 @@ struct bnxt_mark_info { #define BNXT_GRCP_WINDOW_2_BASE 0x2000 #define BNXT_GRCP_WINDOW_3_BASE 0x3000 +#define BNXT_GRCP_BASE_MASK 0xfffff000 +#define BNXT_GRCP_OFFSET_MASK 0x00000ffc + +#define BNXT_FW_STATUS_HEALTHY 0x8000 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 +#define BNXT_ETH_RSS_SUPPORT ( \ + ETH_RSS_IPV4 | \ + ETH_RSS_NONFRAG_IPV4_TCP | \ + ETH_RSS_NONFRAG_IPV4_UDP | \ + ETH_RSS_IPV6 | \ + ETH_RSS_NONFRAG_IPV6_TCP | \ + ETH_RSS_NONFRAG_IPV6_UDP) + +#define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ + DEV_TX_OFFLOAD_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_TCP_CKSUM | \ + DEV_TX_OFFLOAD_UDP_CKSUM | \ + DEV_TX_OFFLOAD_TCP_TSO | \ + DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ + DEV_TX_OFFLOAD_GRE_TNL_TSO | \ + DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ + DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ + DEV_TX_OFFLOAD_QINQ_INSERT | \ + DEV_TX_OFFLOAD_MULTI_SEGS) + +#define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ + DEV_RX_OFFLOAD_VLAN_STRIP | \ + DEV_RX_OFFLOAD_IPV4_CKSUM | \ + DEV_RX_OFFLOAD_UDP_CKSUM | \ + DEV_RX_OFFLOAD_TCP_CKSUM | \ + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ + DEV_RX_OFFLOAD_JUMBO_FRAME | \ + DEV_RX_OFFLOAD_KEEP_CRC | \ + DEV_RX_OFFLOAD_VLAN_EXTEND | \ + DEV_RX_OFFLOAD_TCP_LRO | \ + DEV_RX_OFFLOAD_SCATTER | \ + DEV_RX_OFFLOAD_RSS_HASH) + #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) + +struct bnxt_flow_stat_info { + uint16_t max_fc; + uint16_t flow_count; + struct bnxt_ctx_mem_buf_info rx_fc_in_tbl; + struct bnxt_ctx_mem_buf_info rx_fc_out_tbl; + struct bnxt_ctx_mem_buf_info tx_fc_in_tbl; + struct bnxt_ctx_mem_buf_info tx_fc_out_tbl; +}; + struct bnxt { void *bar0; struct rte_eth_dev *eth_dev; - struct rte_eth_rss_conf rss_conf; struct rte_pci_device *pdev; void *doorbell_base; @@ -529,8 +597,12 @@ struct bnxt { #define BNXT_FLAG_NEW_RM BIT(20) #define BNXT_FLAG_NPAR_PF BIT(21) #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(22) -#define BNXT_FLAG_ADV_FLOW_MGMT BIT(23) +#define BNXT_FLAG_FC_THREAD BIT(23) #define BNXT_FLAG_RX_VECTOR_PKT_MODE BIT(24) +#define BNXT_FLAG_FLOW_XSTATS_EN BIT(25) +#define BNXT_FLAG_DFLT_MAC_SET BIT(26) +#define BNXT_FLAG_TRUFLOW_EN BIT(27) +#define BNXT_FLAG_GFID_ENABLE BIT(28) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->flags & BNXT_FLAG_NPAR_PF) @@ -543,12 +615,19 @@ struct bnxt { #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) +#define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN) +#define BNXT_HAS_DFLT_MAC_SET(bp) ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET) +#define BNXT_TRUFLOW_EN(bp) ((bp)->flags & BNXT_FLAG_TRUFLOW_EN) +#define BNXT_GFID_ENABLED(bp) ((bp)->flags & BNXT_FLAG_GFID_ENABLE) uint32_t fw_cap; #define BNXT_FW_CAP_HOT_RESET BIT(0) #define BNXT_FW_CAP_IF_CHANGE BIT(1) #define BNXT_FW_CAP_ERROR_RECOVERY BIT(2) #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT(3) +#define BNXT_FW_CAP_ADV_FLOW_MGMT BIT(5) +#define BNXT_FW_CAP_ADV_FLOW_COUNTERS BIT(6) +#define BNXT_FW_CAP_HCOMM_FW_STATUS BIT(7) uint32_t flow_flags; #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0) @@ -615,9 +694,9 @@ struct bnxt { /* default HWRM request timeout value */ uint32_t hwrm_cmd_timeout; - struct bnxt_link_info link_info; - struct bnxt_cos_queue_info rx_cos_queue[BNXT_COS_QUEUE_COUNT]; - struct bnxt_cos_queue_info tx_cos_queue[BNXT_COS_QUEUE_COUNT]; + struct bnxt_link_info *link_info; + struct bnxt_cos_queue_info *rx_cos_queue; + struct bnxt_cos_queue_info *tx_cos_queue; uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT]; uint8_t rx_cosq_cnt; uint8_t max_tc; @@ -625,7 +704,6 @@ struct bnxt { uint8_t max_q; uint16_t fw_fid; - uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; uint16_t max_rsscos_ctx; uint16_t max_cp_rings; uint16_t max_tx_rings; @@ -633,10 +711,10 @@ struct bnxt { #define MAX_STINGRAY_RINGS 128U /* For sake of symmetry, max Tx rings == max Rx rings, one stat ctx for each */ #define BNXT_MAX_RX_RINGS(bp) \ - (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings, \ + (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings / 2U, \ MAX_STINGRAY_RINGS), \ bp->max_stat_ctx / 2U) : \ - RTE_MIN(bp->max_rx_rings, \ + RTE_MIN(bp->max_rx_rings / 2U, \ bp->max_stat_ctx / 2U)) #define BNXT_MAX_TX_RINGS(bp) \ (RTE_MIN((bp)->max_tx_rings, BNXT_MAX_RX_RINGS(bp))) @@ -644,6 +722,9 @@ struct bnxt { #define BNXT_MAX_RINGS(bp) \ (RTE_MIN((((bp)->max_cp_rings - BNXT_NUM_ASYNC_CPR(bp)) / 2U), \ BNXT_MAX_TX_RINGS(bp))) + +#define BNXT_MAX_VF_REP_RINGS 8 + uint16_t max_nq_rings; uint16_t max_l2_ctx; uint16_t max_rx_em_flows; @@ -656,7 +737,7 @@ struct bnxt { #define BNXT_OUTER_TPID_BD_MASK 0xffff0000 #define BNXT_OUTER_TPID_BD_SHFT 16 uint32_t outer_tpid_bd; - struct bnxt_pf_info pf; + struct bnxt_pf_info *pf; uint8_t vxlan_port_cnt; uint8_t geneve_port_cnt; uint16_t vxlan_port; @@ -666,15 +747,17 @@ struct bnxt { uint32_t fw_ver; uint32_t hwrm_spec_code; - struct bnxt_led_info leds[BNXT_MAX_LED]; - uint8_t num_leds; + struct bnxt_led_info *leds; struct bnxt_ptp_cfg *ptp_cfg; uint16_t vf_resv_strategy; struct bnxt_ctx_mem_info *ctx; uint16_t fw_reset_min_msecs; uint16_t fw_reset_max_msecs; - + uint16_t switch_domain_id; + uint16_t num_reps; + struct bnxt_rep_info *rep_info; + uint16_t *cfa_code_map; /* Struct to hold adapter error recovery related info */ struct bnxt_error_recovery_info *recovery_info; #define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024) @@ -685,7 +768,42 @@ struct bnxt { #define BNXT_SVIF_INVALID 0xFFFF uint16_t func_svif; uint16_t port_svif; - struct tf tfp; + + struct tf tfp; + struct bnxt_ulp_context *ulp_ctx; + struct bnxt_flow_stat_info *flow_stat; + uint8_t flow_xstat; + uint16_t max_num_kflows; +}; + +#define BNXT_FC_TIMER 1 /* Timer freq in Sec Flow Counters */ + +/** + * Structure to store private data for each VF representor instance + */ +struct bnxt_vf_representor { + uint16_t switch_domain_id; + uint16_t vf_id; + uint16_t tx_cfa_action; + uint16_t rx_cfa_code; + /* Private data store of associated PF/Trusted VF */ + struct rte_eth_dev *parent_dev; + uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; + uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; + struct bnxt_rx_queue **rx_queues; + unsigned int rx_nr_rings; + unsigned int tx_nr_rings; + uint64_t tx_pkts[BNXT_MAX_VF_REP_RINGS]; + uint64_t tx_bytes[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_pkts[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_bytes[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_drop_pkts[BNXT_MAX_VF_REP_RINGS]; + uint64_t rx_drop_bytes[BNXT_MAX_VF_REP_RINGS]; +}; + +struct bnxt_vf_rep_tx_queue { + struct bnxt_tx_queue *txq; + struct bnxt_vf_representor *bp; }; int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); @@ -700,7 +818,13 @@ void bnxt_schedule_fw_health_check(struct bnxt *bp); bool is_bnxt_supported(struct rte_eth_dev *dev); bool bnxt_stratus_device(struct bnxt *bp); +void bnxt_print_link_info(struct rte_eth_dev *eth_dev); +uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp); +int bnxt_link_update_op(struct rte_eth_dev *eth_dev, + int wait_to_complete); + extern const struct rte_flow_ops bnxt_flow_ops; + #define bnxt_acquire_flow_lock(bp) \ pthread_mutex_lock(&(bp)->flow_lock) @@ -727,7 +851,17 @@ extern int bnxt_logtype_driver; #define PMD_DRV_LOG(level, fmt, args...) \ PMD_DRV_LOG_RAW(level, fmt, ## args) +extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops; +int32_t bnxt_ulp_init(struct bnxt *bp); +void bnxt_ulp_deinit(struct bnxt *bp); + uint16_t bnxt_get_vnic_id(uint16_t port); uint16_t bnxt_get_svif(uint16_t port_id, bool func_svif); +uint16_t bnxt_get_fw_func_id(uint16_t port); +void bnxt_cancel_fc_thread(struct bnxt *bp); +void bnxt_flow_cnt_alarm_cb(void *arg); +int bnxt_flow_stats_req(struct bnxt *bp); +int bnxt_flow_stats_cnt(struct bnxt *bp); +uint32_t bnxt_get_speed_capabilities(struct bnxt *bp); #endif