X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fbnxt.h;h=f8a550ba54473a5637c2748cb18db2946d10bb6e;hb=c46c7a71619e30b002bb54fb0d27cf428e2fbdf2;hp=c580ec22b0b2012d6835887933655f55b8e2ee98;hpb=80ad678ae715c8bee2f7a396431d3703df245f5a;p=dpdk.git diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index c580ec22b0..f8a550ba54 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -19,20 +19,37 @@ #include #include "bnxt_cpr.h" +#include "bnxt_util.h" #define BNXT_MAX_MTU 9574 #define VLAN_TAG_SIZE 4 +#define BNXT_NUM_VLANS 2 +#define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\ + RTE_ETHER_CRC_LEN +\ + (BNXT_NUM_VLANS * VLAN_TAG_SIZE)) #define BNXT_VF_RSV_NUM_RSS_CTX 1 #define BNXT_VF_RSV_NUM_L2_CTX 4 /* TODO: For now, do not support VMDq/RFS on VFs. */ #define BNXT_VF_RSV_NUM_VNIC 1 #define BNXT_MAX_LED 4 -#define BNXT_NUM_VLANS 2 #define BNXT_MIN_RING_DESC 16 #define BNXT_MAX_TX_RING_DESC 4096 #define BNXT_MAX_RX_RING_DESC 8192 #define BNXT_DB_SIZE 0x80 +#ifdef RTE_ARCH_ARM64 +#define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1) +#else +#define BNXT_NUM_ASYNC_CPR(bp) 1 +#endif + +/* Chimp Communication Channel */ +#define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0 +#define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 +/* Kong Communication Channel */ +#define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00 +#define GRCPF_REG_KONG_COMM_TRIGGER 0xB00 + #define BNXT_INT_LAT_TMR_MIN 75 #define BNXT_INT_LAT_TMR_MAX 150 #define BNXT_NUM_CMPL_AGGR_INT 36 @@ -175,6 +192,10 @@ struct rte_flow { struct bnxt_vnic_info *vnic; }; +#define BNXT_PTP_FLAGS_PATH_TX 0x0 +#define BNXT_PTP_FLAGS_PATH_RX 0x1 +#define BNXT_PTP_FLAGS_CURRENT_TIME 0x2 + struct bnxt_ptp_cfg { #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 @@ -185,16 +206,16 @@ struct bnxt_ptp_cfg { struct bnxt *bp; #define BNXT_MAX_TX_TS 1 uint16_t rxctl; -#define BNXT_PTP_MSG_SYNC (1 << 0) -#define BNXT_PTP_MSG_DELAY_REQ (1 << 1) -#define BNXT_PTP_MSG_PDELAY_REQ (1 << 2) -#define BNXT_PTP_MSG_PDELAY_RESP (1 << 3) -#define BNXT_PTP_MSG_FOLLOW_UP (1 << 8) -#define BNXT_PTP_MSG_DELAY_RESP (1 << 9) -#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10) -#define BNXT_PTP_MSG_ANNOUNCE (1 << 11) -#define BNXT_PTP_MSG_SIGNALING (1 << 12) -#define BNXT_PTP_MSG_MANAGEMENT (1 << 13) +#define BNXT_PTP_MSG_SYNC BIT(0) +#define BNXT_PTP_MSG_DELAY_REQ BIT(1) +#define BNXT_PTP_MSG_PDELAY_REQ BIT(2) +#define BNXT_PTP_MSG_PDELAY_RESP BIT(3) +#define BNXT_PTP_MSG_FOLLOW_UP BIT(8) +#define BNXT_PTP_MSG_DELAY_RESP BIT(9) +#define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10) +#define BNXT_PTP_MSG_ANNOUNCE BIT(11) +#define BNXT_PTP_MSG_SIGNALING BIT(12) +#define BNXT_PTP_MSG_MANAGEMENT BIT(13) #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \ BNXT_PTP_MSG_DELAY_REQ | \ BNXT_PTP_MSG_PDELAY_REQ | \ @@ -220,6 +241,9 @@ struct bnxt_ptp_cfg { uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS]; uint32_t tx_regs[BNXT_PTP_TX_REGS]; uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS]; + + /* On Thor, the Rx timestamp is present in the Rx completion record */ + uint64_t rx_timestamp; }; struct bnxt_coal { @@ -232,6 +256,153 @@ struct bnxt_coal { uint16_t cmpl_aggr_dma_tmr_during_int; }; +/* 64-bit doorbell */ +#define DBR_XID_SFT 32 +#define DBR_PATH_L2 (0x1ULL << 56) +#define DBR_TYPE_SQ (0x0ULL << 60) +#define DBR_TYPE_SRQ (0x2ULL << 60) +#define DBR_TYPE_CQ (0x4ULL << 60) +#define DBR_TYPE_NQ (0xaULL << 60) +#define DBR_TYPE_NQ_ARM (0xbULL << 60) + +#define BNXT_RSS_TBL_SIZE_THOR 512 +#define BNXT_RSS_ENTRIES_PER_CTX_THOR 64 +#define BNXT_MAX_RSS_CTXTS_THOR \ + (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR) + +#define BNXT_MAX_TC 8 +#define BNXT_MAX_QUEUE 8 +#define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1) +#define BNXT_MAX_Q (bp->max_q + 1) +#define BNXT_PAGE_SHFT 12 +#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT) +#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) + +#define PTU_PTE_VALID 0x1UL +#define PTU_PTE_LAST 0x2UL +#define PTU_PTE_NEXT_TO_LAST 0x4UL + +struct bnxt_ring_mem_info { + int nr_pages; + int page_size; + uint32_t flags; +#define BNXT_RMEM_VALID_PTE_FLAG 1 +#define BNXT_RMEM_RING_PTE_FLAG 2 + + void **pg_arr; + rte_iova_t *dma_arr; + const struct rte_memzone *mz; + + uint64_t *pg_tbl; + rte_iova_t pg_tbl_map; + const struct rte_memzone *pg_tbl_mz; + + int vmem_size; + void **vmem; +}; + +struct bnxt_ctx_pg_info { + uint32_t entries; + void *ctx_pg_arr[MAX_CTX_PAGES]; + rte_iova_t ctx_dma_arr[MAX_CTX_PAGES]; + struct bnxt_ring_mem_info ring_mem; +}; + +struct bnxt_ctx_mem_info { + uint32_t qp_max_entries; + uint16_t qp_min_qp1_entries; + uint16_t qp_max_l2_entries; + uint16_t qp_entry_size; + uint16_t srq_max_l2_entries; + uint32_t srq_max_entries; + uint16_t srq_entry_size; + uint16_t cq_max_l2_entries; + uint32_t cq_max_entries; + uint16_t cq_entry_size; + uint16_t vnic_max_vnic_entries; + uint16_t vnic_max_ring_table_entries; + uint16_t vnic_entry_size; + uint32_t stat_max_entries; + uint16_t stat_entry_size; + uint16_t tqm_entry_size; + uint32_t tqm_min_entries_per_ring; + uint32_t tqm_max_entries_per_ring; + uint32_t mrav_max_entries; + uint16_t mrav_entry_size; + uint16_t tim_entry_size; + uint32_t tim_max_entries; + uint8_t tqm_entries_multiple; + + uint32_t flags; +#define BNXT_CTX_FLAG_INITED 0x01 + + struct bnxt_ctx_pg_info qp_mem; + struct bnxt_ctx_pg_info srq_mem; + struct bnxt_ctx_pg_info cq_mem; + struct bnxt_ctx_pg_info vnic_mem; + struct bnxt_ctx_pg_info stat_mem; + struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q]; +}; + +/* Maximum Firmware Reset bail out value in milliseconds */ +#define BNXT_MAX_FW_RESET_TIMEOUT 6000 +/* Minimum time required for the firmware readiness in milliseconds */ +#define BNXT_MIN_FW_READY_TIMEOUT 2000 +/* Frequency for the firmware readiness check in milliseconds */ +#define BNXT_FW_READY_WAIT_INTERVAL 100 + +#define US_PER_MS 1000 +#define NS_PER_US 1000 + +struct bnxt_error_recovery_info { + /* All units in milliseconds */ + uint32_t driver_polling_freq; + uint32_t master_func_wait_period; + uint32_t normal_func_wait_period; + uint32_t master_func_wait_period_after_reset; + uint32_t max_bailout_time_after_reset; +#define BNXT_FW_STATUS_REG 0 +#define BNXT_FW_HEARTBEAT_CNT_REG 1 +#define BNXT_FW_RECOVERY_CNT_REG 2 +#define BNXT_FW_RESET_INPROG_REG 3 +#define BNXT_FW_STATUS_REG_CNT 4 + uint32_t status_regs[BNXT_FW_STATUS_REG_CNT]; + uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT]; + uint32_t reset_inprogress_reg_mask; +#define BNXT_NUM_RESET_REG 16 + uint8_t reg_array_cnt; + uint32_t reset_reg[BNXT_NUM_RESET_REG]; + uint32_t reset_reg_val[BNXT_NUM_RESET_REG]; + uint8_t delay_after_reset[BNXT_NUM_RESET_REG]; +#define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0) +#define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1) +#define BNXT_FLAG_MASTER_FUNC BIT(2) +#define BNXT_FLAG_RECOVERY_ENABLED BIT(3) + uint32_t flags; + + uint32_t last_heart_beat; + uint32_t last_reset_counter; +}; + +/* address space location of register */ +#define BNXT_FW_STATUS_REG_TYPE_MASK 3 +/* register is located in PCIe config space */ +#define BNXT_FW_STATUS_REG_TYPE_CFG 0 +/* register is located in GRC address space */ +#define BNXT_FW_STATUS_REG_TYPE_GRC 1 +/* register is located in BAR0 */ +#define BNXT_FW_STATUS_REG_TYPE_BAR0 2 +/* register is located in BAR1 */ +#define BNXT_FW_STATUS_REG_TYPE_BAR1 3 + +#define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK) +#define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK) + +#define BNXT_GRCP_WINDOW_2_BASE 0x2000 +#define BNXT_GRCP_WINDOW_3_BASE 0x3000 + +#define BNXT_FW_STATUS_SHUTDOWN 0x100000 + #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) struct bnxt { void *bar0; @@ -242,21 +413,44 @@ struct bnxt { void *doorbell_base; uint32_t flags; -#define BNXT_FLAG_REGISTERED (1 << 0) -#define BNXT_FLAG_VF (1 << 1) -#define BNXT_FLAG_PORT_STATS (1 << 2) -#define BNXT_FLAG_JUMBO (1 << 3) -#define BNXT_FLAG_SHORT_CMD (1 << 4) -#define BNXT_FLAG_UPDATE_HASH (1 << 5) -#define BNXT_FLAG_PTP_SUPPORTED (1 << 6) -#define BNXT_FLAG_MULTI_HOST (1 << 7) -#define BNXT_FLAG_NEW_RM (1 << 30) -#define BNXT_FLAG_INIT_DONE (1 << 31) +#define BNXT_FLAG_REGISTERED BIT(0) +#define BNXT_FLAG_VF BIT(1) +#define BNXT_FLAG_PORT_STATS BIT(2) +#define BNXT_FLAG_JUMBO BIT(3) +#define BNXT_FLAG_SHORT_CMD BIT(4) +#define BNXT_FLAG_UPDATE_HASH BIT(5) +#define BNXT_FLAG_PTP_SUPPORTED BIT(6) +#define BNXT_FLAG_MULTI_HOST BIT(7) +#define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8) +#define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9) +#define BNXT_FLAG_KONG_MB_EN BIT(10) +#define BNXT_FLAG_TRUSTED_VF_EN BIT(11) +#define BNXT_FLAG_DFLT_VNIC_SET BIT(12) +#define BNXT_FLAG_THOR_CHIP BIT(13) +#define BNXT_FLAG_STINGRAY BIT(14) +#define BNXT_FLAG_FW_RESET BIT(15) +#define BNXT_FLAG_FATAL_ERROR BIT(16) +#define BNXT_FLAG_FW_CAP_IF_CHANGE BIT(17) +#define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(18) +#define BNXT_FLAG_FW_CAP_ERROR_RECOVERY BIT(19) +#define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(20) +#define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD BIT(21) +#define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(22) +#define BNXT_FLAG_NEW_RM BIT(23) +#define BNXT_FLAG_INIT_DONE BIT(24) +#define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(25) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->port_partition_type) #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) +#define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp. +#define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN) +#define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN) +#define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP) +#define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY) +#define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp) +#define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp)) unsigned int rx_nr_rings; unsigned int rx_cp_nr_rings; @@ -264,6 +458,9 @@ struct bnxt { const void *rx_mem_zone; struct rx_port_stats *hw_rx_port_stats; rte_iova_t hw_rx_port_stats_map; + struct rx_port_stats_ext *hw_rx_port_stats_ext; + rte_iova_t hw_rx_port_stats_ext_map; + uint16_t fw_rx_port_stats_ext_size; unsigned int tx_nr_rings; unsigned int tx_cp_nr_rings; @@ -271,14 +468,18 @@ struct bnxt { const void *tx_mem_zone; struct tx_port_stats *hw_tx_port_stats; rte_iova_t hw_tx_port_stats_map; + struct tx_port_stats_ext *hw_tx_port_stats_ext; + rte_iova_t hw_tx_port_stats_ext_map; + uint16_t fw_tx_port_stats_ext_size; /* Default completion ring */ - struct bnxt_cp_ring_info *def_cp_ring; + struct bnxt_cp_ring_info *async_cp_ring; uint32_t max_ring_grps; struct bnxt_ring_grp_info *grp_info; unsigned int nr_vnics; +#define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0]) struct bnxt_vnic_info *vnic_info; STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list; @@ -287,10 +488,10 @@ struct bnxt { struct bnxt_irq *irq_tbl; -#define MAX_NUM_MAC_ADDR 32 - uint8_t mac_addr[ETHER_ADDR_LEN]; + uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; uint16_t hwrm_cmd_seq; + uint16_t kong_cmd_seq; void *hwrm_cmd_resp_addr; rte_iova_t hwrm_cmd_resp_dma_addr; void *hwrm_short_cmd_req_addr; @@ -298,22 +499,33 @@ struct bnxt { rte_spinlock_t hwrm_lock; uint16_t max_req_len; uint16_t max_resp_len; + uint16_t hwrm_max_ext_req_len; struct bnxt_link_info link_info; struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT]; uint8_t tx_cosq_id; + uint8_t max_tc; + uint8_t max_lltc; + uint8_t max_q; uint16_t fw_fid; - uint8_t dflt_mac_addr[ETHER_ADDR_LEN]; + uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN]; uint16_t max_rsscos_ctx; uint16_t max_cp_rings; uint16_t max_tx_rings; uint16_t max_rx_rings; + uint16_t max_nq_rings; uint16_t max_l2_ctx; + uint16_t max_rx_em_flows; uint16_t max_vnics; uint16_t max_stat_ctx; + uint16_t first_vf_id; uint16_t vlan; - struct bnxt_pf_info pf; +#define BNXT_OUTER_TPID_MASK 0x0000ffff +#define BNXT_OUTER_TPID_BD_MASK 0xffff0000 +#define BNXT_OUTER_TPID_BD_SHFT 16 + uint32_t outer_tpid_bd; + struct bnxt_pf_info pf; uint8_t port_partition_type; uint8_t dev_stopped; uint8_t vxlan_port_cnt; @@ -329,10 +541,22 @@ struct bnxt { uint8_t num_leds; struct bnxt_ptp_cfg *ptp_cfg; uint16_t vf_resv_strategy; + struct bnxt_ctx_mem_info *ctx; + + uint16_t fw_reset_min_msecs; + uint16_t fw_reset_max_msecs; + + /* Struct to hold adapter error recovery related info */ + struct bnxt_error_recovery_info *recovery_info; }; int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete); int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg); +int is_bnxt_in_error(struct bnxt *bp); + +int bnxt_map_fw_health_status_regs(struct bnxt *bp); +uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index); +void bnxt_schedule_fw_health_check(struct bnxt *bp); bool is_bnxt_supported(struct rte_eth_dev *dev); bool bnxt_stratus_device(struct bnxt *bp);