X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnxt%2Fhsi_struct_def_dpdk.h;h=fb4f712ce28b901dc0006b6bc33ad2bd624177ba;hb=b57c51ef92eb5faa2d6e76efd7a067f6e470f294;hp=c45d0883acb7b627a3467835bc959c68a55bd94d;hpb=84d49664b5b2bf94264601ffca8de931dc91b8ec;p=dpdk.git diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index c45d0883ac..fb4f712ce2 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2019 Broadcom Inc. + * Copyright (c) 2014-2020 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -39,7 +39,7 @@ struct hwrm_cmd_hdr { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* This is the HWRM response header. */ /* hwrm_resp_hdr (size:64b/8B) */ @@ -52,7 +52,7 @@ struct hwrm_resp_hdr { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; -} __attribute__((packed)); +} __rte_packed; /* * TLV encapsulated message. Use the TLV type field of the @@ -80,16 +80,18 @@ struct hwrm_resp_hdr { #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004) /* Engine CKV - The encrypted data. */ #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005) -/* Engine CKV - Supported algorithms. */ -#define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006) +/* Engine CKV - Supported host_algorithms. */ +#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006) /* Engine CKV - The Host EC curve name and ECC public key information. */ #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007) /* Engine CKV - The ECDSA signature. */ #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008) -/* Engine CKV - The SRT EC curve name and ECC public key information. */ -#define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY UINT32_C(0x8009) +/* Engine CKV - The firmware EC curve name and ECC public key information. */ +#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009) +/* Engine CKV - Supported firmware algorithms. */ +#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a) #define TLV_TYPE_LAST \ - TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY + TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS /* tlv (size:64b/8B) */ @@ -145,7 +147,7 @@ struct tlv { * and it must be an integer multiple of 8B. */ uint16_t length; -} __attribute__((packed)); +} __rte_packed; /* Input */ /* input (size:128b/16B) */ @@ -178,7 +180,7 @@ struct input { * and must be cleared to zero before the request is made. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* Output */ /* output (size:64b/8B) */ @@ -201,7 +203,7 @@ struct output { * memory. */ uint16_t resp_len; -} __attribute__((packed)); +} __rte_packed; /* Short Command Structure */ /* hwrm_short_input (size:128b/16B) */ @@ -237,7 +239,7 @@ struct hwrm_short_input { * This area must be 16B aligned. */ uint64_t req_addr; -} __attribute__((packed)); +} __rte_packed; /* * Command numbering @@ -319,11 +321,8 @@ struct cmd_nums { #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38) #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39) #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a) - /* Experimental */ #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b) - /* Experimental */ #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c) - /* Experimental */ #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d) #define HWRM_VNIC_ALLOC UINT32_C(0x40) #define HWRM_VNIC_FREE UINT32_C(0x41) @@ -342,15 +341,23 @@ struct cmd_nums { #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52) #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53) #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54) + #define HWRM_RING_SQ_ALLOC UINT32_C(0x55) + #define HWRM_RING_SQ_CFG UINT32_C(0x56) + #define HWRM_RING_SQ_FREE UINT32_C(0x57) #define HWRM_RING_RESET UINT32_C(0x5e) #define HWRM_RING_GRP_ALLOC UINT32_C(0x60) #define HWRM_RING_GRP_FREE UINT32_C(0x61) + #define HWRM_RING_CFG UINT32_C(0x62) + #define HWRM_RING_QCFG UINT32_C(0x63) /* Reserved for future use. */ #define HWRM_RESERVED5 UINT32_C(0x64) /* Reserved for future use. */ #define HWRM_RESERVED6 UINT32_C(0x65) #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70) #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71) + #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80) + #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81) + #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82) #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90) #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91) #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92) @@ -382,11 +389,15 @@ struct cmd_nums { #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4) #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5) #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6) + #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) + #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) + #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9) + #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) #define HWRM_FW_SYNC UINT32_C(0xc3) - #define HWRM_FW_STATE_BUFFER_QCAPS UINT32_C(0xc4) + #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4) #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5) #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6) #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7) @@ -400,6 +411,8 @@ struct cmd_nums { #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb) /* Experimental */ #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc) + #define HWRM_FW_ECN_CFG UINT32_C(0xcd) + #define HWRM_FW_ECN_QCFG UINT32_C(0xce) #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0) #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1) #define HWRM_FWD_RESP UINT32_C(0xd2) @@ -407,7 +420,15 @@ struct cmd_nums { #define HWRM_OEM_CMD UINT32_C(0xd4) /* Tells the fw to run PRBS test on a given port and lane. */ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5) + #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6) + #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7) + #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8) + /* Tells the fw to collect dsc dump on a given port and lane. */ + #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) + #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) + #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) + #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3) #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0) #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1) #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2) @@ -499,7 +520,7 @@ struct cmd_nums { #define HWRM_CFA_EEM_OP UINT32_C(0x123) /* Experimental */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) - /* Experimental */ + /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) @@ -561,6 +582,8 @@ struct cmd_nums { #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156) /* Engine - Query the statistics accumulator for an Engine. */ #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157) + /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */ + #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158) /* Engine - Allocate an Engine RQ. */ #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e) /* Engine - Free an Engine RQ. */ @@ -593,6 +616,10 @@ struct cmd_nums { #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196) /* Queries pf ids belong to specified host(s) */ #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197) + /* Queries extended stats per function */ + #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198) + /* Queries extended statistics context */ + #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -616,6 +643,68 @@ struct cmd_nums { * to the host test. */ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209) + /* Tells the fw to program the fru memory */ + #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a) + /* Tells the fw to read the fru memory */ + #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b) + /* Experimental */ + #define HWRM_TF UINT32_C(0x2bc) + /* Experimental */ + #define HWRM_TF_VERSION_GET UINT32_C(0x2bd) + /* Experimental */ + #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) + /* Experimental */ + #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) + /* Experimental */ + #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8) + /* Experimental */ + #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9) + /* Experimental */ + #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca) + /* Experimental */ + #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6) + /* Experimental */ + #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7) + /* Experimental */ + #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9) + /* Experimental */ + #define HWRM_TF_EM_INSERT UINT32_C(0x2ea) + /* Experimental */ + #define HWRM_TF_EM_DELETE UINT32_C(0x2eb) + /* Experimental */ + #define HWRM_TF_TCAM_SET UINT32_C(0x2f8) + /* Experimental */ + #define HWRM_TF_TCAM_GET UINT32_C(0x2f9) + /* Experimental */ + #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa) + /* Experimental */ + #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb) + /* Experimental */ + #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc) + /* Experimental */ + #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd) + /* Experimental */ + #define HWRM_SV UINT32_C(0x400) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -645,6 +734,15 @@ struct cmd_nums { #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d) /* Experimental */ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e) + /* Send driver debug information to firmware */ + #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f) + /* Query debug capabilities of firmware */ + #define HWRM_DBG_QCAPS UINT32_C(0xff20) + /* Retrieve debug settings of firmware */ + #define HWRM_DBG_QCFG UINT32_C(0xff21) + /* Set destination parameters for crashdump medium */ + #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22) + #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef) @@ -666,7 +764,7 @@ struct cmd_nums { #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff) #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK uint16_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* Return Codes */ /* ret_codes (size:64b/8B) */ @@ -731,7 +829,7 @@ struct ret_codes { #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb) /* * This error code is only reported by the firmware when during - * flow allocation when a requeest for a flow counter fails because + * flow allocation when a request for a flow counter fails because * the number of flow counters are exhausted. */ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc) @@ -752,11 +850,16 @@ struct ret_codes { * internal error. */ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf) + /* + * Firmware is unable to service the request at the present time. Caller + * may try again later. + */ + #define HWRM_ERR_CODE_BUSY UINT32_C(0x10) /* * This value indicates that the HWRM response is in TLV format and * should be interpreted as one or more TLVs starting with the - * hwrm_resp_hdr TLV. This value is not an indicatation of any error - * by itself, just an indicatation that the response should be parsed + * hwrm_resp_hdr TLV. This value is not an indication of any error + * by itself, just an indication that the response should be parsed * as TLV and the actual error code will be in the hwrm_resp_hdr TLV. */ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000) @@ -767,7 +870,7 @@ struct ret_codes { #define HWRM_ERR_CODE_LAST \ HWRM_ERR_CODE_CMD_NOT_SUPPORTED uint16_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* Output */ /* hwrm_err_output (size:128b/16B) */ @@ -807,7 +910,7 @@ struct hwrm_err_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* * Following is the signature for HWRM message field that indicates not * applicable (All F's). Need to cast it the size of the field if needed. @@ -837,10 +940,10 @@ struct hwrm_err_output { #define HWRM_TARGET_ID_TOOLS 0xFFFD #define HWRM_VERSION_MAJOR 1 #define HWRM_VERSION_MINOR 10 -#define HWRM_VERSION_UPDATE 0 +#define HWRM_VERSION_UPDATE 1 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 91 -#define HWRM_VERSION_STR "1.10.0.91" +#define HWRM_VERSION_RSVD 48 +#define HWRM_VERSION_STR "1.10.1.48" /**************** * hwrm_ver_get * @@ -905,7 +1008,7 @@ struct hwrm_ver_get_input { */ uint8_t hwrm_intf_upd; uint8_t unused_0[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_ver_get_output (size:1408b/176B) */ struct hwrm_ver_get_output { @@ -1125,12 +1228,21 @@ struct hwrm_ver_get_output { #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \ UINT32_C(0x1000) /* + * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. * If set to 0, then the firmware doesn’t support TFLIB features. * By default, this flag should be 0 for older version of core firmware. */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \ UINT32_C(0x2000) + /* + * If set to 1, the firmware is able to support TruFlow features. + * If set to 0, then the firmware doesn’t support TruFlow features. + * By default, this flag should be 0 for older version of + * core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ + UINT32_C(0x4000) /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. @@ -1380,7 +1492,7 @@ struct hwrm_ver_get_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* bd_base (size:64b/8B) */ struct bd_base { @@ -1395,12 +1507,12 @@ struct bd_base { #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0) /* * Indicates that this BD is 1BB long and is an empty - * TX BD. Not valid for use by the driver. + * TX BD. Not valid for use by the driver. */ #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1) /* * Indicates that this BD is 16B long and is an RX Producer - * (ie. empty) buffer descriptor. + * (i.e. empty) buffer descriptor. */ #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4) /* @@ -1426,7 +1538,7 @@ struct bd_base { #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11) #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE uint8_t unused_1[7]; -} __attribute__((packed)); +} __rte_packed; /* tx_bd_short (size:128b/16B) */ struct tx_bd_short { @@ -1454,7 +1566,7 @@ struct tx_bd_short { #define TX_BD_SHORT_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40) @@ -1472,9 +1584,9 @@ struct tx_bd_short { * This value indicates how many 16B BD locations are consumed * in the ring by this packet. * A value of 1 indicates that this BD is the only BD (and that - * the it is a short BD). A value + * it is a short BD). A value * of 3 indicates either 3 short BDs or 1 long BD and one short - * BD in the packet. A value of 0 indicates + * BD in the packet. A value of 0 indicates * that there are 32 BD locations in the packet (the maximum). * * This field is valid only on the first BD of a packet. @@ -1535,7 +1647,7 @@ struct tx_bd_short { * This value must be valid on all BDs of a packet. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* tx_bd_long (size:128b/16B) */ struct tx_bd_long { @@ -1562,7 +1674,7 @@ struct tx_bd_long { #define TX_BD_LONG_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40) @@ -1580,9 +1692,9 @@ struct tx_bd_long { * This value indicates how many 16B BD locations are consumed * in the ring by this packet. * A value of 1 indicates that this BD is the only BD (and that - * the it is a short BD). A value + * it is a short BD). A value * of 3 indicates either 3 short BDs or 1 long BD and one short - * BD in the packet. A value of 0 indicates + * BD in the packet. A value of 0 indicates * that there are 32 BD locations in the packet (the maximum). * * This field is valid only on the first BD of a packet. @@ -1642,7 +1754,7 @@ struct tx_bd_long { * This value must be valid on all BDs of a packet. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* Last 16 bytes of tx_bd_long. */ /* tx_bd_long_hi (size:128b/16B) */ @@ -1663,7 +1775,7 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) /* - * If set to 1, the controller replaces the IP checksum of the + * If set to 1, the controller replaces the IP checksum of the * normal packets, or the inner IP checksum of the encapsulated * packets with the hardware calculated IP checksum for the * packet associated with this descriptor. @@ -1677,9 +1789,9 @@ struct tx_bd_long_hi { * * This bit must be valid on the first BD of a packet. * - * Packet must be 64B or longer when this flag is set. It is not + * Packet must be 64B or longer when this flag is set. It is not * useful to use this bit with any form of TX offload such as - * CSO or LSO. The intent is that the packet from the host already + * CSO or LSO. The intent is that the packet from the host already * has a valid Ethernet CRC on the packet. */ #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) @@ -1708,9 +1820,9 @@ struct tx_bd_long_hi { */ #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) /* - * If set to 1, the device will treat this packet with LSO(Large + * If set to 1, the device will treat this packet with LSO(Large * Send Offload) processing for both normal or encapsulated - * packets, which is a form of TCP segmentation. When this bit + * packets, which is a form of TCP segmentation. When this bit * is 1, the hdr_size and mss fields must be valid. The driver * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum * flags since the controller will replace the appropriate @@ -1743,19 +1855,19 @@ struct tx_bd_long_hi { #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t hdr_size; /* * When LSO is '1', this field must contain the offset of the * TCP payload from the beginning of the packet in as - * 16b words. In case of encapsulated/tunneling packet, this field + * 16b words. In case of encapsulated/tunneling packet, this field * contains the offset of the inner TCP payload from beginning of the * packet as 16-bit words. * @@ -1832,7 +1944,7 @@ struct tx_bd_long_hi { #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) #define TX_BD_LONG_CFA_META_KEY_LAST \ TX_BD_LONG_CFA_META_KEY_VLAN_TAG -} __attribute__((packed)); +} __rte_packed; /* * This structure is used to inform the NIC of packet data that needs to be @@ -1862,7 +1974,7 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_FLAGS_SFT 6 /* * If set to 1, the packet ends with the data in the buffer - * pointed to by this descriptor. This flag must be + * pointed to by this descriptor. This flag must be * valid on every BD. */ #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40) @@ -1967,12 +2079,12 @@ struct tx_bd_long_inline { #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80) /* * If set to '1', then the RoCE ICRC will be appended to the - * packet. Packet must be a valid RoCE format packet. + * packet. Packet must be a valid RoCE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100) /* * If set to '1', then the FCoE CRC will be appended to the - * packet. Packet must be a valid FCoE format packet. + * packet. Packet must be a valid FCoE format packet. */ #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200) uint16_t unused2; @@ -2045,7 +2157,7 @@ struct tx_bd_long_inline { (UINT32_C(0x1) << 28) #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \ TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG -} __attribute__((packed)); +} __rte_packed; /* tx_bd_empty (size:128b/16B) */ struct tx_bd_empty { @@ -2055,7 +2167,7 @@ struct tx_bd_empty { #define TX_BD_EMPTY_TYPE_SFT 0 /* * Indicates that this BD is 1BB long and is an empty - * TX BD. Not valid for use by the driver. + * TX BD. Not valid for use by the driver. */ #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1) #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY @@ -2063,7 +2175,7 @@ struct tx_bd_empty { uint8_t unused_2; uint8_t unused_3[3]; uint8_t unused_4[8]; -} __attribute__((packed)); +} __rte_packed; /* rx_prod_pkt_bd (size:128b/16B) */ struct rx_prod_pkt_bd { @@ -2074,7 +2186,7 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_TYPE_SFT 0 /* * Indicates that this BD is 16B long and is an RX Producer - * (ie. empty) buffer descriptor. + * (i.e. empty) buffer descriptor. */ #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4) #define RX_PROD_PKT_BD_TYPE_LAST \ @@ -2083,7 +2195,7 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_FLAGS_SFT 6 /* * If set to 1, the packet will be placed at the address plus - * 2B. The 2 Bytes of padding will be written as zero. + * 2B. The 2 Bytes of padding will be written as zero. */ #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40) /* @@ -2093,9 +2205,9 @@ struct rx_prod_pkt_bd { #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) /* * This value is the number of additional buffers in the ring that - * describe the buffer space to be consumed for the this packet. + * describe the buffer space to be consumed for this packet. * If the value is zero, then the packet must fit within the - * space described by this BD. If this value is 1 or more, it + * space described by this BD. If this value is 1 or more, it * indicates how many additional "buffer" BDs are in the ring * immediately following this BD to be used for the same * network packet. @@ -2118,10 +2230,10 @@ struct rx_prod_pkt_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* rx_prod_bfr_bd (size:128b/16B) */ struct rx_prod_bfr_bd { @@ -2147,10 +2259,10 @@ struct rx_prod_bfr_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* rx_prod_agg_bd (size:128b/16B) */ struct rx_prod_agg_bd { @@ -2186,10 +2298,10 @@ struct rx_prod_agg_bd { uint32_t opaque; /* * This is the host physical address where data for the packet may - * by placed in host memory. + * be placed in host memory. */ uint64_t address; -} __attribute__((packed)); +} __rte_packed; /* cmpl_base (size:128b/16B) */ struct cmpl_base { @@ -2197,17 +2309,46 @@ struct cmpl_base { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f) #define CMPL_BASE_TYPE_SFT 0 /* * TX L2 completion: - * Completion of TX packet. Length = 16B + * Completion of TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0) + /* + * NO-OP completion: + * Completion of NO-OP. Length = 16B + */ + #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1) + /* + * TX L2 coalesced completion: + * Completion of coalesced TX packet. Length = 16B + */ + #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2) + /* + * TX L2 PTP completion: + * Completion of PTP TX packet. Length = 32B + */ + #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) + /* + * RX L2 TPA Start V2 Completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. + */ + #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd) + /* + * RX L2 V2 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in SR2 + * and later chips. + */ + #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf) /* * RX L2 completion: * Completion of and L2 RX packet. Length = 32B @@ -2216,7 +2357,7 @@ struct cmpl_base { /* * RX Aggregation Buffer completion : * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * TPA, HDS, or Jumbo packet completion. Length = 16B */ #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12) /* @@ -2237,6 +2378,24 @@ struct cmpl_base { * Length = 16B */ #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a) + /* + * VEE Flush Completion: + * This completion is inserted manually by + * the Primate and processed by the VEE hardware to ensure that + * all completions on a VEE function have been processed by the + * VEE hardware before FLR process is completed. + */ + #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c) + /* + * Mid Path Short Completion : + * Completion of a Mid Path Command. Length = 16B + */ + #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e) + /* + * Mid Path Long Completion : + * Completion of a Mid Path Command. Length = 32B + */ + #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f) /* * HWRM Command Completion: * Completion of an HWRM command. @@ -2265,8 +2424,8 @@ struct cmpl_base { uint32_t info2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint32_t info3_v; #define CMPL_BASE_V UINT32_C(0x1) @@ -2274,7 +2433,7 @@ struct cmpl_base { #define CMPL_BASE_INFO3_SFT 1 /* info4 is 32 b */ uint32_t info4; -} __attribute__((packed)); +} __rte_packed; /* tx_cmpl (size:128b/16B) */ struct tx_cmpl { @@ -2282,15 +2441,15 @@ struct tx_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define TX_CMPL_TYPE_MASK UINT32_C(0x3f) #define TX_CMPL_TYPE_SFT 0 /* * TX L2 completion: - * Completion of TX packet. Length = 16B + * Completion of TX packet. Length = 16B */ #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0) #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2 @@ -2298,14 +2457,14 @@ struct tx_cmpl { #define TX_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet completed * was transmitted using the push acceleration data provided - * by the driver. When this bit is '0', it indicates that the + * by the driver. When this bit is '0', it indicates that the * packet had not push acceleration data written or was executed * as a normal packet even though push data was provided. */ @@ -2314,66 +2473,362 @@ struct tx_cmpl { uint16_t unused_0; /* * This is a copy of the opaque field from the first TX BD of this - * transmitted packet. + * transmitted packet. Note that, if the packet was described by a short + * CSO or short CSO inline BD, then the 16-bit opaque field from the + * short CSO BD will appear in the bottom 16 bits of this field. */ uint32_t opaque; uint16_t errors_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define TX_CMPL_V UINT32_C(0x1) - #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define TX_CMPL_ERRORS_SFT 1 + #define TX_CMPL_V UINT32_C(0x1) + #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem * with the BDs for the packet. */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No error */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \ TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT /* * When this bit is '1', it indicates that the length of - * the packet was zero. No packet was transmitted. + * the packet was zero. No packet was transmitted. */ - #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) /* * When this bit is '1', it indicates that the packet * was longer than the programmed limit in TDI. No * packet was transmitted. */ - #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) /* * When this bit is '1', it indicates that one or more of the * BDs associated with this packet generated a PCI error. * This probably means the address was not valid. */ - #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) + #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) /* * When this bit is '1', it indicates that the packet was longer - * than indicated by the hint. No packet was transmitted. + * than indicated by the hint. No packet was transmitted. */ - #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) /* * When this bit is '1', it indicates that the packet was * dropped due to Poison TLP error on one or more of the * TLPs in the PXP completion. */ - #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such completions + * are PTP completions or other TX completions. + */ + #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) /* unused2 is 16 b */ uint16_t unused_1; /* unused3 is 32 b */ uint32_t unused_2; -} __attribute__((packed)); +} __rte_packed; + +/* tx_cmpl_coal (size:128b/16B) */ +struct tx_cmpl_coal { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_COAL_TYPE_SFT 0 + /* + * TX L2 coalesced completion: + * Completion of TX packet. Length = 16B + */ + #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2) + #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL + #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_COAL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push acceleration data provided + * by the driver. When this bit is '0', it indicates that the + * packet had not push acceleration data written or was executed + * as a normal packet even though push data was provided. + */ + #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80) + /* unused1 is 16 b */ + uint16_t unused_0; + /* + * This is a copy of the opaque field from the first TX BD of the packet + * which corresponds with the reported sq_cons_idx. Note that, with + * coalesced completions, completions are generated for only some of the + * packets. The driver will see the opaque field for only those packets. + * Note that, if the packet was described by a short CSO or short CSO + * inline BD, then the 16-bit opaque field from the short CSO BD will + * appear in the bottom 16 bits of this field. For TX rings with + * completion coalescing enabled (which would use the coalesced + * completion record), it is suggested that the driver populate the + * opaque field to indicate the specific TX ring with which the + * completion is associated, then utilize the opaque and sq_cons_idx + * fields in the coalesced completion record to determine the specific + * packets that are to be completed on that ring. + */ + uint32_t opaque; + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define TX_CMPL_COAL_V UINT32_C(0x1) + #define TX_CMPL_COAL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define TX_CMPL_COAL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem + * with the BDs for the packet. + */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) + #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of + * the packet was zero. No packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet + * was longer than the programmed limit in TDI. No + * packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the + * BDs associated with this packet generated a PCI error. + * This probably means the address was not valid. + */ + #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer + * than indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was + * dropped due to Poison TLP error on one or more of the + * TLPs in the PXP completion. + */ + #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \ + UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such + * completions are PTP completions or other TX completions. + */ + #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \ + UINT32_C(0x400) + /* unused2 is 16 b */ + uint16_t unused_1; + uint32_t sq_cons_idx; + /* + * This value is SQ index for the start of the packet following the + * last completed packet. + */ + #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff) + #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0 +} __rte_packed; + +/* tx_cmpl_ptp (size:128b/16B) */ +struct tx_cmpl_ptp { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_PTP_TYPE_SFT 0 + /* + * TX L2 PTP completion: + * Completion of TX packet. Length = 32B + */ + #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2) + #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP + #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_PTP_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed + * was transmitted using the push acceleration data provided + * by the driver. When this bit is '0', it indicates that the + * packet had not push acceleration data written or was executed + * as a normal packet even though push data was provided. + */ + #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80) + /* unused1 is 16 b */ + uint16_t unused_0; + /* + * This is a copy of the opaque field from the first TX BD of this + * transmitted packet. Note that, if the packet was described by a short + * CSO or short CSO inline BD, then the 16-bit opaque field from the + * short CSO BD will appear in the bottom 16 bits of this field. + */ + uint32_t opaque; + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define TX_CMPL_PTP_V UINT32_C(0x1) + #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_PTP_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem + * with the BDs for the packet. + */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \ + (UINT32_C(0x2) << 1) + #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of + * the packet was zero. No packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet + * was longer than the programmed limit in TDI. No + * packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the + * BDs associated with this packet generated a PCI error. + * This probably means the address was not valid. + */ + #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer + * than indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was + * dropped due to Poison TLP error on one or more of the + * TLPs in the PXP completion. + */ + #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the packet was dropped due + * to a transient internal error in TDC. The packet or LSO can be + * retried and may transmit successfully on a subsequent attempt. + */ + #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + /* + * When this bit is '1', it was not possible to collect a a timestamp + * for a PTP completion, in which case the timestamp_hi and + * timestamp_lo fields are invalid. When this bit is '0' for a PTP + * completion, the timestamp_hi and timestamp_lo fields are valid. + * RJRN will copy the value of this bit into the field of the same + * name in all TX completions, regardless of whether such + * completions are PTP completions or other TX completions. + */ + #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) + /* unused2 is 16 b */ + uint16_t unused_1; + /* + * This is timestamp value (lower 32bits) read from PM for the PTP + * timestamp enabled packet. + */ + uint32_t timestamp_lo; +} __rte_packed; + +/* tx_cmpl_ptp_hi (size:128b/16B) */ +struct tx_cmpl_ptp_hi { + /* + * This is timestamp value (lower 32bits) read from PM for the PTP + * timestamp enabled packet. + */ + uint16_t timestamp_hi[3]; + uint16_t reserved16; + uint64_t v2; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue.The even passes will write 1. + * The odd passes will write 0 + */ + #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) +} __rte_packed; /* rx_pkt_cmpl (size:128b/16B) */ struct rx_pkt_cmpl { @@ -2381,8 +2836,8 @@ struct rx_pkt_cmpl { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) @@ -2397,7 +2852,7 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) @@ -2498,9 +2953,9 @@ struct rx_pkt_cmpl { RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP /* * This is the length of the data for the packet stored in the - * buffer(s) identified by the opaque value. This includes - * the packet BD and any associated buffer BDs. This does not include - * the the length of any data places in aggregation BDs. + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -2511,8 +2966,8 @@ struct rx_pkt_cmpl { uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_PKT_CMPL_V1 UINT32_C(0x1) /* @@ -2527,7 +2982,7 @@ struct rx_pkt_cmpl { #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0) #define RX_PKT_CMPL_UNUSED1_SFT 6 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -2558,7 +3013,7 @@ struct rx_pkt_cmpl { uint8_t rss_hash_type; /* * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, + * where the inner payload starts. This value is valid for TCP, UDP, * FCoE, and RoCE packets. * * A value of zero indicates that header is 256B into the packet. @@ -2571,7 +3026,7 @@ struct rx_pkt_cmpl { * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __attribute__((packed)); +} __rte_packed; /* Last 16 bytes of rx_pkt_cmpl. */ /* rx_pkt_cmpl_hi (size:128b/16B) */ @@ -2604,7 +3059,7 @@ struct rx_pkt_cmpl_hi { /* This value indicates what format the metadata field is. */ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ + /* No metadata information. Value is zero. */ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* @@ -2623,7 +3078,7 @@ struct rx_pkt_cmpl_hi { * - VXLAN = VNI[23:0] -> VXLAN Network ID * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0 * - IPV4 = 0 (not populated) * - IPV6 = Flow Label[19:0] * - PPPoE = sessionID[15:0] @@ -2653,7 +3108,7 @@ struct rx_pkt_cmpl_hi { RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. * This value is only valid if itype indicates a packet * with an IP header. */ @@ -2697,8 +3152,8 @@ struct rx_pkt_cmpl_hi { uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define RX_PKT_CMPL_V2 \ UINT32_C(0x1) @@ -2708,7 +3163,7 @@ struct rx_pkt_cmpl_hi { /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \ @@ -2721,7 +3176,7 @@ struct rx_pkt_cmpl_hi { * Did Not Fit: * Packet did not fit into packet buffer provided. * For regular placement, this means the packet did not fit - * in the buffer provided. For HDS and jumbo placement, this + * in the buffer provided. For HDS and jumbo placement, this * means that the packet could not be placed into 7 physical * buffers or less. */ @@ -2774,7 +3229,7 @@ struct rx_pkt_cmpl_hi { UINT32_C(0x80) /* * This indicates that there was a CRC error on either an FCoE - * or RoCE packet. The itype indicates the packet type. + * or RoCE packet. The itype indicates the packet type. */ #define RX_PKT_CMPL_ERRORS_CRC_ERROR \ UINT32_C(0x100) @@ -2912,105 +3367,160 @@ struct rx_pkt_cmpl_hi { * This value holds the reordering sequence number for the packet. * If the reordering sequence is not valid, then this value is zero. * The reordering domain for the packet is in the bottom 8 to 10b of - * the rss_hash value. The bottom 20b of this value contain the + * the rss_hash value. The bottom 20b of this value contain the * ordering domain value for the packet. */ #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff) #define RX_PKT_CMPL_REORDER_SFT 0 -} __attribute__((packed)); +} __rte_packed; -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl (size:128b/16B) */ -struct rx_tpa_start_cmpl { +/* rx_pkt_v2_cmpl (size:128b/16B) */ +struct rx_pkt_v2_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ - #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_START_CMPL_TYPE_SFT 0 + #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_V2_CMPL_TYPE_SFT 0 /* - * RX L2 TPA Start Completion: - * Completion at the beginning of a TPA operation. - * Length = 32B + * RX L2 V2 completion: + * Completion of and L2 RX packet. Length = 32B + * This is the new version of the RX_L2 completion used in SR2 + * and later chips. */ - #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) - #define RX_TPA_START_CMPL_TYPE_LAST \ - RX_TPA_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_START_CMPL_FLAGS_SFT 6 - /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf) + #define RX_PKT_V2_CMPL_TYPE_LAST \ + RX_PKT_V2_CMPL_TYPE_RX_L2_V2 + #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_V2_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Normal: + * Packet was placed using normal algorithm. + */ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \ + (UINT32_C(0x0) << 7) /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Packet was placed using jumbo algorithm. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Truncation: + * Packet was placed using truncation algorithm. The + * placed (truncated) length is indicated in the payload_offset + * field. The original length is indicated in the len field. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \ + (UINT32_C(0x3) << 7) + #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. */ - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) - /* unused is 1 b */ - #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) + #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * Not Known: + * Indicates that the packet type was not known. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \ + (UINT32_C(0x0) << 12) + /* + * IP Packet: + * Indicates that the packet was an IP packet, but further + * classification was not possible. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \ + (UINT32_C(0x1) << 12) /* * TCP Packet: * Indicates that the packet was IP and TCP. + * This indicates that the payload_offset field is valid. */ - #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* - * This value indicates the amount of packet data written to the - * buffer the opaque field in this completion corresponds to. + * UDP Packet: + * Indicates that the packet was IP and UDP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \ + (UINT32_C(0x3) << 12) + /* + * FCoE Packet: + * Indicates that the packet was recognized as a FCoE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \ + (UINT32_C(0x4) << 12) + /* + * RoCE Packet: + * Indicates that the packet was recognized as a RoCE. + * This also indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \ + (UINT32_C(0x5) << 12) + /* + * ICMP Packet: + * Indicates that the packet was recognized as ICMP. + * This indicates that the payload_offset field is valid. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \ + (UINT32_C(0x7) << 12) + /* + * PtP packet wo/timestamp: + * Indicates that the packet was recognized as a PtP + * packet. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \ + (UINT32_C(0x8) << 12) + /* + * PtP packet w/timestamp: + * Indicates that the packet was recognized as a PtP + * packet and that a timestamp was taken for the packet. + */ + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \ + (UINT32_C(0x9) << 12) + #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + /* + * This is the length of the data for the packet stored in the + * buffer(s) identified by the opaque value. This includes + * the packet BD and any associated buffer BDs. This does not include + * the length of any data places in aggregation BDs. */ uint16_t len; /* @@ -3018,21 +3528,26 @@ struct rx_tpa_start_cmpl { * corresponds to. */ uint32_t opaque; + uint8_t agg_bufs_v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - uint8_t v1; + #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided for the packet in the RX ring. */ - #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 + #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e) + #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 2 b */ + #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0) + #define RX_PKT_V2_CMPL_UNUSED1_SFT 6 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -3061,431 +3576,484 @@ struct rx_tpa_start_cmpl { * corresponding to 4-tuples are only valid for TCP traffic. */ uint8_t rss_hash_type; - /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. - */ - uint16_t agg_id; - /* unused2 is 9 b */ - #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_UNUSED2_SFT 0 - /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. - */ - #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) - #define RX_TPA_START_CMPL_AGG_ID_SFT 9 + uint16_t metadata1_payload_offset; + /* + * This is data from the CFA as indicated by the meta_format field. + * If truncation placement is not used, this value indicates the offset + * in bytes from the beginning of the packet where the inner payload + * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If + * truncation placement is used, this value represents the placed + * (truncated) length of the packet. + */ + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff) + #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0 + /* This is data from the CFA as indicated by the meta_format field. */ + #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) /* * This value is the RSS hash value calculated for the packet - * based on the mode bits and key value in the VNIC. + * based on the mode bits and key value in the VNIC. When vee_cmpl_mode + * is set in VNIC context, this is the lower 32b of the host address + * from the first BD used to place the packet. */ uint32_t rss_hash; -} __attribute__((packed)); +} __rte_packed; -/* - * Last 16 bytes of rx_tpa_start_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_start_cmpl_hi { +/* Last 16 bytes of RX Packet V2 Completion Record */ +/* rx_pkt_v2_cmpl_hi (size:128b/16B) */ +struct rx_pkt_v2_cmpl_hi { uint32_t flags2; /* - * This indicates that the ip checksum was calculated for the - * inner packet and that the sum passed for all segments - * included in the aggregation. + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) /* - * This indicates that the TCP, UDP or ICMP checksum was - * calculated for the inner packet and that the sum passed - * for all segments included in the aggregation. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask */ - #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) /* - * This indicates that the ip checksum was calculated for the - * tunnel header and that the sum passed for all segments - * included in the aggregation. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). */ - #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) /* - * This indicates that the UDP checksum was - * calculated for the tunnel packet and that the sum passed for - * all segments included in the aggregation. + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \ + RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) - /* This value indicates what format the metadata field is. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata information. Value is zero. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ - (UINT32_C(0x0) << 4) + #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \ + UINT32_C(0x100) /* - * The metadata field contains the VLAN tag and TPID value. - * - metadata[11:0] contains the vlan VID value. - * - metadata[12] contains the vlan DE value. - * - metadata[15:13] contains the vlan PRI value. - * - metadata[31:16] contains the vlan TPID value. + * This indicates that the complete 1's complement checksum was + * calculated for the packet. */ - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ - (UINT32_C(0x1) << 4) - #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) /* - * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. */ - #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. + */ + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* * This is data from the CFA block as indicated by the meta_format * field. - */ - uint32_t metadata; - /* When meta_format=1, this value is the VLAN VID. */ - #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 - /* When meta_format=1, this value is the VLAN DE. */ - #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When meta_format=1, this value is the VLAN PRI. */ - #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 - /* When meta_format=1, this value is the VLAN TPID. */ - #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 - uint16_t v2; + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_V2 \ + UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1 /* - * This field identifies the CFA action rule that was used for this - * packet. + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - uint16_t cfa_code; + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * Did Not Fit: Packet did not fit into packet buffer provided. + * For regular placement, this means the packet did not fit in + * the buffer provided. For HDS and jumbo placement, this means + * that the packet could not be placed into 8 physical buffers + * (if fixed-size buffers are used), or that the packet could + * not be placed in the number of physical buffers configured + * for the VNIC (if variable-size buffers are used) */ - uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this - * value is zero. + * Not On Chip: All BDs needed for the packet were not on-chip + * when the packet arrived. For regular placement, this error is + * not valid. For HDS and jumbo placement, this means that not + * enough agg BDs were posted to place the packet. */ - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L2 header. + * Bad Format: + * BDs were not formatted correctly. */ - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L3 header. + * Flush: + * There was a bad_format error on the previous operation */ - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * This indicates that there was an error in the outer tunnel + * portion of the packet when this field is non-zero. */ - #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 -} __attribute__((packed)); - -/* - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_end_cmpl (size:128b/16B) */ -struct rx_tpa_end_cmpl { - uint16_t flags_type; + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \ + UINT32_C(0x70) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * No additional error occurred on the outer tunnel portion + * of the packet or the packet does not have a outer tunnel. */ - #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_END_CMPL_TYPE_SFT 0 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 4) /* - * RX L2 TPA End Completion: - * Completion at the end of a TPA operation. - * Length = 32B + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header. */ - #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_END_CMPL_TYPE_LAST \ - RX_TPA_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_END_CMPL_FLAGS_SFT 6 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \ + (UINT32_C(0x1) << 4) /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * Indicates that header length is out of range in the outer + * tunnel header. Valid for IPv4. */ - #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) - /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 4) /* - * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means - * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer - * will be filled before moving to the next aggregation - * buffer. + * Indicates that physical packet is shorter than that claimed + * by the outer tunnel l3 header length. Valid for IPv4, or + * IPv6 outer tunnel packets. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ - (UINT32_C(0x1) << 7) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 4) /* - * Header/Data Separation: - * Packet was placed using Header/Data separation algorithm. - * The separation location is indicated by the itype field. + * Indicates that the physical packet is shorter than that + * claimed by the outer tunnel UDP header length for a outer + * tunnel UDP packet that is not fragmented. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ - (UINT32_C(0x2) << 7) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 4) /* - * GRO/Jumbo: - * Packet will be placed using GRO/Jumbo where the first - * packet is filled with data. Subsequent packets will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Indicates that the IPv4 TTL or IPv6 hop limit check have + * failed (e.g. TTL = 0) in the outer tunnel header. Valid for + * IPv4, and IPv6. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ - (UINT32_C(0x5) << 7) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \ + (UINT32_C(0x5) << 4) /* - * GRO/Header-Data Separation: - * Packet will be placed using GRO/HDS where the header - * is in the first packet. - * Payload of each packet will be - * placed such that any one packet does not span two - * aggregation buffers unless it starts at the beginning of - * an aggregation buffer. + * Indicates that the IP checksum failed its check in the outer + * tunnel header. */ - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ - (UINT32_C(0x6) << 7) - #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* unused is 2 b */ - #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) - #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \ + (UINT32_C(0x6) << 4) /* - * This value indicates what the inner packet determined for the - * packet was. - * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates - * that the ip_cs field is valid and that the tcp_udp_cs - * field is valid and contains the TCP checksum. - * This also indicates that the payload_offset field is valid. + * Indicates that the L4 checksum failed its check in the outer + * tunnel header. */ - #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \ + (UINT32_C(0x7) << 4) + #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR /* - * This value is zero for TPA End completions. - * There is no data in the buffer that corresponds to the opaque - * value in this completion. + * This indicates that there was a CRC error on either an FCoE + * or RoCE packet. The itype indicates the packet type. */ - uint16_t len; + #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \ + UINT32_C(0x100) /* - * This is a copy of the opaque field from the RX BD this completion - * corresponds to. + * This indicates that there was an error in the tunnel portion + * of the packet when this field is non-zero. */ - uint32_t opaque; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \ + UINT32_C(0xe00) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * No additional error occurred on the tunnel portion + * of the packet or the packet does not have a tunnel. */ - uint8_t agg_bufs_v1; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 9) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. */ - #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \ + (UINT32_C(0x1) << 9) /* - * This value is the number of aggregation buffers that follow this - * entry in the completion ring that are a part of this aggregation - * packet. - * If the value is zero, then the packet is completely contained - * in the buffer space provided in the aggregation start completion. + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. */ - #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) - #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 - /* This value is the number of segments in the TPA operation. */ - uint8_t tpa_segs; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 9) /* - * This value indicates the offset in bytes from the beginning of the packet - * where the inner payload starts. This value is valid for TCP, UDP, - * FCoE, and RoCE packets. - * - * A value of zero indicates an offset of 256 bytes. + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel + * packet packets. */ - uint8_t payload_offset; - uint8_t agg_id; - /* unused2 is 1 b */ - #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \ + (UINT32_C(0x3) << 9) /* - * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion - * with the TPA end completion. + * Indicates that the physical packet is shorter than that claimed + * by the tunnel UDP header length for a tunnel UDP packet that is + * not fragmented. */ - #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) - #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \ + (UINT32_C(0x4) << 9) /* - * For non-GRO packets, this value is the - * timestamp delta between earliest and latest timestamp values for - * TPA packet. If packets were not time stamped, then delta will be - * zero. - * - * For GRO packets, this field is zero except for the following - * sub-fields. - * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp - * option is present in the packet. + * Indicates that the IPv4 TTL or IPv6 hop limit check have failed + * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6. */ - uint32_t tsdelta; -} __attribute__((packed)); - -/* - * Last 16 bytes of rx_tpa_end_cmpl. - * - * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. - */ -/* rx_tpa_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_end_cmpl_hi { - uint32_t tpa_dup_acks; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \ + (UINT32_C(0x5) << 9) /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. + * Indicates that the IP checksum failed its check in the tunnel + * header. */ - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \ + (UINT32_C(0x6) << 9) /* - * This value is the valid when TPA completion is active. It - * indicates the length of the longest segment of the TPA operation - * for LRO mode and the length of the first segment in GRO mode. - * - * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used - * to indicate MSS size to the stack. + * Indicates that the L4 checksum failed its check in the tunnel + * header. */ - uint16_t tpa_seg_len; - /* unused4 is 16 b */ - uint16_t unused3; - uint16_t errors_v2; + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \ + (UINT32_C(0x7) << 9) + #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This indicates that there was an error in the inner + * portion of the packet when this + * field is non-zero. */ - #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define RX_TPA_END_CMPL_ERRORS_SFT 1 + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \ + UINT32_C(0xf000) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12 /* - * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as - * invalid. + * No additional error occurred on the tunnel portion + * or the packet of the packet does not have a tunnel. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \ + (UINT32_C(0x0) << 12) /* - * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not - * BDs on chip but that there was adequate reservation. - * provided by the TPA block. + * Indicates that IP header version does not match + * expectation from L2 Ethertype for IPv4 and IPv6 or that + * option other than VFT was parsed on + * FCoE packet. */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ - (UINT32_C(0x2) << 1) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \ + (UINT32_C(0x1) << 12) /* - * This error occurs when TPA block was not configured to - * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. - * - * This error can also be generated when the number of - * segments is not programmed correctly in TPA and the - * 33 total aggregation buffers allowed for the TPA - * operation has been exceeded. + * indicates that header length is out of range. Valid for + * IPv4 and RoCE */ - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ - (UINT32_C(0x4) << 1) - #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR - /* unused5 is 16 b */ - uint16_t unused_4; + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \ + (UINT32_C(0x2) << 12) /* - * This is the opaque value that was completed for the TPA start - * completion that corresponds to this TPA end completion. + * indicates that the IPv4 TTL or IPv6 hop limit check + * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6 */ - uint32_t start_opaque; -} __attribute__((packed)); + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \ + (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that + * claimed by the l3 header length. Valid for IPv4, + * IPv6 packet or RoCE packets. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \ + (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is + * not fragmented. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \ + (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for + * TCP packets only. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \ + (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \ + (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header + * size that does not match data offset in TCP header. Valid + * for TCP. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \ + (UINT32_C(0x8) << 12) + /* + * Indicates that the IP checksum failed its check in the + * inner header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \ + (UINT32_C(0x9) << 12) + /* + * Indicates that the L4 checksum failed its check in the + * inner header. + */ + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \ + (UINT32_C(0xa) << 12) + #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \ + RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint16_t metadata0; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13 + /* + * The timestamp field contains the 32b timestamp for the packet from + * the MAC. + */ + uint32_t timestamp; +} __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_start_cmpl (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl { +/* rx_tpa_start_cmpl (size:128b/16B) */ +struct rx_tpa_start_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_START_CMPL_TYPE_MASK \ - UINT32_C(0x3f) - #define RX_TPA_V2_START_CMPL_TYPE_SFT 0 + #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_START_CMPL_TYPE_SFT 0 /* * RX L2 TPA Start Completion: * Completion at the beginning of a TPA operation. * Length = 32B */ - #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \ - UINT32_C(0x13) - #define RX_TPA_V2_START_CMPL_TYPE_LAST \ - RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START - #define RX_TPA_V2_START_CMPL_FLAGS_MASK \ - UINT32_C(0xffc0) - #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6 + #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) + #define RX_TPA_START_CMPL_TYPE_LAST \ + RX_TPA_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_START_CMPL_FLAGS_SFT 6 /* This bit will always be '0' for TPA start completions. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \ - UINT32_C(0x40) + #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \ - UINT32_C(0x380) - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) /* * GRO/Jumbo: @@ -3495,7 +4063,7 @@ struct rx_tpa_v2_start_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -3506,39 +4074,28 @@ struct rx_tpa_v2_start_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS /* This bit is '1' if the RSS field in this completion is valid. */ - #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \ - UINT32_C(0x400) - /* - * For devices that support timestamps, when this bit is cleared the - * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` - * field contains the 32b timestamp for - * the packet from the MAC. When this bit is set, the - * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` - * field contains the outer_l3_offset, inner_l2_offset, - * inner_l3_offset, and inner_l4_size. - */ - #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \ - UINT32_C(0x800) + #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \ - UINT32_C(0xf000) - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 /* * TCP Packet: * Indicates that the packet was IP and TCP. */ - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \ (UINT32_C(0x2) << 12) - #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \ - RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP + #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_CMPL_FLAGS_ITYPE_TCP /* * This value indicates the amount of packet data written to the * buffer the opaque field in this completion corresponds to. @@ -3551,19 +4108,19 @@ struct rx_tpa_v2_start_cmpl { uint32_t opaque; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) - #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 + #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1 /* - * This is the RSS hash type for the packet. The value is packed + * This is the RSS hash type for the packet. The value is packed * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. * * The value of tuple_extrac_op provides the information about @@ -3594,60 +4151,65 @@ struct rx_tpa_v2_start_cmpl { uint8_t rss_hash_type; /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ uint16_t agg_id; + /* unused2 is 9 b */ + #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_UNUSED2_SFT 0 + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) + #define RX_TPA_START_CMPL_AGG_ID_SFT 9 /* * This value is the RSS hash value calculated for the packet * based on the mode bits and key value in the VNIC. */ uint32_t rss_hash; -} __attribute__((packed)); +} __rte_packed; /* - * Last 16 bytes of rx_tpa_v2_start_cmpl. + * Last 16 bytes of rx_tpa_start_cmpl. * * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_start_cmpl_hi { +/* rx_tpa_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_cmpl_hi { uint32_t flags2; /* * This indicates that the ip checksum was calculated for the * inner packet and that the sum passed for all segments * included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \ - UINT32_C(0x1) + #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) /* * This indicates that the TCP, UDP or ICMP checksum was * calculated for the inner packet and that the sum passed * for all segments included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \ - UINT32_C(0x2) + #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) /* * This indicates that the ip checksum was calculated for the * tunnel header and that the sum passed for all segments * included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \ - UINT32_C(0x4) + #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) /* * This indicates that the UDP checksum was * calculated for the tunnel packet and that the sum passed for * all segments included in the aggregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \ - UINT32_C(0x8) + #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) /* This value indicates what format the metadata field is. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ - UINT32_C(0xf0) - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 - /* No metadata informtaion. Value is zero. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata information. Value is zero. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \ (UINT32_C(0x0) << 4) /* * The metadata field contains the VLAN tag and TPID value. @@ -3656,62 +4218,404 @@ struct rx_tpa_v2_start_cmpl_hi { * - metadata[15:13] contains the vlan PRI value. * - metadata[31:16] contains the vlan TPID value. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \ (UINT32_C(0x1) << 4) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN /* - * If ext_meta_format is equal to 1, the metadata field - * contains the lower 16b of the tunnel ID value, justified - * to LSB - * - VXLAN = VNI[23:0] -> VXLAN Network ID - * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. - * - NVGRE = TNI[23:0] -> Tenant Network ID - * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 - * - IPV4 = 0 (not populated) - * - IPV6 = Flow Label[19:0] - * - PPPoE = sessionID[15:0] - * - MPLs = Outer label[19:0] - * - UPAR = Selected[31:0] with bit mask + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ - (UINT32_C(0x2) << 4) + #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) /* - * if ext_meta_format is equal to 1, metadata field contains - * 16b metadata from the prepended header (chdr_data). + * This is data from the CFA block as indicated by the meta_format + * field. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ - (UINT32_C(0x3) << 4) - /* - * If ext_meta_format is equal to 1, the metadata field contains - * the outer_l3_offset, inner_l2_offset, inner_l3_offset and - * inner_l4_size. - * - metadata[8:0] contains the outer_l3_offset. - * - metadata[17:9] contains the inner_l2_offset. - * - metadata[26:18] contains the inner_l3_offset. - * - metadata[31:27] contains the inner_l4_size. + uint32_t metadata; + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 + uint16_t v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + /* + * This field identifies the CFA action rule that was used for this + * packet. + */ + uint16_t cfa_code; + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + /* + * This is the offset from the beginning of the packet in bytes for + * the outer L3 header. If there is no outer L3 header, then this + * value is zero. + */ + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L2 header. + */ + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L3 header. + */ + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte + * struct) + */ +/* rx_tpa_start_v2_cmpl (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_START_V2_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_START_V2_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA Start V2 Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B + * This is the new version of the RX_TPA_START completion used + * in SR2 and later chips. + */ + #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \ + UINT32_C(0xd) + #define RX_TPA_START_V2_CMPL_TYPE_LAST \ + RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 + #define RX_TPA_START_V2_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) + /* + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. It + * starts at the first 32B boundary after the end of the header for + * HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \ + UINT32_C(0x800) + /* + * This value indicates what the inner packet determined for the + * packet was. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12 + /* + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. If the VNIC is configured to not use an Rx BD for + * the TPA Start completion, then this is a copy of the opaque field + * from the first BD used to place the TPA Start packet. + */ + uint32_t opaque; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + uint8_t v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + uint16_t agg_id; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0 + #define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000) + #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12 + /* When meta_format != 0, this value is the VLAN TPID_SEL. */ + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000) + #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12 + /* When meta_format != 0, this value is the VLAN valid. */ + #define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000) + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + * When vee_cmpl_mode is set in VNIC context, this is the lower + * 32b of the host address from the first BD used to place the packet. + */ + uint32_t rss_hash; +} __rte_packed; + +/* + * Last 16 bytes of RX L2 TPA Start V2 Completion Record + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. + */ +/* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */ +struct rx_tpa_start_v2_cmpl_hi { + uint32_t flags2; + /* This indicates that the aggregation was done using GRO rules. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \ + UINT32_C(0x4) + /* + * When this bit is '0', the cs_ok field has the following definition:- + * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. - + * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum + * in the delivered packet, counted from the outer-most header group to + * the inner-most header group, stopping at the first error. When this + * bit is '1', the cs_ok field has the following definition: - + * hdr_cnt[2:0] = The number of header groups that were parsed by the + * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit + * will be '1' if all the parsed header groups with an IP checksum are + * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed + * header groups with an L4 checksum are valid. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* There is no metadata information. Values are zero. */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], + * de, vid[11:0]} The metadata2 field contains the table scope + * and action record pointer. - metadata2[25:0] contains the + * action record pointer. - metadata2[31:26] contains the table + * scope. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \ + (UINT32_C(0x1) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the Tunnel ID + * value, justified to LSB. i + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0 + * - IPv4 = 0 (not populated) + * - IPv6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]} + * The metadata2 field contains the 32b metadata from the prepended + * header (chdr_data). + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * The {metadata1, metadata0} fields contain the vtag + * information: + * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]} + * The metadata2 field contains the outer_l3_offset, + * inner_l2_offset, inner_l3_offset, and inner_l4_size. + * - metadata2[8:0] contains the outer_l3_offset. + * - metadata2[17:9] contains the inner_l2_offset. + * - metadata2[26:18] contains the inner_l3_offset. + * - metadata2[31:27] contains the inner_l4_size. + */ + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ (UINT32_C(0x4) << 4) - #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \ - RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET /* * This field indicates the IP type for the inner-most IP header. - * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + * This value is only valid if itype indicates a packet + * with an IP header. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ + #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \ UINT32_C(0x100) /* * This indicates that the complete 1's complement checksum was - * calculated for the packet. + * calculated for the packet in the affregation. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ UINT32_C(0x200) /* - * The combination of this value and meta_format indicated what - * format the metadata field is. + * This field indicates the status of IP and L4 CS calculations done + * by the chip. The format of this field is indicated by the + * cs_all_ok_mode bit. + * CS status for TPA packets is always valid. This means that "all_ok" + * status will always be set. The ok count status will be set + * appropriately for the packet header, such that all existing CS + * values are ok. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \ - UINT32_C(0xc00) - #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10 + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \ + UINT32_C(0xfc00) + #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10 /* * This value is the complete 1's complement checksum calculated from * the start of the outer L3 header to the end of the packet (not @@ -3720,158 +4624,156 @@ struct rx_tpa_v2_start_cmpl_hi { * the complete checksum is calculated for the first packet in the * aggregation only. */ - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ UINT32_C(0xffff0000) - #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 /* * This is data from the CFA block as indicated by the meta_format * field. - */ - uint32_t metadata; - /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */ - #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) - #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0 - /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */ - #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000) - /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */ - #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) - #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13 - /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */ - #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) - #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16 + * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped + * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0], + * act_rec_ptr[25:0]} + * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0] + * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0] + * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0] + * When vee_cmpl_mode is set in VNIC context, this is the upper 32b + * of the host address from the first BD used to place the packet. + */ + uint32_t metadata2; uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_START_CMPL_V2 \ + #define RX_TPA_START_V2_CMPL_V2 \ UINT32_C(0x1) - #define RX_TPA_V2_START_CMPL_ERRORS_MASK \ + #define RX_TPA_START_V2_CMPL_ERRORS_MASK \ UINT32_C(0xfffe) - #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1 + #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with - * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * the BDs for the packetThe packet should be treated as * invalid. */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \ UINT32_C(0xe) - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No buffer error */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Packet did not fit into packet buffer provided. This means + * that the TPA Start packet was too big to be placed into the + * per-packet maximum number of physical buffers configured for + * the VNIC, or that it was too big to be placed into the + * per-aggregation maximum number of physical buffers configured + * for the VNIC. This error only occurs when the VNIC is + * configured for variable size receive buffers. + */ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ (UINT32_C(0x3) << 1) /* * Flush: * There was a bad_format error on the previous operation */ - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ (UINT32_C(0x5) << 1) - #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH + #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * This field identifies the CFA action rule that was used for this - * packet. + * This is data from the CFA block as indicated by the meta_format + * field. */ - uint16_t cfa_code; - /* - * For devices that support timestamps this field is overridden - * with the timestamp value. When `flags.timestamp_fld_format` is - * cleared, this field contains the 32b timestamp for the packet from the - * MAC. + uint16_t metadata0; + /* When meta_format != 0, this value is the VLAN VID. */ + #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0 + /* When meta_format != 0, this value is the VLAN DE. */ + #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000) + /* When meta_format != 0, this value is the VLAN PRI. */ + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13 + /* + * This field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. * - * When `flags.timestamp_fld_format` is set, this field contains the - * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size - * as defined below. - */ - uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; - /* - * This is the offset from the beginning of the packet in bytes for - * the outer L3 header. If there is no outer L3 header, then this - * value is zero. - */ - #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) - #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0 - /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L2 header. - */ - #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) - #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9 - /* - * This is the offset from the beginning of the packet in bytes for - * the inner most L3 header. - */ - #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) - #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18 - /* - * This is the size in bytes of the inner most L4 header. - * This can be subtracted from the payload_offset to determine - * the start of the inner most L4 header. + * hdr_offsets[8:0] contains the outer_l3_offset. + * hdr_offsets[17:9] contains the inner_l2_offset. + * hdr_offsets[26:18] contains the inner_l3_offset. + * hdr_offsets[31:27] contains the inner_l4_size. */ - #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) - #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 -} __attribute__((packed)); + uint32_t hdr_offsets; +} __rte_packed; /* * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_end_cmpl (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl { +/* rx_tpa_end_cmpl (size:128b/16B) */ +struct rx_tpa_end_cmpl { uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_V2_END_CMPL_TYPE_SFT 0 + #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_END_CMPL_TYPE_SFT 0 /* * RX L2 TPA End Completion: * Completion at the end of a TPA operation. * Length = 32B */ - #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) - #define RX_TPA_V2_END_CMPL_TYPE_LAST \ - RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END - #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 + #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + #define RX_TPA_END_CMPL_TYPE_LAST \ + RX_TPA_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_END_CMPL_FLAGS_SFT 6 /* * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in + * error of some type. Type of error is indicated in * error_flags. */ - #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) /* This field indicates how the packet was placed in the buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* * Jumbo: - * TPA Packet was placed using jumbo algorithm. This means + * TPA Packet was placed using jumbo algorithm. This means * that the first buffer will be filled with data before - * moving to aggregation buffers. Each aggregation buffer + * moving to aggregation buffers. Each aggregation buffer * will be filled before moving to the next aggregation * buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \ (UINT32_C(0x1) << 7) /* * Header/Data Separation: * Packet was placed using Header/Data separation algorithm. * The separation location is indicated by the itype field. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \ (UINT32_C(0x2) << 7) + /* + * IOC/Jumbo: + * Packet will be placed using In-Order Completion/Jumbo where + * the first packet of the aggregation is placed using Jumbo + * Placement. Subsequent packets will be placed such that each + * packet starts at the beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \ + (UINT32_C(0x4) << 7) /* * GRO/Jumbo: * Packet will be placed using GRO/Jumbo where the first @@ -3880,7 +4782,7 @@ struct rx_tpa_v2_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ (UINT32_C(0x5) << 7) /* * GRO/Header-Data Separation: @@ -3891,24 +4793,42 @@ struct rx_tpa_v2_end_cmpl { * aggregation buffers unless it starts at the beginning of * an aggregation buffer. */ - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ (UINT32_C(0x6) << 7) - #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \ - RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS - /* unused is 2 b */ - #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) - #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10 + /* + * IOC/Header-Data Separation: + * Packet will be placed using In-Order Completion/HDS where + * the header is in the first packet buffer. Payload of each + * packet will be placed such that each packet starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \ + (UINT32_C(0x7) << 7) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS + /* unused is 1 b */ + #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400) + /* + * This bit is '1' if metadata has been added to the end of the + * packet in host memory. Metadata starts at the first 32B boundary + * after the end of the packet for regular and jumbo placement. + * It starts at the first 32B boundary after the end of the header + * for HDS placement. The length of the metadata is indicated in the + * metadata itself. + */ + #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800) /* * This value indicates what the inner packet determined for the * packet was. * - 2 TCP Packet - * Indicates that the packet was IP and TCP. This indicates + * Indicates that the packet was IP and TCP. This indicates * that the ip_cs field is valid and that the tcp_udp_cs * field is valid and contains the TCP checksum. * This also indicates that the payload_offset field is valid. */ - #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) - #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 /* * This value is zero for TPA End completions. * There is no data in the buffer that corresponds to the opaque @@ -3920,21 +4840,47 @@ struct rx_tpa_v2_end_cmpl { * corresponds to. */ uint32_t opaque; - uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) + uint8_t agg_bufs_v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this aggregation + * packet. + * If the value is zero, then the packet is completely contained + * in the buffer space provided in the aggregation start completion. + */ + #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) + #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 /* This value is the number of segments in the TPA operation. */ uint8_t tpa_segs; + /* + * This value indicates the offset in bytes from the beginning of the packet + * where the inner payload starts. This value is valid for TCP, UDP, + * FCoE, and RoCE packets. + * + * A value of zero indicates an offset of 256 bytes. + */ + uint8_t payload_offset; + uint8_t agg_id; + /* unused2 is 1 b */ + #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1) /* * This is the aggregation ID that the completion is associated - * with. Use this number to correlate the TPA start completion + * with. Use this number to correlate the TPA start completion * with the TPA end completion. */ - uint16_t agg_id; + #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) + #define RX_TPA_END_CMPL_AGG_ID_SFT 1 /* * For non-GRO packets, this value is the * timestamp delta between earliest and latest timestamp values for @@ -3944,446 +4890,1085 @@ struct rx_tpa_v2_end_cmpl { * For GRO packets, this field is zero except for the following * sub-fields. * - tsdelta[31] - * Timestamp present indication. When '0', no Timestamp - * option is in the packet. When '1', then a Timestamp + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp * option is present in the packet. */ uint32_t tsdelta; -} __attribute__((packed)); +} __rte_packed; /* - * Last 16 bytes of rx_tpa_v2_end_cmpl. + * Last 16 bytes of rx_tpa_end_cmpl. * * This TPA completion structure is used on devices where the - * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + * `hwrm_vnic_qcaps.max_aggs_supported` value is 0. */ -/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ -struct rx_tpa_v2_end_cmpl_hi { - /* - * This value is the number of duplicate ACKs that have been - * received as part of the TPA operation. - */ - uint16_t tpa_dup_acks; +/* rx_tpa_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_end_cmpl_hi { + uint32_t tpa_dup_acks; /* * This value is the number of duplicate ACKs that have been * received as part of the TPA operation. */ - #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) - #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0 - /* - * This value indicated the offset in bytes from the beginning of - * the packet where the inner payload starts. This value is valid - * for TCP, UDP, FCoE and RoCE packets - */ - uint8_t payload_offset; - /* - * The value is the total number of aggregation buffers that were - * used in the TPA operation. All TPA aggregation buffer completions - * precede the TPA End completion. If the value is zero, then the - * aggregation is completely contained in the buffer space provided - * in the aggregation start completion. - * Note that the field is simply provided as a cross check. - */ - uint8_t tpa_agg_bufs; + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 /* - * This value is the valid when TPA completion is active. It + * This value is the valid when TPA completion is active. It * indicates the length of the longest segment of the TPA operation * for LRO mode and the length of the first segment in GRO mode. * * This value may be used by GRO software to re-construct the original - * packet stream from the TPA packet. This is the length of all - * but the last segment for GRO. In LRO mode this value may be used + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used * to indicate MSS size to the stack. */ uint16_t tpa_seg_len; - uint16_t unused_1; + /* unused4 is 16 b */ + uint16_t unused3; uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) - #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ - UINT32_C(0xfffe) - #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1 + #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define RX_TPA_END_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with * the BDs for the packet that was found after part of the - * packet was already placed. The packet should be treated as + * packet was already placed. The packet should be treated as * invalid. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ - UINT32_C(0xe) - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 - /* No buffer error */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ - (UINT32_C(0x0) << 1) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* * This error occurs when there is a fatal HW problem in - * the chip only. It indicates that there were not + * the chip only. It indicates that there were not * BDs on chip but that there was adequate reservation. * provided by the TPA block. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ (UINT32_C(0x2) << 1) - /* - * Bad Format: - * BDs were not formatted correctly. - */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ - (UINT32_C(0x3) << 1) /* * This error occurs when TPA block was not configured to * reserve adequate BDs for TPA operations on this RX - * ring. All data for the TPA operation was not placed. + * ring. All data for the TPA operation was not placed. * * This error can also be generated when the number of * segments is not programmed correctly in TPA and the * 33 total aggregation buffers allowed for the TPA * operation has been exceeded. */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ (UINT32_C(0x4) << 1) - /* - * Flush: - * There was a bad_format error on the previous operation - */ - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ - (UINT32_C(0x5) << 1) - #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ - RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH - uint16_t unused_2; + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR + /* unused5 is 16 b */ + uint16_t unused_4; /* * This is the opaque value that was completed for the TPA start * completion that corresponds to this TPA end completion. */ uint32_t start_opaque; -} __attribute__((packed)); +} __rte_packed; /* * This TPA completion structure is used on devices where the * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. */ -/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ -struct rx_tpa_v2_abuf_cmpl { - uint16_t type; +/* rx_tpa_v2_start_cmpl (size:128b/16B) */ +struct rx_tpa_v2_start_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ - #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_TYPE_MASK \ + UINT32_C(0x3f) + #define RX_TPA_V2_START_CMPL_TYPE_SFT 0 /* - * RX TPA Aggregation Buffer completion : - * Completion of an L2 aggregation buffer in support of - * TPA packet completion. Length = 16B + * RX L2 TPA Start Completion: + * Completion at the beginning of a TPA operation. + * Length = 32B */ - #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) - #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ - RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG + #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \ + UINT32_C(0x13) + #define RX_TPA_V2_START_CMPL_TYPE_LAST \ + RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START + #define RX_TPA_V2_START_CMPL_FLAGS_MASK \ + UINT32_C(0xffc0) + #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6 + /* This bit will always be '0' for TPA start completions. */ + #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \ + UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \ + UINT32_C(0x380) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not - * include the length of any - * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to - * hdr_offset register during HDS placement mode. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - uint16_t len; + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * This is a copy of the opaque field from the RX BD this aggregation - * buffer corresponds to. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - uint32_t opaque; - uint16_t v; + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) /* - * This is the aggregation ID that the completion is associated with. Use - * this number to correlate the TPA agg completion with the TPA start - * completion and the TPA end completion. - */ - uint16_t agg_id; - uint32_t unused_1; -} __attribute__((packed)); - -/* rx_abuf_cmpl (size:128b/16B) */ -struct rx_abuf_cmpl { - uint16_t type; + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \ + UINT32_C(0x400) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * For devices that support timestamps, when this bit is cleared the + * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` + * field contains the 32b timestamp for + * the packet from the MAC. When this bit is set, the + * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset` + * field contains the outer_l3_offset, inner_l2_offset, + * inner_l3_offset, and inner_l4_size. */ - #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) - #define RX_ABUF_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \ + UINT32_C(0x800) /* - * RX Aggregation Buffer completion : - * Completion of an L2 aggregation buffer in support of - * TPA, HDS, or Jumbo packet completion. Length = 16B + * This value indicates what the inner packet determined for the + * packet was. */ - #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) - #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \ + UINT32_C(0xf000) + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12 /* - * This is the length of the data for the packet stored in this - * aggregation buffer identified by the opaque value. This does not - * include the length of any - * data placed in other aggregation BDs or in the packet or buffer - * BDs. This length does not include any space added due to - * hdr_offset register during HDS placement mode. + * TCP Packet: + * Indicates that the packet was IP and TCP. + */ + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \ + (UINT32_C(0x2) << 12) + #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \ + RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP + /* + * This value indicates the amount of packet data written to the + * buffer the opaque field in this completion corresponds to. */ uint16_t len; /* - * This is a copy of the opaque field from the RX BD this aggregation - * buffer corresponds to. + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. */ uint32_t opaque; - uint32_t v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define RX_ABUF_CMPL_V UINT32_C(0x1) - /* unused3 is 32 b */ - uint32_t unused_2; -} __attribute__((packed)); + uint8_t v1; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1 + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + * + * The value of tuple_extrac_op provides the information about + * what fields the hash was computed on. + * * 0: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of inner + * IP and TCP or UDP headers. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 1: The RSS hash was computed over source IP address and destination + * IP address of inner IP header. Note: For non-tunneled packets, + * the packet headers are considered inner packet headers for the RSS + * hash computation purpose. + * * 2: The RSS hash was computed over source IP address, + * destination IP address, source port, and destination port of + * IP and TCP or UDP headers of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * * 3: The RSS hash was computed over source IP address and + * destination IP address of IP header of outer tunnel headers. + * Note: For non-tunneled packets, this value is not applicable. + * + * Note that 4-tuples values listed above are applicable + * for layer 4 protocols supported and enabled for RSS in the hardware, + * HWRM firmware, and drivers. For example, if RSS hash is supported and + * enabled for TCP traffic only, then the values of tuple_extract_op + * corresponding to 4-tuples are only valid for TCP traffic. + */ + uint8_t rss_hash_type; + /* + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. + */ + uint16_t agg_id; + /* + * This value is the RSS hash value calculated for the packet + * based on the mode bits and key value in the VNIC. + */ + uint32_t rss_hash; +} __rte_packed; -/* eject_cmpl (size:128b/16B) */ -struct eject_cmpl { - uint16_t type; +/* + * Last 16 bytes of rx_tpa_v2_start_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */ +struct rx_tpa_v2_start_cmpl_hi { + uint32_t flags2; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This indicates that the ip checksum was calculated for the + * inner packet and that the sum passed for all segments + * included in the aggregation. */ - #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define EJECT_CMPL_TYPE_SFT 0 + #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \ + UINT32_C(0x1) /* - * Statistics Ejection Completion: - * Completion of statistics data ejection buffer. - * Length = 16B + * This indicates that the TCP, UDP or ICMP checksum was + * calculated for the inner packet and that the sum passed + * for all segments included in the aggregation. */ - #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) - #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT - #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0) - #define EJECT_CMPL_FLAGS_SFT 6 + #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \ + UINT32_C(0x2) /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * This indicates that the ip checksum was calculated for the + * tunnel header and that the sum passed for all segments + * included in the aggregation. */ - #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) + #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \ + UINT32_C(0x4) /* - * This is the length of the statistics data stored in this - * buffer. + * This indicates that the UDP checksum was + * calculated for the tunnel packet and that the sum passed for + * all segments included in the aggregation. */ - uint16_t len; + #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \ + UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \ + UINT32_C(0xf0) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata informtaion. Value is zero. */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \ + (UINT32_C(0x0) << 4) /* - * This is a copy of the opaque field from the RX BD this ejection - * buffer corresponds to. + * The metadata field contains the VLAN tag and TPID value. + * - metadata[11:0] contains the vlan VID value. + * - metadata[12] contains the vlan DE value. + * - metadata[15:13] contains the vlan PRI value. + * - metadata[31:16] contains the vlan TPID value. */ - uint32_t opaque; - uint16_t v; + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \ + (UINT32_C(0x1) << 4) + /* + * If ext_meta_format is equal to 1, the metadata field + * contains the lower 16b of the tunnel ID value, justified + * to LSB + * - VXLAN = VNI[23:0] -> VXLAN Network ID + * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier. + * - NVGRE = TNI[23:0] -> Tenant Network ID + * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0 + * - IPV4 = 0 (not populated) + * - IPV6 = Flow Label[19:0] + * - PPPoE = sessionID[15:0] + * - MPLs = Outer label[19:0] + * - UPAR = Selected[31:0] with bit mask + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \ + (UINT32_C(0x2) << 4) + /* + * if ext_meta_format is equal to 1, metadata field contains + * 16b metadata from the prepended header (chdr_data). + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \ + (UINT32_C(0x3) << 4) + /* + * If ext_meta_format is equal to 1, the metadata field contains + * the outer_l3_offset, inner_l2_offset, inner_l3_offset and + * inner_l4_size. + * - metadata[8:0] contains the outer_l3_offset. + * - metadata[17:9] contains the inner_l2_offset. + * - metadata[26:18] contains the inner_l3_offset. + * - metadata[31:27] contains the inner_l4_size. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \ + (UINT32_C(0x4) << 4) + #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \ + RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET + /* + * This field indicates the IP type for the inner-most IP header. + * A value of '0' indicates IPv4. A value of '1' indicates IPv6. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \ + UINT32_C(0x100) + /* + * This indicates that the complete 1's complement checksum was + * calculated for the packet. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \ + UINT32_C(0x200) + /* + * The combination of this value and meta_format indicated what + * format the metadata field is. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \ + UINT32_C(0xc00) + #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10 + /* + * This value is the complete 1's complement checksum calculated from + * the start of the outer L3 header to the end of the packet (not + * including the ethernet crc). It is valid when the + * 'complete_checksum_calc' flag is set. For TPA Start completions, + * the complete checksum is calculated for the first packet in the + * aggregation only. + */ + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \ + UINT32_C(0xffff0000) + #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16 + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + uint32_t metadata; + /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */ + #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0 + /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */ + #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */ + #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13 + /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */ + #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16 + uint16_t errors_v2; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define EJECT_CMPL_V UINT32_C(0x1) - #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) - #define EJECT_CMPL_ERRORS_SFT 1 + #define RX_TPA_V2_START_CMPL_V2 \ + UINT32_C(0x1) + #define RX_TPA_V2_START_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1 /* * This error indicates that there was some sort of problem with - * the BDs for statistics ejection. The statistics ejection should - * be treated as invalid + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1 /* No buffer error */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ (UINT32_C(0x0) << 1) - /* - * Did Not Fit: - * Statistics did not fit into aggregation buffer provided. - */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ - (UINT32_C(0x1) << 1) /* * Bad Format: * BDs were not formatted correctly. */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ (UINT32_C(0x3) << 1) /* * Flush: * There was a bad_format error on the previous operation */ - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ (UINT32_C(0x5) << 1) - #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \ - EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH - /* reserved16 is 16 b */ - uint16_t reserved16; - /* unused3 is 32 b */ - uint32_t unused_2; -} __attribute__((packed)); - -/* hwrm_cmpl (size:128b/16B) */ -struct hwrm_cmpl { - uint16_t type; + #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field identifies the CFA action rule that was used for this + * packet. */ - #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_CMPL_TYPE_SFT 0 + uint16_t cfa_code; /* - * HWRM Command Completion: - * Completion of an HWRM command. + * For devices that support timestamps this field is overridden + * with the timestamp value. When `flags.timestamp_fld_format` is + * cleared, this field contains the 32b timestamp for the packet from the + * MAC. + * + * When `flags.timestamp_fld_format` is set, this field contains the + * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size + * as defined below. */ - #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) - #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE - /* This is the sequence_id of the HWRM command that has completed. */ - uint16_t sequence_id; - /* unused2 is 32 b */ - uint32_t unused_1; - uint32_t v; + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * This is the offset from the beginning of the packet in bytes for + * the outer L3 header. If there is no outer L3 header, then this + * value is zero. */ - #define HWRM_CMPL_V UINT32_C(0x1) - /* unused4 is 32 b */ - uint32_t unused_3; -} __attribute__((packed)); + #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L2 header. + */ + #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9 + /* + * This is the offset from the beginning of the packet in bytes for + * the inner most L3 header. + */ + #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18 + /* + * This is the size in bytes of the inner most L4 header. + * This can be subtracted from the payload_offset to determine + * the start of the inner most L4 header. + */ + #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27 +} __rte_packed; -/* hwrm_fwd_req_cmpl (size:128b/16B) */ -struct hwrm_fwd_req_cmpl { +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_end_cmpl (size:128b/16B) */ +struct rx_tpa_v2_end_cmpl { + uint16_t flags_type; /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ - uint16_t req_len_type; + #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_V2_END_CMPL_TYPE_SFT 0 /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * RX L2 TPA End Completion: + * Completion at the end of a TPA operation. + * Length = 32B */ - #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 - /* Forwarded HWRM Request */ - #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) - #define HWRM_FWD_REQ_CMPL_TYPE_LAST \ - HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ - /* Length of forwarded request in bytes. */ - #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) - #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 + #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + #define RX_TPA_V2_END_CMPL_TYPE_LAST \ + RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END + #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6 /* - * Source ID of this request. - * Typically used in forwarding requests and responses. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. */ - uint16_t source_id; - /* unused1 is 32 b */ - uint32_t unused0; - /* Address of forwarded request. */ - uint32_t req_buf_addr_v[2]; + #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7 /* - * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * Jumbo: + * TPA Packet was placed using jumbo algorithm. This means + * that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer + * will be filled before moving to the next aggregation + * buffer. */ - #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) - /* Address of forwarded request. */ - #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) - #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 -} __attribute__((packed)); - -/* hwrm_fwd_resp_cmpl (size:128b/16B) */ -struct hwrm_fwd_resp_cmpl { - uint16_t type; + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \ + (UINT32_C(0x1) << 7) /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * Header/Data Separation: + * Packet was placed using Header/Data separation algorithm. + * The separation location is indicated by the itype field. */ - #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 - /* Forwarded HWRM Response */ - #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) - #define HWRM_FWD_RESP_CMPL_TYPE_LAST \ - HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \ + (UINT32_C(0x2) << 7) /* - * Source ID of this response. - * Typically used in forwarding requests and responses. - * 0x0 - 0xFFF8 - Used for function ids - * 0xFFF8 - 0xFFFE - Reserved for internal processors - * 0xFFFF - HWRM + * GRO/Jumbo: + * Packet will be placed using GRO/Jumbo where the first + * packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. */ - uint16_t source_id; - /* Length of forwarded response in bytes. */ - uint16_t resp_len; - /* unused2 is 16 b */ - uint16_t unused_1; - /* Address of forwarded request. */ - uint32_t resp_buf_addr_v[2]; + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \ + (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: + * Packet will be placed using GRO/HDS where the header + * is in the first packet. + * Payload of each packet will be + * placed such that any one packet does not span two + * aggregation buffers unless it starts at the beginning of + * an aggregation buffer. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \ + (UINT32_C(0x6) << 7) + #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \ + RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* unused is 2 b */ + #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00) + #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10 + /* + * This value indicates what the inner packet determined for the + * packet was. + * - 2 TCP Packet + * Indicates that the packet was IP and TCP. This indicates + * that the ip_cs field is valid and that the tcp_udp_cs + * field is valid and contains the TCP checksum. + * This also indicates that the payload_offset field is valid. + */ + #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12 + /* + * This value is zero for TPA End completions. + * There is no data in the buffer that corresponds to the opaque + * value in this completion. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint32_t opaque; + uint8_t v1; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ - #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) - /* Address of forwarded request. */ - #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) - #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 -} __attribute__((packed)); - -/* hwrm_async_event_cmpl (size:128b/16B) */ -struct hwrm_async_event_cmpl { - uint16_t type; + #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1) + /* This value is the number of segments in the TPA operation. */ + uint8_t tpa_segs; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This is the aggregation ID that the completion is associated + * with. Use this number to correlate the TPA start completion + * with the TPA end completion. */ - #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) - #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 - /* HWRM Asynchronous Event Information */ - #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) - #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \ - HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT - /* Identifiers of events. */ - uint16_t event_id; - /* Link status changed */ - #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \ + uint16_t agg_id; + /* + * For non-GRO packets, this value is the + * timestamp delta between earliest and latest timestamp values for + * TPA packet. If packets were not time stamped, then delta will be + * zero. + * + * For GRO packets, this field is zero except for the following + * sub-fields. + * - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp + * option is in the packet. When '1', then a Timestamp + * option is present in the packet. + */ + uint32_t tsdelta; +} __rte_packed; + +/* + * Last 16 bytes of rx_tpa_v2_end_cmpl. + * + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */ +struct rx_tpa_v2_end_cmpl_hi { + /* + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. + */ + uint16_t tpa_dup_acks; + /* + * This value is the number of duplicate ACKs that have been + * received as part of the TPA operation. + */ + #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0 + /* + * This value indicated the offset in bytes from the beginning of + * the packet where the inner payload starts. This value is valid + * for TCP, UDP, FCoE and RoCE packets + */ + uint8_t payload_offset; + /* + * The value is the total number of aggregation buffers that were + * used in the TPA operation. All TPA aggregation buffer completions + * precede the TPA End completion. If the value is zero, then the + * aggregation is completely contained in the buffer space provided + * in the aggregation start completion. + * Note that the field is simply provided as a cross check. + */ + uint8_t tpa_agg_bufs; + /* + * This value is the valid when TPA completion is active. It + * indicates the length of the longest segment of the TPA operation + * for LRO mode and the length of the first segment in GRO mode. + * + * This value may be used by GRO software to re-construct the original + * packet stream from the TPA packet. This is the length of all + * but the last segment for GRO. In LRO mode this value may be used + * to indicate MSS size to the stack. + */ + uint16_t tpa_seg_len; + uint16_t unused_1; + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1) + #define RX_TPA_V2_END_CMPL_ERRORS_MASK \ + UINT32_C(0xfffe) + #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for the packet that was found after part of the + * packet was already placed. The packet should be treated as + * invalid. + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * This error occurs when there is a fatal HW problem in + * the chip only. It indicates that there were not + * BDs on chip but that there was adequate reservation. + * provided by the TPA block. + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \ + (UINT32_C(0x2) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * This error occurs when TPA block was not configured to + * reserve adequate BDs for TPA operations on this RX + * ring. All data for the TPA operation was not placed. + * + * This error can also be generated when the number of + * segments is not programmed correctly in TPA and the + * 33 total aggregation buffers allowed for the TPA + * operation has been exceeded. + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \ + (UINT32_C(0x4) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \ + RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH + uint16_t unused_2; + /* + * This is the opaque value that was completed for the TPA start + * completion that corresponds to this TPA end completion. + */ + uint32_t start_opaque; +} __rte_packed; + +/* + * This TPA completion structure is used on devices where the + * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0. + */ +/* rx_tpa_v2_abuf_cmpl (size:128b/16B) */ +struct rx_tpa_v2_abuf_cmpl { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0 + /* + * RX TPA Aggregation Buffer completion : + * Completion of an L2 aggregation buffer in support of + * TPA packet completion. Length = 16B + */ + #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16) + #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \ + RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any + * data placed in other aggregation BDs or in the packet or buffer + * BDs. This length does not include any space added due to + * hdr_offset register during HDS placement mode. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t opaque; + uint16_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1) + /* + * This is the aggregation ID that the completion is associated with. Use + * this number to correlate the TPA agg completion with the TPA start + * completion and the TPA end completion. + */ + uint16_t agg_id; + uint32_t unused_1; +} __rte_packed; + +/* rx_abuf_cmpl (size:128b/16B) */ +struct rx_abuf_cmpl { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_ABUF_CMPL_TYPE_SFT 0 + /* + * RX Aggregation Buffer completion : + * Completion of an L2 aggregation buffer in support of + * TPA, HDS, or Jumbo packet completion. Length = 16B + */ + #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) + #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any + * data placed in other aggregation BDs or in the packet or buffer + * BDs. This length does not include any space added due to + * hdr_offset register during HDS placement mode. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t opaque; + uint32_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define RX_ABUF_CMPL_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_2; +} __rte_packed; + +/* VEE FLUSH Completion Record (16 bytes) */ +/* vee_flush (size:128b/16B) */ +struct vee_flush { + uint32_t downstream_path_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f) + #define VEE_FLUSH_TYPE_SFT 0 + /* + * VEE Flush Completion: + * This completion is inserted manually by the Primate and processed + * by the VEE hardware to ensure that all completions on a VEE + * function have been processed by the VEE hardware before FLR + * process is completed. + */ + #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c) + #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH + /* downstream_path is 1 b */ + #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40) + /* This completion is associated with VEE Transmit */ + #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6) + /* This completion is associated with VEE Receive */ + #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6) + #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX + /* + * This is an opaque value that is passed through the completion + * to the VEE handler SW and is used to indicate what VEE VQ or + * function has completed FLR processing. + */ + uint32_t opaque; + uint32_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes will + * write 1. The odd passes will write 0. + */ + #define VEE_FLUSH_V UINT32_C(0x1) + /* unused3 is 32 b */ + uint32_t unused_3; +} __rte_packed; + +/* eject_cmpl (size:128b/16B) */ +struct eject_cmpl { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define EJECT_CMPL_TYPE_SFT 0 + /* + * Statistics Ejection Completion: + * Completion of statistics data ejection buffer. + * Length = 16B + */ + #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) + #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT + #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define EJECT_CMPL_FLAGS_SFT 6 + /* + * When this bit is '1', it indicates a packet that has an + * error of some type. Type of error is indicated in + * error_flags. + */ + #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* + * This is the length of the statistics data stored in this + * buffer. + */ + uint16_t len; + /* + * This is a copy of the opaque field from the RX BD this ejection + * buffer corresponds to. + */ + uint32_t opaque; + uint16_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define EJECT_CMPL_V UINT32_C(0x1) + #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define EJECT_CMPL_ERRORS_SFT 1 + /* + * This error indicates that there was some sort of problem with + * the BDs for statistics ejection. The statistics ejection should + * be treated as invalid + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \ + (UINT32_C(0x0) << 1) + /* + * Did Not Fit: + * Statistics did not fit into aggregation buffer provided. + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \ + (UINT32_C(0x1) << 1) + /* + * Bad Format: + * BDs were not formatted correctly. + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \ + (UINT32_C(0x3) << 1) + /* + * Flush: + * There was a bad_format error on the previous operation + */ + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \ + (UINT32_C(0x5) << 1) + #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \ + EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH + /* reserved16 is 16 b */ + uint16_t reserved16; + /* unused3 is 32 b */ + uint32_t unused_2; +} __rte_packed; + +/* hwrm_cmpl (size:128b/16B) */ +struct hwrm_cmpl { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_CMPL_TYPE_SFT 0 + /* + * HWRM Command Completion: + * Completion of an HWRM command. + */ + #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) + #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE + /* This is the sequence_id of the HWRM command that has completed. */ + uint16_t sequence_id; + /* unused2 is 32 b */ + uint32_t unused_1; + uint32_t v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_CMPL_V UINT32_C(0x1) + /* unused4 is 32 b */ + uint32_t unused_3; +} __rte_packed; + +/* hwrm_fwd_req_cmpl (size:128b/16B) */ +struct hwrm_fwd_req_cmpl { + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + uint16_t req_len_type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Request */ + #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) + #define HWRM_FWD_REQ_CMPL_TYPE_LAST \ + HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ + /* Length of forwarded request in bytes. */ + #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) + #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 + /* + * Source ID of this request. + * Typically used in forwarding requests and responses. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t source_id; + /* unused1 is 32 b */ + uint32_t unused0; + /* Address of forwarded request. */ + uint32_t req_buf_addr_v[2]; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 +} __rte_packed; + +/* hwrm_fwd_resp_cmpl (size:128b/16B) */ +struct hwrm_fwd_resp_cmpl { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Response */ + #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) + #define HWRM_FWD_RESP_CMPL_TYPE_LAST \ + HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP + /* + * Source ID of this response. + * Typically used in forwarding requests and responses. + * 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors + * 0xFFFF - HWRM + */ + uint16_t source_id; + /* Length of forwarded response in bytes. */ + uint16_t resp_len; + /* unused2 is 16 b */ + uint16_t unused_1; + /* Address of forwarded request. */ + uint32_t resp_buf_addr_v[2]; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 +} __rte_packed; + +/* hwrm_async_event_cmpl (size:128b/16B) */ +struct hwrm_async_event_cmpl { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \ UINT32_C(0x0) /* Link MTU changed */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \ @@ -4490,12 +6075,37 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ UINT32_C(0x3c) - /* TFLIB unique default VNIC Configuration Change */ + /* + * Deprecated. + * TFLIB unique default VNIC Configuration Change + */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ UINT32_C(0x3d) - /* TFLIB unique link status changed */ + /* + * Deprecated. + * TFLIB unique link status changed + */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ UINT32_C(0x3e) + /* + * An event signifying completion for HWRM_FW_STATE_QUIESCE + * (completion, timeout, or error) + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + /* + * An event signifying a HWRM command is in progress and its + * response will be deferred. This event is used on crypto controllers + * only. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + /* + * An event signifying that a PFC WatchDog configuration + * has changed on any port / cos. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -4513,8 +6123,8 @@ struct hwrm_async_event_cmpl { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) /* opaque is 7 b */ @@ -4526,7 +6136,7 @@ struct hwrm_async_event_cmpl { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_status_change { @@ -4534,8 +6144,8 @@ struct hwrm_async_event_cmpl_link_status_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \ @@ -4558,8 +6168,8 @@ struct hwrm_async_event_cmpl_link_status_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \ UINT32_C(0x1) @@ -4605,7 +6215,7 @@ struct hwrm_async_event_cmpl_link_status_change { UINT32_C(0xff00000) #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \ 20 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_mtu_change { @@ -4613,8 +6223,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \ @@ -4637,8 +6247,8 @@ struct hwrm_async_event_cmpl_link_mtu_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -4655,7 +6265,7 @@ struct hwrm_async_event_cmpl_link_mtu_change { #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \ UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_speed_change { @@ -4663,8 +6273,8 @@ struct hwrm_async_event_cmpl_link_speed_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \ @@ -4687,8 +6297,8 @@ struct hwrm_async_event_cmpl_link_speed_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \ UINT32_C(0x1) @@ -4750,7 +6360,7 @@ struct hwrm_async_event_cmpl_link_speed_change { UINT32_C(0xffff0000) #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */ struct hwrm_async_event_cmpl_dcb_config_change { @@ -4758,8 +6368,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \ @@ -4791,8 +6401,8 @@ struct hwrm_async_event_cmpl_dcb_config_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \ UINT32_C(0x1) @@ -4831,7 +6441,7 @@ struct hwrm_async_event_cmpl_dcb_config_change { (UINT32_C(0xff) << 24) #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \ HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ struct hwrm_async_event_cmpl_port_conn_not_allowed { @@ -4839,8 +6449,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \ @@ -4864,8 +6474,8 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \ UINT32_C(0x1) @@ -4907,7 +6517,7 @@ struct hwrm_async_event_cmpl_port_conn_not_allowed { (UINT32_C(0x3) << 16) #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \ HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { @@ -4915,8 +6525,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \ @@ -4940,8 +6550,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \ UINT32_C(0x1) @@ -4960,7 +6570,7 @@ struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_link_speed_cfg_change { @@ -4968,8 +6578,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \ @@ -4993,8 +6603,8 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \ UINT32_C(0x1) @@ -5029,7 +6639,7 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \ UINT32_C(0x20000) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_port_phy_cfg_change { @@ -5037,8 +6647,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \ @@ -5062,8 +6672,8 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \ UINT32_C(0x1) @@ -5105,7 +6715,7 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \ UINT32_C(0x40000) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ struct hwrm_async_event_cmpl_reset_notify { @@ -5113,8 +6723,8 @@ struct hwrm_async_event_cmpl_reset_notify { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \ @@ -5137,8 +6747,8 @@ struct hwrm_async_event_cmpl_reset_notify { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5205,7 +6815,7 @@ struct hwrm_async_event_cmpl_reset_notify { UINT32_C(0xffff0000) #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \ 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ struct hwrm_async_event_cmpl_error_recovery { @@ -5213,8 +6823,8 @@ struct hwrm_async_event_cmpl_error_recovery { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \ @@ -5242,8 +6852,8 @@ struct hwrm_async_event_cmpl_error_recovery { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5274,7 +6884,7 @@ struct hwrm_async_event_cmpl_error_recovery { */ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \ UINT32_C(0x2) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */ struct hwrm_async_event_cmpl_func_drvr_unload { @@ -5282,8 +6892,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \ @@ -5306,8 +6916,8 @@ struct hwrm_async_event_cmpl_func_drvr_unload { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5325,7 +6935,7 @@ struct hwrm_async_event_cmpl_func_drvr_unload { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */ struct hwrm_async_event_cmpl_func_drvr_load { @@ -5333,8 +6943,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \ @@ -5357,8 +6967,8 @@ struct hwrm_async_event_cmpl_func_drvr_load { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5374,7 +6984,7 @@ struct hwrm_async_event_cmpl_func_drvr_load { #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \ UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { @@ -5382,8 +6992,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \ @@ -5407,8 +7017,8 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \ UINT32_C(0x1) @@ -5427,7 +7037,7 @@ struct hwrm_async_event_cmpl_func_flr_proc_cmplt { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ struct hwrm_async_event_cmpl_pf_drvr_unload { @@ -5435,8 +7045,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \ @@ -5459,8 +7069,8 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5480,7 +7090,7 @@ struct hwrm_async_event_cmpl_pf_drvr_unload { #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \ UINT32_C(0x70000) #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */ struct hwrm_async_event_cmpl_pf_drvr_load { @@ -5488,8 +7098,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \ @@ -5512,8 +7122,8 @@ struct hwrm_async_event_cmpl_pf_drvr_load { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5533,7 +7143,7 @@ struct hwrm_async_event_cmpl_pf_drvr_load { #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \ UINT32_C(0x70000) #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */ struct hwrm_async_event_cmpl_vf_flr { @@ -5541,8 +7151,8 @@ struct hwrm_async_event_cmpl_vf_flr { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \ @@ -5564,8 +7174,8 @@ struct hwrm_async_event_cmpl_vf_flr { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5585,7 +7195,7 @@ struct hwrm_async_event_cmpl_vf_flr { #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \ UINT32_C(0xff0000) #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */ struct hwrm_async_event_cmpl_vf_mac_addr_change { @@ -5593,8 +7203,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \ @@ -5617,8 +7227,8 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \ UINT32_C(0x1) @@ -5637,7 +7247,7 @@ struct hwrm_async_event_cmpl_vf_mac_addr_change { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { @@ -5645,8 +7255,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \ @@ -5670,8 +7280,8 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \ UINT32_C(0x1) @@ -5693,7 +7303,7 @@ struct hwrm_async_event_cmpl_pf_vf_comm_status_change { */ #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \ UINT32_C(0x1) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_vf_cfg_change { @@ -5701,8 +7311,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \ @@ -5725,8 +7335,8 @@ struct hwrm_async_event_cmpl_vf_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5778,7 +7388,7 @@ struct hwrm_async_event_cmpl_vf_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \ UINT32_C(0x10) -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */ struct hwrm_async_event_cmpl_llfc_pfc_change { @@ -5786,8 +7396,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \ @@ -5814,8 +7424,8 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -5857,7 +7467,7 @@ struct hwrm_async_event_cmpl_llfc_pfc_change { UINT32_C(0x1fffe0) #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \ 5 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ struct hwrm_async_event_cmpl_default_vnic_change { @@ -5865,8 +7475,8 @@ struct hwrm_async_event_cmpl_default_vnic_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \ @@ -5885,7 +7495,7 @@ struct hwrm_async_event_cmpl_default_vnic_change { 6 /* Identifiers of events. */ uint16_t event_id; - /* Notification of a default vnic allocaiton or free */ + /* Notification of a default vnic allocation or free */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \ UINT32_C(0x35) #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \ @@ -5895,8 +7505,8 @@ struct hwrm_async_event_cmpl_default_vnic_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \ UINT32_C(0x1) @@ -5939,7 +7549,7 @@ struct hwrm_async_event_cmpl_default_vnic_change { UINT32_C(0x3fffc00) #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \ 10 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ struct hwrm_async_event_cmpl_hw_flow_aged { @@ -5947,8 +7557,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \ @@ -5971,8 +7581,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6006,7 +7616,7 @@ struct hwrm_async_event_cmpl_hw_flow_aged { (UINT32_C(0x1) << 31) #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_cache_flush_req { @@ -6014,8 +7624,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \ @@ -6039,8 +7649,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \ UINT32_C(0x1) @@ -6054,7 +7664,7 @@ struct hwrm_async_event_cmpl_eem_cache_flush_req { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_cache_flush_done { @@ -6062,8 +7672,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \ @@ -6090,8 +7700,8 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \ UINT32_C(0x1) @@ -6110,7 +7720,7 @@ struct hwrm_async_event_cmpl_eem_cache_flush_done { UINT32_C(0xffff) #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \ 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */ struct hwrm_async_event_cmpl_tcp_flag_action_change { @@ -6118,8 +7728,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \ @@ -6143,8 +7753,8 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \ UINT32_C(0x1) @@ -6158,7 +7768,7 @@ struct hwrm_async_event_cmpl_tcp_flag_action_change { uint16_t timestamp_hi; /* Event specific data */ uint32_t event_data1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_flow_active { @@ -6166,8 +7776,8 @@ struct hwrm_async_event_cmpl_eem_flow_active { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \ @@ -6209,8 +7819,8 @@ struct hwrm_async_event_cmpl_eem_flow_active { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6258,7 +7868,7 @@ struct hwrm_async_event_cmpl_eem_flow_active { (UINT32_C(0x1) << 31) #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */ struct hwrm_async_event_cmpl_eem_cfg_change { @@ -6266,8 +7876,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \ @@ -6290,8 +7900,8 @@ struct hwrm_async_event_cmpl_eem_cfg_change { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6315,7 +7925,256 @@ struct hwrm_async_event_cmpl_eem_cfg_change { */ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \ UINT32_C(0x2) -} __attribute__((packed)); +} __rte_packed; + +/* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */ +struct hwrm_async_event_cmpl_quiesce_done { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* An event signifying completion of HWRM_FW_STATE_QUIESCE */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE + /* Event specific data */ + uint32_t event_data2; + /* Status of HWRM_FW_STATE_QUIESCE completion */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \ + 0 + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * completed successfully. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \ + UINT32_C(0x0) + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed + * out. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \ + UINT32_C(0x1) + /* + * The quiesce operation started by HWRM_FW_STATE_QUIESCE + * encountered an error. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \ + UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ + HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + /* opaque is 8 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \ + 8 + /* + * Additional information about internal hardware state related to + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may + * inspect idle_state_flags to determine whether a retry is warranted. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \ + 16 + /* + * Failure to quiesce is caused by host not updating the NQ consumer + * index. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \ + UINT32_C(0x10000) + /* Flag 1 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \ + UINT32_C(0x20000) + /* Flag 2 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \ + UINT32_C(0x40000) + /* Flag 3 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \ + UINT32_C(0x80000) + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ +struct hwrm_async_event_cmpl_deferred_response { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * An event signifying a HWRM command is in progress and its + * response will be deferred + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE + /* Event specific data */ + uint32_t event_data2; + /* + * The PF's mailbox is clear to issue another command. + * A command with this seq_id is still in progress + * and will return a regular HWRM completion when done. + * 'event_data1' field, if non-zero, contains the estimated + * execution time for the command. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Estimated remaining time of command execution in ms (if not zero) */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PFC watchdog configuration change for given port/cos */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * 1 in bit position X indicates PFC watchdog should + * be on for COSX + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \ + 0 + /* 1 means PFC WD for COS0 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \ + UINT32_C(0x1) + /* 1 means PFC WD for COS1 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \ + UINT32_C(0x2) + /* 1 means PFC WD for COS2 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \ + UINT32_C(0x4) + /* 1 means PFC WD for COS3 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \ + UINT32_C(0x8) + /* 1 means PFC WD for COS4 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \ + UINT32_C(0x10) + /* 1 means PFC WD for COS5 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \ + UINT32_C(0x20) + /* 1 means PFC WD for COS6 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \ + UINT32_C(0x40) + /* 1 means PFC WD for COS7 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \ + UINT32_C(0x80) + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff00) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 8 +} __rte_packed; /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { @@ -6323,8 +8182,8 @@ struct hwrm_async_event_cmpl_fw_trace_msg { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \ @@ -6363,8 +8222,8 @@ struct hwrm_async_event_cmpl_fw_trace_msg { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6422,7 +8281,7 @@ struct hwrm_async_event_cmpl_fw_trace_msg { #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \ UINT32_C(0xff000000) #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24 -} __attribute__((packed)); +} __rte_packed; /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ struct hwrm_async_event_cmpl_hwrm_error { @@ -6430,8 +8289,8 @@ struct hwrm_async_event_cmpl_hwrm_error { /* * This field indicates the exact type of the completion. * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B * records. */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \ @@ -6469,8 +8328,8 @@ struct hwrm_async_event_cmpl_hwrm_error { uint8_t opaque_v; /* * This value is written by the NIC such that it will be different - * for each pass through the completion queue. The even passes - * will write 1. The odd passes will write 0. + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) /* opaque is 7 b */ @@ -6485,7 +8344,7 @@ struct hwrm_async_event_cmpl_hwrm_error { /* Time stamp for error event */ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \ UINT32_C(0x1) -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_func_reset * @@ -6568,7 +8427,7 @@ struct hwrm_func_reset_input { #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \ HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_reset_output (size:128b/16B) */ struct hwrm_func_reset_output { @@ -6589,7 +8448,7 @@ struct hwrm_func_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_func_getfid * @@ -6640,7 +8499,7 @@ struct hwrm_func_getfid_input { */ uint16_t pci_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_getfid_output (size:128b/16B) */ struct hwrm_func_getfid_output { @@ -6666,7 +8525,7 @@ struct hwrm_func_getfid_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_vf_alloc * @@ -6716,7 +8575,7 @@ struct hwrm_func_vf_alloc_input { uint16_t first_vf_id; /* The number of virtual functions requested. */ uint16_t num_vfs; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_alloc_output (size:128b/16B) */ struct hwrm_func_vf_alloc_output { @@ -6739,7 +8598,7 @@ struct hwrm_func_vf_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_func_vf_free * @@ -6792,7 +8651,7 @@ struct hwrm_func_vf_free_input { * 0xFFFF - Cleanup all children of this PF. */ uint16_t num_vfs; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_free_output (size:128b/16B) */ struct hwrm_func_vf_free_output { @@ -6813,7 +8672,7 @@ struct hwrm_func_vf_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_func_vf_cfg * @@ -7039,6 +8898,16 @@ struct hwrm_func_vf_cfg_input { */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ UINT32_C(0x80) + /* + * If this bit is set to 1, the VF driver is requesting FW to enable + * PPP TX PUSH feature on all the TX rings specified in the + * num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the VF. This flag is ignored if + * the num_tx_rings field is not specified or the VF doesn't support + * PPP tx push feature. + */ + #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x100) /* The number of RSS/COS contexts requested for the VF. */ uint16_t num_rsscos_ctxs; /* The number of completion rings requested for the VF. */ @@ -7056,7 +8925,7 @@ struct hwrm_func_vf_cfg_input { /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ struct hwrm_func_vf_cfg_output { @@ -7077,7 +8946,7 @@ struct hwrm_func_vf_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_func_qcaps * @@ -7118,12 +8987,14 @@ struct hwrm_func_qcaps_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_func_qcaps_output (size:640b/80B) */ +/* hwrm_func_qcaps_output (size:704b/88B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7335,6 +9206,48 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \ UINT32_C(0x2000000) + /* + * If the query is for a VF, then this flag (always set to 0) shall + * be ignored. If this query is for a PF and this flag is set to 1, + * host, when registered for the default vnic change async event, + * receives async notification whenever a default vnic state is + * changed for any of child or adopted VFs. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ + UINT32_C(0x4000000) + /* If set to 1, then the vlan acceleration for TX is disabled. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \ + UINT32_C(0x8000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_COREDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \ + UINT32_C(0x10000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_CRASHDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \ + UINT32_C(0x20000000) + /* + * If the query is for a VF, then this flag should be ignored. + * If the query is for a PF and this flag is set to 1, then + * the PF has the capability to support retrieval of + * rx_port_stats_ext_pfc_wd statistics (supported by the PFC + * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command. + * If this flag is set to 1, only that (supported) command should + * be used for retrieval of PFC related statistics (rather than + * hwrm_port_qstats_ext command, which could previously be used). + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ + UINT32_C(0x40000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_QCAPS command + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \ + UINT32_C(0x80000000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -7445,7 +9358,58 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0; + uint8_t unused_0[2]; + uint32_t flags_ext; + /* + * If 1, the device can be configured to set the ECN bits in the + * IP header of received packets if the receive queue length + * exceeds a given threshold. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \ + UINT32_C(0x1) + /* + * If 1, the device can report the number of received packets + * that it marked as having experienced congestion. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ + UINT32_C(0x2) + /* + * If 1, the device can report extended hw statistics (including + * additional tpa statistics). + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \ + UINT32_C(0x4) + /* + * If set to 1, then the core firmware has support to enable/ + * disable hot reset support for interface dynamically through + * HWRM_FUNC_CFG. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x8) + /* If 1, the proxy mode is supported on this function */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \ + UINT32_C(0x10) + /* + * If 1, the tx rings source interface override feature is supported + * on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \ + UINT32_C(0x20) + /* + * If 1, the device supports scheduler queues. SQs can be managed + * using RING_SQ_ALLOC/CFG/FREE commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SQ_SUPPORTED \ + UINT32_C(0x40) + /* + * If set to 1, then this function supports the TX push mode that + * uses ping-pong buffers from the push pages. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \ + UINT32_C(0x80) + /* The maximum number of SQs supported by this device. */ + uint8_t max_sqs; + uint8_t unused_1[2]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7454,7 +9418,7 @@ struct hwrm_func_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_func_qcfg * @@ -7495,12 +9459,14 @@ struct hwrm_func_qcfg_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID + * to be used by a trusted VF to query its parent PF. */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_func_qcfg_output (size:704b/88B) */ +/* hwrm_func_qcfg_output (size:768b/96B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7604,6 +9570,22 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ UINT32_C(0x100) + /* + * If set to 1, then the firmware and all currently registered driver + * instances support hot reset. The hot reset support will be updated + * dynamically based on the driver interface advertisement. + * If set to 0, then the adapter is not currently able to initiate + * hot reset. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \ + UINT32_C(0x200) + /* + * If set to 1, then the PPP tx push mode is enabled for all the + * reserved TX rings of this function. If set to 0, then PPP tx push + * mode is disabled for all the reserved TX rings of this function. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \ + UINT32_C(0x400) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -7905,7 +9887,22 @@ struct hwrm_func_qcfg_output { * after receiving the RESET Notify event. */ uint32_t reset_addr_poll; - uint8_t unused_2[3]; + /* + * This field specifies legacy L2 doorbell size in KBytes. Drivers should use + * this value to find out the doorbell page offset from the BAR. + */ + uint16_t legacy_l2_db_size_kb; + uint16_t svif_info; + /* + * This field specifies the source virtual interface of the function being + * queried. Drivers can use this to program svif field in the L2 context + * table + */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 + /* This field specifies whether svif is valid or not */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000) + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7914,14 +9911,14 @@ struct hwrm_func_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_func_cfg * *****************/ -/* hwrm_func_cfg_input (size:704b/88B) */ +/* hwrm_func_cfg_input (size:768b/96B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -8141,6 +10138,27 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \ UINT32_C(0x2000000) + /* + * If this bit is set to 0, then the interface does not support hot + * reset capability which it advertised with the hot_reset_support + * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this + * flag to 0, adapter cannot do the hot reset. In this state, if the + * firmware receives a hot reset request, firmware must fail the + * request. If this bit is set to 1, then interface is renabling the + * hot reset capability. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \ + UINT32_C(0x4000000) + /* + * If this bit is set to 1, the PF driver is requesting FW + * to enable PPP TX PUSH feature on all the TX rings specified in + * the num_tx_rings field. By default, the PPP TX push feature is + * disabled for all the TX rings of the function. This flag is + * ignored if num_tx_rings field is not specified or the function + * doesn't support PPP tx push feature. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \ + UINT32_C(0x8000000) uint32_t enables; /* * This bit must be '1' for the mtu field to be @@ -8280,6 +10298,18 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \ UINT32_C(0x400000) + /* + * This bit must be '1' for the hot_reset_if_en_dis field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \ + UINT32_C(0x800000) + /* + * This bit must be '1' for the sq_id field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_SQ_ID \ + UINT32_C(0x1000000) /* * The maximum transmission unit of the function. * The HWRM should make sure that the mtu of @@ -8544,7 +10574,10 @@ struct hwrm_func_cfg_input { * be reserved for this function on the RX side. */ uint16_t num_mcast_filters; -} __attribute__((packed)); + /* Used by a PF driver to associate a SQ with a VF. */ + uint16_t sq_id; + uint8_t unused_0[6]; +} __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ struct hwrm_func_cfg_output { @@ -8565,7 +10598,7 @@ struct hwrm_func_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_func_qstats * @@ -8606,10 +10639,29 @@ struct hwrm_func_qstats_input { * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * A privileged PF can query for other function's statistics. */ uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[5]; +} __rte_packed; /* hwrm_func_qstats_output (size:1408b/176B) */ struct hwrm_func_qstats_output { @@ -8691,15 +10743,15 @@ struct hwrm_func_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*********************** - * hwrm_func_clr_stats * - ***********************/ +/************************ + * hwrm_func_qstats_ext * + ************************/ -/* hwrm_func_clr_stats_input (size:192b/24B) */ -struct hwrm_func_clr_stats_input { +/* hwrm_func_qstats_ext_input (size:256b/32B) */ +struct hwrm_func_qstats_ext_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -8729,16 +10781,50 @@ struct hwrm_func_clr_stats_input { */ uint64_t resp_addr; /* - * Function ID of the function. + * Function ID of the function that is being queried. * 0xFF... (All Fs) if the query is for the requesting * function. + * A privileged PF can query for other function's statistics. */ uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* This flags indicates the type of statistics request. */ + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * flags should be set to 1 when request is for only RoCE statistics. + * This will be honored only if the caller_fid is a privileged PF. + * In all other cases FID and caller_fid should be the same. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + /* + * flags should be set to 2 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[1]; + uint32_t enables; + /* + * This bit must be '1' for the sq_id and traffic_class fields to be + * configured. + */ + #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SQ_ID UINT32_C(0x1) + /* Specifies the SQ for which to gather statistics */ + uint16_t sq_id; + /* + * Specifies the traffic class for which to gather statistics. Valid + * values are 0 through (max_configurable_queues - 1), where + * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG + */ + uint16_t traffic_class; + uint8_t unused_1[4]; +} __rte_packed; -/* hwrm_func_clr_stats_output (size:128b/16B) */ -struct hwrm_func_clr_stats_output { +/* hwrm_func_qstats_ext_output (size:1472b/184B) */ +struct hwrm_func_qstats_ext_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -8747,6 +10833,48 @@ struct hwrm_func_clr_stats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of discarded packets on received path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -8756,15 +10884,80 @@ struct hwrm_func_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************** - * hwrm_func_vf_resc_free * - **************************/ +/*********************** + * hwrm_func_clr_stats * + ***********************/ -/* hwrm_func_vf_resc_free_input (size:192b/24B) */ -struct hwrm_func_vf_resc_free_input { +/* hwrm_func_clr_stats_input (size:192b/24B) */ +struct hwrm_func_clr_stats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function. + * 0xFF... (All Fs) if the query is for the requesting + * function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_clr_stats_output (size:128b/16B) */ +struct hwrm_func_clr_stats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_func_vf_resc_free * + **************************/ + + +/* hwrm_func_vf_resc_free_input (size:192b/24B) */ +struct hwrm_func_vf_resc_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -8799,7 +10992,7 @@ struct hwrm_func_vf_resc_free_input { */ uint16_t vf_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_resc_free_output (size:128b/16B) */ struct hwrm_func_vf_resc_free_output { @@ -8820,7 +11013,7 @@ struct hwrm_func_vf_resc_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_drv_rgtr * @@ -8928,12 +11121,11 @@ struct hwrm_func_drv_rgtr_input { UINT32_C(0x20) /* * When this bit is 1, the function is indicating the support of the - * Master capability. The Firmware will use this capability to select - * the Master function. The master function will be used to initiate - * designated functionality like error recovery etc. If none of the - * registered PFs or trusted VFs indicate this support, then - * firmware will select the 1st registered PF as Master capable - * instance. + * Master capability. The Firmware will use this capability to select the + * Master function. The master function will be used to initiate + * designated functionality like error recovery etc… If none of the + * registered PF’s or trusted VF’s indicate this support, then + * firmware will select the 1st registered PF as Master capable instance. */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \ UINT32_C(0x40) @@ -9045,7 +11237,7 @@ struct hwrm_func_drv_rgtr_input { uint16_t ver_upd; /* This is the 16bit patch version of the driver. */ uint16_t ver_patch; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_rgtr_output (size:128b/16B) */ struct hwrm_func_drv_rgtr_output { @@ -9073,7 +11265,7 @@ struct hwrm_func_drv_rgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_func_drv_unrgtr * @@ -9118,7 +11310,7 @@ struct hwrm_func_drv_unrgtr_input { #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \ UINT32_C(0x1) uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ struct hwrm_func_drv_unrgtr_output { @@ -9139,7 +11331,7 @@ struct hwrm_func_drv_unrgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_buf_rgtr * @@ -9253,7 +11445,7 @@ struct hwrm_func_buf_rgtr_input { * HWRM. */ uint64_t resp_buf_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_buf_rgtr_output (size:128b/16B) */ struct hwrm_func_buf_rgtr_output { @@ -9274,7 +11466,7 @@ struct hwrm_func_buf_rgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_func_buf_unrgtr * @@ -9323,7 +11515,7 @@ struct hwrm_func_buf_unrgtr_input { */ uint16_t vf_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_buf_unrgtr_output (size:128b/16B) */ struct hwrm_func_buf_unrgtr_output { @@ -9344,7 +11536,7 @@ struct hwrm_func_buf_unrgtr_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_drv_qver * @@ -9390,7 +11582,7 @@ struct hwrm_func_drv_qver_input { */ uint16_t fid; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_qver_output (size:256b/32B) */ struct hwrm_func_drv_qver_output { @@ -9452,7 +11644,7 @@ struct hwrm_func_drv_qver_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_func_resource_qcaps * @@ -9496,7 +11688,7 @@ struct hwrm_func_resource_qcaps_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_resource_qcaps_output (size:448b/56B) */ struct hwrm_func_resource_qcaps_output { @@ -9582,7 +11774,7 @@ struct hwrm_func_resource_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************************* * hwrm_func_backing_store_qcaps * @@ -9619,9 +11811,9 @@ struct hwrm_func_backing_store_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ +/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ struct hwrm_func_backing_store_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -9680,7 +11872,7 @@ struct hwrm_func_backing_store_qcaps_output { * * TQM slowpath rings should be sized as follows: * - * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: * num_vnics is the number of VNICs allocated in the VNIC backing store @@ -9728,6 +11920,23 @@ struct hwrm_func_backing_store_qcaps_output { * limitations. */ uint8_t tqm_entries_multiple; + /* + * Initializer to be used by drivers + * to initialize context memory to ensure + * context subsystem flags an error for an attack + * before the first time context load. + */ + uint8_t ctx_kind_initializer; + /* Reserved for future. */ + uint32_t rsvd; + /* Reserved for future. */ + uint16_t rsvd1; + /* + * Count of TQM fastpath rings to be used for allocating backing store. + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + */ + uint8_t tqm_fp_rings_count; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9736,7 +11945,7 @@ struct hwrm_func_backing_store_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_func_backing_store_cfg * @@ -10586,7 +12795,7 @@ struct hwrm_func_backing_store_cfg_input { * * TQM slowpath rings should be sized as follows: * - * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size + * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size * * Where: * num_vnics is the number of VNICs allocated in the VNIC backing store @@ -10750,7 +12959,7 @@ struct hwrm_func_backing_store_cfg_input { uint16_t mrav_entry_size; /* Number of bytes that have been allocated for each context entry. */ uint16_t tim_entry_size; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ struct hwrm_func_backing_store_cfg_output { @@ -10771,7 +12980,7 @@ struct hwrm_func_backing_store_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************** * hwrm_func_backing_store_qcfg * @@ -10808,7 +13017,7 @@ struct hwrm_func_backing_store_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */ struct hwrm_func_backing_store_qcfg_output { @@ -11685,7 +13894,7 @@ struct hwrm_func_backing_store_qcfg_output { * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_error_recovery_qcfg * @@ -11723,7 +13932,7 @@ struct hwrm_error_recovery_qcfg_input { */ uint64_t resp_addr; uint8_t unused_0[8]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ struct hwrm_error_recovery_qcfg_output { @@ -12042,7 +14251,54 @@ struct hwrm_error_recovery_qcfg_output { * this much time after writing reset_reg_val in reset_reg. */ uint8_t delay_after_reset[16]; - uint8_t unused_1[7]; + /* + * Error recovery counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. + */ + uint32_t err_recovery_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + 0 + /* + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) + /* + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) + /* + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) + /* + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. + */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + 2 + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12052,7 +14308,7 @@ struct hwrm_error_recovery_qcfg_output { * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_func_vlan_qcfg * @@ -12097,7 +14353,7 @@ struct hwrm_func_vlan_qcfg_input { */ uint16_t fid; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vlan_qcfg_output (size:320b/40B) */ struct hwrm_func_vlan_qcfg_output { @@ -12143,7 +14399,7 @@ struct hwrm_func_vlan_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_func_vlan_cfg * @@ -12244,7 +14500,7 @@ struct hwrm_func_vlan_cfg_input { /* Future use. */ uint32_t rsvd2; uint8_t unused_3[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vlan_cfg_output (size:128b/16B) */ struct hwrm_func_vlan_cfg_output { @@ -12265,7 +14521,7 @@ struct hwrm_func_vlan_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_func_vf_vnic_ids_query * @@ -12312,7 +14568,7 @@ struct hwrm_func_vf_vnic_ids_query_input { uint32_t max_vnic_id_cnt; /* This is the address for VF VNIC ID table */ uint64_t vnic_id_tbl_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ struct hwrm_func_vf_vnic_ids_query_output { @@ -12339,7 +14595,7 @@ struct hwrm_func_vf_vnic_ids_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_func_vf_bw_cfg * @@ -12443,7 +14699,7 @@ struct hwrm_func_vf_bw_cfg_input { (UINT32_C(0xf) << 12) #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \ HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */ struct hwrm_func_vf_bw_cfg_output { @@ -12464,7 +14720,7 @@ struct hwrm_func_vf_bw_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_func_vf_bw_qcfg * @@ -12513,7 +14769,7 @@ struct hwrm_func_vf_bw_qcfg_input { /* The physical VF id of interest */ #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff) #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0 -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */ struct hwrm_func_vf_bw_qcfg_output { @@ -12602,7 +14858,7 @@ struct hwrm_func_vf_bw_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_func_drv_if_change * @@ -12655,7 +14911,7 @@ struct hwrm_func_drv_if_change_input { */ #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1) uint32_t unused; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_drv_if_change_output (size:128b/16B) */ struct hwrm_func_drv_if_change_output { @@ -12691,7 +14947,7 @@ struct hwrm_func_drv_if_change_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************************* * hwrm_func_host_pf_ids_query * @@ -12777,7 +15033,7 @@ struct hwrm_func_host_pf_ids_query_input { #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \ HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE uint8_t unused_1[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */ struct hwrm_func_host_pf_ids_query_output { @@ -12897,7 +15153,7 @@ struct hwrm_func_host_pf_ids_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_port_phy_cfg * @@ -12955,8 +15211,13 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \ UINT32_C(0x2) /* - * When this bit is set to '1', the link shall be forced to - * the force_link_speed value. + * When this bit is set to '1', and the force_pam4_link_speed + * bit in the 'enables' field is '0', the link shall be forced + * to the force_link_speed value. + * + * When this bit is set to '1', and the force_pam4_link_speed + * bit in the 'enables' field is '1', the link shall be forced + * to the force_pam4_link_speed value. * * When this bit is set to '1', the HWRM client should * not enable any of the auto negotiation related @@ -13369,7 +15630,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) /* * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external + * host data is sent on the transmitter and based on the external * loopback connection the data will be received without modification. */ #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3) @@ -13429,9 +15690,25 @@ struct hwrm_port_phy_cfg_input { /* 10Gb link speed */ #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \ UINT32_C(0x40) - uint8_t unused_2[2]; /* - * Reuested setting of TX LPI timer in microseconds. + * This is the speed that will be used if the force and force_pam4 + * bits are '1'. If unsupported speed is selected, an error + * will be generated. + */ + uint16_t force_pam4_link_speed; + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \ + UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \ + UINT32_C(0x3e8) + /* 200Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \ + UINT32_C(0x7d0) + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \ + HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB + /* + * Requested setting of TX LPI timer in microseconds. * This field is valid only when EEE is enabled and TX LPI is * enabled. */ @@ -13439,7 +15716,7 @@ struct hwrm_port_phy_cfg_input { #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 uint32_t unused_3; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_cfg_output (size:128b/16B) */ struct hwrm_port_phy_cfg_output { @@ -13460,7 +15737,7 @@ struct hwrm_port_phy_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ struct hwrm_port_phy_cfg_cmd_err { @@ -13489,7 +15766,7 @@ struct hwrm_port_phy_cfg_cmd_err { #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \ HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_phy_qcfg * @@ -13529,7 +15806,7 @@ struct hwrm_port_phy_qcfg_input { /* Port ID of port that is to be queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_qcfg_output (size:768b/96B) */ struct hwrm_port_phy_qcfg_output { @@ -13861,7 +16138,7 @@ struct hwrm_port_phy_qcfg_output { #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) /* * The HW will be configured with external loopback such that - * host data is sent on the trasmitter and based on the external + * host data is sent on the transmitter and based on the external * loopback connection the data will be received without modification. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3) @@ -13903,6 +16180,9 @@ struct hwrm_port_phy_qcfg_output { /* Module is not inserted. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \ UINT32_C(0x4) + /* Module is powered down because of over current fault. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \ + UINT32_C(0x5) /* Module status is not applicable. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \ UINT32_C(0xff) @@ -14377,7 +16657,7 @@ struct hwrm_port_phy_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_port_mac_cfg * @@ -14500,7 +16780,7 @@ struct hwrm_port_mac_cfg_input { #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \ UINT32_C(0x100) /* - * When this bit is '1', the the Out-Of-Box WoL is requested to + * When this bit is '1', the Out-Of-Box WoL is requested to * be disabled on this port. */ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \ @@ -14670,7 +16950,7 @@ struct hwrm_port_mac_cfg_input { * This field shall be ignored if the ptp_tx_ts_capture_enable * flag is not set in this command. * Otherwise, if bit 'i' is set, then the HWRM is being - * requested to configure the transmit sied of the port to + * requested to configure the transmit side of the port to * capture the time stamp of every transmitted PTP message * with messageType field value set to i. */ @@ -14778,7 +17058,7 @@ struct hwrm_port_mac_cfg_input { */ int32_t ptp_freq_adj_ppb; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_mac_cfg_output (size:128b/16B) */ struct hwrm_port_mac_cfg_output { @@ -14832,7 +17112,7 @@ struct hwrm_port_mac_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_mac_qcfg * @@ -14872,9 +17152,9 @@ struct hwrm_port_mac_qcfg_input { /* Port ID of port that is to be configured. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_port_mac_qcfg_output (size:192b/24B) */ +/* hwrm_port_mac_qcfg_output (size:256b/32B) */ struct hwrm_port_mac_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -15114,6 +17394,20 @@ struct hwrm_port_mac_qcfg_output { UINT32_C(0xe0) #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ 5 + uint8_t unused_1; + uint16_t port_svif_info; + /* + * This field specifies the source virtual interface of the port being + * queried. Drivers can use this to program port svif field in the + * L2 context table + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \ + UINT32_C(0x7fff) + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0 + /* This field specifies whether port_svif is valid or not */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \ + UINT32_C(0x8000) + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15122,7 +17416,7 @@ struct hwrm_port_mac_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_port_mac_ptp_qcfg * @@ -15162,7 +17456,7 @@ struct hwrm_port_mac_ptp_qcfg_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ struct hwrm_port_mac_ptp_qcfg_output { @@ -15185,18 +17479,18 @@ struct hwrm_port_mac_ptp_qcfg_output { */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \ UINT32_C(0x1) - /* - * When this bit is set to '1', the PTP information is accessible - * via HWRM commands. - */ - #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ - UINT32_C(0x2) /* * When this bit is set to '1', the device supports one-step * Tx timestamping. */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \ UINT32_C(0x4) + /* + * When this bit is set to '1', the PTP information is accessible + * via HWRM commands. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ + UINT32_C(0x8) uint8_t unused_0[3]; /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ uint32_t rx_ts_reg_off_lower; @@ -15237,9 +17531,9 @@ struct hwrm_port_mac_ptp_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/* Port Tx Statistics Formats */ +/* Port Tx Statistics Format */ /* tx_port_stats (size:3264b/408B) */ struct tx_port_stats { /* Total Number of 64 Bytes frames transmitted */ @@ -15378,9 +17672,9 @@ struct tx_port_stats { uint64_t tx_stat_discard; /* Total Tx Error Drops per Port reported by STATS block */ uint64_t tx_stat_error; -} __attribute__((packed)); +} __rte_packed; -/* Port Rx Statistics Formats */ +/* Port Rx Statistics Format */ /* rx_port_stats (size:4224b/528B) */ struct rx_port_stats { /* Total Number of 64 Bytes frames received */ @@ -15593,7 +17887,7 @@ struct rx_port_stats { /* Total Rx Discards per Port reported by STATS block */ uint64_t rx_stat_discard; uint64_t rx_stat_err; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_port_qstats * @@ -15632,7 +17926,18 @@ struct hwrm_port_qstats_input { uint64_t resp_addr; /* Port ID of port that is being queried. */ uint16_t port_id; - uint8_t unused_0[6]; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \ + HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0[5]; /* * This is the host address where * Tx port statistics will be stored @@ -15643,7 +17948,7 @@ struct hwrm_port_qstats_input { * Rx port statistics will be stored */ uint64_t rx_stat_host_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_qstats_output (size:128b/16B) */ struct hwrm_port_qstats_output { @@ -15668,9 +17973,9 @@ struct hwrm_port_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/* Port Tx Statistics extended Formats */ +/* Port Tx Statistics extended Format */ /* tx_port_stats_ext (size:2048b/256B) */ struct tx_port_stats_ext { /* Total number of tx bytes count on cos queue 0 */ @@ -15737,9 +18042,9 @@ struct tx_port_stats_ext { uint64_t pfc_pri7_tx_duration_us; /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */ uint64_t pfc_pri7_tx_transitions; -} __attribute__((packed)); +} __rte_packed; -/* Port Rx Statistics extended Formats */ +/* Port Rx Statistics extended Format */ /* rx_port_stats_ext (size:3648b/456B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ @@ -15859,7 +18164,425 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos6; /* Total number of rx discard packets count on cos queue 7 */ uint64_t rx_discard_packets_cos7; -} __attribute__((packed)); +} __rte_packed; + +/* + * Port Rx Statistics extended PFC WatchDog Format. + * StormDetect and StormRevert event determination is based + * on an integration period and a percentage threshold. + * StormDetect event - when percentage of XOFF frames received + * within an integration period exceeds the configured threshold. + * StormRevert event - when percentage of XON frames received + * within an integration period exceeds the configured threshold. + * Actual number of XOFF/XON frames for the events to be triggered + * depends on both configured integration period and sampling rate. + * The statistics in this structure represent counts of specified + * events from the moment the feature (PFC WatchDog) is enabled via + * hwrm_queue_pfc_enable_cfg call. + */ +/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */ +struct rx_port_stats_ext_pfc_wd { + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri0; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri1; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri2; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri3; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri4; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri5; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri6; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri7; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri0; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri1; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri2; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri3; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri4; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri5; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri6; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri7; + /* + * Total number of packets received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri0; + /* + * Total number of packets received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri1; + /* + * Total number of packets received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri2; + /* + * Total number of packets received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri3; + /* + * Total number of packets received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri4; + /* + * Total number of packets received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri5; + /* + * Total number of packets received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri6; + /* + * Total number of packets received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri7; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7; + /* + * Number of packets received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0; + /* + * Number of packets received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1; + /* + * Number of packets received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2; + /* + * Number of packets received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3; + /* + * Number of packets received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4; + /* + * Number of packets received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5; + /* + * Number of packets received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6; + /* + * Number of packets received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7; +} __rte_packed; /************************ * hwrm_port_qstats_ext * @@ -15908,7 +18631,18 @@ struct hwrm_port_qstats_ext_input { * statistics block in bytes */ uint16_t rx_stat_size; - uint8_t unused_0[2]; + uint8_t flags; + /* This value is not used to avoid backward compatibility issues. */ + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) + /* + * This bit is set to 1 when request is for the counter mask, + * representing width of each of the stats counters, rather than + * counters themselves. + */ + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \ + HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + uint8_t unused_0; /* * This is the host address where * Tx port statistics will be stored @@ -15919,7 +18653,7 @@ struct hwrm_port_qstats_ext_input { * Rx port statistics will be stored */ uint64_t rx_stat_host_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_qstats_ext_output (size:128b/16B) */ struct hwrm_port_qstats_ext_output { @@ -15952,7 +18686,84 @@ struct hwrm_port_qstats_ext_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/******************************* + * hwrm_port_qstats_ext_pfc_wd * + *******************************/ + + +/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */ +struct hwrm_port_qstats_ext_pfc_wd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + /* + * The size of rx_port_stats_ext_pfc_wd + * block in bytes + */ + uint16_t pfc_wd_stat_size; + uint8_t unused_0[4]; + /* + * This is the host address where + * rx_port_stats_ext_pfc_wd will be stored + */ + uint64_t pfc_wd_stat_host_addr; +} __rte_packed; + +/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */ +struct hwrm_port_qstats_ext_pfc_wd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The size of rx_port_stats_ext_pfc_wd + * statistics block in bytes. + */ + uint16_t pfc_wd_stat_size; + uint8_t flags; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; + uint8_t unused_0[4]; +} __rte_packed; /************************* * hwrm_port_lpbk_qstats * @@ -15989,7 +18800,7 @@ struct hwrm_port_lpbk_qstats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ struct hwrm_port_lpbk_qstats_output { @@ -16030,7 +18841,92 @@ struct hwrm_port_lpbk_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/************************ + * hwrm_port_ecn_qstats * + ************************/ + + +/* hwrm_port_ecn_qstats_input (size:192b/24B) */ +struct hwrm_port_ecn_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port that is being queried. Unused if NIC is in + * multi-host mode. + */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_port_ecn_qstats_output (size:384b/48B) */ +struct hwrm_port_ecn_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of packets marked in CoS queue 0. */ + uint32_t mark_cnt_cos0; + /* Number of packets marked in CoS queue 1. */ + uint32_t mark_cnt_cos1; + /* Number of packets marked in CoS queue 2. */ + uint32_t mark_cnt_cos2; + /* Number of packets marked in CoS queue 3. */ + uint32_t mark_cnt_cos3; + /* Number of packets marked in CoS queue 4. */ + uint32_t mark_cnt_cos4; + /* Number of packets marked in CoS queue 5. */ + uint32_t mark_cnt_cos5; + /* Number of packets marked in CoS queue 6. */ + uint32_t mark_cnt_cos6; + /* Number of packets marked in CoS queue 7. */ + uint32_t mark_cnt_cos7; + /* + * Bitmask that indicates which CoS queues have ECN marking enabled. + * Bit i corresponds to CoS queue i. + */ + uint8_t mark_en; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; /*********************** * hwrm_port_clr_stats * @@ -16081,7 +18977,7 @@ struct hwrm_port_clr_stats_input { */ #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1) uint8_t unused_0[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_clr_stats_output (size:128b/16B) */ struct hwrm_port_clr_stats_output { @@ -16102,7 +18998,7 @@ struct hwrm_port_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_port_phy_qcaps * @@ -16142,7 +19038,7 @@ struct hwrm_port_phy_qcaps_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_qcaps_output (size:192b/24B) */ struct hwrm_port_phy_qcaps_output { @@ -16168,13 +19064,28 @@ struct hwrm_port_phy_qcaps_output { */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \ UINT32_C(0x2) + /* + * If set to 1, then this field indicates that the + * PHY is capable of supporting loopback in autoneg mode. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \ + UINT32_C(0x4) + /* + * Indicates if the configuration of shared PHY settings is supported. + * In cases where a physical port is shared by multiple functions + * (e.g. NPAR, multihost, etc), the configuration of PHY + * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will + * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \ + UINT32_C(0x8) /* * Reserved field. The HWRM shall set this field to 0. * An HWRM client shall ignore this field. */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \ - UINT32_C(0xfc) - #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2 + UINT32_C(0xf0) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4 /* Number of front panel ports for this device. */ uint8_t port_cnt; /* Not supported or unknown */ @@ -16357,7 +19268,7 @@ struct hwrm_port_phy_qcaps_output { #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \ UINT32_C(0xff000000) #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_port_phy_mdio_write * @@ -16413,7 +19324,7 @@ struct hwrm_port_phy_mdio_write_input { uint8_t cl45_mdio; /* */ uint8_t unused_1[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ struct hwrm_port_phy_mdio_write_output { @@ -16434,7 +19345,7 @@ struct hwrm_port_phy_mdio_write_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_port_phy_mdio_read * @@ -16488,7 +19399,7 @@ struct hwrm_port_phy_mdio_read_input { uint8_t cl45_mdio; /* */ uint8_t unused_1; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ struct hwrm_port_phy_mdio_read_output { @@ -16511,7 +19422,7 @@ struct hwrm_port_phy_mdio_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_port_led_cfg * @@ -16914,7 +19825,7 @@ struct hwrm_port_led_cfg_input { uint8_t led3_group_id; /* Reserved field. */ uint8_t rsvd3; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_led_cfg_output (size:128b/16B) */ struct hwrm_port_led_cfg_output { @@ -16935,7 +19846,7 @@ struct hwrm_port_led_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_led_qcfg * @@ -16975,7 +19886,7 @@ struct hwrm_port_led_qcfg_input { /* Port ID of port whose LED configuration is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_led_qcfg_output (size:448b/56B) */ struct hwrm_port_led_qcfg_output { @@ -17241,7 +20152,7 @@ struct hwrm_port_led_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_port_led_qcaps * @@ -17281,7 +20192,7 @@ struct hwrm_port_led_qcaps_input { /* Port ID of port whose LED configuration is being queried. */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_led_qcaps_output (size:384b/48B) */ struct hwrm_port_led_qcaps_output { @@ -17593,7 +20504,7 @@ struct hwrm_port_led_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_port_prbs_test * @@ -17700,7 +20611,7 @@ struct hwrm_port_prbs_test_input { * bit1 = lane1 ..bit31 = lane31 */ uint32_t rx_lane_map; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_prbs_test_output (size:128b/16B) */ struct hwrm_port_prbs_test_output { @@ -17724,7 +20635,554 @@ struct hwrm_port_prbs_test_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/********************** + * hwrm_port_dsc_dump * + **********************/ + + +/* hwrm_port_dsc_dump_input (size:320b/40B) */ +struct hwrm_port_dsc_dump_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Host address where response diagnostic data is returned. */ + uint64_t resp_data_addr; + /* + * Size of the buffer pointed to by resp_data_addr. The firmware + * may use this entire buffer or less than the entire buffer, but + * never more. + */ + uint16_t data_len; + uint16_t unused_0; + uint32_t unused_1; + /* Port ID of port where dsc dump to be collected. */ + uint16_t port_id; + /* Diag level specified by the user */ + uint16_t diag_level; + /* SRDS_DIAG_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \ + UINT32_C(0x0) + /* SRDS_DIAG_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \ + UINT32_C(0x1) + /* SRDS_DIAG_EVENT */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \ + UINT32_C(0x2) + /* SRDS_DIAG_EYE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \ + UINT32_C(0x3) + /* SRDS_DIAG_REG_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \ + UINT32_C(0x4) + /* SRDS_DIAG_REG_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \ + UINT32_C(0x5) + /* SRDS_DIAG_UC_CORE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \ + UINT32_C(0x6) + /* SRDS_DIAG_UC_LANE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \ + UINT32_C(0x7) + /* SRDS_DIAG_LANE_DEBUG */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \ + UINT32_C(0x8) + /* SRDS_DIAG_BER_VERT */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \ + UINT32_C(0x9) + /* SRDS_DIAG_BER_HORZ */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \ + UINT32_C(0xa) + /* SRDS_DIAG_EVENT_SAFE */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \ + UINT32_C(0xb) + /* SRDS_DIAG_TIMESTAMP */ + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \ + UINT32_C(0xc) + #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \ + HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP + /* + * This field is a lane number + * on which to collect the dsc dump + */ + uint16_t lane_number; + /* + * Configuration bits. + * Use enable bit to start dsc dump or retrieve dump + */ + uint16_t dsc_dump_config; + /* + * Set 0 to retrieve the dsc dump + * Set 1 to start the dsc dump + */ + #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \ + UINT32_C(0x1) +} __rte_packed; + +/* hwrm_port_dsc_dump_output (size:128b/16B) */ +struct hwrm_port_dsc_dump_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Total length of stored data. */ + uint16_t total_data_len; + uint16_t unused_0; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_port_sfp_sideband_cfg * + ******************************/ + + +/* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */ +struct hwrm_port_sfp_sideband_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; + /* + * This bitfield is used to specify which bits from the 'flags' + * fields are being configured by the caller. + */ + uint32_t enables; + /* This bit must be '1' for rs0 to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \ + UINT32_C(0x1) + /* This bit must be '1' for rs1 to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \ + UINT32_C(0x2) + /* This bit must be '1' for tx_disable to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \ + UINT32_C(0x4) + /* + * This bit must be '1' for mod_sel to be configured. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \ + UINT32_C(0x8) + /* This bit must be '1' for reset_l to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \ + UINT32_C(0x10) + /* This bit must be '1' for lp_mode to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \ + UINT32_C(0x20) + /* This bit must be '1' for pwr_disable to be configured. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \ + UINT32_C(0x40) + /* + * Only bits that have corresponding bits in the 'enables' + * bitfield are processed by the firmware, all other bits + * of 'flags' are ignored. + */ + uint32_t flags; + /* + * This bit along with rs1 configures the current speed of the dual + * rate module. If these pins are GNDed then the speed can be changed + * by driectly writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \ + UINT32_C(0x1) + /* + * This bit along with rs0 configures the current speed of the dual + * rate module. If these pins are GNDed then the speed can be changed + * by driectly writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \ + UINT32_C(0x2) + /* + * When this bit is set to '1', tx_disable is set. + * On a 1G BASE-T module, if this bit is set, + * module PHY registers will not be accessible. + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \ + UINT32_C(0x4) + /* + * When this bit is set to '1', this module is selected. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \ + UINT32_C(0x8) + /* + * If reset_l is set to 0, Module will be taken out of reset + * and other signals will be set to their requested state once + * the module is out of reset. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \ + UINT32_C(0x10) + /* + * When this bit is set to '1', the module will be configured + * in low power mode. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \ + UINT32_C(0x20) + /* When this bit is set to '1', the module will be powered down. */ + #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \ + UINT32_C(0x40) +} __rte_packed; + +/* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */ +struct hwrm_port_sfp_sideband_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_port_sfp_sideband_qcfg * + *******************************/ + + +/* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */ +struct hwrm_port_sfp_sideband_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */ +struct hwrm_port_sfp_sideband_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Bitmask indicating which sideband signals are valid. + * This is based on the board and nvm cfg that is present on the board. + */ + uint32_t supported_mask; + uint32_t sideband_signals; + /* When this bit is set to '1', the Module is absent. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \ + UINT32_C(0x1) + /* + * When this bit is set to '1', there is no valid signal on RX. + * This signal is a filtered version of Signal Detect. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \ + UINT32_C(0x2) + /* + * This bit along with rs1 indiactes the current speed of the dual + * rate module.If these pins are grounded then the speed can be + * changed by driectky writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \ + UINT32_C(0x4) + /* + * This bit along with rs0 indiactes the current speed of the dual + * rate module.If these pins are grounded then the speed can be + * changed by driectky writing to EEPROM. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \ + UINT32_C(0x8) + /* + * When this bit is set to '1', tx_disable is set. + * On a 1G BASE-T module, if this bit is set, module PHY + * registers will not be accessible. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \ + UINT32_C(0x10) + /* When this bit is set to '1', tx_fault is set. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', module is selected. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \ + UINT32_C(0x40) + /* + * When this bit is set to '0', the module is held in reset. + * if reset_l is set to 1,first module is taken out of reset + * and other signals will be set to their requested state. + * Valid only on QSFP modules. + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \ + UINT32_C(0x80) + /* + * When this bit is set to '1', the module is in low power mode. + * Valid only on QSFP modules + */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \ + UINT32_C(0x100) + /* When this bit is set to '1', module is in power down state. */ + #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \ + UINT32_C(0x200) + uint8_t unused[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. When + * writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_port_phy_mdio_bus_acquire * + **********************************/ + + +/* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */ +struct hwrm_port_phy_mdio_bus_acquire_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of the port. */ + uint16_t port_id; + /* + * client_id of the client requesting BUS access. + * Any value from 0x10 to 0xFFFF can be used. + * Client should make sure that the returned client_id + * in response matches the client_id in request. + * 0-0xF are reserved for internal use. + */ + uint16_t client_id; + /* + * Timeout in milli seconds, MDIO BUS will be released automatically + * after this time, if another mdio acquire command is not received + * within the timeout window from the same client. + * A 0xFFFF will hold the bus until this bus is released. + */ + uint16_t mdio_bus_timeout; + uint8_t unused_0[2]; +} __rte_packed; + +/* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_bus_acquire_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t unused_0; + /* + * client_id of the module holding the BUS. + * 0-0xF are reserved for internal use. + */ + uint16_t client_id; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************** + * hwrm_port_phy_mdio_bus_release * + **********************************/ + + +/* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */ +struct hwrm_port_phy_mdio_bus_release_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of the port. */ + uint16_t port_id; + /* + * client_id of the client requesting BUS release. + * A client should not release any other clients BUS. + */ + uint16_t client_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */ +struct hwrm_port_phy_mdio_bus_release_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t unused_0; + /* The BUS is released if client_id matches the client_id in request. */ + uint16_t clients_id; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; /*********************** * hwrm_queue_qportcfg * @@ -17776,7 +21234,7 @@ struct hwrm_queue_qportcfg_input { HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX /* * Port ID of port for which the queue configuration is being - * queried. This field is only required when sent by IPC. + * queried. This field is only required when sent by IPC. */ uint16_t port_id; /* @@ -17791,7 +21249,7 @@ struct hwrm_queue_qportcfg_input { #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \ HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_qportcfg_output (size:256b/32B) */ struct hwrm_queue_qportcfg_output { @@ -18171,13 +21629,13 @@ struct hwrm_queue_qportcfg_output { HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_queue_qcfg * @@ -18229,7 +21687,7 @@ struct hwrm_queue_qcfg_input { HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX /* Queue ID of the queue. */ uint32_t queue_id; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_qcfg_output (size:128b/16B) */ struct hwrm_queue_qcfg_output { @@ -18242,7 +21700,7 @@ struct hwrm_queue_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * This value is a the estimate packet length used in the + * This value is the estimate packet length used in the * TX arbiter. */ uint32_t queue_len; @@ -18269,13 +21727,13 @@ struct hwrm_queue_qcfg_output { uint8_t unused_0; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_queue_cfg * @@ -18358,7 +21816,7 @@ struct hwrm_queue_cfg_input { #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \ HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_cfg_output (size:128b/16B) */ struct hwrm_queue_cfg_output { @@ -18373,13 +21831,13 @@ struct hwrm_queue_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_queue_pfcenable_qcfg * @@ -18423,7 +21881,7 @@ struct hwrm_queue_pfcenable_qcfg_input { */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ struct hwrm_queue_pfcenable_qcfg_output { @@ -18460,16 +21918,40 @@ struct hwrm_queue_pfcenable_qcfg_output { /* If set to 1, then PFC is enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_queue_pfcenable_cfg * @@ -18513,24 +21995,48 @@ struct hwrm_queue_pfcenable_cfg_input { /* If set to 1, then PFC is requested to be enabled on PRI 1. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \ UINT32_C(0x2) - /* If set to 1, then PFC is requested to be enabled on PRI 2. */ + /* If set to 1, then PFC is requested to be enabled on PRI 2. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \ UINT32_C(0x4) - /* If set to 1, then PFC is requested to be enabled on PRI 3. */ + /* If set to 1, then PFC is requested to be enabled on PRI 3. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \ UINT32_C(0x8) - /* If set to 1, then PFC is requested to be enabled on PRI 4. */ + /* If set to 1, then PFC is requested to be enabled on PRI 4. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \ UINT32_C(0x10) - /* If set to 1, then PFC is requested to be enabled on PRI 5. */ + /* If set to 1, then PFC is requested to be enabled on PRI 5. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \ UINT32_C(0x20) - /* If set to 1, then PFC is requested to be enabled on PRI 6. */ + /* If set to 1, then PFC is requested to be enabled on PRI 6. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \ UINT32_C(0x40) - /* If set to 1, then PFC is requested to be enabled on PRI 7. */ + /* If set to 1, then PFC is requested to be enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed @@ -18538,7 +22044,7 @@ struct hwrm_queue_pfcenable_cfg_input { */ uint16_t port_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ struct hwrm_queue_pfcenable_cfg_output { @@ -18553,13 +22059,13 @@ struct hwrm_queue_pfcenable_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_queue_pri2cos_qcfg * @@ -18611,9 +22117,9 @@ struct hwrm_queue_pri2cos_qcfg_input { HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX /* * When this bit is set to '0', the query is - * for VLAN PRI field in tunnel headers. + * for PRI from tunnel headers. * When this bit is set to '1', the query is - * for VLAN PRI field in inner packet headers. + * for PRI from inner packet headers. */ #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) /* @@ -18623,7 +22129,7 @@ struct hwrm_queue_pri2cos_qcfg_input { */ uint8_t port_id; uint8_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ struct hwrm_queue_pri2cos_qcfg_output { @@ -18636,56 +22142,56 @@ struct hwrm_queue_pri2cos_qcfg_output { /* The length of the response data in number of bytes. */ uint16_t resp_len; /* - * CoS Queue assigned to priority 0. This value can only + * CoS Queue assigned to priority 0. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri0_cos_queue_id; /* - * CoS Queue assigned to priority 1. This value can only + * CoS Queue assigned to priority 1. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri1_cos_queue_id; /* - * CoS Queue assigned to priority 2 This value can only + * CoS Queue assigned to priority 2. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri2_cos_queue_id; /* - * CoS Queue assigned to priority 3. This value can only + * CoS Queue assigned to priority 3. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri3_cos_queue_id; /* - * CoS Queue assigned to priority 4. This value can only + * CoS Queue assigned to priority 4. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri4_cos_queue_id; /* - * CoS Queue assigned to priority 5. This value can only + * CoS Queue assigned to priority 5. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri5_cos_queue_id; /* - * CoS Queue assigned to priority 6. This value can only + * CoS Queue assigned to priority 6. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. */ uint8_t pri6_cos_queue_id; /* - * CoS Queue assigned to priority 7. This value can only + * CoS Queue assigned to priority 7. This value can only * be changed before traffic has started. * A value of 0xff indicates that no CoS queue is assigned to the * specified priority. @@ -18704,13 +22210,13 @@ struct hwrm_queue_pri2cos_qcfg_output { uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_queue_pri2cos_cfg * @@ -18765,9 +22271,9 @@ struct hwrm_queue_pri2cos_cfg_input { HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR /* * When this bit is set to '0', the mapping is requested - * for VLAN PRI field in tunnel headers. + * for PRI from tunnel headers. * When this bit is set to '1', the mapping is requested - * for VLAN PRI field in inner packet headers. + * for PRI from inner packet headers. */ #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4) uint32_t enables; @@ -18826,12 +22332,12 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t port_id; /* - * CoS Queue assigned to priority 0. This value can only + * CoS Queue assigned to priority 0. This value can only * be changed before traffic has started. */ uint8_t pri0_cos_queue_id; /* - * CoS Queue assigned to priority 1. This value can only + * CoS Queue assigned to priority 1. This value can only * be changed before traffic has started. */ uint8_t pri1_cos_queue_id; @@ -18841,32 +22347,32 @@ struct hwrm_queue_pri2cos_cfg_input { */ uint8_t pri2_cos_queue_id; /* - * CoS Queue assigned to priority 3. This value can only + * CoS Queue assigned to priority 3. This value can only * be changed before traffic has started. */ uint8_t pri3_cos_queue_id; /* - * CoS Queue assigned to priority 4. This value can only + * CoS Queue assigned to priority 4. This value can only * be changed before traffic has started. */ uint8_t pri4_cos_queue_id; /* - * CoS Queue assigned to priority 5. This value can only + * CoS Queue assigned to priority 5. This value can only * be changed before traffic has started. */ uint8_t pri5_cos_queue_id; /* - * CoS Queue assigned to priority 6. This value can only + * CoS Queue assigned to priority 6. This value can only * be changed before traffic has started. */ uint8_t pri6_cos_queue_id; /* - * CoS Queue assigned to priority 7. This value can only + * CoS Queue assigned to priority 7. This value can only * be changed before traffic has started. */ uint8_t pri7_cos_queue_id; uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ struct hwrm_queue_pri2cos_cfg_output { @@ -18881,13 +22387,13 @@ struct hwrm_queue_pri2cos_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_queue_cos2bw_qcfg * @@ -18931,7 +22437,7 @@ struct hwrm_queue_cos2bw_qcfg_input { */ uint16_t port_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ struct hwrm_queue_cos2bw_qcfg_output { @@ -19924,13 +23430,13 @@ struct hwrm_queue_cos2bw_qcfg_output { uint8_t unused_2[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_queue_cos2bw_cfg * @@ -21001,7 +24507,7 @@ struct hwrm_queue_cos2bw_cfg_input { */ uint8_t queue_id7_bw_weight; uint8_t unused_1[5]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ struct hwrm_queue_cos2bw_cfg_output { @@ -21016,21 +24522,21 @@ struct hwrm_queue_cos2bw_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************* - * hwrm_vnic_alloc * - *******************/ +/************************* + * hwrm_queue_dscp_qcaps * + *************************/ -/* hwrm_vnic_alloc_input (size:192b/24B) */ -struct hwrm_vnic_alloc_input { +/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ +struct hwrm_queue_dscp_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21059,17 +24565,17 @@ struct hwrm_vnic_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When this bit is '1', this VNIC is requested to - * be the default VNIC for this function. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) - uint8_t unused_0[4]; -} __attribute__((packed)); + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; -/* hwrm_vnic_alloc_output (size:128b/16B) */ -struct hwrm_vnic_alloc_output { +/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ +struct hwrm_queue_dscp_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21078,26 +24584,29 @@ struct hwrm_vnic_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[3]; + /* The number of bits provided by the hardware for the DSCP value. */ + uint8_t num_dscp_bits; + uint8_t unused_0; + /* Max number of DSCP-MASK-PRI entries supported. */ + uint16_t max_entries; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************** - * hwrm_vnic_free * - ******************/ +/**************************** + * hwrm_queue_dscp2pri_qcfg * + ****************************/ -/* hwrm_vnic_free_input (size:192b/24B) */ -struct hwrm_vnic_free_input { +/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ +struct hwrm_queue_dscp2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21126,13 +24635,25 @@ struct hwrm_vnic_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Logical vnic ID */ - uint32_t vnic_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* + * This is the host address where the 24-bits DSCP-MASK-PRI + * tuple(s) will be copied to. + */ + uint64_t dest_data_addr; + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0; + /* Size of the buffer pointed to by dest_data_addr. */ + uint16_t dest_data_buffer_size; + uint8_t unused_1[4]; +} __rte_packed; -/* hwrm_vnic_free_output (size:128b/16B) */ -struct hwrm_vnic_free_output { +/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21141,24 +24662,34 @@ struct hwrm_vnic_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * A count of the number of DSCP-MASK-PRI tuple(s) pointed to + * by the dest_data_addr. + */ + uint16_t entry_cnt; + /* + * This is the default PRI which un-initialized DSCP values are + * mapped to. + */ + uint8_t default_pri; + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/***************** - * hwrm_vnic_cfg * - *****************/ +/*************************** + * hwrm_queue_dscp2pri_cfg * + ***************************/ -/* hwrm_vnic_cfg_input (size:384b/48B) */ -struct hwrm_vnic_cfg_input { +/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ +struct hwrm_queue_dscp2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21187,184 +24718,43 @@ struct hwrm_vnic_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; /* - * When this bit is '1', the VNIC is requested to - * be the default VNIC for the function. + * This is the host address where the 24-bits DSCP-MASK-PRI tuple + * will be copied from. */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \ + uint64_t src_data_addr; + uint32_t flags; + /* use_hw_default_pri is 1 b */ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \ UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is being configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. - */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is being configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is being configured to be - * disabled on this VNIC. - */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to be - * operating in dual VNIC mode. - */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ - UINT32_C(0x8) - /* - * When this flag is set to '1', the VNIC is requested to - * be configured to receive only RoCE traffic. - * If this flag is set to '0', then this flag shall be - * ignored by the HWRM. - * If roce_dual_vnic_mode flag is set to '1' - * or roce_mirroring_capable_vnic_mode flag to 1, - * then the HWRM client shall not set this flag to '1'. - */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ - UINT32_C(0x10) - /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. - * - * This flag is used to enable a mode where - * RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured using hwrm_vnic_rss_cfg. - * - * If this mode is enabled, then the driver should not program - * RSS indirection table for the RSS context that is used for - * computing RSS hash only. - */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \ - UINT32_C(0x20) - /* - * When this bit is '1', the VNIC is being configured to - * receive both RoCE and non-RoCE traffic, but forward only the - * RoCE traffic further. Also, RoCE traffic can be mirrored to - * L2 driver. - */ - #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ - UINT32_C(0x40) uint32_t enables; /* - * This bit must be '1' for the dflt_ring_grp field to be + * This bit must be '1' for the default_pri field to be * configured. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \ + #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \ UINT32_C(0x1) /* - * This bit must be '1' for the rss_rule field to be - * configured. - */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the cos_rule field to be - * configured. - */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \ - UINT32_C(0x4) - /* - * This bit must be '1' for the lb_rule field to be - * configured. - */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \ - UINT32_C(0x8) - /* - * This bit must be '1' for the mru field to be - * configured. - */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \ - UINT32_C(0x10) - /* - * This bit must be '1' for the default_rx_ring_id field to be - * configured. - */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the default_cmpl_ring_id field to be - * configured. - */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \ - UINT32_C(0x40) - /* This bit must be '1' for the queue_id field to be configured. */ - #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \ - UINT32_C(0x80) - /* Logical vnic ID */ - uint16_t vnic_id; - /* - * Default Completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules and if - * there is no COS rule. - */ - uint16_t dflt_ring_grp; - /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. - */ - uint16_t rss_rule; - /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. - */ - uint16_t cos_rule; - /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. - */ - uint16_t lb_rule; - /* - * The maximum receive unit of the vnic. - * Each vnic is associated with a function. - * The vnic mru value overwrites the mru setting of the - * associated function. - * The HWRM shall make sure that vnic mru does not exceed - * the mru of the port the function is associated with. - */ - uint16_t mru; - /* - * Default Rx ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. - * The aggregation ring associated with the Rx ring is - * implied based on the Rx ring specified when the - * aggregation ring was allocated. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure pri2cos mapping on this port. */ - uint16_t default_rx_ring_id; + uint8_t port_id; /* - * Default completion ring for the VNIC. This ring will - * be chosen if packet does not match any RSS rules. + * This is the default PRI which un-initialized DSCP values will be + * mapped to. */ - uint16_t default_cmpl_ring_id; + uint8_t default_pri; /* - * When specified, only incoming packets classified to the specified CoS - * queue ID will be arriving on this VNIC. Packet priority to CoS mapping - * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, - * ntuple filters with VNIC destination specified are invalid since they - * conflict with the the CoS to VNIC steering rules in this mode. - * - * If this field is not specified, packet to VNIC steering will be - * subject to the standard L2 filter rules and any additional ntuple - * filter rules with destination VNIC specified. + * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed + * to by src_data_addr. */ - uint16_t queue_id; - uint8_t unused0[6]; -} __attribute__((packed)); + uint16_t entry_cnt; + uint8_t unused_0[4]; +} __rte_packed; -/* hwrm_vnic_cfg_output (size:128b/16B) */ -struct hwrm_vnic_cfg_output { +/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_dscp2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21376,21 +24766,21 @@ struct hwrm_vnic_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************** - * hwrm_vnic_qcfg * - ******************/ +/************************* + * hwrm_queue_mpls_qcaps * + *************************/ -/* hwrm_vnic_qcfg_input (size:256b/32B) */ -struct hwrm_vnic_qcfg_input { +/* hwrm_queue_mpls_qcaps_input (size:192b/24B) */ +struct hwrm_queue_mpls_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21419,21 +24809,17 @@ struct hwrm_vnic_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; /* - * This bit must be '1' for the vf_id_valid field to be - * configured. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. */ - #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) - /* Logical vnic ID */ - uint32_t vnic_id; - /* ID of Virtual Function whose VNIC resource is being queried. */ - uint16_t vf_id; - uint8_t unused_0[6]; -} __attribute__((packed)); + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; -/* hwrm_vnic_qcfg_output (size:256b/32B) */ -struct hwrm_vnic_qcfg_output { +/* hwrm_queue_mpls_qcaps_output (size:128b/16B) */ +struct hwrm_queue_mpls_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21442,111 +24828,42 @@ struct hwrm_vnic_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Default Completion ring for the VNIC. */ - uint16_t dflt_ring_grp; - /* - * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if - * there is no RSS rule. - */ - uint16_t rss_rule; - /* - * RSS ID for COS rule/table structure. 0xFF... (All Fs) if - * there is no COS rule. - */ - uint16_t cos_rule; - /* - * RSS ID for load balancing rule/table structure. - * 0xFF... (All Fs) if there is no LB rule. - */ - uint16_t lb_rule; - /* The maximum receive unit of the vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* - * When this bit is '1', the VNIC is the default VNIC for - * the function. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \ - UINT32_C(0x1) - /* - * When this bit is '1', the VNIC is configured to - * strip VLAN in the RX path. - * If set to '0', then VLAN stripping is disabled on - * this VNIC. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \ - UINT32_C(0x2) - /* - * When this bit is '1', the VNIC is configured to - * buffer receive packets in the hardware until the host - * posts new receive buffers. - * If set to '0', then bd_stall is disabled on - * this VNIC. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \ - UINT32_C(0x4) - /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic. - * If set to '0', then this VNIC is not configured to - * operate in dual VNIC mode. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ - UINT32_C(0x8) - /* - * When this flag is set to '1', the VNIC is configured to - * receive only RoCE traffic. - * When this flag is set to '0', the VNIC is not configured - * to receive only RoCE traffic. - * If roce_dual_vnic_mode flag and this flag both are set - * to '1', then it is an invalid configuration of the - * VNIC. The HWRM should not allow that type of - * mis-configuration by HWRM clients. - */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ - UINT32_C(0x10) /* - * When a VNIC uses one destination ring group for certain - * application (e.g. Receive Flow Steering) where - * exact match is used to direct packets to a VNIC with one - * destination ring group only, there is no need to configure - * RSS indirection table for that VNIC as only one destination - * ring group is used. + * Bitmask indicating which queues can be configured by the + * hwrm_queue_mplstc2pri_cfg command. * - * When this bit is set to '1', then the VNIC is enabled in a - * mode where RSS is enabled in the VNIC using a RSS context - * for computing RSS hash but the RSS indirection table is - * not configured. + * Each bit represents a specific pri where bit 0 represents + * pri 0 and bit 7 represents pri 7. + * # A value of 0 indicates that the pri is not configurable + * by the hwrm_queue_mplstc2pri_cfg command. + * # A value of 1 indicates that the pri is configurable. + * # A hwrm_queue_mplstc2pri_cfg command shall return error when + * trying to configure a pri that is not configurable. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \ - UINT32_C(0x20) + uint8_t queue_mplstc2pri_cfg_allowed; /* - * When this bit is '1', the VNIC is configured to - * receive both RoCE and non-RoCE traffic, but forward only - * RoCE traffic further. Also RoCE traffic can be mirrored to - * L2 driver. + * This is the default PRI which un-initialized MPLS values will be + * mapped to. */ - #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ - UINT32_C(0x40) - uint8_t unused_1[7]; + uint8_t hw_default_pri; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************* - * hwrm_vnic_qcaps * - *******************/ +/****************************** + * hwrm_queue_mplstc2pri_qcfg * + ******************************/ -/* hwrm_vnic_qcaps_input (size:192b/24B) */ -struct hwrm_vnic_qcaps_input { +/* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21575,12 +24892,17 @@ struct hwrm_vnic_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP) to pri mapping on this port. + */ + uint8_t port_id; + uint8_t unused_0[7]; +} __rte_packed; -/* hwrm_vnic_qcaps_output (size:192b/24B) */ -struct hwrm_vnic_qcaps_output { +/* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */ +struct hwrm_queue_mplstc2pri_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21589,107 +24911,80 @@ struct hwrm_vnic_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The maximum receive unit that is settable on a vnic. */ - uint16_t mru; - uint8_t unused_0[2]; - uint32_t flags; - /* Unused. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \ - UINT32_C(0x1) - /* - * When this bit is '1', the capability of stripping VLAN in - * the RX path is supported on VNIC(s). - * If set to '0', then VLAN stripping capability is - * not supported on VNIC(s). - */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \ - UINT32_C(0x2) /* - * When this bit is '1', the capability to buffer receive - * packets in the hardware until the host posts new receive buffers - * is supported on VNIC(s). - * If set to '0', then bd_stall capability is not supported - * on VNIC(s). + * pri assigned to MPLS TC(EXP) 0. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 0. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \ - UINT32_C(0x4) + uint8_t tc0_pri_queue_id; /* - * When this bit is '1', the capability to - * receive both RoCE and non-RoCE traffic on VNIC(s) is - * supported. - * If set to '0', then the capability to receive - * both RoCE and non-RoCE traffic on VNIC(s) is - * not supported. + * pri assigned to MPLS TC(EXP) 1. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 1. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \ - UINT32_C(0x8) + uint8_t tc1_pri_queue_id; /* - * When this bit is set to '1', the capability to configure - * a VNIC to receive only RoCE traffic is supported. - * When this flag is set to '0', the VNIC capability to - * configure to receive only RoCE traffic is not supported. + * pri assigned to MPLS TC(EXP) 2. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 2. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \ - UINT32_C(0x10) + uint8_t tc2_pri_queue_id; /* - * When this bit is set to '1', then the capability to enable - * a VNIC in a mode where RSS context without configuring - * RSS indirection table is supported (for RSS hash computation). - * When this bit is set to '0', then a VNIC can not be configured - * with a mode to enable RSS context without configuring RSS - * indirection table. + * pri assigned to MPLS TC(EXP) 3. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 3. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \ - UINT32_C(0x20) + uint8_t tc3_pri_queue_id; /* - * When this bit is '1', the capability to - * mirror the the RoCE traffic is supported. - * If set to '0', then the capability to mirror the - * RoCE traffic is not supported. + * pri assigned to MPLS TC(EXP) 4. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 4. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \ - UINT32_C(0x40) + uint8_t tc4_pri_queue_id; /* - * When this bit is '1', the outermost RSS hashing capability - * is supported. If set to '0', then the outermost RSS hashing - * capability is not supported. + * pri assigned to MPLS TC(EXP) 5. This value can only be changed + * before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 5. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \ - UINT32_C(0x80) + uint8_t tc5_pri_queue_id; /* - * When this bit is '1', it indicates that firmware supports the - * ability to steer incoming packets from one CoS queue to one - * VNIC. This optional feature can then be enabled - * using HWRM_VNIC_CFG on any VNIC. This feature is only - * available when NVM option “enable_cos_classfication” is set - * to 1. If set to '0', firmware does not support this feature. + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 6. */ - #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ - UINT32_C(0x100) + uint8_t tc6_pri_queue_id; /* - * This field advertises the maximum concurrent TPA aggregations - * supported by the VNIC on new devices that support TPA v2. - * '0' means that TPA v2 is not supported. + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + * A value of 0xff indicates that no pri is assigned to the + * MPLS TC(EXP) 7. */ - uint16_t max_aggs_supported; - uint8_t unused_1[5]; + uint8_t tc7_pri_queue_id; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************* - * hwrm_vnic_tpa_cfg * - *********************/ +/***************************** + * hwrm_queue_mplstc2pri_cfg * + *****************************/ -/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ -struct hwrm_vnic_tpa_cfg_input { +/* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */ +struct hwrm_queue_mplstc2pri_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21718,158 +25013,106 @@ struct hwrm_vnic_tpa_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint32_t enables; /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * non-tunneled TCP packets. + * This bit must be '1' for the mplstc0_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \ UINT32_C(0x1) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) of - * tunneled TCP packets. + * This bit must be '1' for the mplstc1_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \ UINT32_C(0x2) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Windows Receive Segment Coalescing (RSC) rules. + * This bit must be '1' for the mplstc2_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \ UINT32_C(0x4) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) according - * to Linux Generic Receive Offload (GRO) rules. + * This bit must be '1' for the mplstc3_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \ UINT32_C(0x8) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for TCP - * packets with IP ECN set to non-zero. + * This bit must be '1' for the mplstc4_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \ UINT32_C(0x10) /* - * When this bit is '1', the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * GRE tunneled TCP packets only if all packets have the - * same GRE sequence. + * This bit must be '1' for the mplstc5_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \ UINT32_C(0x20) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP/IPv4 packets with consecutively increasing IPIDs. - * In other words, the last packet that is being - * aggregated to an already existing aggregation context - * shall have IPID 1 more than the IPID of the last packet - * that was aggregated in that aggregation context. + * This bit must be '1' for the mplstc6_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \ UINT32_C(0x40) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall be configured to - * perform transparent packet aggregation (TPA) for - * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) - * value. + * This bit must be '1' for the mplstc7_pri_queue_id field to be + * configured. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \ + #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \ UINT32_C(0x80) /* - * When this bit is '1' and the GRO mode is enabled, - * the VNIC shall DMA payload data using GRO rules. - * When this bit is '0', the VNIC shall DMA payload data - * using the more efficient LRO rules of filling all - * aggregation buffers. + * Port ID of port for which the table is being configured. + * The HWRM needs to check whether this function is allowed + * to configure MPLS TC(EXP)to pri mapping on this port. */ - #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \ - UINT32_C(0x100) - uint32_t enables; + uint8_t port_id; + uint8_t unused_0[3]; /* - * This bit must be '1' for the max_agg_segs field to be - * configured. + * pri assigned to MPLS TC(EXP) 0. This value can only + * be changed before traffic has started. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) + uint8_t tc0_pri_queue_id; /* - * This bit must be '1' for the max_aggs field to be - * configured. + * pri assigned to MPLS TC(EXP) 1. This value can only + * be changed before traffic has started. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) + uint8_t tc1_pri_queue_id; /* - * This bit must be '1' for the max_agg_timer field to be - * configured. + * pri assigned to MPLS TC(EXP) 2 This value can only + * be changed before traffic has started. */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) - /* deprecated bit. Do not use!!! */ - #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) - /* Logical vnic ID */ - uint16_t vnic_id; + uint8_t tc2_pri_queue_id; /* - * This is the maximum number of TCP segments that can - * be aggregated (unit is Log2). Max value is 31. On new - * devices supporting TPA v2, the unit is multiples of 4 and - * valid values are > 0 and <= 63. + * pri assigned to MPLS TC(EXP) 3. This value can only + * be changed before traffic has started. */ - uint16_t max_agg_segs; - /* 1 segment */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) - /* 2 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) - /* 4 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) - /* 8 segments */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) - /* Any segment size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \ - HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX + uint8_t tc3_pri_queue_id; /* - * This is the maximum number of aggregations this VNIC is - * allowed (unit is Log2). Max value is 7. On new devices - * supporting TPA v2, this is in unit of 1 and must be > 0 - * and <= max_aggs_supported in the hwrm_vnic_qcaps response - * to enable TPA v2. + * pri assigned to MPLS TC(EXP) 4. This value can only + * be changed before traffic has started. */ - uint16_t max_aggs; - /* 1 aggregation */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) - /* 2 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) - /* 4 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) - /* 8 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) - /* 16 aggregations */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) - /* Any aggregation size larger than this is not valid */ - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) - #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \ - HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX - uint8_t unused_0[2]; + uint8_t tc4_pri_queue_id; /* - * This is the maximum amount of time allowed for - * an aggregation context to complete after it was initiated. + * pri assigned to MPLS TC(EXP) 5. This value can only + * be changed before traffic has started. */ - uint32_t max_agg_timer; + uint8_t tc5_pri_queue_id; /* - * This is the minimum amount of payload length required to - * start an aggregation context. This field is deprecated and - * should be set to 0. The minimum length is set by firmware - * and can be queried using hwrm_vnic_tpa_qcfg. + * pri assigned to MPLS TC(EXP) 6. This value can only + * be changed before traffic has started. */ - uint32_t min_agg_len; -} __attribute__((packed)); + uint8_t tc6_pri_queue_id; + /* + * pri assigned to MPLS TC(EXP) 7. This value can only + * be changed before traffic has started. + */ + uint8_t tc7_pri_queue_id; +} __rte_packed; -/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ -struct hwrm_vnic_tpa_cfg_output { +/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */ +struct hwrm_queue_mplstc2pri_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -21881,21 +25124,21 @@ struct hwrm_vnic_tpa_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************* - * hwrm_vnic_rss_cfg * - *********************/ +/******************* + * hwrm_vnic_alloc * + *******************/ -/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ -struct hwrm_vnic_rss_cfg_input { +/* hwrm_vnic_alloc_input (size:192b/24B) */ +struct hwrm_vnic_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -21924,103 +25167,17 @@ struct hwrm_vnic_rss_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t hash_type; - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) - /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - /* VNIC ID of VNIC associated with RSS table being configured. */ - uint16_t vnic_id; - /* - * Specifies which VNIC ring table pair to configure. - * Valid values range from 0 to 7. - */ - uint8_t ring_table_pair_index; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; - /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ - UINT32_C(0x1) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ - UINT32_C(0x2) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ - UINT32_C(0x4) - /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. - */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ - UINT32_C(0x8) + uint32_t flags; /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * When this bit is '1', this VNIC is requested to + * be the default VNIC for this function. */ - #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ - UINT32_C(0x10) - /* This is the address for rss ring group table */ - uint64_t ring_grp_tbl_addr; - /* This is the address for rss hash key table */ - uint64_t hash_key_tbl_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t unused_1[6]; -} __attribute__((packed)); + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; -/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ -struct hwrm_vnic_rss_cfg_output { +/* hwrm_vnic_alloc_output (size:128b/16B) */ +struct hwrm_vnic_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22029,7 +25186,9 @@ struct hwrm_vnic_rss_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22038,15 +25197,15 @@ struct hwrm_vnic_rss_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************** - * hwrm_vnic_rss_qcfg * - **********************/ +/****************** + * hwrm_vnic_free * + ******************/ -/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_rss_qcfg_input { +/* hwrm_vnic_free_input (size:192b/24B) */ +struct hwrm_vnic_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22075,13 +25234,13 @@ struct hwrm_vnic_rss_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Index to the rss indirection table. */ - uint16_t rss_ctx_idx; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} __rte_packed; -/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ -struct hwrm_vnic_rss_qcfg_output { +/* hwrm_vnic_free_output (size:128b/16B) */ +struct hwrm_vnic_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22090,244 +25249,267 @@ struct hwrm_vnic_rss_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t hash_type; + uint8_t unused_0[7]; /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv4 - * packets. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + uint8_t valid; +} __rte_packed; + +/***************** + * hwrm_vnic_cfg * + *****************/ + + +/* hwrm_vnic_cfg_input (size:384b/48B) */ +struct hwrm_vnic_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of TCP/IPv4 packets. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + uint16_t cmpl_ring; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv4 addresses and - * source/destination ports of UDP/IPv4 packets. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + uint16_t seq_id; /* - * When this bit is '1', the RSS hash shall be computed - * over source and destination IPv4 addresses of IPv6 - * packets. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + uint16_t target_id; /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of TCP/IPv6 packets. - */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) - /* - * When this bit is '1', the RSS hash shall be computed - * over source/destination IPv6 addresses and - * source/destination ports of UDP/IPv6 packets. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) - uint8_t unused_0[4]; - /* This is the value of rss hash key */ - uint32_t hash_key[10]; - /* Flags to specify different RSS hash modes. */ - uint8_t hash_mode_flags; + uint64_t resp_addr; + uint32_t flags; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * When this bit is '1', the VNIC is requested to + * be the default VNIC for the function. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \ UINT32_C(0x1) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 4 tuples {l3.src, l3.dest, - * l4.src, l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * When this bit is '1', the VNIC is being configured to + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \ UINT32_C(0x2) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * When this bit is '1', the VNIC is being configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is being configured to be + * disabled on this VNIC. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \ UINT32_C(0x4) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, - * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel - * packets, the RSS hash is computed over the normal - * src/dest l3 and src/dest l4 headers. + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to be + * operating in dual VNIC mode. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ UINT32_C(0x8) /* - * When this bit is '1', it indicates requesting support of - * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for - * tunnel packets. For none-tunnel packets, the RSS hash is - * computed over the normal src/dest l3 headers. + * When this flag is set to '1', the VNIC is requested to + * be configured to receive only RoCE traffic. + * If this flag is set to '0', then this flag shall be + * ignored by the HWRM. + * If roce_dual_vnic_mode flag is set to '1' + * or roce_mirroring_capable_vnic_mode flag to 1, + * then the HWRM client shall not set this flag to '1'. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ UINT32_C(0x10) - uint8_t unused_1[6]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/************************** - * hwrm_vnic_plcmodes_cfg * - **************************/ - - -/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ -struct hwrm_vnic_plcmodes_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * This flag is used to enable a mode where + * RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured using hwrm_vnic_rss_cfg. + * + * If this mode is enabled, then the driver should not program + * RSS indirection table for the RSS context that is used for + * computing RSS hash only. */ - uint16_t target_id; + #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \ + UINT32_C(0x20) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When this bit is '1', the VNIC is being configured to + * receive both RoCE and non-RoCE traffic, but forward only the + * RoCE traffic further. Also, RoCE traffic can be mirrored to + * L2 driver. */ - uint64_t resp_addr; - uint32_t flags; + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ + UINT32_C(0x40) + uint32_t enables; /* - * When this bit is '1', the VNIC shall be configured to - * use regular placement algorithm. - * By default, the regular placement algorithm shall be - * enabled on the VNIC. + * This bit must be '1' for the dflt_ring_grp field to be + * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \ UINT32_C(0x1) /* - * When this bit is '1', the VNIC shall be configured - * use the jumbo placement algorithm. + * This bit must be '1' for the rss_rule field to be + * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \ UINT32_C(0x2) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv4 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv4, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv4, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv4 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv4 - * packet. + * This bit must be '1' for the cos_rule field to be + * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \ UINT32_C(0x4) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for IPv6 packets according - * to the following rules: - * # If the packet is identified as TCP/IPv6, then the - * packet is split at the beginning of the TCP payload. - * # If the packet is identified as UDP/IPv6, then the - * packet is split at the beginning of UDP payload. - * # If the packet is identified as non-TCP and non-UDP - * IPv6 packet, then the packet is split at the beginning - * of the upper layer protocol header carried in the IPv6 - * packet. + * This bit must be '1' for the lb_rule field to be + * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \ UINT32_C(0x8) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for FCoE packets at the - * beginning of FC payload. + * This bit must be '1' for the mru field to be + * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \ UINT32_C(0x10) /* - * When this bit is '1', the VNIC shall be configured - * to enable Header-Data split for RoCE packets at the - * beginning of RoCE payload (after BTH/GRH headers). + * This bit must be '1' for the default_rx_ring_id field to be + * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \ UINT32_C(0x20) - uint32_t enables; /* - * This bit must be '1' for the jumbo_thresh_valid field to be + * This bit must be '1' for the default_cmpl_ring_id field to be * configured. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \ - UINT32_C(0x1) + #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \ + UINT32_C(0x40) + /* This bit must be '1' for the queue_id field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \ + UINT32_C(0x80) + /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \ + UINT32_C(0x100) + /* Logical vnic ID */ + uint16_t vnic_id; /* - * This bit must be '1' for the hds_offset_valid field to be - * configured. + * Default Completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules and if + * there is no COS rule. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \ - UINT32_C(0x2) + uint16_t dflt_ring_grp; /* - * This bit must be '1' for the hds_threshold_valid field to be - * configured. + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. */ - #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ - UINT32_C(0x4) - /* Logical vnic ID */ - uint32_t vnic_id; + uint16_t rss_rule; /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. */ - uint16_t jumbo_thresh; + uint16_t cos_rule; /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* + * The maximum receive unit of the vnic. + * Each vnic is associated with a function. + * The vnic mru value overwrites the mru setting of the + * associated function. + * The HWRM shall make sure that vnic mru does not exceed + * the mru of the port the function is associated with. + */ + uint16_t mru; + /* + * Default Rx ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + * The aggregation ring associated with the Rx ring is + * implied based on the Rx ring specified when the + * aggregation ring was allocated. + */ + uint16_t default_rx_ring_id; + /* + * Default completion ring for the VNIC. This ring will + * be chosen if packet does not match any RSS rules. + */ + uint16_t default_cmpl_ring_id; + /* + * When specified, only incoming packets classified to the specified CoS + * queue ID will be arriving on this VNIC. Packet priority to CoS mapping + * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode, + * ntuple filters with VNIC destination specified are invalid since they + * conflict with the the CoS to VNIC steering rules in this mode. * - * The lengths of packet buffers provided for split data - * shall be larger than this value. + * If this field is not specified, packet to VNIC steering will be + * subject to the standard L2 filter rules and any additional ntuple + * filter rules with destination VNIC specified. */ - uint16_t hds_offset; + uint16_t queue_id; /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the two RX checksum modes supported by these + * completion records. */ - uint16_t hds_threshold; - uint8_t unused_0[6]; -} __attribute__((packed)); + uint8_t rx_csum_v2_mode; + /* + * When configured with this checksum mode, the number of header + * groups in the delivered packet with a valid IP checksum and + * the number of header groups in the delivered packet with a valid + * L4 checksum are reported. Valid checksums are counted from the + * outermost header group to the innermost header group, stopping at + * the first error. This is the default checksum mode supported if + * the driver doesn't explicitly configure the RX checksum mode. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * When configured with this checksum mode, the checksum status is + * reported using 'all ok' mode. In the RX completion record, one + * bit indicates if the IP checksum is valid for all the parsed + * header groups with an IP checksum. Another bit indicates if the + * L4 checksum is valid for all the parsed header groups with an L4 + * checksum. The number of header groups that were parsed by the + * chip and passed in the delivered packet is also reported. + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \ + HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX + uint8_t unused0[5]; +} __rte_packed; -/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ -struct hwrm_vnic_plcmodes_cfg_output { +/* hwrm_vnic_cfg_output (size:128b/16B) */ +struct hwrm_vnic_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22345,15 +25527,15 @@ struct hwrm_vnic_plcmodes_cfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*************************** - * hwrm_vnic_plcmodes_qcfg * - ***************************/ +/****************** + * hwrm_vnic_qcfg * + ******************/ -/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_input { +/* hwrm_vnic_qcfg_input (size:256b/32B) */ +struct hwrm_vnic_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22382,13 +25564,21 @@ struct hwrm_vnic_plcmodes_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the vf_id_valid field to be + * configured. + */ + #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) /* Logical vnic ID */ uint32_t vnic_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* ID of Virtual Function whose VNIC resource is being queried. */ + uint16_t vf_id; + uint8_t unused_0[6]; +} __rte_packed; -/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ -struct hwrm_vnic_plcmodes_qcfg_output { +/* hwrm_vnic_qcfg_output (size:256b/32B) */ +struct hwrm_vnic_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22397,75 +25587,126 @@ struct hwrm_vnic_plcmodes_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Default Completion ring for the VNIC. */ + uint16_t dflt_ring_grp; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if + * there is no RSS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if + * there is no COS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for load balancing rule/table structure. + * 0xFF... (All Fs) if there is no LB rule. + */ + uint16_t lb_rule; + /* The maximum receive unit of the vnic. */ + uint16_t mru; + uint8_t unused_0[2]; uint32_t flags; /* - * When this bit is '1', the VNIC is configured to - * use regular placement algorithm. + * When this bit is '1', the VNIC is the default VNIC for + * the function. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \ UINT32_C(0x1) /* * When this bit is '1', the VNIC is configured to - * use the jumbo placement algorithm. + * strip VLAN in the RX path. + * If set to '0', then VLAN stripping is disabled on + * this VNIC. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \ UINT32_C(0x2) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv4 packets. + * When this bit is '1', the VNIC is configured to + * buffer receive packets in the hardware until the host + * posts new receive buffers. + * If set to '0', then bd_stall is disabled on + * this VNIC. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \ UINT32_C(0x4) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for IPv6 packets. + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic. + * If set to '0', then this VNIC is not configured to + * operate in dual VNIC mode. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \ UINT32_C(0x8) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for FCoE packets. + * When this flag is set to '1', the VNIC is configured to + * receive only RoCE traffic. + * When this flag is set to '0', the VNIC is not configured + * to receive only RoCE traffic. + * If roce_dual_vnic_mode flag and this flag both are set + * to '1', then it is an invalid configuration of the + * VNIC. The HWRM should not allow that type of + * mis-configuration by HWRM clients. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \ UINT32_C(0x10) /* - * When this bit is '1', the VNIC is configured - * to enable Header-Data split for RoCE packets. + * When a VNIC uses one destination ring group for certain + * application (e.g. Receive Flow Steering) where + * exact match is used to direct packets to a VNIC with one + * destination ring group only, there is no need to configure + * RSS indirection table for that VNIC as only one destination + * ring group is used. + * + * When this bit is set to '1', then the VNIC is enabled in a + * mode where RSS is enabled in the VNIC using a RSS context + * for computing RSS hash but the RSS indirection table is + * not configured. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \ UINT32_C(0x20) /* - * When this bit is '1', the VNIC is configured - * to be the default VNIC of the requesting function. + * When this bit is '1', the VNIC is configured to + * receive both RoCE and non-RoCE traffic, but forward only + * RoCE traffic further. Also RoCE traffic can be mirrored to + * L2 driver. */ - #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) /* - * When jumbo placement algorithm is enabled, this value - * is used to determine the threshold for jumbo placement. - * Packets with length larger than this value will be - * placed according to the jumbo placement algorithm. + * When returned with a valid CoS Queue id, the CoS Queue/VNIC association + * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS + * queue association. */ - uint16_t jumbo_thresh; + uint16_t queue_id; /* - * This value is used to determine the offset into - * packet buffer where the split data (payload) will be - * placed according to one of of HDS placement algorithm. - * - * The lengths of packet buffers provided for split data - * shall be larger than this value. + * If the device supports the RX V2 and RX TPA start V2 completion + * records as indicated by the HWRM_VNIC_QCAPS command, this field is + * used to specify the current RX checksum mode configured for all the + * RX rings of a VNIC. */ - uint16_t hds_offset; + uint8_t rx_csum_v2_mode; /* - * When one of the HDS placement algorithm is enabled, this - * value is used to determine the threshold for HDS - * placement. - * Packets with length larger than this value will be - * placed according to the HDS placement algorithm. - * This value shall be in multiple of 4 bytes. + * This value indicates that the VNIC is configured to use the + * default RX checksum mode for all the rings associated with this + * VNIC. */ - uint16_t hds_threshold; - uint8_t unused_0[5]; + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0) + /* + * This value indicates that the VNIC is configured to use the RX + * checksum ‘all_ok’ mode for all the rings associated with this + * VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1) + /* + * Any rx_csum_v2_mode value larger than or equal to this is not + * valid + */ + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX + uint8_t unused_1[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22474,15 +25715,15 @@ struct hwrm_vnic_plcmodes_qcfg_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************************** - * hwrm_vnic_rss_cos_lb_ctx_alloc * - **********************************/ +/******************* + * hwrm_vnic_qcaps * + *******************/ -/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { +/* hwrm_vnic_qcaps_input (size:192b/24B) */ +struct hwrm_vnic_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22511,10 +25752,12 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); + uint32_t enables; + uint8_t unused_0[4]; +} __rte_packed; -/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { +/* hwrm_vnic_qcaps_output (size:192b/24B) */ +struct hwrm_vnic_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22523,70 +25766,101 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[5]; + /* The maximum receive unit that is settable on a vnic. */ + uint16_t mru; + uint8_t unused_0[2]; + uint32_t flags; + /* Unused. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \ + UINT32_C(0x1) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When this bit is '1', the capability of stripping VLAN in + * the RX path is supported on VNIC(s). + * If set to '0', then VLAN stripping capability is + * not supported on VNIC(s). */ - uint8_t valid; -} __attribute__((packed)); - -/********************************* - * hwrm_vnic_rss_cos_lb_ctx_free * - *********************************/ - - -/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \ + UINT32_C(0x2) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * When this bit is '1', the capability to buffer receive + * packets in the hardware until the host posts new receive buffers + * is supported on VNIC(s). + * If set to '0', then bd_stall capability is not supported + * on VNIC(s). */ - uint16_t cmpl_ring; + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \ + UINT32_C(0x4) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * When this bit is '1', the capability to + * receive both RoCE and non-RoCE traffic on VNIC(s) is + * supported. + * If set to '0', then the capability to receive + * both RoCE and non-RoCE traffic on VNIC(s) is + * not supported. */ - uint16_t seq_id; + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \ + UINT32_C(0x8) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * When this bit is set to '1', the capability to configure + * a VNIC to receive only RoCE traffic is supported. + * When this flag is set to '0', the VNIC capability to + * configure to receive only RoCE traffic is not supported. */ - uint16_t target_id; + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \ + UINT32_C(0x10) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When this bit is set to '1', then the capability to enable + * a VNIC in a mode where RSS context without configuring + * RSS indirection table is supported (for RSS hash computation). + * When this bit is set to '0', then a VNIC can not be configured + * with a mode to enable RSS context without configuring RSS + * indirection table. */ - uint64_t resp_addr; - /* rss_cos_lb_ctx_id is 16 b */ - uint16_t rss_cos_lb_ctx_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ -struct hwrm_vnic_rss_cos_lb_ctx_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \ + UINT32_C(0x20) + /* + * When this bit is '1', the capability to + * mirror the the RoCE traffic is supported. + * If set to '0', then the capability to mirror the + * RoCE traffic is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \ + UINT32_C(0x40) + /* + * When this bit is '1', the outermost RSS hashing capability + * is supported. If set to '0', then the outermost RSS hashing + * capability is not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \ + UINT32_C(0x80) + /* + * When this bit is '1', it indicates that firmware supports the + * ability to steer incoming packets from one CoS queue to one + * VNIC. This optional feature can then be enabled + * using HWRM_VNIC_CFG on any VNIC. This feature is only + * available when NVM option “enable_cos_classfication” is set + * to 1. If set to '0', firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that HW and firmware supports + * the use of RX V2 and RX TPA start V2 completion records for all + * the RX rings of a VNIC. Once set, this feature is mandatory to + * be used for the RX rings of the VNIC. Additionally, two new RX + * checksum features supported by these ompletion records can be + * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the + * HW and the firmware does not support this feature. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \ + UINT32_C(0x200) + /* + * This field advertises the maximum concurrent TPA aggregations + * supported by the VNIC on new devices that support TPA v2. + * '0' means that TPA v2 is not supported. + */ + uint16_t max_aggs_supported; + uint8_t unused_1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22595,15 +25869,15 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************* - * hwrm_ring_alloc * - *******************/ +/********************* + * hwrm_vnic_tpa_cfg * + *********************/ -/* hwrm_ring_alloc_input (size:704b/88B) */ -struct hwrm_ring_alloc_input { +/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ +struct hwrm_vnic_tpa_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22632,286 +25906,158 @@ struct hwrm_ring_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the ring_arb_cfg field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \ - UINT32_C(0x2) - /* - * This bit must be '1' for the stat_ctx_id_valid field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \ - UINT32_C(0x8) - /* - * This bit must be '1' for the max_bw_valid field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the rx_ring_id field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the nq_ring_id field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \ - UINT32_C(0x80) - /* - * This bit must be '1' for the rx_buf_size field to be - * configured. - */ - #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ - UINT32_C(0x100) - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ - HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ - uint8_t unused_0; - /* Ring allocation flags. */ - uint16_t flags; - /* - * For Rx rings, the incoming packet data can be placed at either - * a 0B or 2B offset from the start of the Rx packet buffer. When - * '1', the received packet will be padded with 2B of zeros at the - * front of the packet. Note that this flag is only used for - * Rx rings and is ignored for all other rings included Rx - * Aggregation rings. - */ - #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) - /* - * This value is a pointer to the page table for the - * Ring. - */ - uint64_t page_tbl_addr; - /* First Byte Offset of the first entry in the first page. */ - uint32_t fbo; - /* - * Actual page size in 2^page_size. The supported range is increments - * in powers of 2 from 16 bytes to 1GB. - * - 4 = 16 B - * Page size is 16 B. - * - 12 = 4 KB - * Page size is 4 KB. - * - 13 = 8 KB - * Page size is 8 KB. - * - 16 = 64 KB - * Page size is 64 KB. - * - 21 = 2 MB - * Page size is 2 MB. - * - 22 = 4 MB - * Page size is 4 MB. - * - 30 = 1 GB - * Page size is 1 GB. - */ - uint8_t page_size; - /* - * This value indicates the depth of page table. - * For this version of the specification, value other than 0 or - * 1 shall be considered as an invalid value. - * When the page_tbl_depth = 0, then it is treated as a - * special case with the following. - * 1. FBO and page size fields are not valid. - * 2. page_tbl_addr is the physical address of the first - * element of the ring. - */ - uint8_t page_tbl_depth; - uint8_t unused_1[2]; - /* - * Number of 16B units in the ring. Minimum size for - * a ring is 16 16B entries. - */ - uint32_t length; + uint32_t flags; /* - * Logical ring number for the ring to be allocated. - * This value determines the position in the doorbell - * area where the update to the ring will be made. - * - * For completion rings, this value is also the MSI-X - * vector number for the function the completion ring is - * associated with. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * non-tunneled TCP packets. */ - uint16_t logical_id; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \ + UINT32_C(0x1) /* - * This field is used only when ring_type is a TX ring. - * This value indicates what completion ring the TX ring - * is associated with. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) of + * tunneled TCP packets. */ - uint16_t cmpl_ring_id; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \ + UINT32_C(0x2) /* - * This field is used only when ring_type is a TX ring. - * This value indicates what CoS queue the TX ring - * is associated with. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Windows Receive Segment Coalescing (RSC) rules. */ - uint16_t queue_id; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \ + UINT32_C(0x4) /* - * When allocating a Rx ring or Rx aggregation ring, this field - * specifies the size of the buffer descriptors posted to the ring. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) according + * to Linux Generic Receive Offload (GRO) rules. */ - uint16_t rx_buf_size; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \ + UINT32_C(0x8) /* - * When allocating an Rx aggregation ring, this field - * specifies the associated Rx ring ID. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for TCP + * packets with IP ECN set to non-zero. */ - uint16_t rx_ring_id; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \ + UINT32_C(0x10) /* - * When allocating a completion ring, this field - * specifies the associated NQ ring ID. + * When this bit is '1', the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * GRE tunneled TCP packets only if all packets have the + * same GRE sequence. */ - uint16_t nq_ring_id; + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \ + UINT32_C(0x20) /* - * This field is used only when ring_type is a TX ring. - * This field is used to configure arbitration related - * parameters for a TX ring. + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. + * In other words, the last packet that is being + * aggregated to an already existing aggregation context + * shall have IPID 1 more than the IPID of the last packet + * that was aggregated in that aggregation context. */ - uint16_t ring_arb_cfg; - /* Arbitration policy used for the ring. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \ - UINT32_C(0xf) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \ + UINT32_C(0x40) /* - * Use strict priority for the TX ring. - * Priority value is specified in arb_policy_param + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall be configured to + * perform transparent packet aggregation (TPA) for + * TCP packets with the same TTL (IPv4) or Hop limit (IPv6) + * value. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \ - UINT32_C(0x1) + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \ + UINT32_C(0x80) /* - * Use weighted fair queue arbitration for the TX ring. - * Weight is specified in arb_policy_param + * When this bit is '1' and the GRO mode is enabled, + * the VNIC shall DMA payload data using GRO rules. + * When this bit is '0', the VNIC shall DMA payload data + * using the more efficient LRO rules of filling all + * aggregation buffers. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \ - UINT32_C(0x2) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \ - HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ - /* Reserved field. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \ - UINT32_C(0xf0) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \ + UINT32_C(0x100) + uint32_t enables; /* - * Arbitration policy specific parameter. - * # For strict priority arbitration policy, this field - * represents a priority value. If set to 0, then the priority - * is not specified and the HWRM is allowed to select - * any priority for this TX ring. - * # For weighted fair queue arbitration policy, this field - * represents a weight value. If set to 0, then the weight - * is not specified and the HWRM is allowed to select - * any weight for this TX ring. + * This bit must be '1' for the max_agg_segs field to be + * configured. */ - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \ - UINT32_C(0xff00) - #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 - uint16_t unused_3; + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) /* - * This field is reserved for the future use. - * It shall be set to 0. + * This bit must be '1' for the max_aggs field to be + * configured. */ - uint32_t reserved3; + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) /* - * This field is used only when ring_type is a TX ring. - * This input indicates what statistics context this ring - * should be associated with. + * This bit must be '1' for the max_agg_timer field to be + * configured. */ - uint32_t stat_ctx_id; + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) + /* deprecated bit. Do not use!!! */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) + /* Logical vnic ID */ + uint16_t vnic_id; /* - * This field is reserved for the future use. - * It shall be set to 0. + * This is the maximum number of TCP segments that can + * be aggregated (unit is Log2). Max value is 31. On new + * devices supporting TPA v2, the unit is multiples of 4 and + * valid values are > 0 and <= 63. */ - uint32_t reserved4; + uint16_t max_agg_segs; + /* 1 segment */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \ + HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX /* - * This field is used only when ring_type is a TX ring - * to specify maximum BW allocated to the TX ring. - * The HWRM will translate this value into byte counter and - * time interval used for this ring inside the device. + * This is the maximum number of aggregations this VNIC is + * allowed (unit is Log2). Max value is 7. On new devices + * supporting TPA v2, this is in unit of 1 and must be > 0 + * and <= max_aggs_supported in the hwrm_vnic_qcaps response + * to enable TPA v2. */ - uint32_t max_bw; - /* The bandwidth value. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \ - HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ - HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + uint16_t max_aggs; + /* 1 aggregation */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \ + HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX + uint8_t unused_0[2]; /* - * This field is used only when ring_type is a Completion ring. - * This value indicates what interrupt mode should be used - * on this completion ring. - * Note: In the legacy interrupt mode, no more than 16 - * completion rings are allowed. + * This is the maximum amount of time allowed for + * an aggregation context to complete after it was initiated. */ - uint8_t int_mode; - /* Legacy INTA */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) - /* Reserved */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) - /* MSI-X */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) - /* No Interrupt - Polled mode */ - #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) - #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ - HWRM_RING_ALLOC_INPUT_INT_MODE_POLL - uint8_t unused_4[3]; + uint32_t max_agg_timer; /* - * The cq_handle is specified when allocating a completion ring. For - * devices that support NQs, this cq_handle will be included in the - * NQE to specify which CQ should be read to retrieve the completion - * record. + * This is the minimum amount of payload length required to + * start an aggregation context. This field is deprecated and + * should be set to 0. The minimum length is set by firmware + * and can be queried using hwrm_vnic_tpa_qcfg. */ - uint64_t cq_handle; -} __attribute__((packed)); + uint32_t min_agg_len; +} __rte_packed; -/* hwrm_ring_alloc_output (size:128b/16B) */ -struct hwrm_ring_alloc_output { +/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ +struct hwrm_vnic_tpa_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22920,14 +26066,7 @@ struct hwrm_ring_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * Physical number of ring allocated. - * This value shall be unique for a ring type. - */ - uint16_t ring_id; - /* Logical number of ring allocated. */ - uint16_t logical_ring_id; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -22936,15 +26075,15 @@ struct hwrm_ring_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************** - * hwrm_ring_free * - ******************/ +/********************* + * hwrm_vnic_rss_cfg * + *********************/ -/* hwrm_ring_free_input (size:192b/24B) */ -struct hwrm_ring_free_input { +/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ +struct hwrm_vnic_rss_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22973,104 +26112,103 @@ struct hwrm_ring_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - /* RX Aggregation Ring */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) - /* Notification Queue */ - #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) - #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ - HWRM_RING_FREE_INPUT_RING_TYPE_NQ - uint8_t unused_0; - /* Physical number of ring allocated. */ - uint16_t ring_id; - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_ring_free_output (size:128b/16B) */ -struct hwrm_ring_free_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t hash_type; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - uint8_t valid; -} __attribute__((packed)); - -/******************* - * hwrm_ring_reset * - *******************/ - - -/* hwrm_ring_reset_input (size:192b/24B) */ -struct hwrm_ring_reset_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - uint16_t cmpl_ring; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - uint16_t seq_id; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. */ - uint16_t target_id; + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - uint64_t resp_addr; - /* Ring Type. */ - uint8_t ring_type; - /* L2 Completion Ring (CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) - /* TX Ring (TR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) - /* RX Ring (RR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) - /* RoCE Notification Completion Ring (ROCE_CR) */ - #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) - #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ - HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL - uint8_t unused_0; - /* Physical number of the ring. */ - uint16_t ring_id; - uint8_t unused_1[4]; -} __attribute__((packed)); + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + /* VNIC ID of VNIC associated with RSS table being configured. */ + uint16_t vnic_id; + /* + * Specifies which VNIC ring table pair to configure. + * Valid values range from 0 to 7. + */ + uint8_t ring_table_pair_index; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; + /* + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + /* This is the address for rss ring group table */ + uint64_t ring_grp_tbl_addr; + /* This is the address for rss hash key table */ + uint64_t hash_key_tbl_addr; + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; + uint8_t unused_1[6]; +} __rte_packed; -/* hwrm_ring_reset_output (size:128b/16B) */ -struct hwrm_ring_reset_output { +/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ +struct hwrm_vnic_rss_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23079,9 +26217,7 @@ struct hwrm_ring_reset_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[4]; - /* Position of consumer index after ring reset completes. */ - uint8_t consumer_idx[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -23090,15 +26226,36 @@ struct hwrm_ring_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************** - * hwrm_ring_aggint_qcaps * - **************************/ +/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ +struct hwrm_vnic_rss_cfg_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* + * Unable to change global RSS mode to outer due to all active + * interfaces are not ready to support outer RSS hashing. + */ + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \ + UINT32_C(0x1) + #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \ + HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY + uint8_t unused_0[7]; +} __rte_packed; +/********************** + * hwrm_vnic_rss_qcfg * + **********************/ -/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ -struct hwrm_ring_aggint_qcaps_input { + +/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_rss_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23127,10 +26284,13 @@ struct hwrm_ring_aggint_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); + /* Index to the rss indirection table. */ + uint16_t rss_ctx_idx; + uint8_t unused_0[6]; +} __rte_packed; -/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ -struct hwrm_ring_aggint_qcaps_output { +/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ +struct hwrm_vnic_rss_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23139,99 +26299,89 @@ struct hwrm_ring_aggint_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t cmpl_params; + uint32_t hash_type; /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on completion rings. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv4 + * packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ - UINT32_C(0x1) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) /* - * When this bit is set to '1', int_lat_tmr_max can be configured - * on completion rings. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ - UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) /* - * When this bit is set to '1', timer_reset can be enabled - * on completion rings. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv4 addresses and + * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ - UINT32_C(0x4) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) /* - * When this bit is set to '1', ring_idle can be enabled - * on completion rings. + * When this bit is '1', the RSS hash shall be computed + * over source and destination IPv4 addresses of IPv6 + * packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ - UINT32_C(0x8) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) /* - * When this bit is set to '1', num_cmpl_dma_aggr can be configured - * on completion rings. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ - UINT32_C(0x10) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) /* - * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured - * on completion rings. + * When this bit is '1', the RSS hash shall be computed + * over source/destination IPv6 addresses and + * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ - UINT32_C(0x20) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + uint8_t unused_0[4]; + /* This is the value of rss hash key */ + uint32_t hash_key[10]; + /* Flags to specify different RSS hash modes. */ + uint8_t hash_mode_flags; /* - * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured - * on completion rings. + * When this bit is '1', it indicates using current RSS + * hash mode setting configured in the device. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ - UINT32_C(0x40) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ + UINT32_C(0x1) /* - * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured - * on completion rings. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 4 tuples {l3.src, l3.dest, + * l4.src, l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ - UINT32_C(0x80) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \ + UINT32_C(0x2) /* - * When this bit is set to '1', num_cmpl_aggr_int can be configured - * on completion rings. + * When this bit is '1', it indicates requesting support of + * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ - UINT32_C(0x100) - uint32_t nq_params; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \ + UINT32_C(0x4) /* - * When this bit is set to '1', int_lat_tmr_min can be configured - * on notification queues. + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest, + * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel + * packets, the RSS hash is computed over the normal + * src/dest l3 and src/dest l4 headers. */ - #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ - UINT32_C(0x1) - /* Minimum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_min; - /* Maximum value for num_cmpl_dma_aggr */ - uint16_t num_cmpl_dma_aggr_max; - /* Minimum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_min; - /* Maximum value for num_cmpl_dma_aggr_during_int */ - uint16_t num_cmpl_dma_aggr_during_int_max; - /* Minimum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_min; - /* Maximum value for cmpl_aggr_dma_tmr */ - uint16_t cmpl_aggr_dma_tmr_max; - /* Minimum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_min; - /* Maximum value for cmpl_aggr_dma_tmr_during_int */ - uint16_t cmpl_aggr_dma_tmr_during_int_max; - /* Minimum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_min; - /* Maximum value for int_lat_tmr_min */ - uint16_t int_lat_tmr_min_max; - /* Minimum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_min; - /* Maximum value for int_lat_tmr_max */ - uint16_t int_lat_tmr_max_max; - /* Minimum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_min; - /* Maximum value for num_cmpl_aggr_int */ - uint16_t num_cmpl_aggr_int_max; - /* The units for timer parameters, in nanoseconds. */ - uint16_t timer_units; - uint8_t unused_0[1]; + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates requesting support of + * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for + * tunnel packets. For none-tunnel packets, the RSS hash is + * computed over the normal src/dest l3 headers. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \ + UINT32_C(0x10) + uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -23240,15 +26390,15 @@ struct hwrm_ring_aggint_qcaps_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************************** - * hwrm_ring_cmpl_ring_qaggint_params * - **************************************/ +/************************** + * hwrm_vnic_plcmodes_cfg * + **************************/ -/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_input { +/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ +struct hwrm_vnic_plcmodes_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23277,85 +26427,170 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ -struct hwrm_ring_cmpl_ring_qaggint_params_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint16_t flags; + uint32_t flags; /* - * When this bit is set to '1', interrupt max - * timer is reset whenever a completion is received. + * When this bit is '1', the VNIC shall be configured to + * use regular placement algorithm. + * By default, the regular placement algorithm shall be + * enabled on the VNIC. */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \ UINT32_C(0x1) /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. + * When this bit is '1', the VNIC shall be configured + * use the jumbo placement algorithm. */ - #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \ UINT32_C(0x2) /* - * Number of completions to aggregate before DMA - * during the normal mode. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv4 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv4, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv4, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv4 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv4 + * packet. */ - uint16_t num_cmpl_dma_aggr; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \ + UINT32_C(0x4) /* - * Number of completions to aggregate before DMA - * during the interrupt mode. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for IPv6 packets according + * to the following rules: + * # If the packet is identified as TCP/IPv6, then the + * packet is split at the beginning of the TCP payload. + * # If the packet is identified as UDP/IPv6, then the + * packet is split at the beginning of UDP payload. + * # If the packet is identified as non-TCP and non-UDP + * IPv6 packet, then the packet is split at the beginning + * of the upper layer protocol header carried in the IPv6 + * packet. */ - uint16_t num_cmpl_dma_aggr_during_int; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \ + UINT32_C(0x8) /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for FCoE packets at the + * beginning of FC payload. */ - uint16_t cmpl_aggr_dma_tmr; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \ + UINT32_C(0x10) /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. + * When this bit is '1', the VNIC shall be configured + * to enable Header-Data split for RoCE packets at the + * beginning of RoCE payload (after BTH/GRH headers). */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \ + UINT32_C(0x20) /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * completions before signaling the interrupt after the - * interrupt is enabled. + * When this bit is '1', the VNIC shall be configured use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. */ - uint16_t int_lat_tmr_max; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \ + UINT32_C(0x40) + uint32_t enables; /* - * Minimum number of completions aggregated before signaling - * an interrupt. + * This bit must be '1' for the jumbo_thresh_valid field to be + * configured. */ - uint16_t num_cmpl_aggr_int; + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the hds_offset_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the hds_threshold_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the max_bds_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \ + UINT32_C(0x8) + /* Logical vnic ID */ + uint32_t vnic_id; + /* + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. + */ + uint16_t jumbo_thresh; + /* + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of HDS placement algorithm. + * + * The lengths of packet buffers provided for split data + * shall be larger than this value. + */ + uint16_t hds_offset; + /* + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. + */ + uint16_t hds_threshold; + /* + * When virtio placement algorithm is enabled, this + * value is used to determine the the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is + * supported on the function. + */ + uint16_t max_bds; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ +struct hwrm_vnic_plcmodes_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/***************************************** - * hwrm_ring_cmpl_ring_cfg_aggint_params * - *****************************************/ +/*************************** + * hwrm_vnic_plcmodes_qcfg * + ***************************/ -/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { +/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */ +struct hwrm_vnic_plcmodes_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23384,135 +26619,129 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Physical number of completion ring. */ - uint16_t ring_id; - uint16_t flags; + /* Logical vnic ID */ + uint32_t vnic_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */ +struct hwrm_vnic_plcmodes_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; /* - * When this bit is set to '1', interrupt latency max - * timer is reset whenever a completion is received. + * When this bit is '1', the VNIC is configured to + * use regular placement algorithm. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \ UINT32_C(0x1) /* - * When this bit is set to '1', ring idle mode - * aggregation will be enabled. + * When this bit is '1', the VNIC is configured to + * use the jumbo placement algorithm. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \ UINT32_C(0x2) /* - * Set this flag to 1 when configuring parameters on a - * notification queue. Set this flag to 0 when configuring - * parameters on a completion queue. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv4 packets. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \ UINT32_C(0x4) /* - * Number of completions to aggregate before DMA - * during the normal mode. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for IPv6 packets. */ - uint16_t num_cmpl_dma_aggr; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \ + UINT32_C(0x8) /* - * Number of completions to aggregate before DMA - * during the interrupt mode. + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for FCoE packets. */ - uint16_t num_cmpl_dma_aggr_during_int; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \ + UINT32_C(0x10) /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the normal mode (not in interrupt mode). + * When this bit is '1', the VNIC is configured + * to enable Header-Data split for RoCE packets. */ - uint16_t cmpl_aggr_dma_tmr; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \ + UINT32_C(0x20) /* - * Timer in unit of 80-nsec used to aggregate completions before - * DMA during the interrupt mode. + * When this bit is '1', the VNIC is configured + * to be the default VNIC of the requesting function. */ - uint16_t cmpl_aggr_dma_tmr_during_int; - /* Minimum time (in unit of 80-nsec) between two interrupts. */ - uint16_t int_lat_tmr_min; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \ + UINT32_C(0x40) /* - * Maximum wait time (in unit of 80-nsec) spent aggregating - * cmpls before signaling the interrupt after the - * interrupt is enabled. + * When this bit is '1', the VNIC is configured to use the virtio + * placement algorithm. This feature can only be configured when + * proxy mode is supported on the function. */ - uint16_t int_lat_tmr_max; + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \ + UINT32_C(0x80) /* - * Minimum number of completions aggregated before signaling - * an interrupt. + * When jumbo placement algorithm is enabled, this value + * is used to determine the threshold for jumbo placement. + * Packets with length larger than this value will be + * placed according to the jumbo placement algorithm. */ - uint16_t num_cmpl_aggr_int; - /* - * Bitfield that indicates which parameters are to be applied. Only - * required when configuring devices with notification queues, and - * used in that case to set certain parameters on completion queues - * and others on notification queues. - */ - uint16_t enables; - /* - * This bit must be '1' for the num_cmpl_dma_aggr field to be - * configured. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \ - UINT32_C(0x1) - /* - * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be - * configured. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \ - UINT32_C(0x2) - /* - * This bit must be '1' for the cmpl_aggr_dma_tmr field to be - * configured. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \ - UINT32_C(0x4) + uint16_t jumbo_thresh; /* - * This bit must be '1' for the int_lat_tmr_min field to be - * configured. + * This value is used to determine the offset into + * packet buffer where the split data (payload) will be + * placed according to one of HDS placement algorithm. + * + * The lengths of packet buffers provided for split data + * shall be larger than this value. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \ - UINT32_C(0x8) + uint16_t hds_offset; /* - * This bit must be '1' for the int_lat_tmr_max field to be - * configured. + * When one of the HDS placement algorithm is enabled, this + * value is used to determine the threshold for HDS + * placement. + * Packets with length larger than this value will be + * placed according to the HDS placement algorithm. + * This value shall be in multiple of 4 bytes. */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \ - UINT32_C(0x10) + uint16_t hds_threshold; /* - * This bit must be '1' for the num_cmpl_aggr_int field to be - * configured. - */ - #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ - UINT32_C(0x20) - uint8_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ -struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + * When virtio placement algorithm is enabled, this + * value is used to determine the the maximum number of BDs + * that can be used to place an Rx Packet. + * If an incoming packet does not fit in the buffers described + * by the max BDs, the packet will be dropped and an error + * will be reported in the completion. Valid values for this + * field are between 1 and 8. If the VNIC uses header-data- + * separation and/or TPA with buffer spanning enabled, valid + * values for this field are between 2 and 8. + * This feature can only be configured when proxy mode is supported + * on the function + */ + uint16_t max_bds; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*********************** - * hwrm_ring_grp_alloc * - ***********************/ +/********************************** + * hwrm_vnic_rss_cos_lb_ctx_alloc * + **********************************/ -/* hwrm_ring_grp_alloc_input (size:192b/24B) */ -struct hwrm_ring_grp_alloc_input { +/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23541,31 +26770,10 @@ struct hwrm_ring_grp_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * This value identifies the CR associated with the ring - * group. - */ - uint16_t cr; - /* - * This value identifies the main RR associated with the ring - * group. - */ - uint16_t rr; - /* - * This value identifies the aggregation RR associated with - * the ring group. If this value is 0xFF... (All Fs), then no - * Aggregation ring will be set. - */ - uint16_t ar; - /* - * This value identifies the statistics context associated - * with the ring group. - */ - uint16_t sc; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_ring_grp_alloc_output (size:128b/16B) */ -struct hwrm_ring_grp_alloc_output { +/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23574,13 +26782,9 @@ struct hwrm_ring_grp_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* - * This is the ring group ID value. Use this value to program - * the default ring group for the VNIC or as table entries - * in an RSS/COS context. - */ - uint32_t ring_group_id; - uint8_t unused_0[3]; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -23589,15 +26793,15 @@ struct hwrm_ring_grp_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************** - * hwrm_ring_grp_free * - **********************/ +/********************************* + * hwrm_vnic_rss_cos_lb_ctx_free * + *********************************/ -/* hwrm_ring_grp_free_input (size:192b/24B) */ -struct hwrm_ring_grp_free_input { +/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ +struct hwrm_vnic_rss_cos_lb_ctx_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23626,13 +26830,13 @@ struct hwrm_ring_grp_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This is the ring group ID value. */ - uint32_t ring_group_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t rss_cos_lb_ctx_id; + uint8_t unused_0[6]; +} __rte_packed; -/* hwrm_ring_grp_free_output (size:128b/16B) */ -struct hwrm_ring_grp_free_output { +/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ +struct hwrm_vnic_rss_cos_lb_ctx_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -23650,35 +26854,15 @@ struct hwrm_ring_grp_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); -/* - * special reserved flow ID to identify per function default - * flows for vSwitch offload - */ -#define DEFAULT_FLOW_ID 0xFFFFFFFFUL -/* - * special reserved flow ID to identify per function RoCEv1 - * flows - */ -#define ROCEV1_FLOW_ID 0xFFFFFFFEUL -/* - * special reserved flow ID to identify per function RoCEv2 - * flows - */ -#define ROCEV2_FLOW_ID 0xFFFFFFFDUL -/* - * special reserved flow ID to identify per function RoCEv2 - * CNP flows - */ -#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL +} __rte_packed; -/**************************** - * hwrm_cfa_l2_filter_alloc * - ****************************/ +/******************* + * hwrm_ring_alloc * + *******************/ -/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ -struct hwrm_cfa_l2_filter_alloc_input { +/* hwrm_ring_alloc_input (size:704b/88B) */ +struct hwrm_ring_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -23707,385 +26891,6052 @@ struct hwrm_cfa_l2_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \ - UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x2) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ - UINT32_C(0x4) - /* - * If this flag is set, all t_l2_* fields are invalid - * and they should not be specified. - * If this flag is set, then l2_* fields refer to - * fields of outermost L2 header. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ - UINT32_C(0x8) - /* - * Enumeration denoting NO_ROCE_L2 to support old drivers. - * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \ - UINT32_C(0x30) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 - /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ - (UINT32_C(0x0) << 4) - /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \ - (UINT32_C(0x1) << 4) - /* Roce & L2 traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \ - (UINT32_C(0x2) << 4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE - /* - * Setting of this flag indicates that no XDP filter is created with - * L2 filter. - * 0 - legacy behavior, XDP filter is created with L2 filter - * 1 - XDP filter won't be created with L2 filter - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \ - UINT32_C(0x40) - /* - * Setting this flag to 1 indicate the L2 fields in this command - * pertain to source fields. Setting this flag to 0 indicate the - * L2 fields in this command pertain to the destination fields - * and this is the default/legacy behavior. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \ - UINT32_C(0x80) uint32_t enables; /* - * This bit must be '1' for the l2_addr field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ - UINT32_C(0x1) - /* - * This bit must be '1' for the l2_addr_mask field to be + * This bit must be '1' for the ring_arb_cfg field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \ UINT32_C(0x2) /* - * This bit must be '1' for the l2_ovlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \ - UINT32_C(0x4) - /* - * This bit must be '1' for the l2_ovlan_mask field to be + * This bit must be '1' for the stat_ctx_id_valid field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \ UINT32_C(0x8) /* - * This bit must be '1' for the l2_ivlan field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ - UINT32_C(0x10) - /* - * This bit must be '1' for the l2_ivlan_mask field to be + * This bit must be '1' for the max_bw_valid field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \ UINT32_C(0x20) /* - * This bit must be '1' for the t_l2_addr field to be + * This bit must be '1' for the rx_ring_id field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \ UINT32_C(0x40) /* - * This bit must be '1' for the t_l2_addr_mask field to be + * This bit must be '1' for the nq_ring_id field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \ UINT32_C(0x80) /* - * This bit must be '1' for the t_l2_ovlan field to be + * This bit must be '1' for the rx_buf_size field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \ UINT32_C(0x100) /* - * This bit must be '1' for the t_l2_ovlan_mask field to be + * This bit must be '1' for the sq_id field to be * configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \ + #define HWRM_RING_ALLOC_INPUT_ENABLES_SQ_ID \ UINT32_C(0x200) + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \ + HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ + uint8_t unused_0; + /* Ring allocation flags. */ + uint16_t flags; /* - * This bit must be '1' for the t_l2_ivlan field to be - * configured. + * For Rx rings, the incoming packet data can be placed at either + * a 0B or 2B offset from the start of the Rx packet buffer. When + * '1', the received packet will be padded with 2B of zeros at the + * front of the packet. Note that this flag is only used for + * Rx rings and is ignored for all other rings included Rx + * Aggregation rings. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \ - UINT32_C(0x400) + #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1) /* - * This bit must be '1' for the t_l2_ivlan_mask field to be - * configured. + * This value is a pointer to the page table for the + * Ring. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \ - UINT32_C(0x800) + uint64_t page_tbl_addr; + /* First Byte Offset of the first entry in the first page. */ + uint32_t fbo; /* - * This bit must be '1' for the src_type field to be - * configured. + * Actual page size in 2^page_size. The supported range is increments + * in powers of 2 from 16 bytes to 1GB. + * - 4 = 16 B + * Page size is 16 B. + * - 12 = 4 KB + * Page size is 4 KB. + * - 13 = 8 KB + * Page size is 8 KB. + * - 16 = 64 KB + * Page size is 64 KB. + * - 21 = 2 MB + * Page size is 2 MB. + * - 22 = 4 MB + * Page size is 4 MB. + * - 30 = 1 GB + * Page size is 1 GB. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \ - UINT32_C(0x1000) + uint8_t page_size; /* - * This bit must be '1' for the src_id field to be - * configured. + * This value indicates the depth of page table. + * For this version of the specification, value other than 0 or + * 1 shall be considered as an invalid value. + * When the page_tbl_depth = 0, then it is treated as a + * special case with the following. + * 1. FBO and page size fields are not valid. + * 2. page_tbl_addr is the physical address of the first + * element of the ring. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \ - UINT32_C(0x2000) + uint8_t page_tbl_depth; + /* Used by a PF driver to associate a SQ with one of its TX rings. */ + uint16_t sq_id; /* - * This bit must be '1' for the tunnel_type field to be - * configured. + * Number of 16B units in the ring. Minimum size for + * a ring is 16 16B entries. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x4000) + uint32_t length; /* - * This bit must be '1' for the dst_id field to be - * configured. + * Logical ring number for the ring to be allocated. + * This value determines the position in the doorbell + * area where the update to the ring will be made. + * + * For completion rings, this value is also the MSI-X + * vector number for the function the completion ring is + * associated with. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x8000) + uint16_t logical_id; /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. + * This field is used only when ring_type is a TX ring. + * This value indicates what completion ring the TX ring + * is associated with. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x10000) + uint16_t cmpl_ring_id; /* - * This bit must be '1' for the num_vlans field to be - * configured. + * This field is used only when ring_type is a TX ring. + * This value indicates what CoS queue the TX ring + * is associated with. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \ - UINT32_C(0x20000) + uint16_t queue_id; /* - * This bit must be '1' for the t_num_vlans field to be - * configured. + * When allocating a Rx ring or Rx aggregation ring, this field + * specifies the size of the buffer descriptors posted to the ring. */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \ - UINT32_C(0x40000) + uint16_t rx_buf_size; /* - * This value sets the match value for the L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. + * When allocating an Rx aggregation ring, this field + * specifies the associated Rx ring ID. */ - uint8_t l2_addr[6]; - /* This value sets the match value for the number of VLANs. */ - uint8_t num_vlans; + uint16_t rx_ring_id; /* - * This value sets the match value for the number of VLANs - * in the tunnel headers. + * When allocating a completion ring, this field + * specifies the associated NQ ring ID. */ - uint8_t t_num_vlans; + uint16_t nq_ring_id; /* - * This value sets the mask value for the L2 address. - * A value of 0 will mask the corresponding bit from - * compare. + * This field is used only when ring_type is a TX ring. + * This field is used to configure arbitration related + * parameters for a TX ring. */ - uint8_t l2_addr_mask[6]; - /* This value sets VLAN ID value for outer VLAN. */ - uint16_t l2_ovlan; + uint16_t ring_arb_cfg; + /* Arbitration policy used for the ring. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \ + UINT32_C(0xf) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0 /* - * This value sets the mask value for the ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. + * Use strict priority for the TX ring. + * Priority value is specified in arb_policy_param */ - uint16_t l2_ovlan_mask; - /* This value sets VLAN ID value for inner VLAN. */ - uint16_t l2_ivlan; + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \ + UINT32_C(0x1) /* - * This value sets the mask value for the ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. + * Use weighted fair queue arbitration for the TX ring. + * Weight is specified in arb_policy_param */ - uint16_t l2_ivlan_mask; - uint8_t unused_1[2]; + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \ + UINT32_C(0x2) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \ + HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ + /* Reserved field. */ + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \ + UINT32_C(0xf0) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4 /* - * This value sets the match value for the tunnel - * L2 MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. + * Arbitration policy specific parameter. + * # For strict priority arbitration policy, this field + * represents a priority value. If set to 0, then the priority + * is not specified and the HWRM is allowed to select + * any priority for this TX ring. + * # For weighted fair queue arbitration policy, this field + * represents a weight value. If set to 0, then the weight + * is not specified and the HWRM is allowed to select + * any weight for this TX ring. */ - uint8_t t_l2_addr[6]; - uint8_t unused_2[2]; + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \ + UINT32_C(0xff00) + #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 + uint16_t unused_3; /* - * This value sets the mask value for the tunnel L2 - * address. - * A value of 0 will mask the corresponding bit from - * compare. + * This field is reserved for the future use. + * It shall be set to 0. */ - uint8_t t_l2_addr_mask[6]; - /* This value sets VLAN ID value for tunnel outer VLAN. */ - uint16_t t_l2_ovlan; + uint32_t reserved3; /* - * This value sets the mask value for the tunnel ovlan id. - * A value of 0 will mask the corresponding bit from - * compare. + * This field is used only when ring_type is a TX ring. + * This input indicates what statistics context this ring + * should be associated with. */ - uint16_t t_l2_ovlan_mask; - /* This value sets VLAN ID value for tunnel inner VLAN. */ - uint16_t t_l2_ivlan; + uint32_t stat_ctx_id; /* - * This value sets the mask value for the tunnel ivlan id. - * A value of 0 will mask the corresponding bit from - * compare. + * This field is reserved for the future use. + * It shall be set to 0. */ - uint16_t t_l2_ivlan_mask; - /* This value identifies the type of source of the packet. */ - uint8_t src_type; - /* Network port */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) - /* Physical function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) - /* Virtual function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) - /* Virtual NIC of a function */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) - /* Embedded processor for CFA management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) - /* Embedded processor for OOB management */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) - /* Embedded processor for RoCE */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) - /* Embedded processor for network proxy functions */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG - uint8_t unused_3; + uint32_t reserved4; /* - * This value is the id of the source. - * For a network port, it represents port_id. - * For a physical function, it represents fid. - * For a virtual function, it represents vf_id. - * For a vnic, it represents vnic_id. - * For embedded processors, this id is not valid. - * - * Notes: - * 1. The function ID is implied if it src_id is - * not provided for a src_type that is either + * This field is used only when ring_type is a TX ring + * to specify maximum BW allocated to the TX ring. + * The HWRM will translate this value into byte counter and + * time interval used for this ring inside the device. */ - uint32_t src_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + uint32_t max_bw; + /* The bandwidth value. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \ + HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \ + HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID + /* + * This field is used only when ring_type is a Completion ring. + * This value indicates what interrupt mode should be used + * on this completion ring. + * Note: In the legacy interrupt mode, no more than 16 + * completion rings are allowed. + */ + uint8_t int_mode; + /* Legacy INTA */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) + /* Reserved */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) + /* MSI-X */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) + /* No Interrupt - Polled mode */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \ + HWRM_RING_ALLOC_INPUT_INT_MODE_POLL + uint8_t unused_4[3]; + /* + * The cq_handle is specified when allocating a completion ring. For + * devices that support NQs, this cq_handle will be included in the + * NQE to specify which CQ should be read to retrieve the completion + * record. + */ + uint64_t cq_handle; +} __rte_packed; + +/* hwrm_ring_alloc_output (size:128b/16B) */ +struct hwrm_ring_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Physical number of ring allocated. + * This value shall be unique for a ring type. + */ + uint16_t ring_id; + /* Logical number of ring allocated. */ + uint16_t logical_ring_id; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_ring_free * + ******************/ + + +/* hwrm_ring_free_input (size:192b/24B) */ +struct hwrm_ring_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* RX Aggregation Ring */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4) + /* Notification Queue */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5) + #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \ + HWRM_RING_FREE_INPUT_RING_TYPE_NQ + uint8_t unused_0; + /* Physical number of ring allocated. */ + uint16_t ring_id; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_free_output (size:128b/16B) */ +struct hwrm_ring_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************* + * hwrm_ring_reset * + *******************/ + + +/* hwrm_ring_reset_input (size:192b/24B) */ +struct hwrm_ring_reset_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* L2 Completion Ring (CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + /* RoCE Notification Completion Ring (ROCE_CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3) + /* + * Rx Ring Group. This is to reset rx and aggregation in an atomic + * operation. Completion ring associated with this ring group is + * not reset. + */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6) + #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \ + HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP + uint8_t unused_0; + /* + * Physical number of the ring. When ring type is rx_ring_grp, ring id + * actually refers to ring group id. + */ + uint16_t ring_id; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_reset_output (size:128b/16B) */ +struct hwrm_ring_reset_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[4]; + /* Position of consumer index after ring reset completes. */ + uint8_t consumer_idx[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************** + * hwrm_ring_cfg * + *****************/ + + +/* hwrm_ring_cfg_input (size:256b/32B) */ +struct hwrm_ring_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \ + HWRM_RING_CFG_INPUT_RING_TYPE_RX + uint8_t unused_0; + /* Physical number of the ring. */ + uint16_t ring_id; + /* Ring config enable bits. */ + uint16_t enables; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \ UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \ UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + /* + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid + * is used as source interface of the transmitted packets. + */ + #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + /* The sq_id field is valid */ + #define HWRM_RING_CFG_INPUT_ENABLES_SQ_ID \ UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_4; + /* Update completion ring ID associated with Tx or Rx ring. */ + #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \ + UINT32_C(0x10) /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from + * the TX ring. */ - uint16_t dst_id; + uint16_t proxy_fid; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * Identifies the new scheduler queue (SQ) to associate with the ring. + * Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated + * with the default scheduler queue (SQ). + */ + uint16_t sq_id; + /* + * This field is valid for TX or Rx rings. This value identifies the + * new completion ring ID to associate with the TX or Rx ring. + */ + uint16_t cmpl_ring_id; + /* + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. + */ + uint8_t rx_sop_pad_bytes; + uint8_t unused_1[3]; +} __rte_packed; + +/* hwrm_ring_cfg_output (size:128b/16B) */ +struct hwrm_ring_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_ring_qcfg * + ******************/ + + +/* hwrm_ring_qcfg_input (size:192b/24B) */ +struct hwrm_ring_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Ring Type. */ + uint8_t ring_type; + /* TX Ring (TR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2) + #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \ + HWRM_RING_QCFG_INPUT_RING_TYPE_RX + uint8_t unused_0[5]; + /* Physical number of the ring. */ + uint16_t ring_id; +} __rte_packed; + +/* hwrm_ring_qcfg_output (size:192b/24B) */ +struct hwrm_ring_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Ring config enable bits. */ + uint16_t enables; + /* + * For Rx rings, the incoming packet data can be placed at either + * a 0B, 2B, 10B or 12B offset from the start of the Rx packet + * buffer. + * When '1', the received packet will be padded with 2B, 10B or 12B + * of zeros at the front of the packet. The exact offset is specified + * by rx_sop_pad_bytes parameter. + * When '0', the received packet will not be padded. + * Note that this flag is only used for Rx rings and is ignored + * for all other rings included Rx Aggregation rings. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \ + UINT32_C(0x1) + /* + * Proxy mode enable, for Tx, Rx and Rx aggregation rings only. + * When rings are allocated, the PCI function on which driver issues + * HWRM_RING_CFG command is assumed to own the rings. Hardware takes + * the buffer descriptors (BDs) from those rings is assumed to issue + * packet payload DMA using same PCI function. When proxy mode is + * enabled, hardware can perform payload DMA using another PCI + * function on same or different host. + * When set to '0', the PCI function on which driver issues + * HWRM_RING_CFG command is used for host payload DMA operation. + * When set to '1', the host PCI function specified by proxy_fid is + * used for host payload DMA operation. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \ + UINT32_C(0x2) + /* + * Tx ring packet source interface override, for Tx rings only. + * When TX rings are allocated, the PCI function on which driver + * issues HWRM_RING_CFG is assumed to be source interface of + * packets sent from TX ring. + * When set to '1', the host PCI function specified by proxy_fid is + * used as source interface of the transmitted packets. + */ + #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \ + UINT32_C(0x4) + /* + * Proxy function FID value. + * This value is only used when either proxy_mode_enable flag or + * tx_proxy_svif_override is set to '1'. + * When proxy_mode_enable is set to '1', it identifies a host PCI + * function used for host payload DMA operations. + * When tx_proxy_src_intf is set to '1', it identifies a host PCI + * function as source interface for all transmitted packets from the TX + * ring. + */ + uint16_t proxy_fid; + /* + * Identifies the new scheduler queue (SQ) to associate with the ring. + * Only valid for Tx rings. + * A value of zero indicates that the Tx ring should be associated with + * the default scheduler queue (SQ). + */ + uint16_t sq_id; + /* + * This field is used when ring_type is a TX or Rx ring. + * This value indicates what completion ring the TX or Rx ring + * is associated with. + */ + uint16_t cmpl_ring_id; + /* + * Rx SOP padding amount in bytes. + * This value is only used when rx_sop_pad_enable flag is set to '1'. + */ + uint8_t rx_sop_pad_bytes; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_ring_aggint_qcaps * + **************************/ + + +/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ +struct hwrm_ring_aggint_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ +struct hwrm_ring_aggint_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t cmpl_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* + * When this bit is set to '1', int_lat_tmr_max can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \ + UINT32_C(0x2) + /* + * When this bit is set to '1', timer_reset can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \ + UINT32_C(0x4) + /* + * When this bit is set to '1', ring_idle can be enabled + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \ + UINT32_C(0x8) + /* + * When this bit is set to '1', num_cmpl_dma_aggr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \ + UINT32_C(0x10) + /* + * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \ + UINT32_C(0x20) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \ + UINT32_C(0x40) + /* + * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \ + UINT32_C(0x80) + /* + * When this bit is set to '1', num_cmpl_aggr_int can be configured + * on completion rings. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \ + UINT32_C(0x100) + uint32_t nq_params; + /* + * When this bit is set to '1', int_lat_tmr_min can be configured + * on notification queues. + */ + #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \ + UINT32_C(0x1) + /* Minimum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_min; + /* Maximum value for num_cmpl_dma_aggr */ + uint16_t num_cmpl_dma_aggr_max; + /* Minimum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_min; + /* Maximum value for num_cmpl_dma_aggr_during_int */ + uint16_t num_cmpl_dma_aggr_during_int_max; + /* Minimum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_min; + /* Maximum value for cmpl_aggr_dma_tmr */ + uint16_t cmpl_aggr_dma_tmr_max; + /* Minimum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_min; + /* Maximum value for cmpl_aggr_dma_tmr_during_int */ + uint16_t cmpl_aggr_dma_tmr_during_int_max; + /* Minimum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_min; + /* Maximum value for int_lat_tmr_min */ + uint16_t int_lat_tmr_min_max; + /* Minimum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_min; + /* Maximum value for int_lat_tmr_max */ + uint16_t int_lat_tmr_max_max; + /* Minimum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_min; + /* Maximum value for num_cmpl_aggr_int */ + uint16_t num_cmpl_aggr_int_max; + /* The units for timer parameters, in nanoseconds. */ + uint16_t timer_units; + uint8_t unused_0[1]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************** + * hwrm_ring_cmpl_ring_qaggint_params * + **************************************/ + + +/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \ + UINT32_C(0x3) + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0 + /* + * Set this flag to 1 when querying parameters on a notification + * queue. Set this flag to 0 when querying parameters on a + * completion queue or completion ring. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + UINT32_C(0x4) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ +struct hwrm_ring_cmpl_ring_qaggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint16_t flags; + /* + * When this bit is set to '1', interrupt max + * timer is reset whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer used to aggregate completions before + * DMA when in interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************************** + * hwrm_ring_cmpl_ring_cfg_aggint_params * + *****************************************/ + + +/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Physical number of completion ring. */ + uint16_t ring_id; + uint16_t flags; + /* + * When this bit is set to '1', interrupt latency max + * timer is reset whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \ + UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode + * aggregation will be enabled. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \ + UINT32_C(0x2) + /* + * Set this flag to 1 when configuring parameters on a + * notification queue. Set this flag to 0 when configuring + * parameters on a completion queue or completion ring. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \ + UINT32_C(0x4) + /* + * Number of completions to aggregate before DMA + * during the normal mode. + */ + uint16_t num_cmpl_dma_aggr; + /* + * Number of completions to aggregate before DMA + * during the interrupt mode. + */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Timer used to aggregate completions before + * DMA during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer used to aggregate completions before + * DMA while in interrupt mode. + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* Minimum time between two interrupts. */ + uint16_t int_lat_tmr_min; + /* + * Maximum wait time spent aggregating + * completions before signaling the interrupt after the + * interrupt is enabled. + */ + uint16_t int_lat_tmr_max; + /* + * Minimum number of completions aggregated before signaling + * an interrupt. + */ + uint16_t num_cmpl_aggr_int; + /* + * Bitfield that indicates which parameters are to be applied. Only + * required when configuring devices with notification queues, and + * used in that case to set certain parameters on completion queues + * and others on notification queues. + */ + uint16_t enables; + /* + * This bit must be '1' for the num_cmpl_dma_aggr field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \ + UINT32_C(0x1) + /* + * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \ + UINT32_C(0x2) + /* + * This bit must be '1' for the cmpl_aggr_dma_tmr field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \ + UINT32_C(0x4) + /* + * This bit must be '1' for the int_lat_tmr_min field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \ + UINT32_C(0x8) + /* + * This bit must be '1' for the int_lat_tmr_max field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \ + UINT32_C(0x10) + /* + * This bit must be '1' for the num_cmpl_aggr_int field to be + * configured. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \ + UINT32_C(0x20) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ +struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_ring_grp_alloc * + ***********************/ + + +/* hwrm_ring_grp_alloc_input (size:192b/24B) */ +struct hwrm_ring_grp_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value identifies the CR associated with the ring + * group. + */ + uint16_t cr; + /* + * This value identifies the main RR associated with the ring + * group. + */ + uint16_t rr; + /* + * This value identifies the aggregation RR associated with + * the ring group. If this value is 0xFF... (All Fs), then no + * Aggregation ring will be set. + */ + uint16_t ar; + /* + * This value identifies the statistics context associated + * with the ring group. + */ + uint16_t sc; +} __rte_packed; + +/* hwrm_ring_grp_alloc_output (size:128b/16B) */ +struct hwrm_ring_grp_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is the ring group ID value. Use this value to program + * the default ring group for the VNIC or as table entries + * in an RSS/COS context. + */ + uint32_t ring_group_id; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_ring_grp_free * + **********************/ + + +/* hwrm_ring_grp_free_input (size:192b/24B) */ +struct hwrm_ring_grp_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* This is the ring group ID value. */ + uint32_t ring_group_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_ring_grp_free_output (size:128b/16B) */ +struct hwrm_ring_grp_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_ring_sq_alloc * + **********************/ + + +/* hwrm_ring_sq_alloc_input (size:1088b/136B) */ +struct hwrm_ring_sq_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the tqm_ring0 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1) + /* + * This bit must be '1' for the tqm_ring1 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2) + /* + * This bit must be '1' for the tqm_ring2 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4) + /* + * This bit must be '1' for the tqm_ring3 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8) + /* + * This bit must be '1' for the tqm_ring4 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10) + /* + * This bit must be '1' for the tqm_ring5 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20) + /* + * This bit must be '1' for the tqm_ring6 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40) + /* + * This bit must be '1' for the tqm_ring7 fields to be + * configured. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80) + /* Reserved for future use. */ + uint32_t reserved; + /* TQM ring 0 page size and level. */ + uint8_t tqm_ring0_pg_size_tqm_ring0_lvl; + /* TQM ring 0 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 + /* TQM ring 0 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G + /* TQM ring 1 page size and level. */ + uint8_t tqm_ring1_pg_size_tqm_ring1_lvl; + /* TQM ring 1 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 + /* TQM ring 1 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G + /* TQM ring 2 page size and level. */ + uint8_t tqm_ring2_pg_size_tqm_ring2_lvl; + /* TQM ring 2 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 + /* TQM ring 2 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G + /* TQM ring 3 page size and level. */ + uint8_t tqm_ring3_pg_size_tqm_ring3_lvl; + /* TQM ring 3 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 + /* TQM ring 3 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G + /* TQM ring 4 page size and level. */ + uint8_t tqm_ring4_pg_size_tqm_ring4_lvl; + /* TQM ring 4 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 + /* TQM ring 4 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G + /* TQM ring 5 page size and level. */ + uint8_t tqm_ring5_pg_size_tqm_ring5_lvl; + /* TQM ring 5 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 + /* TQM ring 5 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G + /* TQM ring 6 page size and level. */ + uint8_t tqm_ring6_pg_size_tqm_ring6_lvl; + /* TQM ring 6 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 + /* TQM ring 6 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G + /* TQM ring 7 page size and level. */ + uint8_t tqm_ring7_pg_size_tqm_ring7_lvl; + /* TQM ring 7 PBL indirect levels. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0 + /* PBL pointer is physical start address. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \ + UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \ + UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing to PTE + * tables. + */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \ + UINT32_C(0x2) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 + /* TQM ring 7 page size. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4 + /* 4KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \ + (UINT32_C(0x0) << 4) + /* 8KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \ + (UINT32_C(0x1) << 4) + /* 64KB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \ + (UINT32_C(0x2) << 4) + /* 2MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \ + (UINT32_C(0x3) << 4) + /* 8MB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \ + (UINT32_C(0x4) << 4) + /* 1GB. */ + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \ + (UINT32_C(0x5) << 4) + #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \ + HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G + /* TQM ring 0 page directory. */ + uint64_t tqm_ring0_page_dir; + /* TQM ring 1 page directory. */ + uint64_t tqm_ring1_page_dir; + /* TQM ring 2 page directory. */ + uint64_t tqm_ring2_page_dir; + /* TQM ring 3 page directory. */ + uint64_t tqm_ring3_page_dir; + /* TQM ring 4 page directory. */ + uint64_t tqm_ring4_page_dir; + /* TQM ring 5 page directory. */ + uint64_t tqm_ring5_page_dir; + /* TQM ring 6 page directory. */ + uint64_t tqm_ring6_page_dir; + /* TQM ring 7 page directory. */ + uint64_t tqm_ring7_page_dir; + /* + * Number of TQM ring 0 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring0_num_entries; + /* + * Number of TQM ring 1 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring1_num_entries; + /* + * Number of TQM ring 2 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring2_num_entries; + /* + * Number of TQM ring 3 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring3_num_entries; + /* + * Number of TQM ring 4 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring4_num_entries; + /* + * Number of TQM ring 5 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring5_num_entries; + /* + * Number of TQM ring 6 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring6_num_entries; + /* + * Number of TQM ring 7 entries. + * + * TQM fastpath rings should be sized large enough to accommodate the + * maximum number of QPs (either L2 or RoCE, or both if shared) + * that can be enqueued to the TQM ring. + * + * Note that TQM ring sizes cannot be extended while the system is + * operational. If a PF driver needs to extend a TQM ring, it needs + * to delete the SQ and then reallocate it. + */ + uint32_t tqm_ring7_num_entries; + /* Number of bytes that have been allocated for each context entry. */ + uint16_t tqm_entry_size; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_ring_sq_alloc_output (size:128b/16B) */ +struct hwrm_ring_sq_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This is an identifier for the SQ to be used in other HWRM commands + * that need to reference this SQ. This value is greater than zero + * (i.e. a sq_id of zero references the default SQ). + */ + uint16_t sq_id; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************** + * hwrm_ring_sq_cfg * + ********************/ + + +/* hwrm_ring_sq_cfg_input (size:768b/96B) */ +struct hwrm_ring_sq_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Identifies the SQ being configured. A sq_id of zero refers to the + * default SQ. + */ + uint16_t sq_id; + /* + * This field is an 8 bit bitmap that indicates which TCs are enabled + * in this SQ. Bit 0 represents traffic class 0 and bit 7 represents + * traffic class 7. + */ + uint8_t tc_enabled; + uint8_t unused_0; + uint32_t flags; + /* The tc_max_bw array and the max_bw parameters are valid */ + #define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \ + UINT32_C(0x1) + /* The tc_min_bw array is valid */ + #define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \ + UINT32_C(0x2) + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc0; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc1; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc2; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc3; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc4; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc5; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc6; + /* Maximum bandwidth of the traffic class, specified in Mbps. */ + uint32_t max_bw_tc7; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc0; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc1; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc2; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc3; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc4; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc5; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc6; + /* + * Bandwidth reservation for the traffic class, specified in Mbps. + * A value of zero signifies that traffic belonging to this class + * shares the bandwidth reservation for the same traffic class of + * the default SQ. + */ + uint32_t min_bw_tc7; + /* + * Indicates the max bandwidth for all enabled traffic classes in + * this SQ, specified in Mbps. + */ + uint32_t max_bw; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_ring_sq_cfg_output (size:128b/16B) */ +struct hwrm_ring_sq_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_ring_sq_free * + *********************/ + + +/* hwrm_ring_sq_free_input (size:192b/24B) */ +struct hwrm_ring_sq_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Identifies the SQ being freed. */ + uint16_t sq_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_ring_sq_free_output (size:128b/16B) */ +struct hwrm_ring_sq_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; +/* + * special reserved flow ID to identify per function default + * flows for vSwitch offload + */ +#define DEFAULT_FLOW_ID 0xFFFFFFFFUL +/* + * special reserved flow ID to identify per function RoCEv1 + * flows + */ +#define ROCEV1_FLOW_ID 0xFFFFFFFEUL +/* + * special reserved flow ID to identify per function RoCEv2 + * flows + */ +#define ROCEV2_FLOW_ID 0xFFFFFFFDUL +/* + * special reserved flow ID to identify per function RoCEv2 + * CNP flows + */ +#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL + +/**************************** + * hwrm_cfa_l2_filter_alloc * + ****************************/ + + +/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ +struct hwrm_cfa_l2_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x2) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \ + UINT32_C(0x4) + /* + * If this flag is set, all t_l2_* fields are invalid + * and they should not be specified. + * If this flag is set, then l2_* fields refer to + * fields of outermost L2 header. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \ + UINT32_C(0x8) + /* + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \ + UINT32_C(0x30) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ + (UINT32_C(0x0) << 4) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \ + (UINT32_C(0x1) << 4) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \ + (UINT32_C(0x2) << 4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE + /* + * Setting of this flag indicates that no XDP filter is created with + * L2 filter. + * 0 - legacy behavior, XDP filter is created with L2 filter + * 1 - XDP filter won't be created with L2 filter + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \ + UINT32_C(0x40) + /* + * Setting this flag to 1 indicate the L2 fields in this command + * pertain to source fields. Setting this flag to 0 indicate the + * L2 fields in this command pertain to the destination fields + * and this is the default/legacy behavior. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \ + UINT32_C(0x80) + uint32_t enables; + /* + * This bit must be '1' for the l2_addr field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ + UINT32_C(0x1) + /* + * This bit must be '1' for the l2_addr_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \ + UINT32_C(0x2) + /* + * This bit must be '1' for the l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \ + UINT32_C(0x4) + /* + * This bit must be '1' for the l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \ + UINT32_C(0x8) + /* + * This bit must be '1' for the l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ + UINT32_C(0x10) + /* + * This bit must be '1' for the l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \ + UINT32_C(0x20) + /* + * This bit must be '1' for the t_l2_addr field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \ + UINT32_C(0x40) + /* + * This bit must be '1' for the t_l2_addr_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \ + UINT32_C(0x80) + /* + * This bit must be '1' for the t_l2_ovlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \ + UINT32_C(0x100) + /* + * This bit must be '1' for the t_l2_ovlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \ + UINT32_C(0x200) + /* + * This bit must be '1' for the t_l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \ + UINT32_C(0x400) + /* + * This bit must be '1' for the t_l2_ivlan_mask field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \ + UINT32_C(0x800) + /* + * This bit must be '1' for the src_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the src_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the num_vlans field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the t_num_vlans field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \ + UINT32_C(0x40000) + /* + * This value sets the match value for the L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t l2_addr[6]; + /* This value sets the match value for the number of VLANs. */ + uint8_t num_vlans; + /* + * This value sets the match value for the number of VLANs + * in the tunnel headers. + */ + uint8_t t_num_vlans; + /* + * This value sets the mask value for the L2 address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t l2_addr_mask[6]; + /* This value sets VLAN ID value for outer VLAN. */ + uint16_t l2_ovlan; + /* + * This value sets the mask value for the ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t l2_ovlan_mask; + /* This value sets VLAN ID value for inner VLAN. */ + uint16_t l2_ivlan; + /* + * This value sets the mask value for the ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t l2_ivlan_mask; + uint8_t unused_1[2]; + /* + * This value sets the match value for the tunnel + * L2 MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t t_l2_addr[6]; + uint8_t unused_2[2]; + /* + * This value sets the mask value for the tunnel L2 + * address. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint8_t t_l2_addr_mask[6]; + /* This value sets VLAN ID value for tunnel outer VLAN. */ + uint16_t t_l2_ovlan; + /* + * This value sets the mask value for the tunnel ovlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ovlan_mask; + /* This value sets VLAN ID value for tunnel inner VLAN. */ + uint16_t t_l2_ivlan; + /* + * This value sets the mask value for the tunnel ivlan id. + * A value of 0 will mask the corresponding bit from + * compare. + */ + uint16_t t_l2_ivlan_mask; + /* This value identifies the type of source of the packet. */ + uint8_t src_type; + /* Network port */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) + /* Physical function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) + /* Virtual function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) + /* Virtual NIC of a function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) + /* Embedded processor for CFA management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) + /* Embedded processor for OOB management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) + /* Embedded processor for RoCE */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) + /* Embedded processor for network proxy functions */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG + uint8_t unused_3; + /* + * This value is the id of the source. + * For a network port, it represents port_id. + * For a physical function, it represents fid. + * For a virtual function, it represents vf_id. + * For a vnic, it represents vnic_id. + * For embedded processors, this id is not valid. + * + * Notes: + * 1. The function ID is implied if it src_id is + * not provided for a src_type that is either + */ + uint32_t src_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_4; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* + * This hint is provided to help in placing + * the filter in the filter table. + */ + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ + UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \ + UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \ + UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \ + UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \ + UINT32_C(0x4) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN + uint8_t unused_5; + uint32_t unused_6; + /* + * This is the ID of the filter that goes along with + * the pri_hint. + * + * This field is valid only for the following values. + * 1 - Above the given filter + * 2 - Below the given filter + */ + uint64_t l2_filter_id_hint; +} __rte_packed; + +/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_l2_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_l2_filter_free * + ***************************/ + + +/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_l2_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; +} __rte_packed; + +/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_l2_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_l2_filter_cfg * + **************************/ + + +/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ +struct hwrm_cfa_l2_filter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ + UINT32_C(0x2) + /* + * Enumeration denoting NO_ROCE_L2 to support old drivers. + * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 + /* To support old drivers */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ + (UINT32_C(0x0) << 2) + /* Only L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \ + (UINT32_C(0x1) << 2) + /* Roce & L2 traffic */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \ + HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE + uint32_t enables; + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ + UINT32_C(0x2) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint32_t dst_id; + /* + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t new_mirror_vnic_id; +} __rte_packed; + +/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_l2_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_l2_set_rx_mask * + ***************************/ + + +/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ +struct hwrm_cfa_l2_set_rx_mask_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* VNIC ID */ + uint32_t vnic_id; + uint32_t mask; + /* + * When this bit is '1', the function is requested to accept + * multi-cast packets specified by the multicast addr table. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \ + UINT32_C(0x2) + /* + * When this bit is '1', the function is requested to accept + * all multi-cast packets. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \ + UINT32_C(0x4) + /* + * When this bit is '1', the function is requested to accept + * broadcast packets. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \ + UINT32_C(0x8) + /* + * When this bit is '1', the function is requested to be + * put in the promiscuous mode. + * + * The HWRM should accept any function to set up + * promiscuous mode. + * + * The HWRM shall follow the semantics below for the + * promiscuous mode support. + * # When partitioning is not enabled on a port + * (i.e. single PF on the port), then the PF shall + * be allowed to be in the promiscuous mode. When the + * PF is in the promiscuous mode, then it shall + * receive all host bound traffic on that port. + * # When partitioning is enabled on a port + * (i.e. multiple PFs per port) and a PF on that + * port is in the promiscuous mode, then the PF + * receives all traffic within that partition as + * identified by a unique identifier for the + * PF (e.g. S-Tag). If a unique outer VLAN + * for the PF is specified, then the setting of + * promiscuous mode on that PF shall result in the + * PF receiving all host bound traffic with matching + * outer VLAN. + * # A VF shall can be set in the promiscuous mode. + * In the promiscuous mode, the VF does not receive any + * traffic unless a unique outer VLAN for the + * VF is specified. If a unique outer VLAN + * for the VF is specified, then the setting of + * promiscuous mode on that VF shall result in the + * VF receiving all host bound traffic with the + * matching outer VLAN. + * # The HWRM shall allow the setting of promiscuous + * mode on a function independently from the + * promiscuous mode settings on other functions. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \ + UINT32_C(0x10) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the outermost Layer 2 destination MAC + * address field. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \ + UINT32_C(0x20) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for the VLAN-tagged packets that match the + * TPID and VID fields of VLAN tags in the VLAN tag + * table specified in this command. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \ + UINT32_C(0x40) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets that match the TPID and VID fields of VLAN + * tags in the VLAN tag table specified in this command. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \ + UINT32_C(0x80) + /* + * If this flag is set, the corresponding RX + * filters shall be set up to cover multicast/broadcast + * filters for non-VLAN tagged packets and VLAN-tagged + * packets matching any VLAN tag. + * + * If this flag is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan + * flags is set, then the HWRM shall ignore + * VLAN tags specified in vlan_tag_tbl. + * + * The HWRM client shall set at most one flag out of + * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \ + UINT32_C(0x100) + /* This is the address for mcast address tbl. */ + uint64_t mc_tbl_addr; + /* + * This value indicates how many entries in mc_tbl are valid. + * Each entry is 6 bytes. + */ + uint32_t num_mc_entries; + uint8_t unused_0[4]; + /* + * This is the address for VLAN tag table. + * Each VLAN entry in the table is 4 bytes of a VLAN tag + * including TPID, PCP, DEI, and VID fields in network byte + * order. + */ + uint64_t vlan_tag_tbl_addr; + /* + * This value indicates how many entries in vlan_tag_tbl are + * valid. Each entry is 4 bytes. + */ + uint32_t num_vlan_tags; + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ +struct hwrm_cfa_l2_set_rx_mask_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ +struct hwrm_cfa_l2_set_rx_mask_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* Unable to complete operation due to conflict with Ntuple Filter */ + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \ + UINT32_C(0x1) + #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ + HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR + uint8_t unused_0[7]; +} __rte_packed; + +/******************************* + * hwrm_cfa_vlan_antispoof_cfg * + *******************************/ + + +/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ +struct hwrm_cfa_vlan_antispoof_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being configured. + * Only valid for a VF FID configured by the PF. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* Number of VLAN entries in the vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + /* + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table. Each table entry contains the 16-bit TPID + * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, + * all in network order to match hwrm_cfa_l2_set_rx_mask. + * For an individual VLAN entry, the mask value should be 0xfff + * for the 12-bit VLAN ID. + */ + uint64_t vlan_tag_mask_tbl_addr; +} __rte_packed; + +/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ +struct hwrm_cfa_vlan_antispoof_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_vlan_antispoof_qcfg * + ********************************/ + + +/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ +struct hwrm_cfa_vlan_antispoof_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being queried. + * Only valid for a VF FID queried by the PF. + */ + uint16_t fid; + uint8_t unused_0[2]; + /* + * Maximum number of VLAN entries the firmware is allowed to DMA + * to vlan_tag_mask_tbl. + */ + uint32_t max_vlan_entries; + /* + * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN + * antispoof table to which firmware will DMA to. Each table + * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), + * 16-bit VLAN ID, and a 16-bit mask, all in network order to + * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, + * the mask value should be 0xfff for the 12-bit VLAN ID. + */ + uint64_t vlan_tag_mask_tbl_addr; +} __rte_packed; + +/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ +struct hwrm_cfa_vlan_antispoof_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ + uint32_t num_vlan_entries; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_tunnel_filter_alloc * + ********************************/ + + +/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ +struct hwrm_cfa_tunnel_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the l2_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ + UINT32_C(0x2) + /* + * This bit must be '1' for the l2_ivlan field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ + UINT32_C(0x4) + /* + * This bit must be '1' for the l3_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the l3_addr_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the t_l3_addr_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \ + UINT32_C(0x20) + /* + * This bit must be '1' for the t_l3_addr field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \ + UINT32_C(0x40) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x80) + /* + * This bit must be '1' for the vni field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \ + UINT32_C(0x100) + /* + * This bit must be '1' for the dst_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \ + UINT32_C(0x200) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x400) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * This value sets the match value for the inner L2 + * MAC address. + * Destination MAC address for RX path. + * Source MAC address for TX path. + */ + uint8_t l2_addr[6]; + /* + * This value sets VLAN ID value for inner VLAN. + * Only 12-bits of VLAN ID are used in setting the filter. + */ + uint16_t l2_ivlan; + /* + * The value of inner destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t l3_addr[4]; + /* + * The value of tunnel destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t t_l3_addr[4]; + /* + * This value indicates the type of inner IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t l3_addr_type; + /* + * This value indicates the type of tunnel IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t t_l3_addr_type; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* + * tunnel_flags allows the user to indicate the tunnel tag detection + * for the tunnel type specified in tunnel_type. + */ + uint8_t tunnel_flags; + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to match the geneve OAM packet. + * If the tunnel_type is nvgre or gre, then this bit indicates if + * we need to detect checksum present bit in geneve header. + * If the tunnel_type is mpls, then this bit indicates if we need + * to match mpls packet with explicit IPV4/IPV6 null header. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \ + UINT32_C(0x1) + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to detect the critical option bit set in the oam packet. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with key present bit set in + * gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from inner/second label. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \ + UINT32_C(0x2) + /* + * If the tunnel_type is geneve, then this bit indicates if we + * need to match geneve packet with extended header bit set in + * geneve header. + * If the tunnel_type is nvgre or gre, then this bit indicates + * if we need to match nvgre packets with sequence number + * present bit set in gre header. + * If the tunnel_type is mpls, then this bit indicates if we + * need to match mpls packet with S bit from out/first label. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \ + UINT32_C(0x4) + /* + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t vni; + /* Logical VNIC ID of the destination VNIC. */ + uint32_t dst_vnic_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t mirror_vnic_id; +} __rte_packed; + +/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_tunnel_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t tunnel_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_cfa_tunnel_filter_free * + *******************************/ + + +/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_tunnel_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint64_t tunnel_filter_id; +} __rte_packed; + +/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_tunnel_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************************** + * hwrm_cfa_redirect_tunnel_type_alloc * + ***************************************/ + + +/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* Tunnel alloc flags. */ + uint8_t flags; + /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ + UINT32_C(0x1) + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************** + * hwrm_cfa_redirect_tunnel_type_free * + **************************************/ + + +/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************************** + * hwrm_cfa_redirect_tunnel_type_info * + **************************************/ + + +/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ +struct hwrm_cfa_redirect_tunnel_type_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The source function id. */ + uint16_t src_fid; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[5]; +} __rte_packed; + +/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ +struct hwrm_cfa_redirect_tunnel_type_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The destination function id, to whom the traffic is redirected. */ + uint16_t dest_fid; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ +struct hwrm_vxlan_ipv4_hdr { + /* IPv4 version and header length. */ + uint8_t ver_hlen; + /* IPv4 header length */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 + /* Version */ + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) + #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 + /* IPv4 type of service. */ + uint8_t tos; + /* IPv4 identification. */ + uint16_t ip_id; + /* IPv4 flags and offset. */ + uint16_t flags_frag_offset; + /* IPv4 TTL. */ + uint8_t ttl; + /* IPv4 protocol. */ + uint8_t protocol; + /* IPv4 source address. */ + uint32_t src_ip_addr; + /* IPv4 destination address. */ + uint32_t dest_ip_addr; +} __rte_packed; + +/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ +struct hwrm_vxlan_ipv6_hdr { + /* IPv6 version, traffic class and flow label. */ + uint32_t ver_tc_flow_label; + /* IPv6 version shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \ + UINT32_C(0x1c) + /* IPv6 version mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \ + UINT32_C(0xf0000000) + /* IPv6 TC shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \ + UINT32_C(0x14) + /* IPv6 TC mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \ + UINT32_C(0xff00000) + /* IPv6 flow label shift */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \ + UINT32_C(0x0) + /* IPv6 flow label mask */ + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \ + UINT32_C(0xfffff) + #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \ + HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK + /* IPv6 payload length. */ + uint16_t payload_len; + /* IPv6 next header. */ + uint8_t next_hdr; + /* IPv6 TTL. */ + uint8_t ttl; + /* IPv6 source address. */ + uint32_t src_ip_addr[4]; + /* IPv6 destination address. */ + uint32_t dest_ip_addr[4]; +} __rte_packed; + +/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ +struct hwrm_cfa_encap_data_vxlan { + /* Source MAC address. */ + uint8_t src_mac_addr[6]; + /* reserved. */ + uint16_t unused_0; + /* Destination MAC address. */ + uint8_t dst_mac_addr[6]; + /* Number of VLAN tags. */ + uint8_t num_vlan_tags; + /* reserved. */ + uint8_t unused_1; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + /* L3 header fields. */ + uint32_t l3[10]; + /* IP version mask. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) + /* IP version 4. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) + /* IP version 6. */ + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) + #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \ + HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 + /* UDP source port. */ + uint16_t src_port; + /* UDP destination port. */ + uint16_t dst_port; + /* VXLAN Network Identifier. */ + uint32_t vni; + /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */ + uint8_t hdr_rsvd0[3]; + /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ + uint8_t hdr_rsvd1; + /* VXLAN header flags field. */ + uint8_t hdr_flags; + uint8_t unused[3]; +} __rte_packed; + +/******************************* + * hwrm_cfa_encap_record_alloc * + *******************************/ + + +/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ +struct hwrm_cfa_encap_record_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + /* + * Setting of this flag indicates this encap record is external encap record. + * Resetting of this flag indicates this flag is internal encap record and + * this is the default setting. + */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \ + UINT32_C(0x2) + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ + UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ + HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 + uint8_t unused_0[3]; + /* This value is encap data used for the given encap type. */ + uint32_t encap_data[20]; +} __rte_packed; + +/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ +struct hwrm_cfa_encap_record_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_cfa_encap_record_free * + ******************************/ + + +/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ +struct hwrm_cfa_encap_record_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint32_t encap_record_id; + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ +struct hwrm_cfa_encap_record_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_ntuple_filter_alloc * + ********************************/ + + +/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ +struct hwrm_cfa_ntuple_filter_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* Setting of this flag indicates the applicability to the loopback path. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + UINT32_C(0x1) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ + UINT32_C(0x2) + /* + * Setting of this flag indicates that a meter is expected to be attached + * to this flow. This hint can be used when choosing the action record + * format required for the flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ + UINT32_C(0x4) + /* + * Setting of this flag indicates that the dst_id field contains function ID. + * If this is not set it indicates dest_id is VNIC or VPORT. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ + UINT32_C(0x8) + /* + * Setting of this flag indicates match on arp reply when ethertype is 0x0806. + * If this is not set it indicates no specific arp opcode matching. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \ + UINT32_C(0x10) + /* + * Setting of this flag indicates that the dst_id field contains RFS ring + * table index. If this is not set it indicates dst_id is VNIC or VPORT + * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at + * the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x20) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x4) + /* + * This bit must be '1' for the src_macaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x10) + /* + * This bit must be '1' for the src_ipaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x20) + /* + * This bit must be '1' for the src_ipaddr_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \ + UINT32_C(0x40) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x80) + /* + * This bit must be '1' for the dst_ipaddr_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \ + UINT32_C(0x100) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x200) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x400) + /* + * This bit must be '1' for the src_port_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \ + UINT32_C(0x800) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the dst_port_mask field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the pri_hint field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the ntuple_filter_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x20000) + /* + * This bit must be '1' for the dst_macaddr field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ + UINT32_C(0x40000) + /* This flag is deprecated. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \ + UINT32_C(0x80000) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ + UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* + * This value indicates the tunnel type for this filter. + * If this field is not specified, then the filter shall + * apply to both non-tunneled and tunneled packets. + * If this field conflicts with the tunnel_type specified + * in the l2_filter_id, then the HWRM shall return an + * error for this command. + */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + /* + * This hint is provided to help in placing + * the filter in the filter table. + */ + uint8_t pri_hint; + /* No preference */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ + UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \ + UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \ + UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \ + UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \ + UINT32_C(0x4) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * The value of source IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. + */ + uint32_t src_ipaddr_mask[4]; + /* + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of destination IP address mask to be used in + * filtering. + * For IPv4, first four bytes represent the IP address mask. + */ + uint32_t dst_ipaddr_mask[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of source port mask to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port_mask; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * The value of destination port mask to be used in + * filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port_mask; + /* + * This is the ID of the filter that goes along with + * the pri_hint. + */ + uint64_t ntuple_filter_id_hint; +} __rte_packed; + +/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ +struct hwrm_cfa_ntuple_filter_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ +struct hwrm_cfa_ntuple_filter_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \ + UINT32_C(0x0) + /* Unable to complete operation due to conflict with Rx Mask VLAN */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \ + UINT32_C(0x1) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ + HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR + uint8_t unused_0[7]; +} __rte_packed; + +/******************************* + * hwrm_cfa_ntuple_filter_free * + *******************************/ + + +/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_ntuple_filter_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; +} __rte_packed; + +/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_ntuple_filter_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_cfa_ntuple_filter_cfg * + ******************************/ + + +/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ +struct hwrm_cfa_ntuple_filter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t enables; + /* + * This bit must be '1' for the new_dst_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ + UINT32_C(0x2) + /* + * This bit must be '1' for the new_meter_instance_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ + UINT32_C(0x4) + uint32_t flags; + /* + * Setting this bit to 1 indicates that dest_id field contains FID. + * Setting this to 0 indicates that dest_id field contains VNIC or VPORT. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ + UINT32_C(0x1) + /* + * Setting of this flag indicates that the new_dst_id field contains + * RFS ring table index. If this is not set it indicates new_dst_id is + * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx + * can’t be set at the same time. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \ + UINT32_C(0x2) + /* This value is an opaque id into CFA data structures. */ + uint64_t ntuple_filter_id; + /* + * If set, this value shall represent the new + * Logical VNIC ID of the destination VNIC for the RX + * path and new network port id of the destination port for + * the TX path. + */ + uint32_t new_dst_id; + /* + * New Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint32_t new_mirror_vnic_id; + /* + * New meter to attach to the flow. Specifying the + * invalid instance ID is used to remove any existing + * meter from the flow. + */ + uint16_t new_meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ + HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID + uint8_t unused_1[6]; +} __rte_packed; + +/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_ntuple_filter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_cfa_em_flow_alloc * + **************************/ + + +/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ +struct hwrm_cfa_em_flow_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates enabling of a byte counter for a given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) + /* + * Setting of this flag indicates enabling of a packet counter for a given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) + /* Setting of this flag indicates de-capsulation action for the given flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) + /* Setting of this flag indicates encapsulation action for the given flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) + /* + * Setting of this flag indicates that a meter is expected to be attached + * to this flow. This hint can be used when choosing the action record + * format required for the flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) + uint32_t enables; + /* + * This bit must be '1' for the l2_filter_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ + UINT32_C(0x1) + /* + * This bit must be '1' for the tunnel_type field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x2) + /* + * This bit must be '1' for the tunnel_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \ + UINT32_C(0x4) + /* + * This bit must be '1' for the src_macaddr field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + UINT32_C(0x8) + /* + * This bit must be '1' for the dst_macaddr field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \ + UINT32_C(0x10) + /* + * This bit must be '1' for the ovlan_vid field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \ + UINT32_C(0x20) + /* + * This bit must be '1' for the ivlan_vid field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \ + UINT32_C(0x40) + /* + * This bit must be '1' for the ethertype field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \ + UINT32_C(0x80) + /* + * This bit must be '1' for the src_ipaddr field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x100) + /* + * This bit must be '1' for the dst_ipaddr field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x200) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x400) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x800) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the encap_record_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \ + UINT32_C(0x10000) + /* + * This bit must be '1' for the meter_instance_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \ + UINT32_C(0x20000) + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint64_t l2_filter_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0[3]; + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t tunnel_id; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + /* The meter instance to attach to the flow. */ + uint16_t meter_instance_id; + /* + * A value of 0xfff is considered invalid and implies the + * instance is not configured. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID + /* + * This value indicates the destination MAC address in + * the Ethernet header. + */ + uint8_t dst_macaddr[6]; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. + */ + uint16_t ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. + */ + uint16_t ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; + /* + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. + */ + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + /* + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP + */ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* TCP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP + uint8_t unused_1[2]; + /* + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t src_ipaddr[4]; + /* + * big_endian = True + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; + /* + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t src_port; + /* + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. + */ + uint16_t dst_port; + /* + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path and network port id of the destination port for + * the TX path. + */ + uint16_t dst_id; + /* + * Logical VNIC ID of the VNIC where traffic is + * mirrored. + */ + uint16_t mirror_vnic_id; + /* Logical ID of the encapsulation record. */ + uint32_t encap_record_id; + uint8_t unused_2[4]; +} __rte_packed; + +/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ +struct hwrm_cfa_em_flow_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; + /* + * The flow id value in bit 0-29 is the actual ID of the flow + * associated with this filter and it shall be used to match + * and associate the flow identifier returned in completion + * records. A value of 0xFFFFFFFF in the 32-bit flow_id field + * shall indicate no valid flow id. + */ + uint32_t flow_id; + /* Indicate the flow id value. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + UINT32_C(0x3fffffff) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + /* Indicate type of the flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ + UINT32_C(0x40000000) + /* + * If this bit set to 0, then it indicates that the flow is + * internal flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + (UINT32_C(0x0) << 30) + /* + * If this bit is set to 1, then it indicates that the flow is + * external flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + /* Indicate the flow direction. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ + UINT32_C(0x80000000) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + (UINT32_C(0x0) << 31) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + (UINT32_C(0x1) << 31) + #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_cfa_em_flow_free * + *************************/ + + +/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ +struct hwrm_cfa_em_flow_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* This value is an opaque id into CFA data structures. */ + uint64_t em_filter_id; +} __rte_packed; + +/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ +struct hwrm_cfa_em_flow_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_cfa_meter_qcaps * + ************************/ + + +/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_meter_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ +struct hwrm_cfa_meter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * Enumeration denoting the clock at which the Meter is running with. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 + /* 375 MHz */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0) + /* 625 MHz */ + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1) + #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \ + HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ + uint8_t unused_0[4]; + /* + * The minimum guaranteed number of tx meter profiles supported + * for this function. + */ + uint16_t min_tx_profile; + /* + * The maximum non-guaranteed number of tx meter profiles supported + * for this function. + */ + uint16_t max_tx_profile; + /* + * The minimum guaranteed number of rx meter profiles supported + * for this function. + */ + uint16_t min_rx_profile; + /* + * The maximum non-guaranteed number of rx meter profiles supported + * for this function. + */ + uint16_t max_rx_profile; + /* + * The minimum guaranteed number of tx meter instances supported + * for this function. + */ + uint16_t min_tx_instance; + /* + * The maximum non-guaranteed number of tx meter instances supported + * for this function. + */ + uint16_t max_tx_instance; + /* + * The minimum guaranteed number of rx meter instances supported + * for this function. + */ + uint16_t min_rx_instance; + /* + * The maximum non-guaranteed number of rx meter instances supported + * for this function. + */ + uint16_t max_rx_instance; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_cfa_meter_profile_alloc * + ********************************/ + + +/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ +struct hwrm_cfa_meter_profile_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \ + UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \ + UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \ + UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint16_t reserved1; + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved2; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw value */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid value */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID +} __rte_packed; + +/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_cfa_meter_profile_free * + *******************************/ + + +/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ +struct hwrm_cfa_meter_profile_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; +} __rte_packed; + +/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_cfa_meter_profile_cfg * + ******************************/ + + +/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ +struct hwrm_cfa_meter_profile_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. + */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX + /* The meter algorithm type. */ + uint8_t meter_type; + /* RFC 2697 (srTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \ + UINT32_C(0x0) + /* RFC 2698 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \ + UINT32_C(0x1) + /* RFC 4115 (trTCM) */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \ + UINT32_C(0x2) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; + /* + * A value of 0xfff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID + /* + * This field is reserved for the future use. + * It shall be set to 0. + */ + uint32_t reserved; + /* A meter rate specified in bytes-per-second. */ + uint32_t commit_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw value */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t commit_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid value */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID + /* A meter rate specified in bytes-per-second. */ + uint32_t excess_peak_rate; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Raw unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW + /* A meter burst size specified in bytes. */ + uint32_t excess_peak_burst; + /* The bandwidth value. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ + UINT32_C(0xfffffff) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ + 0 + /* The granularity of the value (bits or bytes). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \ + UINT32_C(0x10000000) + /* Value is in bits. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ + (UINT32_C(0x0) << 28) + /* Value is in bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ + (UINT32_C(0x1) << 28) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES + /* bw_value_unit is 3 b */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ + UINT32_C(0xe0000000) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ + 29 + /* Value is in Mb or MB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ + (UINT32_C(0x0) << 29) + /* Value is in Kb or KB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ + (UINT32_C(0x2) << 29) + /* Value is in bits or bytes. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ + (UINT32_C(0x4) << 29) + /* Value is in Gb or GB (base 10). */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ + (UINT32_C(0x6) << 29) + /* Value is in 1/100th of a percentage of total bandwidth. */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ + (UINT32_C(0x1) << 29) + /* Invalid unit */ + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ + (UINT32_C(0x7) << 29) + #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ + HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID +} __rte_packed; + +/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ +struct hwrm_cfa_meter_profile_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************* + * hwrm_cfa_meter_instance_alloc * + *********************************/ + + +/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t mirror_vnic_id; + uint64_t resp_addr; + uint8_t flags; /* - * This hint is provided to help in placing - * the filter in the filter table. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \ + UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \ UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \ + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \ UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \ - UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \ - UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \ - UINT32_C(0x4) - #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN - uint8_t unused_5; - uint32_t unused_6; + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter profile in CFA. */ + uint16_t meter_profile_id; /* - * This is the ID of the filter that goes along with - * the pri_hint. - * - * This field is valid only for the following values. - * 1 - Above the given filter - * 2 - Below the given filter + * A value of 0xffff is considered invalid and implies the + * profile is not configured. */ - uint64_t l2_filter_id_hint; -} __attribute__((packed)); + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID + uint8_t unused_1[4]; +} __rte_packed; -/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_l2_filter_alloc_output { +/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24094,69 +32945,34 @@ struct hwrm_cfa_l2_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) - /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * A value of 0xffff is considered invalid and implies the + * instance is not configured. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*************************** - * hwrm_cfa_l2_filter_free * - ***************************/ +/******************************* + * hwrm_cfa_meter_instance_cfg * + *******************************/ -/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_l2_filter_free_input { +/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24185,15 +33001,45 @@ struct hwrm_cfa_l2_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint8_t flags; /* - * This value identifies a set of CFA data structures used for an L2 - * context. + * Enumeration denoting the RX, TX type of the resource. + * This enumeration is used for resources that are similar for both + * TX and RX paths of the chip. */ - uint64_t l2_filter_id; -} __attribute__((packed)); + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* + * This value identifies a new meter profile to be associated with + * the meter instance specified in this command. + */ + uint16_t meter_profile_id; + /* + * A value of 0xffff is considered invalid and implies the + * profile is not configured. + */ + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID + /* + * This value identifies the ID of a meter instance that needs to be updated with + * a new meter profile specified in this command. + */ + uint16_t meter_instance_id; + uint8_t unused_1[2]; +} __rte_packed; -/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_free_output { +/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24205,21 +33051,21 @@ struct hwrm_cfa_l2_filter_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************** - * hwrm_cfa_l2_filter_cfg * - **************************/ +/******************************** + * hwrm_cfa_meter_instance_free * + ********************************/ -/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ -struct hwrm_cfa_l2_filter_cfg_input { +/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ +struct hwrm_cfa_meter_instance_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24248,80 +33094,37 @@ struct hwrm_cfa_l2_filter_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; + uint8_t flags; /* * Enumeration denoting the RX, TX type of the resource. * This enumeration is used for resources that are similar for both * TX and RX paths of the chip. */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \ - UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) /* tx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \ UINT32_C(0x0) /* rx path */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \ - UINT32_C(0x2) - /* - * Enumeration denoting NO_ROCE_L2 to support old drivers. - * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic - */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \ - UINT32_C(0xc) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2 - /* To support old drivers */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \ - (UINT32_C(0x0) << 2) - /* Only L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \ - (UINT32_C(0x1) << 2) - /* Roce & L2 traffic */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \ - (UINT32_C(0x2) << 2) - #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \ - HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE - uint32_t enables; - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \ + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \ UINT32_C(0x1) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX + uint8_t unused_0; + /* This value identifies a meter instance in CFA. */ + uint16_t meter_instance_id; /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint32_t dst_id; - /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. + * A value of 0xfff is considered invalid and implies the + * instance is not configured. */ - uint32_t new_mirror_vnic_id; -} __attribute__((packed)); + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \ + UINT32_C(0xffff) + #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ + HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID + uint8_t unused_1[4]; +} __rte_packed; -/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_l2_filter_cfg_output { +/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ +struct hwrm_cfa_meter_instance_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24333,21 +33136,21 @@ struct hwrm_cfa_l2_filter_cfg_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*************************** - * hwrm_cfa_l2_set_rx_mask * - ***************************/ +/******************************* + * hwrm_cfa_decap_filter_alloc * + *******************************/ -/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ -struct hwrm_cfa_l2_set_rx_mask_input { +/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ +struct hwrm_cfa_decap_filter_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24376,227 +33179,275 @@ struct hwrm_cfa_l2_set_rx_mask_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* VNIC ID */ - uint32_t vnic_id; - uint32_t mask; + uint32_t flags; + /* ovs_tunnel is 1 b */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \ + UINT32_C(0x1) + uint32_t enables; /* - * When this bit is '1', the function is requested to accept - * multi-cast packets specified by the multicast addr table. + * This bit must be '1' for the tunnel_type field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the tunnel_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \ UINT32_C(0x2) /* - * When this bit is '1', the function is requested to accept - * all multi-cast packets. + * This bit must be '1' for the src_macaddr field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ UINT32_C(0x4) /* - * When this bit is '1', the function is requested to accept - * broadcast packets. + * This bit must be '1' for the dst_macaddr field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ UINT32_C(0x8) /* - * When this bit is '1', the function is requested to be - * put in the promiscuous mode. - * - * The HWRM should accept any function to set up - * promiscuous mode. - * - * The HWRM shall follow the semantics below for the - * promiscuous mode support. - * # When partitioning is not enabled on a port - * (i.e. single PF on the port), then the PF shall - * be allowed to be in the promiscuous mode. When the - * PF is in the promiscuous mode, then it shall - * receive all host bound traffic on that port. - * # When partitioning is enabled on a port - * (i.e. multiple PFs per port) and a PF on that - * port is in the promiscuous mode, then the PF - * receives all traffic within that partition as - * identified by a unique identifier for the - * PF (e.g. S-Tag). If a unique outer VLAN - * for the PF is specified, then the setting of - * promiscuous mode on that PF shall result in the - * PF receiving all host bound traffic with matching - * outer VLAN. - * # A VF shall can be set in the promiscuous mode. - * In the promiscuous mode, the VF does not receive any - * traffic unless a unique outer VLAN for the - * VF is specified. If a unique outer VLAN - * for the VF is specified, then the setting of - * promiscuous mode on that VF shall result in the - * VF receiving all host bound traffic with the - * matching outer VLAN. - * # The HWRM shall allow the setting of promiscuous - * mode on a function independently from the - * promiscuous mode settings on other functions. + * This bit must be '1' for the ovlan_vid field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \ UINT32_C(0x10) /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the outermost Layer 2 destination MAC - * address field. + * This bit must be '1' for the ivlan_vid field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \ UINT32_C(0x20) /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for the VLAN-tagged packets that match the - * TPID and VID fields of VLAN tags in the VLAN tag - * table specified in this command. + * This bit must be '1' for the t_ovlan_vid field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \ UINT32_C(0x40) /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets that match the TPID and VID fields of VLAN - * tags in the VLAN tag table specified in this command. + * This bit must be '1' for the t_ivlan_vid field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \ UINT32_C(0x80) /* - * If this flag is set, the corresponding RX - * filters shall be set up to cover multicast/broadcast - * filters for non-VLAN tagged packets and VLAN-tagged - * packets matching any VLAN tag. - * - * If this flag is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan - * flags is set, then the HWRM shall ignore - * VLAN tags specified in vlan_tag_tbl. - * - * The HWRM client shall set at most one flag out of - * vlanonly, vlan_nonvlan, and anyvlan_nonvlan. + * This bit must be '1' for the ethertype field to be + * configured. */ - #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ UINT32_C(0x100) - /* This is the address for mcast address tbl. */ - uint64_t mc_tbl_addr; /* - * This value indicates how many entries in mc_tbl are valid. - * Each entry is 6 bytes. + * This bit must be '1' for the src_ipaddr field to be + * configured. */ - uint32_t num_mc_entries; - uint8_t unused_0[4]; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + UINT32_C(0x200) /* - * This is the address for VLAN tag table. - * Each VLAN entry in the table is 4 bytes of a VLAN tag - * including TPID, PCP, DEI, and VID fields in network byte - * order. + * This bit must be '1' for the dst_ipaddr field to be + * configured. */ - uint64_t vlan_tag_tbl_addr; + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + UINT32_C(0x400) + /* + * This bit must be '1' for the ipaddr_type field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + UINT32_C(0x800) + /* + * This bit must be '1' for the ip_protocol field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + UINT32_C(0x1000) + /* + * This bit must be '1' for the src_port field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + UINT32_C(0x2000) + /* + * This bit must be '1' for the dst_port field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + UINT32_C(0x4000) + /* + * This bit must be '1' for the dst_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ + UINT32_C(0x8000) + /* + * This bit must be '1' for the mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + UINT32_C(0x10000) + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. + * Only lower 24-bits of VNI field are used + * in setting up the filter. + */ + uint32_t tunnel_id; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused_0; + uint16_t unused_1; + /* + * This value indicates the source MAC address in + * the Ethernet header. + */ + uint8_t src_macaddr[6]; + uint8_t unused_2[2]; + /* + * This value indicates the destination MAC address in + * the Ethernet header. + */ + uint8_t dst_macaddr[6]; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the Ethernet header. + */ + uint16_t ovlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag + * in the Ethernet header. + */ + uint16_t ivlan_vid; + /* + * This value indicates the VLAN ID of the outer VLAN tag + * in the tunnel Ethernet header. + */ + uint16_t t_ovlan_vid; /* - * This value indicates how many entries in vlan_tag_tbl are - * valid. Each entry is 4 bytes. + * This value indicates the VLAN ID of the inner VLAN tag + * in the tunnel Ethernet header. */ - uint32_t num_vlan_tags; - uint8_t unused_1[4]; -} __attribute__((packed)); - -/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ -struct hwrm_cfa_l2_set_rx_mask_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint8_t unused_0[7]; + uint16_t t_ivlan_vid; + /* This value indicates the ethertype in the Ethernet header. */ + uint16_t ethertype; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This value indicates the type of IP address. + * 4 - IPv4 + * 6 - IPv6 + * All others are invalid. */ - uint8_t valid; -} __attribute__((packed)); - -/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ -struct hwrm_cfa_l2_set_rx_mask_cmd_err { + uint8_t ip_addr_type; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ + UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ + UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ + UINT32_C(0x6) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. + * The value of protocol filed in IP header. + * Applies to UDP and TCP traffic. + * 6 - TCP + * 17 - UDP */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \ + uint8_t ip_protocol; + /* invalid */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ UINT32_C(0x0) - /* Unable to complete operation due to conflict with Ntuple Filter */ - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \ - UINT32_C(0x1) - #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \ - HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR - uint8_t unused_0[7]; -} __attribute__((packed)); - -/******************************* - * hwrm_cfa_vlan_antispoof_cfg * - *******************************/ - - -/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_cfg_input { - /* The HWRM command request type. */ - uint16_t req_type; + /* TCP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ + UINT32_C(0x6) + /* UDP */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ + UINT32_C(0x11) + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ + HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + uint16_t unused_3; + uint32_t unused_4; /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * The value of source IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - uint16_t cmpl_ring; + uint32_t src_ipaddr[4]; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * The value of destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. */ - uint16_t seq_id; + uint32_t dst_ipaddr[4]; /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * The value of source port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint16_t target_id; + uint16_t src_port; /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * The value of destination port to be used in filtering. + * Applies to UDP and TCP traffic. */ - uint64_t resp_addr; + uint16_t dst_port; /* - * Function ID of the function that is being configured. - * Only valid for a VF FID configured by the PF. + * If set, this value shall represent the + * Logical VNIC ID of the destination VNIC for the RX + * path. */ - uint16_t fid; - uint8_t unused_0[2]; - /* Number of VLAN entries in the vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; + uint16_t dst_id; /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table. Each table entry contains the 16-bit TPID - * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask, - * all in network order to match hwrm_cfa_l2_set_rx_mask. - * For an individual VLAN entry, the mask value should be 0xfff - * for the 12-bit VLAN ID. + * If set, this value shall represent the L2 context that matches the L2 + * information of the decap filter. */ - uint64_t vlan_tag_mask_tbl_addr; -} __attribute__((packed)); + uint16_t l2_ctxt_ref_id; +} __rte_packed; -/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_cfg_output { +/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ +struct hwrm_cfa_decap_filter_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24605,24 +33456,26 @@ struct hwrm_cfa_vlan_antispoof_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************** - * hwrm_cfa_vlan_antispoof_qcfg * - ********************************/ +/****************************** + * hwrm_cfa_decap_filter_free * + ******************************/ -/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_input { +/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ +struct hwrm_cfa_decap_filter_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24651,30 +33504,13 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being queried. - * Only valid for a VF FID queried by the PF. - */ - uint16_t fid; - uint8_t unused_0[2]; - /* - * Maximum number of VLAN entries the firmware is allowed to DMA - * to vlan_tag_mask_tbl. - */ - uint32_t max_vlan_entries; - /* - * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN - * antispoof table to which firmware will DMA to. Each table - * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only), - * 16-bit VLAN ID, and a 16-bit mask, all in network order to - * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, - * the mask value should be 0xfff for the 12-bit VLAN ID. - */ - uint64_t vlan_tag_mask_tbl_addr; -} __attribute__((packed)); + /* This value is an opaque id into CFA data structures. */ + uint32_t decap_filter_id; + uint8_t unused_0[4]; +} __rte_packed; -/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */ -struct hwrm_cfa_vlan_antispoof_qcfg_output { +/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ +struct hwrm_cfa_decap_filter_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24683,26 +33519,24 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */ - uint32_t num_vlan_entries; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************** - * hwrm_cfa_tunnel_filter_alloc * - ********************************/ +/*********************** + * hwrm_cfa_flow_alloc * + ***********************/ -/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ -struct hwrm_cfa_tunnel_filter_alloc_input { +/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ +struct hwrm_cfa_flow_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24731,220 +33565,255 @@ struct hwrm_cfa_tunnel_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ + uint16_t flags; + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \ UINT32_C(0x1) - uint32_t enables; + /* num_vlan is 2 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \ + UINT32_C(0x6) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 + /* no tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \ + (UINT32_C(0x0) << 1) + /* 1 tag */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \ + (UINT32_C(0x1) << 1) + /* 2 tags */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \ + (UINT32_C(0x2) << 1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO + /* Enumeration denoting the Flow Type. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \ + UINT32_C(0x38) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 + /* L2 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \ + (UINT32_C(0x0) << 3) + /* IPV4 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \ + (UINT32_C(0x1) << 3) + /* IPV6 flow */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \ + (UINT32_C(0x2) << 3) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 /* - * This bit must be '1' for the l2_filter_id field to be - * configured. + * when set to 1, indicates TX flow offload for function specified in src_fid and + * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both + * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload + * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV + * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID + * belong to the children VFs of the same PF to indicate VM to VM flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ - UINT32_C(0x1) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ + UINT32_C(0x40) /* - * This bit must be '1' for the l2_addr field to be - * configured. + * when set to 1, indicates RX flow offload for function specified in dst_fid and + * the src_fid should be set to invalid value. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \ - UINT32_C(0x2) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x80) /* - * This bit must be '1' for the l2_ivlan field to be - * configured. + * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is + * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field. + * This flag is only valid when the flow direction is RX. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \ - UINT32_C(0x4) + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ + UINT32_C(0x100) + /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \ + UINT32_C(0x200) /* - * This bit must be '1' for the l3_addr field to be - * configured. + * Tx Flow: vf fid. + * Rx Flow: pf fid. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \ - UINT32_C(0x8) + uint16_t src_fid; + /* Tunnel handle valid when tunnel flag is set. */ + uint32_t tunnel_handle; + uint16_t action_flags; /* - * This bit must be '1' for the l3_addr_type field to be - * configured. + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \ - UINT32_C(0x10) + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ + UINT32_C(0x1) + /* recycle is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ + UINT32_C(0x2) /* - * This bit must be '1' for the t_l3_addr_type field to be - * configured. + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ + UINT32_C(0x4) + /* meter is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \ + UINT32_C(0x8) + /* tunnel is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \ + UINT32_C(0x10) + /* nat_src is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \ UINT32_C(0x20) - /* - * This bit must be '1' for the t_l3_addr field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \ + /* nat_dest is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \ UINT32_C(0x40) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + /* nat_ipv4_address is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \ UINT32_C(0x80) - /* - * This bit must be '1' for the vni field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \ + /* l2_header_rewrite is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \ UINT32_C(0x100) - /* - * This bit must be '1' for the dst_vnic_id field to be - * configured. - */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \ + /* ttl_decrement is 1 b */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ UINT32_C(0x200) /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. + * If set to 1 and flow direction is TX, it indicates decap of L2 header + * and encap of tunnel header. If set to 1 and flow direction is RX, it + * indicates decap of tunnel header and encap L2 header. The type of tunnel + * is specified in the tunnel_type field. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ UINT32_C(0x400) + /* If set to 1, flow aging is enabled for this flow. */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \ + UINT32_C(0x800) /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This value sets the match value for the inner L2 - * MAC address. - * Destination MAC address for RX path. - * Source MAC address for TX path. - */ - uint8_t l2_addr[6]; - /* - * This value sets VLAN ID value for inner VLAN. - * Only 12-bits of VLAN ID are used in setting the filter. - */ - uint16_t l2_ivlan; - /* - * The value of inner destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t l3_addr[4]; - /* - * The value of tunnel destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * If set to 1 an attempt will be made to try to offload this flow to the + * most optimal flow table resource. If set to 0, the flow will be + * placed to the default flow table resource. */ - uint32_t t_l3_addr[4]; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ + UINT32_C(0x1000) /* - * This value indicates the type of inner IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * If set to 1 there will be no attempt to allocate an on-chip try to + * offload this flow. If set to 0, which will keep compatibility with the + * older drivers, will cause the FW to attempt to allocate an on-chip flow + * counter for the newly created flow. This will keep the existing behavior + * with EM flows which always had an associated flow counter. */ - uint8_t l3_addr_type; + #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ + UINT32_C(0x2000) /* - * This value indicates the type of tunnel IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * Tx Flow: pf or vf fid. + * Rx Flow: vf fid. */ - uint8_t t_l3_addr_type; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL + uint16_t dst_fid; + /* VLAN tpid, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci, valid when push_vlan flag is set. */ + uint16_t l2_rewrite_vlan_tci; + /* Meter id, valid when meter flag is set. */ + uint16_t act_meter_id; + /* Flow with the same l2 context tcam key. */ + uint16_t ref_flow_handle; + /* This value sets the match value for the ethertype. */ + uint16_t ethertype; + /* valid when num tags is 1 or 2. */ + uint16_t outer_vlan_tci; + /* This value sets the match value for the Destination MAC address. */ + uint16_t dmac[3]; + /* valid when num tags is 2. */ + uint16_t inner_vlan_tci; + /* This value sets the match value for the Source MAC address. */ + uint16_t smac[3]; + /* The bit length of destination IP address mask. */ + uint8_t ip_dst_mask_len; + /* The bit length of source IP address mask. */ + uint8_t ip_src_mask_len; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; /* - * tunnel_flags allows the user to indicate the tunnel tag detection - * for the tunnel type specified in tunnel_type. + * The value of source port. + * Applies to UDP and TCP traffic. */ - uint8_t tunnel_flags; + uint16_t l4_src_port; /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to match the geneve OAM packet. - * If the tunnel_type is nvgre or gre, then this bit indicates if - * we need to detect checksum present bit in geneve header. - * If the tunnel_type is mpls, then this bit indicates if we need - * to match mpls packet with explicit IPV4/IPV6 null header. + * The value of source port mask. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \ - UINT32_C(0x1) + uint16_t l4_src_port_mask; /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to detect the critical option bit set in the oam packet. - * If the tunnel_type is nvgre or gre, then this bit indicates - * if we need to match nvgre packets with key present bit set in - * gre header. - * If the tunnel_type is mpls, then this bit indicates if we - * need to match mpls packet with S bit from inner/second label. + * The value of destination port. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \ - UINT32_C(0x2) + uint16_t l4_dst_port; /* - * If the tunnel_type is geneve, then this bit indicates if we - * need to match geneve packet with extended header bit set in - * geneve header. - * If the tunnel_type is nvgre or gre, then this bit indicates - * if we need to match nvgre packets with sequence number - * present bit set in gre header. - * If the tunnel_type is mpls, then this bit indicates if we - * need to match mpls packet with S bit from out/first label. + * The value of destination port mask. + * Applies to UDP and TCP traffic. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \ - UINT32_C(0x4) + uint16_t l4_dst_port_mask; /* - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. + * NAT IPv4/6 address based on address type flag. + * 0 values are ignored. */ - uint32_t vni; - /* Logical VNIC ID of the destination VNIC. */ - uint32_t dst_vnic_id; + uint32_t nat_ip_address[4]; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * The NAT source/destination port based on direction flag. + * Applies to UDP and TCP traffic. + * 0 values are ignored. */ - uint32_t mirror_vnic_id; -} __attribute__((packed)); + uint16_t nat_port; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* The value of ip protocol. */ + uint8_t ip_proto; + /* Tunnel Type. */ + uint8_t tunnel_type; + /* Non-tunnel */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ + UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + UINT32_C(0xc) + /* Any tunneled traffic */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + UINT32_C(0xff) + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL +} __rte_packed; -/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_tunnel_filter_alloc_output { +/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ +struct hwrm_cfa_flow_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -24953,8 +33822,9 @@ struct hwrm_cfa_tunnel_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t tunnel_filter_id; + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[2]; /* * The flow id value in bit 0-29 is the actual ID of the flow * associated with this filter and it shall be used to match @@ -24964,55 +33834,86 @@ struct hwrm_cfa_tunnel_filter_alloc_output { */ uint32_t flow_id; /* Indicate the flow id value. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ UINT32_C(0x3fffffff) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 /* Indicate type of the flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ UINT32_C(0x40000000) /* * If this bit set to 0, then it indicates that the flow is * internal flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ (UINT32_C(0x0) << 30) /* * If this bit is set to 1, then it indicates that the flow is * external flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ (UINT32_C(0x1) << 30) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ + HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT /* Indicate the flow direction. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ UINT32_C(0x80000000) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ (UINT32_C(0x0) << 31) /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ (UINT32_C(0x1) << 31) - #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ + HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; + uint32_t flow_counter_id; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************* - * hwrm_cfa_tunnel_filter_free * - *******************************/ +/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ +struct hwrm_cfa_flow_alloc_cmd_err { + /* + * command specific error codes that goes to + * the cmd_err field in Common HWRM Error Response. + */ + uint8_t code; + /* Unknown error */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) + /* No more L2 Context TCAM */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1) + /* No more action records */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2) + /* No more flow counters */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) + /* No more wild-card TCAM */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) + /* Hash collsion in exact match tables */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) + /* Key is already installed */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) + /* Flow Context DB is out of resource */ + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7) + #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \ + HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB + uint8_t unused_0[7]; +} __rte_packed; +/********************** + * hwrm_cfa_flow_free * + **********************/ -/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_tunnel_filter_free_input { + +/* hwrm_cfa_flow_free_input (size:256b/32B) */ +struct hwrm_cfa_flow_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25041,12 +33942,17 @@ struct hwrm_cfa_tunnel_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t tunnel_filter_id; -} __attribute__((packed)); + /* Flow record index. */ + uint16_t flow_handle; + uint16_t unused_0; + /* Flow counter id to be freed. */ + uint32_t flow_counter_id; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; +} __rte_packed; -/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_tunnel_filter_free_output { +/* hwrm_cfa_flow_free_output (size:256b/32B) */ +struct hwrm_cfa_flow_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25055,110 +33961,470 @@ struct hwrm_cfa_tunnel_filter_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* packet is 64 b */ + uint64_t packet; + /* byte is 64 b */ + uint64_t byte; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); - -/*************************************** - * hwrm_cfa_redirect_tunnel_type_alloc * - ***************************************/ +} __rte_packed; - -/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_alloc_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; +/* hwrm_cfa_flow_action_data (size:960b/120B) */ +struct hwrm_cfa_flow_action_data { + uint16_t action_flags; + /* Setting of this flag indicates accept action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \ + UINT32_C(0x1) + /* Setting of this flag indicates recycle action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \ + UINT32_C(0x2) + /* Setting of this flag indicates drop action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \ + UINT32_C(0x4) + /* Setting of this flag indicates meter action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \ + UINT32_C(0x8) + /* Setting of this flag indicates tunnel action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \ + UINT32_C(0x10) /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If set to 1 and flow direction is TX, it indicates decap of L2 header + * and encap of tunnel header. If set to 1 and flow direction is RX, it + * indicates decap of tunnel header and encap L2 header. */ - uint64_t resp_addr; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \ + UINT32_C(0x20) + /* Setting of this flag indicates ttl decrement action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \ + UINT32_C(0x40) + /* If set to 1, flow aging is enabled for this flow. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \ + UINT32_C(0x80) + /* Setting of this flag indicates encap action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \ + UINT32_C(0x100) + /* Setting of this flag indicates decap action. */ + #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \ + UINT32_C(0x200) + /* Meter id. */ + uint16_t act_meter_id; + /* VNIC id. */ + uint16_t vnic_id; + /* vport number. */ + uint16_t vport_id; + /* The NAT source/destination. */ + uint16_t nat_port; + uint16_t unused_0[3]; + /* NAT IPv4/IPv6 address. */ + uint32_t nat_ip_address[4]; + /* Encapsulation Type. */ + uint8_t encap_type; + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ + HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 + uint8_t unused[7]; + /* This value is encap data for the associated encap type. */ + uint32_t encap_data[20]; +} __rte_packed; + +/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ +struct hwrm_cfa_flow_tunnel_hdr_data { /* Tunnel Type. */ uint8_t tunnel_type; /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \ UINT32_C(0x0) /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \ UINT32_C(0x1) /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \ UINT32_C(0x2) /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \ UINT32_C(0x3) /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \ UINT32_C(0x4) /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \ UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \ UINT32_C(0x6) /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \ UINT32_C(0x7) /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \ UINT32_C(0x8) /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \ UINT32_C(0x9) /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \ UINT32_C(0xa) /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \ UINT32_C(0xb) /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* Tunnel alloc flags. */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \ + HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL + uint8_t unused[3]; + /* + * Tunnel identifier. + * Virtual Network Identifier (VNI). + */ + uint32_t tunnel_id; +} __rte_packed; + +/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ +struct hwrm_cfa_flow_l4_key_data { + /* The value of source port. */ + uint16_t l4_src_port; + /* The value of destination port. */ + uint16_t l4_dst_port; + uint32_t unused; +} __rte_packed; + +/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ +struct hwrm_cfa_flow_l3_key_data { + /* The value of ip protocol. */ + uint8_t ip_protocol; + uint8_t unused_0[7]; + /* The value of destination IPv4/IPv6 address. */ + uint32_t ip_dst[4]; + /* The source IPv4/IPv6 address. */ + uint32_t ip_src[4]; + /* NAT IPv4/IPv6 address. */ + uint32_t nat_ip_address[4]; + uint32_t unused[2]; +} __rte_packed; + +/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ +struct hwrm_cfa_flow_l2_key_data { + /* Destination MAC address. */ + uint16_t dmac[3]; + uint16_t unused_0; + /* Source MAC address. */ + uint16_t smac[3]; + uint16_t unused_1; + /* L2 header re-write Destination MAC address. */ + uint16_t l2_rewrite_dmac[3]; + uint16_t unused_2; + /* L2 header re-write Source MAC address. */ + uint16_t l2_rewrite_smac[3]; + /* Ethertype. */ + uint16_t ethertype; + /* Number of VLAN tags. */ + uint16_t num_vlan_tags; + /* VLAN tpid. */ + uint16_t l2_rewrite_vlan_tpid; + /* VLAN tci. */ + uint16_t l2_rewrite_vlan_tci; + uint8_t unused_3[2]; + /* Outer VLAN TPID. */ + uint16_t ovlan_tpid; + /* Outer VLAN TCI. */ + uint16_t ovlan_tci; + /* Inner VLAN TPID. */ + uint16_t ivlan_tpid; + /* Inner VLAN TCI. */ + uint16_t ivlan_tci; + uint8_t unused[8]; +} __rte_packed; + +/* hwrm_cfa_flow_key_data (size:4160b/520B) */ +struct hwrm_cfa_flow_key_data { + /* Flow associated tunnel L2 header key info. */ + uint32_t t_l2_key_data[14]; + /* Flow associated tunnel L2 header mask info. */ + uint32_t t_l2_key_mask[14]; + /* Flow associated tunnel L3 header key info. */ + uint32_t t_l3_key_data[16]; + /* Flow associated tunnel L3 header mask info. */ + uint32_t t_l3_key_mask[16]; + /* Flow associated tunnel L4 header key info. */ + uint32_t t_l4_key_data[2]; + /* Flow associated tunnel L4 header mask info. */ + uint32_t t_l4_key_mask[2]; + /* Flow associated tunnel header info. */ + uint32_t tunnel_hdr[2]; + /* Flow associated L2 header key info. */ + uint32_t l2_key_data[14]; + /* Flow associated L2 header mask info. */ + uint32_t l2_key_mask[14]; + /* Flow associated L3 header key info. */ + uint32_t l3_key_data[16]; + /* Flow associated L3 header mask info. */ + uint32_t l3_key_mask[16]; + /* Flow associated L4 header key info. */ + uint32_t l4_key_data[2]; + /* Flow associated L4 header mask info. */ + uint32_t l4_key_mask[2]; +} __rte_packed; + +/********************** + * hwrm_cfa_flow_info * + **********************/ + + +/* hwrm_cfa_flow_info_input (size:256b/32B) */ +struct hwrm_cfa_flow_info_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Flow record index. */ + uint16_t flow_handle; + /* Max flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ + UINT32_C(0xfff) + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ + UINT32_C(0x1000) + /* RoCEv1 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \ + UINT32_C(0x2000) + /* RoCEv2 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \ + UINT32_C(0x4000) + /* Direction rx = 1 */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ + UINT32_C(0x8000) + uint8_t unused_0[6]; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; +} __rte_packed; + +/* hwrm_cfa_flow_info_output (size:5632b/704B) */ +struct hwrm_cfa_flow_info_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint8_t flags; - /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \ + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) + /* profile is 8 b */ + uint8_t profile; + /* src_fid is 16 b */ + uint16_t src_fid; + /* dst_fid is 16 b */ + uint16_t dst_fid; + /* l2_ctxt_id is 16 b */ + uint16_t l2_ctxt_id; + /* em_info is 64 b */ + uint64_t em_info; + /* tcam_info is 64 b */ + uint64_t tcam_info; + /* vfp_tcam_info is 64 b */ + uint64_t vfp_tcam_info; + /* ar_id is 16 b */ + uint16_t ar_id; + /* flow_handle is 16 b */ + uint16_t flow_handle; + /* tunnel_handle is 32 b */ + uint32_t tunnel_handle; + /* The flow aging timer for the flow, the unit is 100 milliseconds */ + uint16_t flow_timer; + uint8_t unused_0[6]; + /* Flow associated L2, L3 and L4 headers info. */ + uint32_t flow_key_data[130]; + /* Flow associated action record info. */ + uint32_t flow_action_info[30]; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_cfa_flow_flush * + ***********************/ + + +/* hwrm_cfa_flow_flush_input (size:256b/32B) */ +struct hwrm_cfa_flow_flush_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* flags is 32 b */ + uint32_t flags; + /* + * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr + * fields are valid. The flow flush operation should only flush the flows from the + * flow table specified. This flag is set to 0 by older driver. For older firmware, + * setting this flag has no effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \ UINT32_C(0x1) - uint8_t unused_0[4]; -} __attribute__((packed)); + /* + * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA + * context memory tables etc. This flag is set to 0 by older driver. For older firmware, + * setting this flag has no effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ + UINT32_C(0x2) + /* + * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller. + * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \ + UINT32_C(0x4) + /* Set to 1 to indicate the flow counter IDs are included in the flow table. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \ + UINT32_C(0x8000000) + /* + * This specifies the size of flow handle entries provided by the driver + * in the flow table specified below. Only two flow handle size enums are defined. + */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \ + UINT32_C(0xc0000000) + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \ + 30 + /* The flow handle is 16bit */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \ + (UINT32_C(0x0) << 30) + /* The flow handle is 64bit */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \ + (UINT32_C(0x1) << 30) + #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \ + HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT + /* Specify page size of the flow table memory. */ + uint8_t page_size; + /* The page size is 4K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* The page size is 8K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* The page size is 64K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* The page size is 256K */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* The page size is 1M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* The page size is 2M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* The page size is 4M */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* The page size is 1G */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \ + HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G + /* FLow table memory indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 + /* number of flows in the flow table */ + uint16_t num_flows; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} __rte_packed; -/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_alloc_output { +/* hwrm_cfa_flow_flush_output (size:128b/16B) */ +struct hwrm_cfa_flow_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25170,21 +34436,21 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************************** - * hwrm_cfa_redirect_tunnel_type_free * - **************************************/ +/*********************** + * hwrm_cfa_flow_stats * + ***********************/ -/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_free_input { +/* hwrm_cfa_flow_stats_input (size:640b/80B) */ +struct hwrm_cfa_flow_stats_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25213,59 +34479,53 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[5]; -} __attribute__((packed)); + /* Flow handle. */ + uint16_t num_flows; + /* Flow handle. */ + uint16_t flow_handle_0; + /* Flow handle. */ + uint16_t flow_handle_1; + /* Flow handle. */ + uint16_t flow_handle_2; + /* Flow handle. */ + uint16_t flow_handle_3; + /* Flow handle. */ + uint16_t flow_handle_4; + /* Flow handle. */ + uint16_t flow_handle_5; + /* Flow handle. */ + uint16_t flow_handle_6; + /* Flow handle. */ + uint16_t flow_handle_7; + /* Flow handle. */ + uint16_t flow_handle_8; + /* Flow handle. */ + uint16_t flow_handle_9; + uint8_t unused_0[2]; + /* Flow ID of a flow. */ + uint32_t flow_id_0; + /* Flow ID of a flow. */ + uint32_t flow_id_1; + /* Flow ID of a flow. */ + uint32_t flow_id_2; + /* Flow ID of a flow. */ + uint32_t flow_id_3; + /* Flow ID of a flow. */ + uint32_t flow_id_4; + /* Flow ID of a flow. */ + uint32_t flow_id_5; + /* Flow ID of a flow. */ + uint32_t flow_id_6; + /* Flow ID of a flow. */ + uint32_t flow_id_7; + /* Flow ID of a flow. */ + uint32_t flow_id_8; + /* Flow ID of a flow. */ + uint32_t flow_id_9; +} __rte_packed; -/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_free_output { +/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ +struct hwrm_cfa_flow_stats_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25274,24 +34534,64 @@ struct hwrm_cfa_redirect_tunnel_type_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* packet_0 is 64 b */ + uint64_t packet_0; + /* packet_1 is 64 b */ + uint64_t packet_1; + /* packet_2 is 64 b */ + uint64_t packet_2; + /* packet_3 is 64 b */ + uint64_t packet_3; + /* packet_4 is 64 b */ + uint64_t packet_4; + /* packet_5 is 64 b */ + uint64_t packet_5; + /* packet_6 is 64 b */ + uint64_t packet_6; + /* packet_7 is 64 b */ + uint64_t packet_7; + /* packet_8 is 64 b */ + uint64_t packet_8; + /* packet_9 is 64 b */ + uint64_t packet_9; + /* byte_0 is 64 b */ + uint64_t byte_0; + /* byte_1 is 64 b */ + uint64_t byte_1; + /* byte_2 is 64 b */ + uint64_t byte_2; + /* byte_3 is 64 b */ + uint64_t byte_3; + /* byte_4 is 64 b */ + uint64_t byte_4; + /* byte_5 is 64 b */ + uint64_t byte_5; + /* byte_6 is 64 b */ + uint64_t byte_6; + /* byte_7 is 64 b */ + uint64_t byte_7; + /* byte_8 is 64 b */ + uint64_t byte_8; + /* byte_9 is 64 b */ + uint64_t byte_9; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************************** - * hwrm_cfa_redirect_tunnel_type_info * - **************************************/ +/*********************************** + * hwrm_cfa_flow_aging_timer_reset * + ***********************************/ -/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */ -struct hwrm_cfa_redirect_tunnel_type_info_input { +/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ +struct hwrm_cfa_flow_aging_timer_reset_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25320,59 +34620,20 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The source function id. */ - uint16_t src_fid; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[5]; -} __attribute__((packed)); + /* Flow record index. */ + uint16_t flow_handle; + uint8_t unused_0[2]; + /* + * New flow timer value for the flow specified in the ext_flow_handle. + * The flow timer unit is 100ms. + */ + uint32_t flow_timer; + /* This value identifies a set of CFA data structures used for a flow. */ + uint64_t ext_flow_handle; +} __rte_packed; -/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */ -struct hwrm_cfa_redirect_tunnel_type_info_output { +/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ +struct hwrm_cfa_flow_aging_timer_reset_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25381,133 +34642,24 @@ struct hwrm_cfa_redirect_tunnel_type_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The destination function id, to whom the traffic is redirected. */ - uint16_t dest_fid; - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); - -/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ -struct hwrm_vxlan_ipv4_hdr { - /* IPv4 version and header length. */ - uint8_t ver_hlen; - /* IPv4 header length */ - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf) - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 - /* Version */ - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0) - #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 - /* IPv4 type of service. */ - uint8_t tos; - /* IPv4 identification. */ - uint16_t ip_id; - /* IPv4 flags and offset. */ - uint16_t flags_frag_offset; - /* IPv4 TTL. */ - uint8_t ttl; - /* IPv4 protocol. */ - uint8_t protocol; - /* IPv4 source address. */ - uint32_t src_ip_addr; - /* IPv4 destination address. */ - uint32_t dest_ip_addr; -} __attribute__((packed)); - -/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ -struct hwrm_vxlan_ipv6_hdr { - /* IPv6 version, traffic class and flow label. */ - uint32_t ver_tc_flow_label; - /* IPv6 version shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \ - UINT32_C(0x1c) - /* IPv6 version mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \ - UINT32_C(0xf0000000) - /* IPv6 TC shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \ - UINT32_C(0x14) - /* IPv6 TC mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \ - UINT32_C(0xff00000) - /* IPv6 flow label shift */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \ - UINT32_C(0x0) - /* IPv6 flow label mask */ - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \ - UINT32_C(0xfffff) - #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \ - HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK - /* IPv6 payload length. */ - uint16_t payload_len; - /* IPv6 next header. */ - uint8_t next_hdr; - /* IPv6 TTL. */ - uint8_t ttl; - /* IPv6 source address. */ - uint32_t src_ip_addr[4]; - /* IPv6 destination address. */ - uint32_t dest_ip_addr[4]; -} __attribute__((packed)); - -/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ -struct hwrm_cfa_encap_data_vxlan { - /* Source MAC address. */ - uint8_t src_mac_addr[6]; - /* reserved. */ - uint16_t unused_0; - /* Destination MAC address. */ - uint8_t dst_mac_addr[6]; - /* Number of VLAN tags. */ - uint8_t num_vlan_tags; - /* reserved. */ - uint8_t unused_1; - /* Outer VLAN TPID. */ - uint16_t ovlan_tpid; - /* Outer VLAN TCI. */ - uint16_t ovlan_tci; - /* Inner VLAN TPID. */ - uint16_t ivlan_tpid; - /* Inner VLAN TCI. */ - uint16_t ivlan_tci; - /* L3 header fields. */ - uint32_t l3[10]; - /* IP version mask. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf) - /* IP version 4. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4) - /* IP version 6. */ - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6) - #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \ - HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 - /* UDP source port. */ - uint16_t src_port; - /* UDP destination port. */ - uint16_t dst_port; - /* VXLAN Network Identifier. */ - uint32_t vni; - /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */ - uint8_t hdr_rsvd0[3]; - /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */ - uint8_t hdr_rsvd1; - /* VXLAN header flags field. */ - uint8_t hdr_flags; - uint8_t unused[3]; -} __attribute__((packed)); +} __rte_packed; -/******************************* - * hwrm_cfa_encap_record_alloc * - *******************************/ +/*************************** + * hwrm_cfa_flow_aging_cfg * + ***************************/ -/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ -struct hwrm_cfa_encap_record_alloc_input { +/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ +struct hwrm_cfa_flow_aging_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25536,64 +34688,77 @@ struct hwrm_cfa_encap_record_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x1) - /* - * Setting of this flag indicates this encap record is external encap record. - * Resetting of this flag indicates this flag is internal encap record and - * this is the default setting. - */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \ - UINT32_C(0x2) - /* Encapsulation Type. */ - uint8_t encap_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \ + /* The bit field to enable per flow aging configuration. */ + uint16_t enables; + /* This bit must be '1' for the tcp flow timer field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \ UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \ + /* This bit must be '1' for the tcp finish timer field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \ UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \ + /* This bit must be '1' for the udp flow timer field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \ UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \ - UINT32_C(0x6) - /* VLAN */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \ + /* This bit must be '1' for the eem dma interval field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \ UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ - HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 - uint8_t unused_0[3]; - /* This value is encap data used for the given encap type. */ - uint32_t encap_data[20]; -} __attribute__((packed)); + /* This bit must be '1' for the eem notice interval field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \ + UINT32_C(0x10) + /* This bit must be '1' for the eem context memory maximum entries field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \ + UINT32_C(0x20) + /* This bit must be '1' for the eem context memory ID field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \ + UINT32_C(0x40) + /* This bit must be '1' for the eem context memory type field to be configured */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \ + UINT32_C(0x80) + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the enable, disable eem flow aging configuration. */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \ + (UINT32_C(0x0) << 1) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \ + (UINT32_C(0x1) << 1) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \ + HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE + uint8_t unused_0; + /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */ + uint32_t tcp_flow_timer; + /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */ + uint32_t tcp_fin_timer; + /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */ + uint32_t udp_flow_timer; + /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ + uint16_t eem_dma_interval; + /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ + uint16_t eem_notice_interval; + /* The maximum entries number in the eem context memory. */ + uint32_t eem_ctx_max_entries; + /* The context memory ID for eem flow aging. */ + uint16_t eem_ctx_id; + uint16_t eem_ctx_mem_type; + /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */ + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \ + UINT32_C(0x0) + #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ + HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA + uint8_t unused_1[4]; +} __rte_packed; -/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ -struct hwrm_cfa_encap_record_alloc_output { +/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ +struct hwrm_cfa_flow_aging_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25602,26 +34767,24 @@ struct hwrm_cfa_encap_record_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint32_t encap_record_id; - uint8_t unused_0[3]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************************** - * hwrm_cfa_encap_record_free * - ******************************/ +/**************************** + * hwrm_cfa_flow_aging_qcfg * + ****************************/ -/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ -struct hwrm_cfa_encap_record_free_input { +/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ +struct hwrm_cfa_flow_aging_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25650,13 +34813,21 @@ struct hwrm_cfa_encap_record_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint32_t encap_record_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; +} __rte_packed; -/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ -struct hwrm_cfa_encap_record_free_output { +/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ +struct hwrm_cfa_flow_aging_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -25665,24 +34836,40 @@ struct hwrm_cfa_encap_record_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */ + uint32_t tcp_flow_timer; + /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */ + uint32_t tcp_fin_timer; + /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */ + uint32_t udp_flow_timer; + /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ + uint16_t eem_dma_interval; + /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ + uint16_t eem_notice_interval; + /* The maximum entries number in the eem context memory. */ + uint32_t eem_ctx_max_entries; + /* The context memory ID for eem flow aging. */ + uint16_t eem_ctx_id; + /* The context memory type for eem flow aging. */ + uint16_t eem_ctx_mem_type; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************** - * hwrm_cfa_ntuple_filter_alloc * - ********************************/ +/***************************** + * hwrm_cfa_flow_aging_qcaps * + *****************************/ -/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */ -struct hwrm_cfa_ntuple_filter_alloc_input { +/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ +struct hwrm_cfa_flow_aging_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -25711,344 +34898,21 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* Setting of this flag indicates the applicability to the loopback path. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \ - UINT32_C(0x1) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \ - UINT32_C(0x2) - /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \ - UINT32_C(0x4) - /* - * Setting of this flag indicates that the dest_id field contains function ID. - * If this is not set it indicates dest_id is VNIC or VPORT. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \ - UINT32_C(0x8) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ - UINT32_C(0x10) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ - UINT32_C(0x20) - /* - * This bit must be '1' for the src_ipaddr_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \ - UINT32_C(0x40) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ - UINT32_C(0x80) - /* - * This bit must be '1' for the dst_ipaddr_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \ - UINT32_C(0x100) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ - UINT32_C(0x200) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ - UINT32_C(0x400) - /* - * This bit must be '1' for the src_port_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \ - UINT32_C(0x800) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the dst_port_mask field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the pri_hint field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the ntuple_filter_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x20000) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x40000) - /* - * This bit must be '1' for the rfs_ring_tbl_idx field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \ - UINT32_C(0x80000) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; - /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ - UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ - UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ - UINT32_C(0x6) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 - /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ - UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ - UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ - UINT32_C(0x11) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint16_t dst_id; - /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint16_t mirror_vnic_id; - /* - * This value indicates the tunnel type for this filter. - * If this field is not specified, then the filter shall - * apply to both non-tunneled and tunneled packets. - * If this field conflicts with the tunnel_type specified - * in the l2_filter_id, then the HWRM shall return an - * error for this command. - */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - /* - * This hint is provided to help in placing - * the filter in the filter table. - */ - uint8_t pri_hint; - /* No preference */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \ - UINT32_C(0x0) - /* Above the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \ - UINT32_C(0x1) - /* Below the given filter */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \ - UINT32_C(0x2) - /* As high as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \ - UINT32_C(0x3) - /* As low as possible */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \ - UINT32_C(0x4) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST - /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t src_ipaddr[4]; - /* - * The value of source IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. - */ - uint32_t src_ipaddr_mask[4]; - /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t dst_ipaddr[4]; - /* - * The value of destination IP address mask to be used in - * filtering. - * For IPv4, first four bytes represent the IP address mask. - */ - uint32_t dst_ipaddr_mask[4]; - /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. - */ - uint16_t src_port; - /* - * The value of source port mask to be used in filtering. - * Applies to UDP and TCP traffic. - */ - uint16_t src_port_mask; - /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. - */ - uint16_t dst_port; - /* - * The value of destination port mask to be used in - * filtering. - * Applies to UDP and TCP traffic. - */ - uint16_t dst_port_mask; - /* - * This is the ID of the filter that goes along with - * the pri_hint. - */ - uint64_t ntuple_filter_id_hint; - /* - * The value of rfs_ring_tbl_idx to be used for RFS for this filter. - * This index is used in lieu of the RSS hash when selecting the - * index into the RSS table to determine the rx ring. - */ - uint16_t rfs_ring_tbl_idx; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ + uint8_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX + uint8_t unused_0[7]; +} __rte_packed; -/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_alloc_output { +/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ +struct hwrm_cfa_flow_aging_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26057,84 +34921,32 @@ struct hwrm_cfa_ntuple_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) - /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. - */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX - uint8_t unused_0[3]; + /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */ + uint32_t max_tcp_flow_timer; + /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */ + uint32_t max_tcp_fin_timer; + /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */ + uint32_t max_udp_flow_timer; + /* The maximum aging flows that HW can support. */ + uint32_t max_aging_flows; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); - -/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_ntuple_filter_alloc_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \ - UINT32_C(0x0) - /* Unable to complete operation due to conflict with Rx Mask VLAN */ - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \ - UINT32_C(0x1) - #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR - uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; -/******************************* - * hwrm_cfa_ntuple_filter_free * - *******************************/ +/********************************** + * hwrm_cfa_tcp_flag_process_qcfg * + **********************************/ -/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_ntuple_filter_free_input { +/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ +struct hwrm_cfa_tcp_flag_process_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26163,12 +34975,10 @@ struct hwrm_cfa_ntuple_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_free_output { +/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ +struct hwrm_cfa_tcp_flag_process_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26177,24 +34987,32 @@ struct hwrm_cfa_ntuple_filter_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* The port 0 RX mirror action record ID. */ + uint16_t rx_ar_id_port0; + /* The port 1 RX mirror action record ID. */ + uint16_t rx_ar_id_port1; + /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */ + uint16_t tx_ar_id_port0; + /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */ + uint16_t tx_ar_id_port1; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************************** - * hwrm_cfa_ntuple_filter_cfg * - ******************************/ +/********************** + * hwrm_cfa_pair_info * + **********************/ -/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ -struct hwrm_cfa_ntuple_filter_cfg_input { +/* hwrm_cfa_pair_info_input (size:448b/56B) */ +struct hwrm_cfa_pair_info_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26223,65 +35041,23 @@ struct hwrm_cfa_ntuple_filter_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t enables; - /* - * This bit must be '1' for the new_dst_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the new_mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \ - UINT32_C(0x2) - /* - * This bit must be '1' for the new_meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \ - UINT32_C(0x4) uint32_t flags; - /* - * Setting this bit to 1 indicates that dest_id field contains FID. - * Setting this to 0 indicates that dest_id field contains VNIC or VPORT. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \ - UINT32_C(0x1) - /* This value is an opaque id into CFA data structures. */ - uint64_t ntuple_filter_id; - /* - * If set, this value shall represent the new - * Logical VNIC ID of the destination VNIC for the RX - * path and new network port id of the destination port for - * the TX path. - */ - uint32_t new_dst_id; - /* - * New Logical VNIC ID of the VNIC where traffic is - * mirrored. - */ - uint32_t new_mirror_vnic_id; - /* - * New meter to attach to the flow. Specifying the - * invalid instance ID is used to remove any existing - * meter from the flow. - */ - uint16_t new_meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \ - HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID - uint8_t unused_1[6]; -} __attribute__((packed)); + /* If this flag is set, lookup by name else lookup by index. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) + /* If this flag is set, lookup by PF id and VF id. */ + #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) + /* Pair table index. */ + uint16_t pair_index; + /* Pair pf index. */ + uint8_t pair_pfid; + /* Pair vf index. */ + uint8_t pair_vfid; + /* Pair name (32 byte string). */ + char pair_name[32]; +} __rte_packed; -/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ -struct hwrm_cfa_ntuple_filter_cfg_output { +/* hwrm_cfa_pair_info_output (size:576b/72B) */ +struct hwrm_cfa_pair_info_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26290,24 +35066,74 @@ struct hwrm_cfa_ntuple_filter_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Pair table index. */ + uint16_t next_pair_index; + /* Pair member a's fid. */ + uint16_t a_fid; + /* Logical host number. */ + uint8_t host_a_index; + /* Logical PF number. */ + uint8_t pf_a_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_a_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_a; + /* Tx CFA action. */ + uint16_t tx_cfa_action_a; + /* Pair member b's fid. */ + uint16_t b_fid; + /* Logical host number. */ + uint8_t host_b_index; + /* Logical PF number. */ + uint8_t pf_b_index; + /* Pair member a's Linux logical VF number. */ + uint16_t vf_b_index; + /* Rx CFA code. */ + uint16_t rx_cfa_code_b; + /* Tx CFA action. */ + uint16_t tx_cfa_action_b; + /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ + uint8_t pair_mode; + /* Pair between VF on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) + /* Pair between REP on local host with PF or VF on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) + /* Pair between REP on local host with REP on specified host. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) + /* Pair for the proxy interface. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) + /* Pair for the PF interface. */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ + HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR + /* Pair state. */ + uint8_t pair_state; + /* Pair has been allocated */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) + /* Both pair members are active */ + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) + #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ + HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE + /* Pair name (32 byte string). */ + char pair_name[32]; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************** - * hwrm_cfa_em_flow_alloc * - **************************/ +/********************** + * hwrm_cfa_vfr_alloc * + **********************/ -/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */ -struct hwrm_cfa_em_flow_alloc_input { +/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ +struct hwrm_cfa_vfr_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26336,316 +35162,20 @@ struct hwrm_cfa_em_flow_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX - /* - * Setting of this flag indicates enabling of a byte counter for a given - * flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) - /* - * Setting of this flag indicates enabling of a packet counter for a given - * flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) - /* Setting of this flag indicates de-capsulation action for the given flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) - /* Setting of this flag indicates encapsulation action for the given flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) - /* - * Setting of this flag indicates that a meter is expected to be attached - * to this flow. This hint can be used when choosing the action record - * format required for the flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40) - uint32_t enables; - /* - * This bit must be '1' for the l2_filter_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \ - UINT32_C(0x1) - /* - * This bit must be '1' for the tunnel_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ - UINT32_C(0x2) - /* - * This bit must be '1' for the tunnel_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \ - UINT32_C(0x4) - /* - * This bit must be '1' for the src_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \ - UINT32_C(0x8) - /* - * This bit must be '1' for the dst_macaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \ - UINT32_C(0x10) - /* - * This bit must be '1' for the ovlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \ - UINT32_C(0x20) - /* - * This bit must be '1' for the ivlan_vid field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \ - UINT32_C(0x40) - /* - * This bit must be '1' for the ethertype field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \ - UINT32_C(0x80) - /* - * This bit must be '1' for the src_ipaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \ - UINT32_C(0x100) - /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \ - UINT32_C(0x200) - /* - * This bit must be '1' for the ipaddr_type field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ - UINT32_C(0x400) - /* - * This bit must be '1' for the ip_protocol field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ - UINT32_C(0x800) - /* - * This bit must be '1' for the src_port field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \ - UINT32_C(0x1000) - /* - * This bit must be '1' for the dst_port field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \ - UINT32_C(0x2000) - /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x4000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the encap_record_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \ - UINT32_C(0x10000) - /* - * This bit must be '1' for the meter_instance_id field to be - * configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \ - UINT32_C(0x20000) - /* - * This value identifies a set of CFA data structures used for an L2 - * context. - */ - uint64_t l2_filter_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0[3]; - /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. - */ - uint32_t tunnel_id; - /* - * This value indicates the source MAC address in - * the Ethernet header. - */ - uint8_t src_macaddr[6]; - /* The meter instance to attach to the flow. */ - uint16_t meter_instance_id; - /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID - /* - * This value indicates the destination MAC address in - * the Ethernet header. - */ - uint8_t dst_macaddr[6]; - /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the Ethernet header. - */ - uint16_t ovlan_vid; - /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the Ethernet header. - */ - uint16_t ivlan_vid; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; - /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. - */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 - /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP - */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11) - #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP - uint8_t unused_1[2]; - /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t src_ipaddr[4]; - /* - * big_endian = True - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. - */ - uint32_t dst_ipaddr[4]; - /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. - */ - uint16_t src_port; - /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. - */ - uint16_t dst_port; - /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path and network port id of the destination port for - * the TX path. - */ - uint16_t dst_id; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; /* - * Logical VNIC ID of the VNIC where traffic is - * mirrored. + * This field is reserved for the future use. + * It shall be set to 0. */ - uint16_t mirror_vnic_id; - /* Logical ID of the encapsulation record. */ - uint32_t encap_record_id; - uint8_t unused_2[4]; -} __attribute__((packed)); + uint16_t reserved; + uint8_t unused_0[4]; + /* VF Representor name (32 byte string). */ + char vfr_name[32]; +} __rte_packed; -/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */ -struct hwrm_cfa_em_flow_alloc_output { +/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ +struct hwrm_cfa_vfr_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26654,48 +35184,10 @@ struct hwrm_cfa_em_flow_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) - /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. - */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX + /* Rx CFA code. */ + uint16_t rx_cfa_code; + /* Tx CFA action. */ + uint16_t tx_cfa_action; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -26705,15 +35197,15 @@ struct hwrm_cfa_em_flow_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************* - * hwrm_cfa_em_flow_free * - *************************/ +/********************* + * hwrm_cfa_vfr_free * + *********************/ -/* hwrm_cfa_em_flow_free_input (size:192b/24B) */ -struct hwrm_cfa_em_flow_free_input { +/* hwrm_cfa_vfr_free_input (size:448b/56B) */ +struct hwrm_cfa_vfr_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26742,12 +35234,16 @@ struct hwrm_cfa_em_flow_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint64_t em_filter_id; -} __attribute__((packed)); + /* VF Representor name (32 byte string). */ + char vfr_name[32]; + /* Logical VF number (range: 0 -> MAX_VFS -1). */ + uint16_t vf_id; + uint16_t reserved; + uint8_t unused_0[4]; +} __rte_packed; -/* hwrm_cfa_em_flow_free_output (size:128b/16B) */ -struct hwrm_cfa_em_flow_free_output { +/* hwrm_cfa_vfr_free_output (size:128b/16B) */ +struct hwrm_cfa_vfr_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26765,15 +35261,17 @@ struct hwrm_cfa_em_flow_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************ - * hwrm_cfa_meter_qcaps * - ************************/ -/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_meter_qcaps_input { +/*************************************** + * hwrm_cfa_redirect_query_tunnel_type * + ***************************************/ + + +/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ +struct hwrm_cfa_redirect_query_tunnel_type_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26802,10 +35300,13 @@ struct hwrm_cfa_meter_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); + /* The source function id. */ + uint16_t src_fid; + uint8_t unused_0[6]; +} __rte_packed; -/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */ -struct hwrm_cfa_meter_qcaps_output { +/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ +struct hwrm_cfa_redirect_query_tunnel_type_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -26814,79 +35315,229 @@ struct hwrm_cfa_meter_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; + /* Tunnel Mask. */ + uint32_t tunnel_mask; + /* Non-tunnel */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \ + UINT32_C(0x1) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \ + UINT32_C(0x2) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \ + UINT32_C(0x4) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \ + UINT32_C(0x8) + /* IP in IP */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \ + UINT32_C(0x10) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ + UINT32_C(0x20) + /* Multi-Protocol Label Switching (MPLS) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ + UINT32_C(0x40) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \ + UINT32_C(0x80) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \ + UINT32_C(0x100) + /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ + UINT32_C(0x200) + /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ + UINT32_C(0x400) + /* Any tunneled traffic */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \ + UINT32_C(0x800) + /* Use fixed layer 2 ether type of 0xFFFF */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \ + UINT32_C(0x1000) + /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ + UINT32_C(0x2000) + uint8_t unused_0[3]; /* - * Enumeration denoting the clock at which the Meter is running with. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf) - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0 - /* 375 MHz */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0) - /* 625 MHz */ - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1) - #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \ - HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ - uint8_t unused_0[4]; + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_cfa_ctx_mem_rgtr * + *************************/ + + +/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ +struct hwrm_cfa_ctx_mem_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The minimum guaranteed number of tx meter profiles supported - * for this function. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t min_tx_profile; + uint16_t cmpl_ring; /* - * The maximum non-guaranteed number of tx meter profiles supported - * for this function. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t max_tx_profile; + uint16_t seq_id; /* - * The minimum guaranteed number of rx meter profiles supported - * for this function. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t min_rx_profile; + uint16_t target_id; /* - * The maximum non-guaranteed number of rx meter profiles supported - * for this function. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t max_rx_profile; + uint64_t resp_addr; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ + HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G + uint32_t unused_0; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} __rte_packed; + +/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; /* - * The minimum guaranteed number of tx meter instances supported - * for this function. + * Id/Handle to the recently register context memory. This handle is passed + * to the CFA feature. */ - uint16_t min_tx_instance; + uint16_t ctx_id; + uint8_t unused_0[5]; /* - * The maximum non-guaranteed number of tx meter instances supported - * for this function. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t max_tx_instance; + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_ctx_mem_unrgtr * + ***************************/ + + +/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ +struct hwrm_cfa_ctx_mem_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The minimum guaranteed number of rx meter instances supported - * for this function. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t min_rx_instance; + uint16_t cmpl_ring; /* - * The maximum non-guaranteed number of rx meter instances supported - * for this function. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t max_rx_instance; - uint8_t unused_1[7]; + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Id/Handle to the recently register context memory. This handle is passed + * to the CFA feature. + */ + uint16_t ctx_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************** - * hwrm_cfa_meter_profile_alloc * - ********************************/ +/************************* + * hwrm_cfa_ctx_mem_qctx * + *************************/ -/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_alloc_input { +/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ +struct hwrm_cfa_ctx_mem_qctx_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -26915,220 +35566,16 @@ struct hwrm_cfa_meter_profile_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \ - UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \ - UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \ - UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 - /* - * This field is reserved for the future use. - * It shall be set to 0. - */ - uint16_t reserved1; /* - * This field is reserved for the future use. - * It shall be set to 0. + * Id/Handle to the recently register context memory. This handle is passed + * to the CFA feature. */ - uint32_t reserved2; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw value */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid value */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __attribute__((packed)); + uint16_t ctx_id; + uint8_t unused_0[6]; +} __rte_packed; -/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_alloc_output { +/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ +struct hwrm_cfa_ctx_mem_qctx_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27137,34 +35584,58 @@ struct hwrm_cfa_meter_profile_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID - uint8_t unused_0[5]; + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ + HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \ + HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G + uint8_t unused_0[4]; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************* - * hwrm_cfa_meter_profile_free * - *******************************/ +/************************** + * hwrm_cfa_ctx_mem_qcaps * + **************************/ -/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_profile_free_input { +/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27193,37 +35664,10 @@ struct hwrm_cfa_meter_profile_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; -/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_free_output { +/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_ctx_mem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27232,24 +35676,26 @@ struct hwrm_cfa_meter_profile_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Indicates the maximum number of context memory which can be registered. */ + uint16_t max_entries; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************************** - * hwrm_cfa_meter_profile_cfg * - ******************************/ +/********************** + * hwrm_cfa_eem_qcaps * + **********************/ -/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */ -struct hwrm_cfa_meter_profile_cfg_input { +/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ +struct hwrm_cfa_eem_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27278,223 +35724,29 @@ struct hwrm_cfa_meter_profile_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX - /* The meter algorithm type. */ - uint8_t meter_type; - /* RFC 2697 (srTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \ - UINT32_C(0x0) - /* RFC 2698 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \ UINT32_C(0x1) - /* RFC 4115 (trTCM) */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \ - UINT32_C(0x2) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; - /* - * A value of 0xfff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID /* - * This field is reserved for the future use. - * It shall be set to 0. + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. */ - uint32_t reserved; - /* A meter rate specified in bytes-per-second. */ - uint32_t commit_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw value */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t commit_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid value */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID - /* A meter rate specified in bytes-per-second. */ - uint32_t excess_peak_rate; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Raw unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW - /* A meter burst size specified in bytes. */ - uint32_t excess_peak_burst; - /* The bandwidth value. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \ - UINT32_C(0xfffffff) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \ - 0 - /* The granularity of the value (bits or bytes). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \ - UINT32_C(0x10000000) - /* Value is in bits. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \ - (UINT32_C(0x0) << 28) - /* Value is in bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \ - (UINT32_C(0x1) << 28) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES - /* bw_value_unit is 3 b */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \ - UINT32_C(0xe0000000) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \ - 29 - /* Value is in Mb or MB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \ - (UINT32_C(0x0) << 29) - /* Value is in Kb or KB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \ - (UINT32_C(0x2) << 29) - /* Value is in bits or bytes. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \ - (UINT32_C(0x4) << 29) - /* Value is in Gb or GB (base 10). */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \ - (UINT32_C(0x6) << 29) - /* Value is in 1/100th of a percentage of total bandwidth. */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \ - (UINT32_C(0x1) << 29) - /* Invalid unit */ - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \ - (UINT32_C(0x7) << 29) - #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \ - HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID -} __attribute__((packed)); + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + uint32_t unused_0; +} __rte_packed; -/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_profile_cfg_output { +/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ +struct hwrm_cfa_eem_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27503,24 +35755,104 @@ struct hwrm_cfa_meter_profile_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t flags; + /* + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \ + UINT32_C(0x1) + /* + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* + * When set to 1, indicates the the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others ‘subscribe’ to it. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x4) + /* + * When set to 1, indicates the the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x8) + uint32_t unused_0; + uint32_t supported; + /* + * If set to 1, then EEM KEY0 table is supported using crc32 hash. + * If set to 0, EEM KEY0 table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ + UINT32_C(0x1) + /* + * If set to 1, then EEM KEY1 table is supported using lookup3 hash. + * If set to 0, EEM KEY1 table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ + UINT32_C(0x2) + /* + * If set to 1, then EEM External Record table is supported. + * If set to 0, EEM External Record table is not supported. + * (This table includes action record, EFC pointers, encap pointers) + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ + UINT32_C(0x4) + /* + * If set to 1, then EEM External Flow Counters table is supported. + * If set to 0, EEM External Flow Counters table is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ + UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush is supported. + * If set to 0, then FID table used for implicit flow flush is not supported. + */ + #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ + UINT32_C(0x10) + /* + * The maximum number of entries supported by EEM. When configuring the host memory + * the number of numbers of entries that can supported are - + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. + * Any value that are not these values, the FW will round down to the closest support + * number of entries. + */ + uint32_t max_entries_supported; + /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ + uint16_t key_entry_size; + /* The entry size in bytes of each entry in the EEM RECORD tables. */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EEM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EEM FID tables. */ + uint16_t fid_entry_size; + uint8_t unused_1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************************* - * hwrm_cfa_meter_instance_alloc * - *********************************/ +/******************** + * hwrm_cfa_eem_cfg * + ********************/ -/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_alloc_input { +/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ +struct hwrm_cfa_eem_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27549,38 +35881,56 @@ struct hwrm_cfa_meter_instance_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When set to 1, indicates the configuration will apply to TX flows + * which are to be offloaded. + * Note if this bit is set then the path_rx bit can't be set. */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \ - UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \ UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter profile in CFA. */ - uint16_t meter_profile_id; /* - * A value of 0xffff is considered invalid and implies the - * profile is not configured. + * When set to 1, indicates the configuration will apply to RX flows + * which are to be offloaded. + * Note if this bit is set then the path_tx bit can't be set. */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID - uint8_t unused_1[4]; -} __attribute__((packed)); + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \ + UINT32_C(0x8) + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + uint16_t unused_0; + /* + * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, + * RECORD, EFC all have the same number of entries and all tables will be configured + * using this value. Current minimum value is 32k. Current maximum value is 128M. + */ + uint32_t num_entries; + uint32_t unused_1; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint16_t unused_2; + uint32_t unused_3; +} __rte_packed; -/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_alloc_output { +/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ +struct hwrm_cfa_eem_cfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27589,34 +35939,24 @@ struct hwrm_cfa_meter_instance_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; - /* - * A value of 0xffff is considered invalid and implies the - * instance is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_0[5]; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************* - * hwrm_cfa_meter_instance_cfg * - *******************************/ +/********************* + * hwrm_cfa_eem_qcfg * + *********************/ -/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_cfg_input { +/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ +struct hwrm_cfa_eem_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27645,45 +35985,16 @@ struct hwrm_cfa_meter_instance_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; - /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. - */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* - * This value identifies a new meter profile to be associated with - * the meter instance specified in this command. - */ - uint16_t meter_profile_id; - /* - * A value of 0xffff is considered invalid and implies the - * profile is not configured. - */ - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID - /* - * This value identifies the ID of a meter instance that needs to be updated with - * a new meter profile specified in this command. - */ - uint16_t meter_instance_id; - uint8_t unused_1[2]; -} __attribute__((packed)); + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint32_t unused_0; +} __rte_packed; -/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_cfg_output { +/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ +struct hwrm_cfa_eem_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27692,24 +36003,46 @@ struct hwrm_cfa_meter_instance_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \ + UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + /* The number of entries the FW has configured for EEM. */ + uint32_t num_entries; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************** - * hwrm_cfa_meter_instance_free * - ********************************/ +/******************* + * hwrm_cfa_eem_op * + *******************/ -/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */ -struct hwrm_cfa_meter_instance_free_input { +/* hwrm_cfa_eem_op_input (size:192b/24B) */ +struct hwrm_cfa_eem_op_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27738,37 +36071,49 @@ struct hwrm_cfa_meter_instance_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint8_t flags; + uint32_t flags; /* - * Enumeration denoting the RX, TX type of the resource. - * This enumeration is used for resources that are similar for both - * TX and RX paths of the chip. + * When set to 1, indicates the host memory which is passed will be + * used for the TX flow offload function specified in fid. + * Note if this bit is set then the path_rx bit can't be set. */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x1) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX - uint8_t unused_0; - /* This value identifies a meter instance in CFA. */ - uint16_t meter_instance_id; + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) /* - * A value of 0xfff is considered invalid and implies the - * instance is not configured. + * When set to 1, indicates the host memory which is passed will be + * used for the RX flow offload function specified in fid. + * Note if this bit is set then the path_tx bit can't be set. */ - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \ - UINT32_C(0xffff) - #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \ - HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID - uint8_t unused_1[4]; -} __attribute__((packed)); + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint16_t unused_0; + /* The number of EEM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EEM and ensure there are no DMA's, the caller + * must disable EEM for the given PF, using this call. This will + * safely disable EEM and ensure that all DMA'ed to the + * keys/records/efc have been completed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) + /* + * Once the EEM host memory has been configured, EEM options have + * been configured. Then the caller should enable EEM for the given + * PF. Note once this call has been made, then the EEM mechanism + * will be active and DMA's will occur as packets are processed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) + /* + * Clear EEM settings for the given PF so that the register values + * are reset back to there initial state. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) + #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ + HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP +} __rte_packed; -/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */ -struct hwrm_cfa_meter_instance_free_output { +/* hwrm_cfa_eem_op_output (size:128b/16B) */ +struct hwrm_cfa_eem_op_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -27780,21 +36125,21 @@ struct hwrm_cfa_meter_instance_free_output { uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. * When writing a command completion or response to an internal processor, * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************* - * hwrm_cfa_decap_filter_alloc * - *******************************/ +/******************************** + * hwrm_cfa_adv_flow_mgnt_qcaps * + ********************************/ -/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ -struct hwrm_cfa_decap_filter_alloc_input { +/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -27823,275 +36168,327 @@ struct hwrm_cfa_decap_filter_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + uint32_t unused_0[4]; +} __rte_packed; + +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; uint32_t flags; - /* ovs_tunnel is 1 b */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \ - UINT32_C(0x1) - uint32_t enables; /* - * This bit must be '1' for the tunnel_type field to be - * configured. + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ UINT32_C(0x1) /* - * This bit must be '1' for the tunnel_id field to be - * configured. + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ UINT32_C(0x2) /* - * This bit must be '1' for the src_macaddr field to be - * configured. + * Value of 1 to indicate firmware support flow batch delete operation through + * HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow batch delete + * operation. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ UINT32_C(0x4) /* - * This bit must be '1' for the dst_macaddr field to be - * configured. + * Value of 1 to indicate that the firmware support flow reset all operation through + * HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all operation. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ UINT32_C(0x8) /* - * This bit must be '1' for the ovlan_vid field to be - * configured. + * Value of 1 to indicate that firmware supports use of FID as dest_id in + * HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as dest_id. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ UINT32_C(0x10) /* - * This bit must be '1' for the ivlan_vid field to be - * configured. + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ UINT32_C(0x20) /* - * This bit must be '1' for the t_ovlan_vid field to be - * configured. + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ UINT32_C(0x40) /* - * This bit must be '1' for the t_ivlan_vid field to be - * configured. + * Value of 1 to indicate that firmware supports the dynamic allocation of an + * on-chip flow counter which can be used for EEM flows. + * Value of 0 indicates firmware does not support the dynamic allocation of an + * on-chip flow counter. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ UINT32_C(0x80) /* - * This bit must be '1' for the ethertype field to be - * configured. + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ UINT32_C(0x100) /* - * This bit must be '1' for the src_ipaddr field to be - * configured. + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ UINT32_C(0x200) /* - * This bit must be '1' for the dst_ipaddr field to be - * configured. + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ UINT32_C(0x400) /* - * This bit must be '1' for the ipaddr_type field to be - * configured. + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ UINT32_C(0x800) /* - * This bit must be '1' for the ip_protocol field to be - * configured. + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ UINT32_C(0x1000) /* - * This bit must be '1' for the src_port field to be - * configured. + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ UINT32_C(0x2000) /* - * This bit must be '1' for the dst_port field to be - * configured. + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ UINT32_C(0x4000) + uint8_t unused_0[3]; /* - * This bit must be '1' for the dst_id field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \ - UINT32_C(0x8000) - /* - * This bit must be '1' for the mirror_vnic_id field to be - * configured. - */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \ - UINT32_C(0x10000) - /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). Only valid with - * tunnel_types VXLAN, NVGRE, and Geneve. - * Only lower 24-bits of VNI field are used - * in setting up the filter. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint32_t tunnel_id; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused_0; - uint16_t unused_1; + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_cfa_tflib * + ******************/ + + +/* hwrm_cfa_tflib_input (size:1024b/128B) */ +struct hwrm_cfa_tflib_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This value indicates the source MAC address in - * the Ethernet header. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint8_t src_macaddr[6]; - uint8_t unused_2[2]; + uint16_t cmpl_ring; /* - * This value indicates the destination MAC address in - * the Ethernet header. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t dst_macaddr[6]; + uint16_t seq_id; /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the Ethernet header. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t ovlan_vid; + uint16_t target_id; /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the Ethernet header. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t ivlan_vid; + uint64_t resp_addr; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; +} __rte_packed; + +/* hwrm_cfa_tflib_output (size:5632b/704B) */ +struct hwrm_cfa_tflib_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; + /* unused. */ + uint8_t unused1[7]; /* - * This value indicates the VLAN ID of the outer VLAN tag - * in the tunnel Ethernet header. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t t_ovlan_vid; + uint8_t valid; +} __rte_packed; + +/*********** + * hwrm_tf * + ***********/ + + +/* hwrm_tf_input (size:1024b/128B) */ +struct hwrm_tf_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * This value indicates the VLAN ID of the inner VLAN tag - * in the tunnel Ethernet header. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t t_ivlan_vid; - /* This value indicates the ethertype in the Ethernet header. */ - uint16_t ethertype; + uint16_t cmpl_ring; /* - * This value indicates the type of IP address. - * 4 - IPv4 - * 6 - IPv6 - * All others are invalid. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint8_t ip_addr_type; - /* invalid */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \ - UINT32_C(0x0) - /* IPv4 */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \ - UINT32_C(0x4) - /* IPv6 */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \ - UINT32_C(0x6) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \ - HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 + uint16_t seq_id; /* - * The value of protocol filed in IP header. - * Applies to UDP and TCP traffic. - * 6 - TCP - * 17 - UDP + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint8_t ip_protocol; - /* invalid */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \ - UINT32_C(0x0) - /* TCP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \ - UINT32_C(0x6) - /* UDP */ - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ - UINT32_C(0x11) - #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP - uint16_t unused_3; - uint32_t unused_4; + uint16_t target_id; /* - * The value of source IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint32_t src_ipaddr[4]; + uint64_t resp_addr; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* unused. */ + uint8_t unused0[4]; + /* TF request data. */ + uint32_t req[26]; +} __rte_packed; + +/* hwrm_tf_output (size:5632b/704B) */ +struct hwrm_tf_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* TF response code */ + uint32_t resp_code; + /* TF response data. */ + uint32_t resp[170]; + /* unused. */ + uint8_t unused1[7]; /* - * The value of destination IP address to be used in filtering. - * For IPv4, first four bytes represent the IP address. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ - uint32_t dst_ipaddr[4]; + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tf_version_get * + ***********************/ + + +/* hwrm_tf_version_get_input (size:128b/16B) */ +struct hwrm_tf_version_get_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * The value of source port to be used in filtering. - * Applies to UDP and TCP traffic. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t src_port; + uint16_t cmpl_ring; /* - * The value of destination port to be used in filtering. - * Applies to UDP and TCP traffic. + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. */ - uint16_t dst_port; + uint16_t seq_id; /* - * If set, this value shall represent the - * Logical VNIC ID of the destination VNIC for the RX - * path. + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM */ - uint16_t dst_id; + uint16_t target_id; /* - * If set, this value shall represent the L2 context that matches the L2 - * information of the decap filter. + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. */ - uint16_t l2_ctxt_ref_id; -} __attribute__((packed)); + uint64_t resp_addr; +} __rte_packed; -/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ -struct hwrm_cfa_decap_filter_alloc_output { +/* hwrm_tf_version_get_output (size:128b/16B) */ +struct hwrm_tf_version_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28100,26 +36497,32 @@ struct hwrm_cfa_decap_filter_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* This value is an opaque id into CFA data structures. */ - uint32_t decap_filter_id; - uint8_t unused_0[3]; + /* Version Major number. */ + uint8_t major; + /* Version Minor number. */ + uint8_t minor; + /* Version Update number. */ + uint8_t update; + /* unused. */ + uint8_t unused0[4]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/****************************** - * hwrm_cfa_decap_filter_free * - ******************************/ +/************************ + * hwrm_tf_session_open * + ************************/ -/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ -struct hwrm_cfa_decap_filter_free_input { +/* hwrm_tf_session_open_input (size:640b/80B) */ +struct hwrm_tf_session_open_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28148,13 +36551,12 @@ struct hwrm_cfa_decap_filter_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* This value is an opaque id into CFA data structures. */ - uint32_t decap_filter_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + /* Name of the session. */ + uint8_t session_name[64]; +} __rte_packed; -/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ -struct hwrm_cfa_decap_filter_free_output { +/* hwrm_tf_session_open_output (size:192b/24B) */ +struct hwrm_tf_session_open_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28163,24 +36565,38 @@ struct hwrm_cfa_decap_filter_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint32_t fw_session_id; + /* + * Unique session client identifier for the first client on + * the newly created session. + */ + uint32_t fw_session_client_id; + /* unused. */ + uint32_t unused0; + /* unused. */ + uint8_t unused1[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*********************** - * hwrm_cfa_flow_alloc * - ***********************/ +/************************** + * hwrm_tf_session_attach * + **************************/ -/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ -struct hwrm_cfa_flow_alloc_input { +/* hwrm_tf_session_attach_input (size:704b/88B) */ +struct hwrm_tf_session_attach_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28209,255 +36625,25 @@ struct hwrm_cfa_flow_alloc_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \ - UINT32_C(0x1) - /* num_vlan is 2 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \ - UINT32_C(0x6) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1 - /* no tags */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \ - (UINT32_C(0x0) << 1) - /* 1 tag */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \ - (UINT32_C(0x1) << 1) - /* 2 tags */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \ - (UINT32_C(0x2) << 1) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \ - HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO - /* Enumeration denoting the Flow Type. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \ - UINT32_C(0x38) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3 - /* L2 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \ - (UINT32_C(0x0) << 3) - /* IPV4 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \ - (UINT32_C(0x1) << 3) - /* IPV6 flow */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \ - (UINT32_C(0x2) << 3) - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \ - HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 - /* - * when set to 1, indicates TX flow offload for function specified in src_fid and - * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both - * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload - * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV - * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID - * belong to the children VFs of the same PF to indicate VM to VM flow. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x40) - /* - * when set to 1, indicates RX flow offload for function specified in dst_fid and - * the src_fid should be set to invalid value. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x80) - /* - * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is - * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field. - * This flag is only valid when the flow direction is RX. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \ - UINT32_C(0x100) - /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \ - UINT32_C(0x200) - /* - * Tx Flow: vf fid. - * Rx Flow: pf fid. - */ - uint16_t src_fid; - /* Tunnel handle valid when tunnel flag is set. */ - uint32_t tunnel_handle; - uint16_t action_flags; - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \ - UINT32_C(0x1) - /* recycle is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \ - UINT32_C(0x2) - /* - * Setting of this flag indicates drop action. If this flag is not set, - * then it should be considered accept action. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \ - UINT32_C(0x4) - /* meter is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \ - UINT32_C(0x8) - /* tunnel is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \ - UINT32_C(0x10) - /* nat_src is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \ - UINT32_C(0x20) - /* nat_dest is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \ - UINT32_C(0x40) - /* nat_ipv4_address is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \ - UINT32_C(0x80) - /* l2_header_rewrite is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \ - UINT32_C(0x100) - /* ttl_decrement is 1 b */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \ - UINT32_C(0x200) - /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. The type of tunnel - * is specified in the tunnel_type field. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \ - UINT32_C(0x400) - /* If set to 1, flow aging is enabled for this flow. */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \ - UINT32_C(0x800) - /* - * If set to 1 an attempt will be made to try to offload this flow to the - * most optimal flow table resource. If set to 0, the flow will be - * placed to the default flow table resource. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \ - UINT32_C(0x1000) - /* - * If set to 1 there will be no attempt to allocate an on-chip try to - * offload this flow. If set to 0, which will keep compatibility with the - * older drivers, will cause the FW to attempt to allocate an on-chip flow - * counter for the newly created flow. This will keep the existing behavior - * with EM flows which always had an associated flow counter. - */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \ - UINT32_C(0x2000) - /* - * Tx Flow: pf or vf fid. - * Rx Flow: vf fid. - */ - uint16_t dst_fid; - /* VLAN tpid, valid when push_vlan flag is set. */ - uint16_t l2_rewrite_vlan_tpid; - /* VLAN tci, valid when push_vlan flag is set. */ - uint16_t l2_rewrite_vlan_tci; - /* Meter id, valid when meter flag is set. */ - uint16_t act_meter_id; - /* Flow with the same l2 context tcam key. */ - uint16_t ref_flow_handle; - /* This value sets the match value for the ethertype. */ - uint16_t ethertype; - /* valid when num tags is 1 or 2. */ - uint16_t outer_vlan_tci; - /* This value sets the match value for the Destination MAC address. */ - uint16_t dmac[3]; - /* valid when num tags is 2. */ - uint16_t inner_vlan_tci; - /* This value sets the match value for the Source MAC address. */ - uint16_t smac[3]; - /* The bit length of destination IP address mask. */ - uint8_t ip_dst_mask_len; - /* The bit length of source IP address mask. */ - uint8_t ip_src_mask_len; - /* The value of destination IPv4/IPv6 address. */ - uint32_t ip_dst[4]; - /* The source IPv4/IPv6 address. */ - uint32_t ip_src[4]; - /* - * The value of source port. - * Applies to UDP and TCP traffic. - */ - uint16_t l4_src_port; - /* - * The value of source port mask. - * Applies to UDP and TCP traffic. - */ - uint16_t l4_src_port_mask; - /* - * The value of destination port. - * Applies to UDP and TCP traffic. - */ - uint16_t l4_dst_port; /* - * The value of destination port mask. - * Applies to UDP and TCP traffic. - */ - uint16_t l4_dst_port_mask; - /* - * NAT IPv4/6 address based on address type flag. - * 0 values are ignored. - */ - uint32_t nat_ip_address[4]; - /* L2 header re-write Destination MAC address. */ - uint16_t l2_rewrite_dmac[3]; - /* - * The NAT source/destination port based on direction flag. - * Applies to UDP and TCP traffic. - * 0 values are ignored. + * Unique session identifier for the session that the attach + * request want to attach to. This value originates from the + * shared session memory that the attach request opened by + * way of the 'attach name' that was passed in to the core + * attach API. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. */ - uint16_t nat_port; - /* L2 header re-write Source MAC address. */ - uint16_t l2_rewrite_smac[3]; - /* The value of ip protocol. */ - uint8_t ip_proto; - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL -} __attribute__((packed)); + uint32_t attach_fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session it self. */ + uint8_t session_name[64]; +} __rte_packed; -/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ -struct hwrm_cfa_flow_alloc_output { +/* hwrm_tf_session_attach_output (size:128b/16B) */ +struct hwrm_tf_session_attach_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28466,98 +36652,34 @@ struct hwrm_cfa_flow_alloc_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Flow record index. */ - uint16_t flow_handle; - uint8_t unused_0[2]; - /* - * The flow id value in bit 0-29 is the actual ID of the flow - * associated with this filter and it shall be used to match - * and associate the flow identifier returned in completion - * records. A value of 0xFFFFFFFF in the 32-bit flow_id field - * shall indicate no valid flow id. - */ - uint32_t flow_id; - /* Indicate the flow id value. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \ - UINT32_C(0x3fffffff) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0 - /* Indicate type of the flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \ - UINT32_C(0x40000000) - /* - * If this bit set to 0, then it indicates that the flow is - * internal flow. - */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \ - (UINT32_C(0x0) << 30) /* - * If this bit is set to 1, then it indicates that the flow is - * external flow. + * Unique session identifier for the session created by the + * firmware. It includes PCIe bus info to distinguish the PF + * and session info to identify the associated TruFlow + * session. This fw_session_id is unique to the attach + * request. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \ - HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT - /* Indicate the flow direction. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \ - UINT32_C(0x80000000) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \ - (UINT32_C(0x0) << 31) - /* If this bit is set to 1, then it indicates that tx flow. */ - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \ - (UINT32_C(0x1) << 31) - #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \ - HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; - uint32_t flow_counter_id; - uint8_t unused_1[3]; + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[3]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); - -/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ -struct hwrm_cfa_flow_alloc_cmd_err { - /* - * command specific error codes that goes to - * the cmd_err field in Common HWRM Error Response. - */ - uint8_t code; - /* Unknown error */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0) - /* No more L2 Context TCAM */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1) - /* No more action records */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2) - /* No more flow counters */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3) - /* No more wild-card TCAM */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4) - /* Hash collsion in exact match tables */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5) - /* Key is already installed */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6) - /* Flow Context DB is out of resource */ - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7) - #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \ - HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB - uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; -/********************** - * hwrm_cfa_flow_free * - **********************/ +/**************************** + * hwrm_tf_session_register * + ****************************/ -/* hwrm_cfa_flow_free_input (size:256b/32B) */ -struct hwrm_cfa_flow_free_input { +/* hwrm_tf_session_register_input (size:704b/88B) */ +struct hwrm_tf_session_register_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28586,17 +36708,23 @@ struct hwrm_cfa_flow_free_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - uint16_t unused_0; - /* Flow counter id to be freed. */ - uint32_t flow_counter_id; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; -} __attribute__((packed)); + /* + * Unique session identifier for the session that the + * register request want to create a new client on. This + * value originates from the first open request. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. + */ + uint32_t fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session client. */ + uint8_t session_client_name[64]; +} __rte_packed; -/* hwrm_cfa_flow_free_output (size:256b/32B) */ -struct hwrm_cfa_flow_free_output { +/* hwrm_tf_session_register_output (size:128b/16B) */ +struct hwrm_tf_session_register_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28605,251 +36733,102 @@ struct hwrm_cfa_flow_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* packet is 64 b */ - uint64_t packet; - /* byte is 64 b */ - uint64_t byte; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/* hwrm_cfa_flow_action_data (size:960b/120B) */ -struct hwrm_cfa_flow_action_data { - uint16_t action_flags; - /* Setting of this flag indicates accept action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \ - UINT32_C(0x1) - /* Setting of this flag indicates recycle action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \ - UINT32_C(0x2) - /* Setting of this flag indicates drop action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \ - UINT32_C(0x4) - /* Setting of this flag indicates meter action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \ - UINT32_C(0x8) - /* Setting of this flag indicates tunnel action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \ - UINT32_C(0x10) /* - * If set to 1 and flow direction is TX, it indicates decap of L2 header - * and encap of tunnel header. If set to 1 and flow direction is RX, it - * indicates decap of tunnel header and encap L2 header. + * Unique session client identifier for the session created + * by the firmware. It includes the session the client it + * attached to and session client info. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \ - UINT32_C(0x20) - /* Setting of this flag indicates ttl decrement action. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \ - UINT32_C(0x40) - /* If set to 1, flow aging is enabled for this flow. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \ - UINT32_C(0x80) - /* Setting of this flag indicates encap action.. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \ - UINT32_C(0x100) - /* Setting of this flag indicates decap action.. */ - #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \ - UINT32_C(0x200) - /* Meter id. */ - uint16_t act_meter_id; - /* VNIC id. */ - uint16_t vnic_id; - /* vport number. */ - uint16_t vport_id; - /* The NAT source/destination. */ - uint16_t nat_port; - uint16_t unused_0[3]; - /* NAT IPv4/IPv6 address. */ - uint32_t nat_ip_address[4]; - /* Encapsulation Type. */ - uint8_t encap_type; - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6) - /* VLAN */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) - #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ - HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 - uint8_t unused[7]; - /* This value is encap data for the associated encap type. */ - uint32_t encap_data[20]; -} __attribute__((packed)); - -/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */ -struct hwrm_cfa_flow_tunnel_hdr_data { - /* Tunnel Type. */ - uint8_t tunnel_type; - /* Non-tunnel */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \ - UINT32_C(0x0) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \ - UINT32_C(0x1) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \ - UINT32_C(0x2) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \ - UINT32_C(0x3) - /* IP in IP */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \ - UINT32_C(0x4) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \ - UINT32_C(0x5) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \ - UINT32_C(0x6) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \ - UINT32_C(0x7) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \ - UINT32_C(0x8) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \ - UINT32_C(0x9) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \ - UINT32_C(0xa) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \ - UINT32_C(0xb) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ - UINT32_C(0xc) - /* Any tunneled traffic */ - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \ - UINT32_C(0xff) - #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \ - HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL - uint8_t unused[3]; + uint32_t fw_session_client_id; + /* unused. */ + uint8_t unused0[3]; /* - * Tunnel identifier. - * Virtual Network Identifier (VNI). - */ - uint32_t tunnel_id; -} __attribute__((packed)); - -/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */ -struct hwrm_cfa_flow_l4_key_data { - /* The value of source port. */ - uint16_t l4_src_port; - /* The value of destination port. */ - uint16_t l4_dst_port; - uint32_t unused; -} __attribute__((packed)); + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; -/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */ -struct hwrm_cfa_flow_l3_key_data { - /* The value of ip protocol. */ - uint8_t ip_protocol; - uint8_t unused_0[7]; - /* The value of destination IPv4/IPv6 address. */ - uint32_t ip_dst[4]; - /* The source IPv4/IPv6 address. */ - uint32_t ip_src[4]; - /* NAT IPv4/IPv6 address. */ - uint32_t nat_ip_address[4]; - uint32_t unused[2]; -} __attribute__((packed)); +/****************************** + * hwrm_tf_session_unregister * + ******************************/ -/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */ -struct hwrm_cfa_flow_l2_key_data { - /* Destination MAC address. */ - uint16_t dmac[3]; - uint16_t unused_0; - /* Source MAC address. */ - uint16_t smac[3]; - uint16_t unused_1; - /* L2 header re-write Destination MAC address. */ - uint16_t l2_rewrite_dmac[3]; - uint16_t unused_2; - /* L2 header re-write Source MAC address. */ - uint16_t l2_rewrite_smac[3]; - /* Ethertype. */ - uint16_t ethertype; - /* Number of VLAN tags. */ - uint16_t num_vlan_tags; - /* VLAN tpid. */ - uint16_t l2_rewrite_vlan_tpid; - /* VLAN tci. */ - uint16_t l2_rewrite_vlan_tci; - uint8_t unused_3[2]; - /* Outer VLAN TPID. */ - uint16_t ovlan_tpid; - /* Outer VLAN TCI. */ - uint16_t ovlan_tci; - /* Inner VLAN TPID. */ - uint16_t ivlan_tpid; - /* Inner VLAN TCI. */ - uint16_t ivlan_tci; - uint8_t unused[8]; -} __attribute__((packed)); -/* hwrm_cfa_flow_key_data (size:4160b/520B) */ -struct hwrm_cfa_flow_key_data { - /* Flow associated tunnel L2 header key info. */ - uint32_t t_l2_key_data[14]; - /* Flow associated tunnel L2 header mask info. */ - uint32_t t_l2_key_mask[14]; - /* Flow associated tunnel L3 header key info. */ - uint32_t t_l3_key_data[16]; - /* Flow associated tunnel L3 header mask info. */ - uint32_t t_l3_key_mask[16]; - /* Flow associated tunnel L4 header key info. */ - uint32_t t_l4_key_data[2]; - /* Flow associated tunnel L4 header mask info. */ - uint32_t t_l4_key_mask[2]; - /* Flow associated tunnel header info. */ - uint32_t tunnel_hdr[2]; - /* Flow associated L2 header key info. */ - uint32_t l2_key_data[14]; - /* Flow associated L2 header mask info. */ - uint32_t l2_key_mask[14]; - /* Flow associated L3 header key info. */ - uint32_t l3_key_data[16]; - /* Flow associated L3 header mask info. */ - uint32_t l3_key_mask[16]; - /* Flow associated L4 header key info. */ - uint32_t l4_key_data[2]; - /* Flow associated L4 header mask info. */ - uint32_t l4_key_mask[2]; -} __attribute__((packed)); +/* hwrm_tf_session_unregister_input (size:192b/24B) */ +struct hwrm_tf_session_unregister_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session that the + * unregister request want to close a session client on. + */ + uint32_t fw_session_id; + /* + * Unique session client identifier for the session that the + * unregister request want to close. + */ + uint32_t fw_session_client_id; +} __rte_packed; -/********************** - * hwrm_cfa_flow_info * - **********************/ +/* hwrm_tf_session_unregister_output (size:128b/16B) */ +struct hwrm_tf_session_unregister_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; +/************************* + * hwrm_tf_session_close * + *************************/ -/* hwrm_cfa_flow_info_input (size:256b/32B) */ -struct hwrm_cfa_flow_info_input { + +/* hwrm_tf_session_close_input (size:192b/24B) */ +struct hwrm_tf_session_close_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28878,31 +36857,14 @@ struct hwrm_cfa_flow_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - /* Max flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ - UINT32_C(0xfff) - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 - /* CNP flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ - UINT32_C(0x1000) - /* RoCEv1 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \ - UINT32_C(0x2000) - /* RoCEv2 flow handle */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \ - UINT32_C(0x4000) - /* Direction rx = 1 */ - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ - UINT32_C(0x8000) - uint8_t unused_0[6]; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; -} __attribute__((packed)); + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __rte_packed; -/* hwrm_cfa_flow_info_output (size:5632b/704B) */ -struct hwrm_cfa_flow_info_output { +/* hwrm_tf_session_close_output (size:128b/16B) */ +struct hwrm_tf_session_close_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -28911,56 +36873,26 @@ struct hwrm_cfa_flow_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2) - /* profile is 8 b */ - uint8_t profile; - /* src_fid is 16 b */ - uint16_t src_fid; - /* dst_fid is 16 b */ - uint16_t dst_fid; - /* l2_ctxt_id is 16 b */ - uint16_t l2_ctxt_id; - /* em_info is 64 b */ - uint64_t em_info; - /* tcam_info is 64 b */ - uint64_t tcam_info; - /* vfp_tcam_info is 64 b */ - uint64_t vfp_tcam_info; - /* ar_id is 16 b */ - uint16_t ar_id; - /* flow_handle is 16 b */ - uint16_t flow_handle; - /* tunnel_handle is 32 b */ - uint32_t tunnel_handle; - /* The flow aging timer for the flow, the unit is 100 milliseconds */ - uint16_t flow_timer; - uint8_t unused_0[6]; - /* Flow associated L2, L3 and L4 headers info. */ - uint32_t flow_key_data[130]; - /* Flow associated action record info. */ - uint32_t flow_action_info[30]; - uint8_t unused_1[7]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*********************** - * hwrm_cfa_flow_flush * - ***********************/ +/************************ + * hwrm_tf_session_qcfg * + ************************/ -/* hwrm_cfa_flow_flush_input (size:256b/32B) */ -struct hwrm_cfa_flow_flush_input { +/* hwrm_tf_session_qcfg_input (size:192b/24B) */ +struct hwrm_tf_session_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -28989,86 +36921,148 @@ struct hwrm_cfa_flow_flush_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* flags is 32 b */ - uint32_t flags; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __rte_packed; + +/* hwrm_tf_session_qcfg_output (size:128b/16B) */ +struct hwrm_tf_session_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* RX action control settings flags. */ + uint8_t rx_act_flags; /* - * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr - * fields are valid. The flow flush operation should only flush the flows from the - * flow table specified. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. + * A value of 1 in this field indicates that Global Flow ID + * reporting into cfa_code and cfa_metadata is enabled. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \ UINT32_C(0x1) /* - * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA - * context memory tables..etc. This flag is set to 0 by older driver. For older firmware, - * setting this flag has no effect. + * A value of 1 in this field indicates that both inner and outer + * are stripped and inner tag is passed. + * Enabled. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \ UINT32_C(0x2) /* - * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller. - * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect. + * A value of 1 in this field indicates that the re-use of + * existing tunnel L2 header SMAC is enabled for + * Non-tunnel L2, L2-L3 and IP-IP tunnel. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \ UINT32_C(0x4) - /* Set to 1 to indicate the flow counter IDs are included in the flow table. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \ - UINT32_C(0x8000000) + /* TX Action control settings flags. */ + uint8_t tx_act_flags; + /* Disabled. */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \ + UINT32_C(0x1) /* - * This specifies the size of flow handle entries provided by the driver - * in the flow table specified below. Only two flow handle size enums are defined. + * When set to 1 any GRE tunnels will include the + * optional Key field. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \ - UINT32_C(0xc0000000) - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \ - 30 - /* The flow handle is 16bit */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \ - (UINT32_C(0x0) << 30) - /* The flow handle is 64bit */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \ - (UINT32_C(0x1) << 30) - #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \ - HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT - /* Specify page size of the flow table memory. */ - uint8_t page_size; - /* The page size is 4K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* The page size is 8K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* The page size is 64K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* The page size is 256K */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* The page size is 1M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* The page size is 2M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* The page size is 4M */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* The page size is 1G */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \ - HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G - /* FLow table memory indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 - /* number of flows in the flow table */ - uint16_t num_flows; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; -} __attribute__((packed)); + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \ + UINT32_C(0x2) + /* + * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap + * record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \ + UINT32_C(0x4) + /* + * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \ + UINT32_C(0x8) + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; -/* hwrm_cfa_flow_flush_output (size:128b/16B) */ -struct hwrm_cfa_flow_flush_output { +/****************************** + * hwrm_tf_session_resc_qcaps * + ******************************/ + + +/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ +struct hwrm_tf_session_resc_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX + /* + * Defines the size of the provided qcaps_addr array + * buffer. The size should be set to the Resource Manager + * provided max number of qcaps entries which is device + * specific. Resource Manager gets the max size from HCAPI + * RM. + */ + uint16_t qcaps_size; + /* + * This is the DMA address for the qcaps output data array + * buffer. Array is of tf_rm_resc_req_entry type and is + * device specific. + */ + uint64_t qcaps_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ +struct hwrm_tf_session_resc_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29077,24 +37071,55 @@ struct hwrm_cfa_flow_flush_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Control flags. */ + uint32_t flags; + /* Session reservation strategy. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \ + 0 + /* Static partitioning. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \ + UINT32_C(0x0) + /* Strategy 1. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \ + UINT32_C(0x1) + /* Strategy 2. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \ + UINT32_C(0x2) + /* Strategy 3. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 + /* + * Size of the returned qcaps_addr data array buffer. The + * value cannot exceed the size defined by the input msg, + * qcaps_size. + */ + uint16_t size; + /* unused. */ + uint16_t unused0; + /* unused. */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*********************** - * hwrm_cfa_flow_stats * - ***********************/ +/****************************** + * hwrm_tf_session_resc_alloc * + ******************************/ -/* hwrm_cfa_flow_stats_input (size:640b/80B) */ -struct hwrm_cfa_flow_stats_input { +/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */ +struct hwrm_tf_session_resc_alloc_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29123,53 +37148,42 @@ struct hwrm_cfa_flow_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow handle. */ - uint16_t num_flows; - /* Flow handle. */ - uint16_t flow_handle_0; - /* Flow handle. */ - uint16_t flow_handle_1; - /* Flow handle. */ - uint16_t flow_handle_2; - /* Flow handle. */ - uint16_t flow_handle_3; - /* Flow handle. */ - uint16_t flow_handle_4; - /* Flow handle. */ - uint16_t flow_handle_5; - /* Flow handle. */ - uint16_t flow_handle_6; - /* Flow handle. */ - uint16_t flow_handle_7; - /* Flow handle. */ - uint16_t flow_handle_8; - /* Flow handle. */ - uint16_t flow_handle_9; - uint8_t unused_0[2]; - /* Flow ID of a flow. */ - uint32_t flow_id_0; - /* Flow ID of a flow. */ - uint32_t flow_id_1; - /* Flow ID of a flow. */ - uint32_t flow_id_2; - /* Flow ID of a flow. */ - uint32_t flow_id_3; - /* Flow ID of a flow. */ - uint32_t flow_id_4; - /* Flow ID of a flow. */ - uint32_t flow_id_5; - /* Flow ID of a flow. */ - uint32_t flow_id_6; - /* Flow ID of a flow. */ - uint32_t flow_id_7; - /* Flow ID of a flow. */ - uint32_t flow_id_8; - /* Flow ID of a flow. */ - uint32_t flow_id_9; -} __attribute__((packed)); + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_size; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tf_rm_resc_req_entry type. Size of the + * array buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tf_rm_resc_entry type. Size of the array + * buffer is provided by the 'req_size' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; -/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ -struct hwrm_cfa_flow_stats_output { +/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ +struct hwrm_tf_session_resc_alloc_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29178,64 +37192,117 @@ struct hwrm_cfa_flow_stats_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* packet_0 is 64 b */ - uint64_t packet_0; - /* packet_1 is 64 b */ - uint64_t packet_1; - /* packet_2 is 64 b */ - uint64_t packet_2; - /* packet_3 is 64 b */ - uint64_t packet_3; - /* packet_4 is 64 b */ - uint64_t packet_4; - /* packet_5 is 64 b */ - uint64_t packet_5; - /* packet_6 is 64 b */ - uint64_t packet_6; - /* packet_7 is 64 b */ - uint64_t packet_7; - /* packet_8 is 64 b */ - uint64_t packet_8; - /* packet_9 is 64 b */ - uint64_t packet_9; - /* byte_0 is 64 b */ - uint64_t byte_0; - /* byte_1 is 64 b */ - uint64_t byte_1; - /* byte_2 is 64 b */ - uint64_t byte_2; - /* byte_3 is 64 b */ - uint64_t byte_3; - /* byte_4 is 64 b */ - uint64_t byte_4; - /* byte_5 is 64 b */ - uint64_t byte_5; - /* byte_6 is 64 b */ - uint64_t byte_6; - /* byte_7 is 64 b */ - uint64_t byte_7; - /* byte_8 is 64 b */ - uint64_t byte_8; - /* byte_9 is 64 b */ - uint64_t byte_9; - uint8_t unused_0[7]; + /* + * Size of the returned tf_rm_resc_entry data array. The value + * cannot exceed the req_size defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tf_session_resc_free * + *****************************/ + + +/* hwrm_tf_session_resc_free_input (size:256b/32B) */ +struct hwrm_tf_session_resc_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided free_addr + * buffer. + */ + uint16_t free_size; + /* + * This is the DMA address for the free input data array + * buffer. Array is of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'free_size' field of this + * message. + */ + uint64_t free_addr; +} __rte_packed; + +/* hwrm_tf_session_resc_free_output (size:128b/16B) */ +struct hwrm_tf_session_resc_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*********************************** - * hwrm_cfa_flow_aging_timer_reset * - ***********************************/ +/****************************** + * hwrm_tf_session_resc_flush * + ******************************/ -/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */ -struct hwrm_cfa_flow_aging_timer_reset_input { +/* hwrm_tf_session_resc_flush_input (size:256b/32B) */ +struct hwrm_tf_session_resc_flush_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29264,20 +37331,34 @@ struct hwrm_cfa_flow_aging_timer_reset_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow record index. */ - uint16_t flow_handle; - uint8_t unused_0[2]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX /* - * New flow timer value for the flow specified in the ext_flow_handle. - * The flow timer unit is 100ms. + * Defines the size, in bytes, of the provided flush_addr + * buffer. */ - uint32_t flow_timer; - /* This value identifies a set of CFA data structures used for a flow. */ - uint64_t ext_flow_handle; -} __attribute__((packed)); + uint16_t flush_size; + /* + * This is the DMA address for the flush input data array + * buffer. Array of tf_rm_resc_entry type. Size of the + * buffer is provided by the 'flush_size' field in this + * message. + */ + uint64_t flush_addr; +} __rte_packed; -/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */ -struct hwrm_cfa_flow_aging_timer_reset_output { +/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ +struct hwrm_tf_session_resc_flush_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29286,24 +37367,48 @@ struct hwrm_cfa_flow_aging_timer_reset_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/* TruFlow RM capability of a resource. */ +/* tf_rm_resc_req_entry (size:64b/8B) */ +struct tf_rm_resc_req_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} __rte_packed; + +/* TruFlow RM reservation information. */ +/* tf_rm_resc_entry (size:64b/8B) */ +struct tf_rm_resc_entry { + /* Type of the resource, defined globally in HCAPI RM. */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} __rte_packed; -/*************************** - * hwrm_cfa_flow_aging_cfg * - ***************************/ +/************************ + * hwrm_tf_tbl_type_get * + ************************/ -/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */ -struct hwrm_cfa_flow_aging_cfg_input { +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +struct hwrm_tf_tbl_type_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29332,77 +37437,31 @@ struct hwrm_cfa_flow_aging_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The bit field to enable per flow aging configuration. */ - uint16_t enables; - /* This bit must be '1' for the tcp flow timer field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \ - UINT32_C(0x1) - /* This bit must be '1' for the tcp finish timer field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \ - UINT32_C(0x2) - /* This bit must be '1' for the udp flow timer field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \ - UINT32_C(0x4) - /* This bit must be '1' for the eem dma interval field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \ - UINT32_C(0x8) - /* This bit must be '1' for the eem notice interval field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \ - UINT32_C(0x10) - /* This bit must be '1' for the eem context memory maximum entries field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \ - UINT32_C(0x20) - /* This bit must be '1' for the eem context memory ID field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \ - UINT32_C(0x40) - /* This bit must be '1' for the eem context memory type field to be configured */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \ - UINT32_C(0x80) - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX - /* Enumeration denoting the enable, disable eem flow aging configuration. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \ - (UINT32_C(0x0) << 1) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \ - (UINT32_C(0x1) << 1) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \ - HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE - uint8_t unused_0; - /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */ - uint32_t tcp_flow_timer; - /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */ - uint32_t tcp_fin_timer; - /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */ - uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ - uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ - uint16_t eem_notice_interval; - /* The maximum entries number in the eem context memory. */ - uint32_t eem_ctx_max_entries; - /* The context memory ID for eem flow aging. */ - uint16_t eem_ctx_id; - uint16_t eem_ctx_mem_type; - /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */ - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \ - UINT32_C(0x0) - #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \ - HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA - uint8_t unused_1[4]; -} __attribute__((packed)); + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; +} __rte_packed; -/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */ -struct hwrm_cfa_flow_aging_cfg_output { +/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */ +struct hwrm_tf_tbl_type_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29411,24 +37470,34 @@ struct hwrm_cfa_flow_aging_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[128]; + /* unused */ + uint8_t unused1[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/**************************** - * hwrm_cfa_flow_aging_qcfg * - ****************************/ +/************************ + * hwrm_tf_tbl_type_set * + ************************/ -/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */ -struct hwrm_cfa_flow_aging_qcfg_input { +/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ +struct hwrm_tf_tbl_type_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29457,21 +37526,37 @@ struct hwrm_cfa_flow_aging_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; -} __attribute__((packed)); - -/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */ -struct hwrm_cfa_flow_aging_qcfg_output { + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} __rte_packed; + +/* hwrm_tf_tbl_type_set_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29480,40 +37565,26 @@ struct hwrm_cfa_flow_aging_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t tcp_flow_timer; - /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t tcp_fin_timer; - /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */ - uint32_t udp_flow_timer; - /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */ - uint16_t eem_dma_interval; - /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */ - uint16_t eem_notice_interval; - /* The maximum entries number in the eem context memory. */ - uint32_t eem_ctx_max_entries; - /* The context memory ID for eem flow aging. */ - uint16_t eem_ctx_id; - /* The context memory type for eem flow aging. */ - uint16_t eem_ctx_mem_type; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' + * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/***************************** - * hwrm_cfa_flow_aging_qcaps * - *****************************/ +/************************* + * hwrm_tf_ctxt_mem_rgtr * + *************************/ -/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */ -struct hwrm_cfa_flow_aging_qcaps_input { +/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */ +struct hwrm_tf_ctxt_mem_rgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29542,21 +37613,49 @@ struct hwrm_cfa_flow_aging_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */ - uint8_t flags; - /* Enumeration denoting the RX, TX type of the resource. */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1) - /* tx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) - /* rx path */ - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) - #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \ - HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX - uint8_t unused_0[7]; -} __attribute__((packed)); + /* Control flags. */ + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G + /* unused. */ + uint32_t unused0; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} __rte_packed; -/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */ -struct hwrm_cfa_flow_aging_qcaps_output { +/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_rgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29565,32 +37664,31 @@ struct hwrm_cfa_flow_aging_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t max_tcp_flow_timer; - /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */ - uint32_t max_tcp_fin_timer; - /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */ - uint32_t max_udp_flow_timer; - /* The maximum aging flows that HW can support. */ - uint32_t max_aging_flows; - uint8_t unused_0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************************** - * hwrm_cfa_tcp_flag_process_qcfg * - **********************************/ +/*************************** + * hwrm_tf_ctxt_mem_unrgtr * + ***************************/ -/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_input { +/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_unrgtr_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29619,10 +37717,17 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); + /* + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[6]; +} __rte_packed; -/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */ -struct hwrm_cfa_tcp_flag_process_qcfg_output { +/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_unrgtr_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29631,32 +37736,26 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* The port 0 RX mirror action record ID. */ - uint16_t rx_ar_id_port0; - /* The port 1 RX mirror action record ID. */ - uint16_t rx_ar_id_port1; - /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */ - uint16_t tx_ar_id_port0; - /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */ - uint16_t tx_ar_id_port1; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************** - * hwrm_cfa_pair_info * - **********************/ +/************************ + * hwrm_tf_ext_em_qcaps * + ************************/ -/* hwrm_cfa_pair_info_input (size:448b/56B) */ -struct hwrm_cfa_pair_info_input { +/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcaps_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29685,23 +37784,28 @@ struct hwrm_cfa_pair_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Control flags. */ uint32_t flags; - /* If this flag is set, lookup by name else lookup by index. */ - #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1) - /* If this flag is set, lookup by PF id and VF id. */ - #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2) - /* Pair table index. */ - uint16_t pair_index; - /* Pair pf index. */ - uint8_t pair_pfid; - /* Pair vf index. */ - uint8_t pair_vfid; - /* Pair name (32 byte string). */ - char pair_name[32]; -} __attribute__((packed)); + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* unused. */ + uint32_t unused0; +} __rte_packed; -/* hwrm_cfa_pair_info_output (size:576b/72B) */ -struct hwrm_cfa_pair_info_output { +/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */ +struct hwrm_tf_ext_em_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29710,74 +37814,109 @@ struct hwrm_cfa_pair_info_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Pair table index. */ - uint16_t next_pair_index; - /* Pair member a's fid. */ - uint16_t a_fid; - /* Logical host number. */ - uint8_t host_a_index; - /* Logical PF number. */ - uint8_t pf_a_index; - /* Pair member a's Linux logical VF number. */ - uint16_t vf_a_index; - /* Rx CFA code. */ - uint16_t rx_cfa_code_a; - /* Tx CFA action. */ - uint16_t tx_cfa_action_a; - /* Pair member b's fid. */ - uint16_t b_fid; - /* Logical host number. */ - uint8_t host_b_index; - /* Logical PF number. */ - uint8_t pf_b_index; - /* Pair member a's Linux logical VF number. */ - uint16_t vf_b_index; - /* Rx CFA code. */ - uint16_t rx_cfa_code_b; - /* Tx CFA action. */ - uint16_t tx_cfa_action_b; - /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ - uint8_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ - HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR - /* Pair state. */ - uint8_t pair_state; - /* Pair has been allocated */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1) - /* Both pair members are active */ - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2) - #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \ - HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE - /* Pair name (32 byte string). */ - char pair_name[32]; - uint8_t unused_0[7]; + uint32_t flags; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When set to 1, indicates the the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others ‘subscribe’ to it. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x1) + /* + * When set to 1, indicates the the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x2) + /* unused. */ + uint32_t unused0; + /* Support flags. */ + uint32_t supported; + /* + * If set to 1, then EXT EM KEY0 table is supported using + * crc32 hash. + * If set to 0, EXT EM KEY0 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ + UINT32_C(0x1) + /* + * If set to 1, then EXT EM KEY1 table is supported using + * lookup3 hash. + * If set to 0, EXT EM KEY1 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ + UINT32_C(0x2) + /* + * If set to 1, then EXT EM External Record table is supported. + * If set to 0, EXT EM External Record table is not + * supported. (This table includes action record, EFC + * pointers, encap pointers) + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ + UINT32_C(0x4) + /* + * If set to 1, then EXT EM External Flow Counters table is + * supported. + * If set to 0, EXT EM External Flow Counters table is not + * supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ + UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush + * is supported. + * If set to 0, then FID table used for implicit flow flush + * is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ + UINT32_C(0x10) + /* + * The maximum number of entries supported by EXT EM. When + * configuring the host memory the number of numbers of + * entries that can supported are - + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, + * 128M entries. + * Any value that are not these values, the FW will round + * down to the closest support number of entries. + */ + uint32_t max_entries_supported; + /* + * The entry size in bytes of each entry in the EXT EM + * KEY0/KEY1 tables. + */ + uint16_t key_entry_size; + /* + * The entry size in bytes of each entry in the EXT EM RECORD + * tables. + */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EXT EM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EXT EM FID tables. */ + uint16_t fid_entry_size; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*************************************** - * hwrm_cfa_redirect_query_tunnel_type * - ***************************************/ +/********************* + * hwrm_tf_ext_em_op * + *********************/ -/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */ -struct hwrm_cfa_redirect_query_tunnel_type_input { +/* hwrm_tf_ext_em_op_input (size:192b/24B) */ +struct hwrm_tf_ext_em_op_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29806,13 +37945,51 @@ struct hwrm_cfa_redirect_query_tunnel_type_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* The source function id. */ - uint16_t src_fid; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX + /* unused. */ + uint16_t unused0; + /* The number of EXT EM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EXT EM and ensure there are no DMA's, + * the caller must disable EXT EM for the given PF, using + * this call. This will safely disable EXT EM and ensure + * that all DMA'ed to the keys/records/efc have been + * completed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1) + /* + * Once the EXT EM host memory has been configured, EXT EM + * options have been configured. Then the caller should + * enable EXT EM for the given PF. Note once this call has + * been made, then the EXT EM mechanism will be active and + * DMA's will occur as packets are processed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2) + /* + * Clear EXT EM settings for the given PF so that the + * register values are reset back to their initial state. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3) + #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP + /* unused. */ + uint16_t unused1; +} __rte_packed; -/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */ -struct hwrm_cfa_redirect_query_tunnel_type_output { +/* hwrm_tf_ext_em_op_output (size:128b/16B) */ +struct hwrm_tf_ext_em_op_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29821,68 +37998,141 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Tunnel Mask. */ - uint32_t tunnel_mask; - /* Non-tunnel */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \ + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_tf_ext_em_cfg * + **********************/ + + +/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */ +struct hwrm_tf_ext_em_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \ UINT32_C(0x1) - /* Virtual eXtensible Local Area Network (VXLAN) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \ + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ UINT32_C(0x2) - /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \ - UINT32_C(0x4) - /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \ - UINT32_C(0x8) - /* IP in IP */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \ - UINT32_C(0x10) - /* Generic Network Virtualization Encapsulation (Geneve) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \ - UINT32_C(0x20) - /* Multi-Protocol Lable Switching (MPLS) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \ - UINT32_C(0x40) - /* Stateless Transport Tunnel (STT) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \ - UINT32_C(0x80) - /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \ - UINT32_C(0x100) - /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \ - UINT32_C(0x200) - /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \ - UINT32_C(0x400) - /* Any tunneled traffic */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \ - UINT32_C(0x800) - /* Use fixed layer 2 ether type of 0xFFFF */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \ - UINT32_C(0x1000) - /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ - #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ - UINT32_C(0x2000) - uint8_t unused_0[3]; + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \ + UINT32_C(0x4) /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* + * Dynamically reconfigure EEM pending cache every 1/10th of second. + * If set to 0 it will disable the EEM HW flush of the pending cache. + */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused0; + /* + * Configured EXT EM with the given number of entries. All + * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the + * same number of entries and all tables will be configured + * using this value. Current minimum value is 32k. Current + * maximum value is 128M. + */ + uint32_t num_entries; + /* unused. */ + uint32_t unused1; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint16_t unused2; + /* unused. */ + uint32_t unused3; +} __rte_packed; + +/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ +struct hwrm_tf_ext_em_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/************************* - * hwrm_cfa_ctx_mem_rgtr * - *************************/ +/*********************** + * hwrm_tf_ext_em_qcfg * + ***********************/ -/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_rgtr_input { +/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -29911,44 +38161,22 @@ struct hwrm_cfa_ctx_mem_rgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ - HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G - uint32_t unused_0; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; -} __attribute__((packed)); + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + /* unused. */ + uint32_t unused0; +} __rte_packed; -/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_rgtr_output { +/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */ +struct hwrm_tf_ext_em_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -29957,29 +38185,54 @@ struct hwrm_cfa_ctx_mem_rgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* The number of entries the FW has configured for EXT EM. */ + uint32_t num_entries; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint8_t unused0[5]; /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. - */ - uint16_t ctx_id; - uint8_t unused_0[5]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/*************************** - * hwrm_cfa_ctx_mem_unrgtr * - ***************************/ +/********************* + * hwrm_tf_em_insert * + *********************/ -/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */ -struct hwrm_cfa_ctx_mem_unrgtr_input { +/* hwrm_tf_em_insert_input (size:832b/104B) */ +struct hwrm_tf_em_insert_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30008,16 +38261,34 @@ struct hwrm_cfa_ctx_mem_unrgtr_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. - */ - uint16_t ctx_id; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* Firmware Session Id. */ + uint32_t fw_session_id; + /* Control Flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX + /* Reported match strength. */ + uint16_t strength; + /* Index to action. */ + uint32_t action_ptr; + /* Index of EM record. */ + uint32_t em_record_idx; + /* EM Key value. */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; -/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_unrgtr_output { +/* hwrm_tf_em_insert_output (size:128b/16B) */ +struct hwrm_tf_em_insert_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30026,24 +38297,23 @@ struct hwrm_cfa_ctx_mem_unrgtr_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); + /* EM record pointer index. */ + uint16_t rptr_index; + /* EM record offset 0~3. */ + uint8_t rptr_entry; + /* Number of word entries consumed by the key. */ + uint8_t num_of_entries; + /* unused. */ + uint32_t unused0; +} __rte_packed; -/************************* - * hwrm_cfa_ctx_mem_qctx * - *************************/ +/********************* + * hwrm_tf_em_delete * + *********************/ -/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */ -struct hwrm_cfa_ctx_mem_qctx_input { +/* hwrm_tf_em_delete_input (size:832b/104B) */ +struct hwrm_tf_em_delete_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30072,16 +38342,32 @@ struct hwrm_cfa_ctx_mem_qctx_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Id/Handle to the recently register context memory. This handle is passed - * to the CFA feature. - */ - uint16_t ctx_id; - uint8_t unused_0[6]; -} __attribute__((packed)); + /* Session Id. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX + /* Unused0 */ + uint16_t unused0; + /* EM internal flow hanndle. */ + uint64_t flow_handle; + /* EM Key value */ + uint64_t em_key[8]; + /* Number of bits in em_key. */ + uint16_t em_key_bitlen; + /* unused. */ + uint16_t unused1[3]; +} __rte_packed; -/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */ -struct hwrm_cfa_ctx_mem_qctx_output { +/* hwrm_tf_em_delete_output (size:128b/16B) */ +struct hwrm_tf_em_delete_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30090,58 +38376,19 @@ struct hwrm_cfa_ctx_mem_qctx_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint16_t flags; - /* Counter PBL indirect levels. */ - uint8_t page_level; - /* PBL pointer is physical start address. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) - /* PBL pointer points to PTE table. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) - /* PBL pointer points to PDE table with each entry pointing to PTE tables. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \ - HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 - /* Page size. */ - uint8_t page_size; - /* 4KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0) - /* 8KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1) - /* 64KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4) - /* 256KB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6) - /* 1MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8) - /* 2MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9) - /* 4MB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa) - /* 1GB page size. */ - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12) - #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \ - HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G - uint8_t unused_0[4]; - /* Pointer to the PBL, or PDL depending on number of levels */ - uint64_t page_dir; - uint8_t unused_1[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); + /* Original stack allocation index. */ + uint16_t em_index; + /* unused. */ + uint16_t unused0[3]; +} __rte_packed; -/************************** - * hwrm_cfa_ctx_mem_qcaps * - **************************/ +/******************** + * hwrm_tf_tcam_set * + ********************/ -/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_input { +/* hwrm_tf_tcam_set_input (size:1024b/128B) */ +struct hwrm_tf_tcam_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30170,10 +38417,52 @@ struct hwrm_cfa_ctx_mem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data is packing does not change. + */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of TCAM entry. */ + uint16_t idx; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM result. */ + uint8_t result_size; + /* + * Offset from which the mask bytes start in the device data + * array, key offset is always 0. + */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[6]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[88]; +} __rte_packed; -/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_ctx_mem_qcaps_output { +/* hwrm_tf_tcam_set_output (size:128b/16B) */ +struct hwrm_tf_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30182,26 +38471,26 @@ struct hwrm_cfa_ctx_mem_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Indicates the maximum number of context memory which can be registered. */ - uint16_t max_entries; - uint8_t unused_0[5]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/********************** - * hwrm_cfa_eem_qcaps * - **********************/ +/******************** + * hwrm_tf_tcam_get * + ********************/ -/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ -struct hwrm_cfa_eem_qcaps_input { +/* hwrm_tf_tcam_get_input (size:256b/32B) */ +struct hwrm_tf_tcam_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30230,29 +38519,31 @@ struct hwrm_cfa_eem_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - uint32_t unused_0; -} __attribute__((packed)); + uint32_t type; + /* Index of a TCAM entry. */ + uint16_t idx; + /* unused. */ + uint16_t unused0; +} __rte_packed; -/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ -struct hwrm_cfa_eem_qcaps_output { +/* hwrm_tf_tcam_get_output (size:2368b/296B) */ +struct hwrm_tf_tcam_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30261,104 +38552,41 @@ struct hwrm_cfa_eem_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* - * When set to 1, indicates the the FW supports the Centralized - * Memory Model. The concept designates one entity for the - * memory allocation while all others ‘subscribe’ to it. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ - UINT32_C(0x4) - /* - * When set to 1, indicates the the FW supports the Detached - * Centralized Memory Model. The memory is allocated and managed - * as a separate entity. All PFs and VFs will be granted direct - * or semi-direct access to the allocated memory while none of - * which can interfere with the management of the memory. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ - UINT32_C(0x8) - uint32_t unused_0; - uint32_t supported; - /* - * If set to 1, then EEM KEY0 table is supported using crc32 hash. - * If set to 0, EEM KEY0 table is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ - UINT32_C(0x1) - /* - * If set to 1, then EEM KEY1 table is supported using lookup3 hash. - * If set to 0, EEM KEY1 table is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ - UINT32_C(0x2) - /* - * If set to 1, then EEM External Record table is supported. - * If set to 0, EEM External Record table is not supported. - * (This table includes action record, EFC pointers, encap pointers) - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ - UINT32_C(0x4) - /* - * If set to 1, then EEM External Flow Counters table is supported. - * If set to 0, EEM External Flow Counters table is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ - UINT32_C(0x8) - /* - * If set to 1, then FID table used for implicit flow flush is supported. - * If set to 0, then FID table used for implicit flow flush is not supported. - */ - #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ - UINT32_C(0x10) + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM entry. */ + uint8_t result_size; + /* Offset from which the mask bytes start in the device data array. */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[4]; /* - * The maximum number of entries supported by EEM. When configuring the host memory - * the number of numbers of entries that can supported are - - * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries. - * Any value that are not these values, the FW will round down to the closest support - * number of entries. + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. */ - uint32_t max_entries_supported; - /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */ - uint16_t key_entry_size; - /* The entry size in bytes of each entry in the EEM RECORD tables. */ - uint16_t record_entry_size; - /* The entry size in bytes of each entry in the EEM EFC tables. */ - uint16_t efc_entry_size; - /* The FID size in bytes of each entry in the EEM FID tables. */ - uint16_t fid_entry_size; - uint8_t unused_1[7]; + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************** - * hwrm_cfa_eem_cfg * - ********************/ +/********************* + * hwrm_tf_tcam_move * + *********************/ -/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ -struct hwrm_cfa_eem_cfg_input { +/* hwrm_tf_tcam_move_input (size:1024b/128B) */ +struct hwrm_tf_tcam_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30387,56 +38615,33 @@ struct hwrm_cfa_eem_cfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX /* - * When set to 1, indicates the configuration will apply to TX flows - * which are to be offloaded. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* - * When set to 1, indicates the configuration will apply to RX flows - * which are to be offloaded. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - /* When set to 1, secondary, 0 means primary. */ - #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \ - UINT32_C(0x8) - /* - * Group_id which used by Firmware to identify memory pools belonging - * to certain group. - */ - uint16_t group_id; - uint16_t unused_0; - /* - * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1, - * RECORD, EFC all have the same number of entries and all tables will be configured - * using this value. Current minimum value is 32k. Current maximum value is 128M. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - uint32_t num_entries; - uint32_t unused_1; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint16_t unused_2; - uint32_t unused_3; -} __attribute__((packed)); + uint32_t type; + /* Number of TCAM index pairs to be swapped for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index pairs to be swapped for the device. */ + uint16_t idx_pairs[48]; +} __rte_packed; -/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ -struct hwrm_cfa_eem_cfg_output { +/* hwrm_tf_tcam_move_output (size:128b/16B) */ +struct hwrm_tf_tcam_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30445,24 +38650,26 @@ struct hwrm_cfa_eem_cfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* - * hwrm_cfa_eem_qcfg * + * hwrm_tf_tcam_free * *********************/ -/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ -struct hwrm_cfa_eem_qcfg_input { +/* hwrm_tf_tcam_free_input (size:1024b/128B) */ +struct hwrm_tf_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30491,16 +38698,33 @@ struct hwrm_cfa_eem_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint32_t unused_0; -} __attribute__((packed)); + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; +} __rte_packed; -/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ -struct hwrm_cfa_eem_qcfg_output { +/* hwrm_tf_tcam_free_output (size:128b/16B) */ +struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30509,46 +38733,26 @@ struct hwrm_cfa_eem_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - /* The number of entries the FW has configured for EEM. */ - uint32_t num_entries; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint8_t unused_2[5]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************* - * hwrm_cfa_eem_op * - *******************/ +/************************** + * hwrm_tf_global_cfg_set * + **************************/ -/* hwrm_cfa_eem_op_input (size:192b/24B) */ -struct hwrm_cfa_eem_op_input { +/* hwrm_tf_global_cfg_set_input (size:448b/56B) */ +struct hwrm_tf_global_cfg_set_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30577,49 +38781,32 @@ struct hwrm_cfa_eem_op_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; - /* - * When set to 1, indicates the host memory which is passed will be - * used for the TX flow offload function specified in fid. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* - * When set to 1, indicates the host memory which is passed will be - * used for the RX flow offload function specified in fid. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint16_t unused_0; - /* The number of EEM key table entries to be configured. */ - uint16_t op; - /* This value is reserved and should not be used. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) - /* - * To properly stop EEM and ensure there are no DMA's, the caller - * must disable EEM for the given PF, using this call. This will - * safely disable EEM and ensure that all DMA'ed to the - * keys/records/efc have been completed. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) - /* - * Once the EEM host memory has been configured, EEM options have - * been configured. Then the caller should enable EEM for the given - * PF. Note once this call has been made, then the EEM mechanism - * will be active and DMA's will occur as packets are processed. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) - /* - * Clear EEM settings for the given PF so that the register values - * are reset back to there initial state. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) - #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ - HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP -} __attribute__((packed)); + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; + /* unused. */ + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[16]; +} __rte_packed; -/* hwrm_cfa_eem_op_output (size:128b/16B) */ -struct hwrm_cfa_eem_op_output { +/* hwrm_tf_global_cfg_set_output (size:128b/16B) */ +struct hwrm_tf_global_cfg_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30628,24 +38815,26 @@ struct hwrm_cfa_eem_op_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; -/******************************** - * hwrm_cfa_adv_flow_mgnt_qcaps * - ********************************/ +/************************** + * hwrm_tf_global_cfg_get * + **************************/ -/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_input { +/* hwrm_tf_global_cfg_get_input (size:320b/40B) */ +struct hwrm_tf_global_cfg_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -30674,160 +38863,30 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; -} __attribute__((packed)); - -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; - /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ - UINT32_C(0x1) - /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ - UINT32_C(0x2) - /* - * Value of 1 to indicate firmware support flow batch delete operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow batch delete - * operation. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ - UINT32_C(0x4) - /* - * Value of 1 to indicate that the firmware support flow reset all operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all operation. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ - UINT32_C(0x8) - /* - * Value of 1 to indicate that firmware supports use of FID as dest_id in - * HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as dest_id. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ - UINT32_C(0x10) - /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x20) - /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x40) - /* - * Value of 1 to indicate that firmware supports the dynamic allocation of an - * on-chip flow counter which can be used for EEM flows. - * Value of 0 indicates firmware does not support the dynamic allocation of an - * on-chip flow counter. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ - UINT32_C(0x80) - /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ - UINT32_C(0x100) - /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ - UINT32_C(0x200) - /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ - UINT32_C(0x400) - /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ - UINT32_C(0x800) - uint8_t unused_0[3]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/****************** - * hwrm_cfa_tflib * - ******************/ - - -/* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; + /* Indicates the flow direction. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX + /* Global Cfg type */ + uint32_t type; + /* Offset of the type */ + uint32_t offset; + /* Size of the data to set in bytes */ + uint16_t size; /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; -} __attribute__((packed)); + uint8_t unused0[6]; +} __rte_packed; -/* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +/* hwrm_tf_global_cfg_get_output (size:256b/32B) */ +struct hwrm_tf_global_cfg_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -30836,25 +38895,13 @@ struct hwrm_cfa_tflib_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; + /* Size of the data read in bytes */ + uint16_t size; /* unused. */ - uint8_t unused1[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. - */ - uint8_t valid; -} __attribute__((packed)); + uint8_t unused0[6]; + /* Data to set */ + uint8_t data[16]; +} __rte_packed; /****************************** * hwrm_tunnel_dst_port_query * @@ -30914,7 +38961,7 @@ struct hwrm_tunnel_dst_port_query_input { #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ struct hwrm_tunnel_dst_port_query_output { @@ -30953,7 +39000,7 @@ struct hwrm_tunnel_dst_port_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************************** * hwrm_tunnel_dst_port_alloc * @@ -31025,7 +39072,7 @@ struct hwrm_tunnel_dst_port_alloc_input { */ uint16_t tunnel_dst_port_val; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ struct hwrm_tunnel_dst_port_alloc_output { @@ -31051,7 +39098,7 @@ struct hwrm_tunnel_dst_port_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_tunnel_dst_port_free * @@ -31117,7 +39164,7 @@ struct hwrm_tunnel_dst_port_free_input { */ uint16_t tunnel_dst_port_id; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ struct hwrm_tunnel_dst_port_free_output { @@ -31138,7 +39185,7 @@ struct hwrm_tunnel_dst_port_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* Periodic statistics context DMA to host. */ /* ctx_hw_stats (size:1280b/160B) */ @@ -31149,10 +39196,10 @@ struct ctx_hw_stats { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ + /* Number of discarded packets on receive path */ uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -31165,10 +39212,10 @@ struct ctx_hw_stats { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; /* Number of discarded packets on transmit path */ uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -31183,9 +39230,13 @@ struct ctx_hw_stats { uint64_t tpa_events; /* Number of TPA aborts */ uint64_t tpa_aborts; -} __attribute__((packed)); +} __rte_packed; -/* Periodic statistics context DMA to host. */ +/* + * Extended periodic statistics context DMA to host. On cards that + * support TPA v2, additional TPA related stats exist and can be retrieved + * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure. + */ /* ctx_hw_stats_ext (size:1344b/168B) */ struct ctx_hw_stats_ext { /* Number of received unicast packets */ @@ -31194,10 +39245,10 @@ struct ctx_hw_stats_ext { uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of discarded packets on received path */ + /* Number of discarded packets on receive path */ uint64_t rx_discard_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ @@ -31210,10 +39261,10 @@ struct ctx_hw_stats_ext { uint64_t tx_mcast_pkts; /* Number of transmitted broadcast packets */ uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; /* Number of discarded packets on transmit path */ uint64_t tx_discard_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; /* Number of transmitted bytes for unicast traffic */ uint64_t tx_ucast_bytes; /* Number of transmitted bytes for multicast traffic */ @@ -31230,7 +39281,7 @@ struct ctx_hw_stats_ext { uint64_t rx_tpa_bytes; /* Number of TPA errors */ uint64_t rx_tpa_errors; -} __attribute__((packed)); +} __rte_packed; /* Periodic Engine statistics context DMA to host. */ /* ctx_eng_stats (size:512b/64B) */ @@ -31276,7 +39327,7 @@ struct ctx_eng_stats { * the unit is count of clock cycles */ uint64_t cdd_engine_usage; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_stat_ctx_alloc * @@ -31354,7 +39405,7 @@ struct hwrm_stat_ctx_alloc_input { * for the periodic DMA updates. */ uint16_t stats_dma_length; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ struct hwrm_stat_ctx_alloc_output { @@ -31377,7 +39428,7 @@ struct hwrm_stat_ctx_alloc_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_stat_ctx_free * @@ -31417,7 +39468,7 @@ struct hwrm_stat_ctx_free_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_free_output (size:128b/16B) */ struct hwrm_stat_ctx_free_output { @@ -31440,7 +39491,7 @@ struct hwrm_stat_ctx_free_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*********************** * hwrm_stat_ctx_query * @@ -31477,13 +39528,129 @@ struct hwrm_stat_ctx_query_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* ID of the statistics context that is being queried. */ + /* ID of the statistics context that is being queried. */ + uint32_t stat_ctx_id; + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) + uint8_t unused_0[3]; +} __rte_packed; + +/* hwrm_stat_ctx_query_output (size:1408b/176B) */ +struct hwrm_stat_ctx_query_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of transmitted packets with error */ + uint64_t tx_err_pkts; + /* Number of dropped packets on transmit path */ + uint64_t tx_drop_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of received unicast packets */ + uint64_t rx_ucast_pkts; + /* Number of received multicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_bcast_pkts; + /* Number of received packets with error */ + uint64_t rx_err_pkts; + /* Number of dropped packets on receive path */ + uint64_t rx_drop_pkts; + /* Number of received bytes for unicast traffic */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_bcast_bytes; + /* Number of aggregated unicast packets */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast bytes */ + uint64_t rx_agg_bytes; + /* Number of aggregation events */ + uint64_t rx_agg_events; + /* Number of aborted aggregations */ + uint64_t rx_agg_aborts; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_stat_ext_ctx_query * + ***************************/ + + +/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ +struct hwrm_stat_ext_ctx_query_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* ID of the extended statistics context that is being queried. */ uint32_t stat_ctx_id; - uint8_t unused_0[4]; -} __attribute__((packed)); + uint8_t flags; + /* + * This bit is set to 1 when request is for a counter mask, + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \ + UINT32_C(0x1) + uint8_t unused_0[3]; +} __rte_packed; -/* hwrm_stat_ctx_query_output (size:1408b/176B) */ -struct hwrm_stat_ctx_query_output { +/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */ +struct hwrm_stat_ext_ctx_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31492,46 +39659,48 @@ struct hwrm_stat_ctx_query_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Number of transmitted unicast packets */ - uint64_t tx_ucast_pkts; - /* Number of transmitted multicast packets */ - uint64_t tx_mcast_pkts; - /* Number of transmitted broadcast packets */ - uint64_t tx_bcast_pkts; - /* Number of transmitted packets with error */ - uint64_t tx_err_pkts; - /* Number of dropped packets on transmit path */ - uint64_t tx_drop_pkts; - /* Number of transmitted bytes for unicast traffic */ - uint64_t tx_ucast_bytes; - /* Number of transmitted bytes for multicast traffic */ - uint64_t tx_mcast_bytes; - /* Number of transmitted bytes for broadcast traffic */ - uint64_t tx_bcast_bytes; /* Number of received unicast packets */ uint64_t rx_ucast_pkts; /* Number of received multicast packets */ uint64_t rx_mcast_pkts; /* Number of received broadcast packets */ uint64_t rx_bcast_pkts; - /* Number of received packets with error */ - uint64_t rx_err_pkts; - /* Number of dropped packets on received path */ - uint64_t rx_drop_pkts; + /* Number of discarded packets on receive path */ + uint64_t rx_discard_pkts; + /* Number of packets on receive path with error */ + uint64_t rx_error_pkts; /* Number of received bytes for unicast traffic */ uint64_t rx_ucast_bytes; /* Number of received bytes for multicast traffic */ uint64_t rx_mcast_bytes; /* Number of received bytes for broadcast traffic */ uint64_t rx_bcast_bytes; - /* Number of aggregated unicast packets */ - uint64_t rx_agg_pkts; - /* Number of aggregated unicast bytes */ - uint64_t rx_agg_bytes; - /* Number of aggregation events */ - uint64_t rx_agg_events; - /* Number of aborted aggregations */ - uint64_t rx_agg_aborts; + /* Number of transmitted unicast packets */ + uint64_t tx_ucast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_bcast_pkts; + /* Number of packets on transmit path with error */ + uint64_t tx_error_pkts; + /* Number of discarded packets on transmit path */ + uint64_t tx_discard_pkts; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_bcast_bytes; + /* Number of TPA eligible packets */ + uint64_t rx_tpa_eligible_pkt; + /* Number of TPA eligible bytes */ + uint64_t rx_tpa_eligible_bytes; + /* Number of TPA packets */ + uint64_t rx_tpa_pkt; + /* Number of TPA bytes */ + uint64_t rx_tpa_bytes; + /* Number of TPA errors */ + uint64_t rx_tpa_errors; uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output @@ -31541,7 +39710,7 @@ struct hwrm_stat_ctx_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_stat_ctx_eng_query * @@ -31581,7 +39750,7 @@ struct hwrm_stat_ctx_eng_query_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */ struct hwrm_stat_ctx_eng_query_output { @@ -31643,7 +39812,7 @@ struct hwrm_stat_ctx_eng_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_stat_ctx_clr_stats * @@ -31683,7 +39852,7 @@ struct hwrm_stat_ctx_clr_stats_input { /* ID of the statistics context that is being queried. */ uint32_t stat_ctx_id; uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ struct hwrm_stat_ctx_clr_stats_output { @@ -31704,7 +39873,7 @@ struct hwrm_stat_ctx_clr_stats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /******************** * hwrm_pcie_qstats * @@ -31753,7 +39922,7 @@ struct hwrm_pcie_qstats_input { * PCIe statistics will be stored */ uint64_t pcie_stat_host_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_pcie_qstats_output (size:128b/16B) */ struct hwrm_pcie_qstats_output { @@ -31776,7 +39945,7 @@ struct hwrm_pcie_qstats_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* PCIe Statistics Formats */ /* pcie_ctx_hw_stats (size:768b/96B) */ @@ -31792,11 +39961,11 @@ struct pcie_ctx_hw_stats { uint64_t pcie_tl_signal_integrity; /* Number of times LTSSM entered Recovery state */ uint64_t pcie_link_integrity; - /* Number of TLP bytes that have been trasmitted */ + /* Report number of TLP bits that have been transmitted in Mbps */ uint64_t pcie_tx_traffic_rate; - /* Number of TLP bytes that have been received */ + /* Report number of TLP bits that have been received in Mbps */ uint64_t pcie_rx_traffic_rate; - /* Number of DLLP bytes that have been trasmitted */ + /* Number of DLLP bytes that have been transmitted */ uint64_t pcie_tx_dllp_statistics; /* Number of DLLP bytes that have been received */ uint64_t pcie_rx_dllp_statistics; @@ -31812,7 +39981,7 @@ struct pcie_ctx_hw_stats { * to Recovery */ uint64_t pcie_recovery_histogram; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_exec_fwd_resp * @@ -31865,7 +40034,7 @@ struct hwrm_exec_fwd_resp_input { */ uint16_t encap_resp_target_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_exec_fwd_resp_output (size:128b/16B) */ struct hwrm_exec_fwd_resp_output { @@ -31886,7 +40055,7 @@ struct hwrm_exec_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************ * hwrm_reject_fwd_resp * @@ -31939,7 +40108,7 @@ struct hwrm_reject_fwd_resp_input { */ uint16_t encap_resp_target_id; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_reject_fwd_resp_output (size:128b/16B) */ struct hwrm_reject_fwd_resp_output { @@ -31960,7 +40129,7 @@ struct hwrm_reject_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_fwd_resp * @@ -32028,7 +40197,7 @@ struct hwrm_fwd_resp_input { uint64_t encap_resp_addr; /* This is an encapsulated response. */ uint32_t encap_resp[24]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fwd_resp_output (size:128b/16B) */ struct hwrm_fwd_resp_output { @@ -32049,7 +40218,7 @@ struct hwrm_fwd_resp_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************************** * hwrm_fwd_async_event_cmpl * @@ -32098,7 +40267,7 @@ struct hwrm_fwd_async_event_cmpl_input { uint8_t unused_0[6]; /* This is an encapsulated asynchronous event completion. */ uint32_t encap_async_event_cmpl[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ struct hwrm_fwd_async_event_cmpl_output { @@ -32119,7 +40288,7 @@ struct hwrm_fwd_async_event_cmpl_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_nvm_raw_write_blk * @@ -32158,7 +40327,7 @@ struct hwrm_nvm_raw_write_blk_input { uint64_t resp_addr; /* * 64-bit Host Source Address. - * This is the loation of the source data to be written. + * This is the location of the source data to be written. */ uint64_t host_src_addr; /* @@ -32168,7 +40337,7 @@ struct hwrm_nvm_raw_write_blk_input { uint32_t dest_addr; /* Length of data to be written, in bytes. */ uint32_t len; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */ struct hwrm_nvm_raw_write_blk_output { @@ -32189,7 +40358,7 @@ struct hwrm_nvm_raw_write_blk_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /***************** * hwrm_nvm_read * @@ -32239,7 +40408,7 @@ struct hwrm_nvm_read_input { /* The length of the data to be read, in bytes. */ uint32_t len; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_read_output (size:128b/16B) */ struct hwrm_nvm_read_output { @@ -32260,7 +40429,7 @@ struct hwrm_nvm_read_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************* * hwrm_nvm_raw_dump * @@ -32306,7 +40475,7 @@ struct hwrm_nvm_raw_dump_input { uint32_t offset; /* Total length of NVRAM contents to be read, in bytes. */ uint32_t len; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_raw_dump_output (size:128b/16B) */ struct hwrm_nvm_raw_dump_output { @@ -32327,7 +40496,7 @@ struct hwrm_nvm_raw_dump_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_nvm_get_dir_entries * @@ -32369,7 +40538,7 @@ struct hwrm_nvm_get_dir_entries_input { * This is the host address where the directory will be written. */ uint64_t host_dest_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ struct hwrm_nvm_get_dir_entries_output { @@ -32390,7 +40559,7 @@ struct hwrm_nvm_get_dir_entries_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_get_dir_info * @@ -32427,7 +40596,7 @@ struct hwrm_nvm_get_dir_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ struct hwrm_nvm_get_dir_info_output { @@ -32452,7 +40621,7 @@ struct hwrm_nvm_get_dir_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_nvm_write * @@ -32523,12 +40692,12 @@ struct hwrm_nvm_write_input { * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length). * If this value is less than the specified data length, it will be ignored. * The response will contain the actual allocated item length, which may be greater than the requested item length. - * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate + * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data). */ uint32_t dir_item_length; uint32_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_write_output (size:128b/16B) */ struct hwrm_nvm_write_output { @@ -32556,7 +40725,7 @@ struct hwrm_nvm_write_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_write_cmd_err (size:64b/8B) */ struct hwrm_nvm_write_cmd_err { @@ -32574,7 +40743,7 @@ struct hwrm_nvm_write_cmd_err { #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \ HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /******************* * hwrm_nvm_modify * @@ -32618,7 +40787,23 @@ struct hwrm_nvm_modify_input { uint64_t host_src_addr; /* 16-bit directory entry index. */ uint16_t dir_idx; - uint8_t unused_0[2]; + uint16_t flags; + /* + * This flag indicates the sender wants to modify a continuous NVRAM + * area using a batch of this HWRM requests. The offset of a request + * must be continuous to the end of previous request's. Firmware does + * not update the directory entry until receiving the last request, + * which is indicated by the batch_last flag. + * This flag is set usually when a sender does not have a block of + * memory that is big enough to hold the entire NVRAM data for send + * at one time. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1) + /* + * This flag can be used only when the batch_mode flag is set. + * It indicates this request is the last of batch requests. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2) /* 32-bit NVRAM byte-offset to modify content from. */ uint32_t offset; /* @@ -32627,7 +40812,7 @@ struct hwrm_nvm_modify_input { */ uint32_t len; uint8_t unused_1[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_modify_output (size:128b/16B) */ struct hwrm_nvm_modify_output { @@ -32648,7 +40833,7 @@ struct hwrm_nvm_modify_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_nvm_find_dir_entry * @@ -32717,7 +40902,7 @@ struct hwrm_nvm_find_dir_entry_input { #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \ HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT uint8_t unused_0[3]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ struct hwrm_nvm_find_dir_entry_output { @@ -32751,7 +40936,7 @@ struct hwrm_nvm_find_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_nvm_erase_dir_entry * @@ -32791,7 +40976,7 @@ struct hwrm_nvm_erase_dir_entry_input { /* Directory Entry Index */ uint16_t dir_idx; uint8_t unused_0[6]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ struct hwrm_nvm_erase_dir_entry_output { @@ -32812,7 +40997,7 @@ struct hwrm_nvm_erase_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_get_dev_info * @@ -32849,7 +41034,7 @@ struct hwrm_nvm_get_dev_info_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ struct hwrm_nvm_get_dev_info_output { @@ -32886,7 +41071,7 @@ struct hwrm_nvm_get_dev_info_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_nvm_mod_dir_entry * @@ -32945,7 +41130,7 @@ struct hwrm_nvm_mod_dir_entry_input { * value of the content in the directory entry. */ uint32_t checksum; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ struct hwrm_nvm_mod_dir_entry_output { @@ -32966,7 +41151,7 @@ struct hwrm_nvm_mod_dir_entry_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /************************** * hwrm_nvm_verify_update * @@ -33019,7 +41204,7 @@ struct hwrm_nvm_verify_update_input { */ uint16_t dir_ext; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_verify_update_output (size:128b/16B) */ struct hwrm_nvm_verify_update_output { @@ -33040,7 +41225,7 @@ struct hwrm_nvm_verify_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /*************************** * hwrm_nvm_install_update * @@ -33105,7 +41290,7 @@ struct hwrm_nvm_install_update_input { #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \ UINT32_C(0x1) /* - * If set to 1, then unspecifed images, images not in the package file, will be safely deleted. + * If set to 1, then unspecified images, images not in the package file, will be safely deleted. * When combined with erase_unused_space then unspecified images will be securely erased. */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \ @@ -33116,8 +41301,15 @@ struct hwrm_nvm_install_update_input { */ #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \ UINT32_C(0x4) + /* + * If set to 1, FW will verify the package in the "UPDATE" NVM item + * without installing it. This flag is for FW internal use only. + * Users should not set this flag. The request will otherwise fail. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \ + UINT32_C(0x8) uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_install_update_output (size:192b/24B) */ struct hwrm_nvm_install_update_output { @@ -33186,7 +41378,7 @@ struct hwrm_nvm_install_update_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ struct hwrm_nvm_install_update_cmd_err { @@ -33204,7 +41396,7 @@ struct hwrm_nvm_install_update_cmd_err { #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /****************** * hwrm_nvm_flush * @@ -33241,7 +41433,7 @@ struct hwrm_nvm_flush_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_flush_output (size:128b/16B) */ struct hwrm_nvm_flush_output { @@ -33262,7 +41454,7 @@ struct hwrm_nvm_flush_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_flush_cmd_err (size:64b/8B) */ struct hwrm_nvm_flush_cmd_err { @@ -33278,7 +41470,7 @@ struct hwrm_nvm_flush_cmd_err { #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \ HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_get_variable * @@ -33355,7 +41547,7 @@ struct hwrm_nvm_get_variable_input { #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \ UINT32_C(0x1) uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_variable_output (size:128b/16B) */ struct hwrm_nvm_get_variable_output { @@ -33394,7 +41586,7 @@ struct hwrm_nvm_get_variable_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ struct hwrm_nvm_get_variable_cmd_err { @@ -33414,7 +41606,7 @@ struct hwrm_nvm_get_variable_cmd_err { #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \ HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /************************* * hwrm_nvm_set_variable * @@ -33512,7 +41704,7 @@ struct hwrm_nvm_set_variable_input { #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \ UINT32_C(0x80) uint8_t unused_0; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_set_variable_output (size:128b/16B) */ struct hwrm_nvm_set_variable_output { @@ -33533,7 +41725,7 @@ struct hwrm_nvm_set_variable_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ struct hwrm_nvm_set_variable_cmd_err { @@ -33551,7 +41743,7 @@ struct hwrm_nvm_set_variable_cmd_err { #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \ HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; /**************************** * hwrm_nvm_validate_option * @@ -33622,7 +41814,7 @@ struct hwrm_nvm_validate_option_input { /* index for the 4th dimensions */ uint16_t index_3; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_validate_option_output (size:128b/16B) */ struct hwrm_nvm_validate_option_output { @@ -33650,7 +41842,7 @@ struct hwrm_nvm_validate_option_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */ struct hwrm_nvm_validate_option_cmd_err { @@ -33664,7 +41856,73 @@ struct hwrm_nvm_validate_option_cmd_err { #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \ HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN uint8_t unused_0[7]; -} __attribute__((packed)); +} __rte_packed; + +/**************** + * hwrm_oem_cmd * + ****************/ + + +/* hwrm_oem_cmd_input (size:1024b/128B) */ +struct hwrm_oem_cmd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t IANA; + uint32_t unused_0; + /* This field contains the vendor specific command data. */ + uint32_t oem_data[26]; +} __rte_packed; + +/* hwrm_oem_cmd_output (size:768b/96B) */ +struct hwrm_oem_cmd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t IANA; + uint32_t unused_0; + /* This field contains the vendor specific response data. */ + uint32_t oem_data[18]; + uint8_t unused_1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; /***************** * hwrm_fw_reset * @@ -33764,7 +42022,7 @@ struct hwrm_fw_reset_input { */ #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1) uint8_t unused_0[4]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_fw_reset_output (size:128b/16B) */ struct hwrm_fw_reset_output { @@ -33801,7 +42059,7 @@ struct hwrm_fw_reset_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; /********************** * hwrm_port_ts_query * @@ -33859,7 +42117,7 @@ struct hwrm_port_ts_query_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t unused_0[2]; -} __attribute__((packed)); +} __rte_packed; /* hwrm_port_ts_query_output (size:192b/24B) */ struct hwrm_port_ts_query_output { @@ -33887,6 +42145,339 @@ struct hwrm_port_ts_query_output { * the order of writes has to be such that this field is written last. */ uint8_t valid; -} __attribute__((packed)); +} __rte_packed; + +/* + * This structure is fixed at the beginning of the ChiMP SRAM (GRC + * offset: 0x31001F0). Host software is expected to read from this + * location for a defined signature. If it exists, the software can + * assume the presence of this structure and the validity of the + * FW_STATUS location in the next field. + */ +/* hcomm_status (size:64b/8B) */ +struct hcomm_status { + uint32_t sig_ver; + /* + * This field defines the version of the structure. The latest + * version value is 1. + */ + #define HCOMM_STATUS_VER_MASK UINT32_C(0xff) + #define HCOMM_STATUS_VER_SFT 0 + #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1) + #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST + /* + * This field is to store the signature value to indicate the + * presence of the structure. + */ + #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00) + #define HCOMM_STATUS_SIGNATURE_SFT 8 + #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8) + #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL + uint32_t fw_status_loc; + #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3) + #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 + /* PCIE configuration space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0) + /* GRC space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1) + /* BAR0 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2) + /* BAR1 space */ + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3) + #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \ + HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 + /* + * This offset where the fw_status register is located. The value + * is generally 4-byte aligned. + */ + #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc) + #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 +} __rte_packed; +/* This is the GRC offset where the hcomm_status struct resides. */ +#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL + +/************************** + * hwrm_cfa_counter_qcaps * + **************************/ + + +/* hwrm_cfa_counter_qcaps_input (size:128b/16B) */ +struct hwrm_cfa_counter_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_cfa_counter_qcaps_output (size:576b/72B) */ +struct hwrm_cfa_counter_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* Enumeration denoting the supported CFA counter format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \ + UINT32_C(0x1) + /* CFA counter types are not supported. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \ + UINT32_C(0x0) + /* 64-bit packet counters followed by 64-bit byte counters format. */ + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \ + HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT + uint32_t unused_0; + /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */ + uint32_t min_rx_fc; + /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */ + uint32_t max_rx_fc; + /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */ + uint32_t min_tx_fc; + /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */ + uint32_t max_tx_fc; + /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */ + uint32_t min_rx_efc; + /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */ + uint32_t max_rx_efc; + /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */ + uint32_t min_tx_efc; + /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */ + uint32_t max_tx_efc; + /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */ + uint32_t min_rx_mdc; + /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */ + uint32_t max_rx_mdc; + /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */ + uint32_t min_tx_mdc; + /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */ + uint32_t max_tx_mdc; + /* Maximum guaranteed number of flow counters which can be used during flow alloc. */ + uint32_t max_flow_alloc_fc; + uint8_t unused_1[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_cfa_counter_cfg * + ************************/ + + +/* hwrm_cfa_counter_cfg_input (size:256b/32B) */ +struct hwrm_cfa_counter_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \ + UINT32_C(0x1) + /* Disable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \ + UINT32_C(0x0) + /* Enable the configuration mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \ + UINT32_C(0x1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \ + UINT32_C(0x2) + /* Tx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \ + (UINT32_C(0x0) << 1) + /* Rx path. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \ + (UINT32_C(0x1) << 1) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX + /* Enumeration denoting the data transfer mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \ + UINT32_C(0xc) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2 + /* Push mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \ + (UINT32_C(0x0) << 2) + /* Pull mode. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \ + (UINT32_C(0x1) << 2) + /* Pull on async update. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \ + (UINT32_C(0x2) << 2) + #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC + uint16_t counter_type; + /* Flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0) + /* Extended flow counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1) + /* Meter drop counters. */ + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2) + #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \ + HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC + /* Ctx memory handle to be used for the counter. */ + uint16_t ctx_id; + /* Counter update cadence hint (only in Push mode). */ + uint16_t update_tmr_ms; + /* Total number of entries. */ + uint32_t num_entries; + uint32_t unused_0; +} __rte_packed; + +/* hwrm_cfa_counter_cfg_output (size:128b/16B) */ +struct hwrm_cfa_counter_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_cfa_counter_qstats * + ***************************/ + + +/* hwrm_cfa_counter_qstats_input (size:320b/40B) */ +struct hwrm_cfa_counter_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint16_t flags; + /* Enumeration denoting the RX, TX type of the resource. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1) + /* Tx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* Rx path. */ + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \ + HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX + uint16_t counter_type; + uint16_t input_flow_ctx_id; + uint16_t num_entries; + uint16_t delta_time_ms; + uint16_t meter_instance_id; + uint16_t mdc_ctx_id; + uint8_t unused_0[2]; + uint64_t expected_count; +} __rte_packed; + +/* hwrm_cfa_counter_qstats_output (size:128b/16B) */ +struct hwrm_cfa_counter_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; #endif /* _HSI_STRUCT_DEF_DPDK_H_ */