X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fenetc%2Fenetc_ethdev.c;h=6c5501acb3a14c9afabdd304281ba874bf0862b7;hb=35b2d13fd6fdcbd191f2a30d74648faeb1186c65;hp=10b2b396d27e897684e33d1e49642d5102d1bdc4;hpb=01128d310338a3d8434b770ed552d64d48150268;p=dpdk.git diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c index 10b2b396d2..6c5501acb3 100644 --- a/drivers/net/enetc/enetc_ethdev.c +++ b/drivers/net/enetc/enetc_ethdev.c @@ -10,149 +10,36 @@ int enetc_logtype_pmd; -/* Functions Prototypes */ -static int enetc_dev_configure(struct rte_eth_dev *dev); -static int enetc_dev_start(struct rte_eth_dev *dev); -static void enetc_dev_stop(struct rte_eth_dev *dev); -static void enetc_dev_close(struct rte_eth_dev *dev); -static void enetc_dev_infos_get(struct rte_eth_dev *dev, - struct rte_eth_dev_info *dev_info); -static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete); -static int enetc_hardware_init(struct enetc_eth_hw *hw); -static int enetc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, - uint16_t nb_rx_desc, unsigned int socket_id, - const struct rte_eth_rxconf *rx_conf, - struct rte_mempool *mb_pool); -static void enetc_rx_queue_release(void *rxq); -static int enetc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, - uint16_t nb_tx_desc, unsigned int socket_id, - const struct rte_eth_txconf *tx_conf); -static void enetc_tx_queue_release(void *txq); -static const uint32_t *enetc_supported_ptypes_get(struct rte_eth_dev *dev); -static int enetc_stats_get(struct rte_eth_dev *dev, - struct rte_eth_stats *stats); -static void enetc_stats_reset(struct rte_eth_dev *dev); - -/* - * The set of PCI devices this driver supports - */ -static const struct rte_pci_id pci_id_enetc_map[] = { - { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) }, - { .vendor_id = 0, /* sentinel */ }, -}; - -/* Features supported by this driver */ -static const struct eth_dev_ops enetc_ops = { - .dev_configure = enetc_dev_configure, - .dev_start = enetc_dev_start, - .dev_stop = enetc_dev_stop, - .dev_close = enetc_dev_close, - .link_update = enetc_link_update, - .stats_get = enetc_stats_get, - .stats_reset = enetc_stats_reset, - .dev_infos_get = enetc_dev_infos_get, - .rx_queue_setup = enetc_rx_queue_setup, - .rx_queue_release = enetc_rx_queue_release, - .tx_queue_setup = enetc_tx_queue_setup, - .tx_queue_release = enetc_tx_queue_release, - .dev_supported_ptypes_get = enetc_supported_ptypes_get, -}; - -/** - * Initialisation of the enetc device - * - * @param eth_dev - * - Pointer to the structure rte_eth_dev - * - * @return - * - On success, zero. - * - On failure, negative value. - */ -static int -enetc_dev_init(struct rte_eth_dev *eth_dev) -{ - int error = 0; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - struct enetc_eth_hw *hw = - ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); - - PMD_INIT_FUNC_TRACE(); - eth_dev->dev_ops = &enetc_ops; - eth_dev->rx_pkt_burst = &enetc_recv_pkts; - eth_dev->tx_pkt_burst = &enetc_xmit_pkts; - - /* Retrieving and storing the HW base address of device */ - hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; - hw->device_id = pci_dev->id.device_id; - - error = enetc_hardware_init(hw); - if (error != 0) { - ENETC_PMD_ERR("Hardware initialization failed"); - return -1; - } - - /* Allocate memory for storing MAC addresses */ - eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", ETHER_ADDR_LEN, 0); - if (!eth_dev->data->mac_addrs) { - ENETC_PMD_ERR("Failed to allocate %d bytes needed to " - "store MAC addresses", - ETHER_ADDR_LEN * 1); - error = -ENOMEM; - return -1; - } - - /* Copy the permanent MAC address */ - ether_addr_copy((struct ether_addr *)hw->mac.addr, - ð_dev->data->mac_addrs[0]); - - ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x", - eth_dev->data->port_id, pci_dev->id.vendor_id, - pci_dev->id.device_id); - return 0; -} - -static int -enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) -{ - PMD_INIT_FUNC_TRACE(); - return 0; -} - -static int -enetc_dev_configure(struct rte_eth_dev *dev __rte_unused) -{ - PMD_INIT_FUNC_TRACE(); - return 0; -} - static int enetc_dev_start(struct rte_eth_dev *dev) { struct enetc_eth_hw *hw = ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; uint32_t val; PMD_INIT_FUNC_TRACE(); - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, - ENETC_PM0_CMD_CFG)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), - val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); + val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, + val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); /* Enable port */ - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), - val | ENETC_PMR_EN); + val = enetc_port_rd(enetc_hw, ENETC_PMR); + enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN); /* set auto-speed for RGMII */ - if (enetc_port_rd(&hw->hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { - enetc_port_wr(&hw->hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_RGAUTO); - enetc_port_wr(&hw->hw, ENETC_PM1_IF_MODE, ENETC_PM0_IFM_RGAUTO); + if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { + enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, + ENETC_PM0_IFM_RGAUTO); + enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, + ENETC_PM0_IFM_RGAUTO); } - if (enetc_global_rd(&hw->hw, + if (enetc_global_rd(enetc_hw, ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) { - enetc_port_wr(&hw->hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_XGMII); - enetc_port_wr(&hw->hw, ENETC_PM1_IF_MODE, ENETC_PM0_IFM_XGMII); + enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, + ENETC_PM0_IFM_XGMII); + enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, + ENETC_PM0_IFM_XGMII); } return 0; @@ -163,39 +50,17 @@ enetc_dev_stop(struct rte_eth_dev *dev) { struct enetc_eth_hw *hw = ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; uint32_t val; PMD_INIT_FUNC_TRACE(); /* Disable port */ - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), - val & (~ENETC_PMR_EN)); - - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, - ENETC_PM0_CMD_CFG)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), - val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); -} - -static void -enetc_dev_close(struct rte_eth_dev *dev) -{ - uint16_t i; - - PMD_INIT_FUNC_TRACE(); - enetc_dev_stop(dev); + val = enetc_port_rd(enetc_hw, ENETC_PMR); + enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN)); - for (i = 0; i < dev->data->nb_rx_queues; i++) { - enetc_rx_queue_release(dev->data->rx_queues[i]); - dev->data->rx_queues[i] = NULL; - } - dev->data->nb_rx_queues = 0; - - for (i = 0; i < dev->data->nb_tx_queues; i++) { - enetc_tx_queue_release(dev->data->tx_queues[i]); - dev->data->tx_queues[i] = NULL; - } - dev->data->nb_tx_queues = 0; + val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, + val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); } static const uint32_t * @@ -221,6 +86,7 @@ enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) { struct enetc_eth_hw *hw = ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; struct rte_eth_link link; uint32_t status; @@ -228,8 +94,7 @@ enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) memset(&link, 0, sizeof(link)); - status = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, - ENETC_PM0_STATUS)); + status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS); if (status & ENETC_LINK_MODE) link.link_duplex = ETH_LINK_FULL_DUPLEX; @@ -261,7 +126,8 @@ enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) static int enetc_hardware_init(struct enetc_eth_hw *hw) { - uint32_t psipmr = 0; + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t *mac = (uint32_t *)hw->mac.addr; PMD_INIT_FUNC_TRACE(); /* Calculating and storing the base HW addresses */ @@ -269,25 +135,11 @@ enetc_hardware_init(struct enetc_eth_hw *hw) hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE); /* Enabling Station Interface */ - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.reg, ENETC_SIMR), - ENETC_SIMR_EN); - - /* Setting to accept broadcast packets for each inetrface */ - psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0) | - ENETC_PSIPMR_SET_VLAN_MP(0); - psipmr |= ENETC_PSIPMR_SET_UP(1) | ENETC_PSIPMR_SET_MP(1) | - ENETC_PSIPMR_SET_VLAN_MP(1); - psipmr |= ENETC_PSIPMR_SET_UP(2) | ENETC_PSIPMR_SET_MP(2) | - ENETC_PSIPMR_SET_VLAN_MP(2); - - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMR), - psipmr); - - /* Enabling broadcast address */ - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR0(0)), - 0xFFFFFFFF); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR1(0)), - 0xFFFF << 16); + enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN); + + *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0)); + mac++; + *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0)); return 0; } @@ -309,7 +161,13 @@ enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused, }; dev_info->max_rx_queues = MAX_RX_RINGS; dev_info->max_tx_queues = MAX_TX_RINGS; - dev_info->max_rx_pktlen = 1500; + dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE; + dev_info->rx_offload_capa = + (DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_KEEP_CRC | + DEV_RX_OFFLOAD_JUMBO_FRAME); } static int @@ -350,7 +208,6 @@ static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) { int idx = tx_ring->index; - uint32_t tbmr; phys_addr_t bd_address; bd_address = (phys_addr_t) @@ -362,9 +219,6 @@ enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) enetc_txbdr_wr(hw, idx, ENETC_TBLENR, ENETC_RTBLENR_LEN(tx_ring->bd_count)); - tbmr = ENETC_TBMR_EN; - /* enable ring */ - enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0); enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0); tx_ring->tcir = (void *)((size_t)hw->reg + @@ -374,16 +228,22 @@ enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) } static int -enetc_alloc_tx_resources(struct rte_eth_dev *dev, - uint16_t queue_idx, - uint16_t nb_desc) +enetc_tx_queue_setup(struct rte_eth_dev *dev, + uint16_t queue_idx, + uint16_t nb_desc, + unsigned int socket_id __rte_unused, + const struct rte_eth_txconf *tx_conf) { - int err; + int err = 0; struct enetc_bdr *tx_ring; struct rte_eth_dev_data *data = dev->data; struct enetc_eth_adapter *priv = ENETC_DEV_PRIVATE(data->dev_private); + PMD_INIT_FUNC_TRACE(); + if (nb_desc > MAX_BD_COUNT) + return -1; + tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); if (tx_ring == NULL) { ENETC_PMD_ERR("Failed to allocate TX ring memory"); @@ -400,6 +260,17 @@ enetc_alloc_tx_resources(struct rte_eth_dev *dev, enetc_setup_txbdr(&priv->hw.hw, tx_ring); data->tx_queues[queue_idx] = tx_ring; + if (!tx_conf->tx_deferred_start) { + /* enable ring */ + enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, + ENETC_TBMR, ENETC_TBMR_EN); + dev->data->tx_queue_state[tx_ring->index] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + dev->data->tx_queue_state[tx_ring->index] = + RTE_ETH_QUEUE_STATE_STOPPED; + } + return 0; fail: rte_free(tx_ring); @@ -407,24 +278,6 @@ fail: return err; } -static int -enetc_tx_queue_setup(struct rte_eth_dev *dev, - uint16_t queue_idx, - uint16_t nb_desc, - unsigned int socket_id __rte_unused, - const struct rte_eth_txconf *tx_conf __rte_unused) -{ - int err = 0; - - PMD_INIT_FUNC_TRACE(); - if (nb_desc > MAX_BD_COUNT) - return -1; - - err = enetc_alloc_tx_resources(dev, queue_idx, nb_desc); - - return err; -} - static void enetc_tx_queue_release(void *txq) { @@ -514,22 +367,27 @@ enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) - RTE_PKTMBUF_HEADROOM); enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size); - /* enable ring */ - enetc_rxbdr_wr(hw, idx, ENETC_RBMR, ENETC_RBMR_EN); enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); } static int -enetc_alloc_rx_resources(struct rte_eth_dev *dev, - uint16_t rx_queue_id, - uint16_t nb_rx_desc, - struct rte_mempool *mb_pool) +enetc_rx_queue_setup(struct rte_eth_dev *dev, + uint16_t rx_queue_id, + uint16_t nb_rx_desc, + unsigned int socket_id __rte_unused, + const struct rte_eth_rxconf *rx_conf, + struct rte_mempool *mb_pool) { - int err; + int err = 0; struct enetc_bdr *rx_ring; struct rte_eth_dev_data *data = dev->data; struct enetc_eth_adapter *adapter = ENETC_DEV_PRIVATE(data->dev_private); + uint64_t rx_offloads = data->dev_conf.rxmode.offloads; + + PMD_INIT_FUNC_TRACE(); + if (nb_rx_desc > MAX_BD_COUNT) + return -1; rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); if (rx_ring == NULL) { @@ -547,6 +405,20 @@ enetc_alloc_rx_resources(struct rte_eth_dev *dev, enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool); data->rx_queues[rx_queue_id] = rx_ring; + if (!rx_conf->rx_deferred_start) { + /* enable ring */ + enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR, + ENETC_RBMR_EN); + dev->data->rx_queue_state[rx_ring->index] = + RTE_ETH_QUEUE_STATE_STARTED; + } else { + dev->data->rx_queue_state[rx_ring->index] = + RTE_ETH_QUEUE_STATE_STOPPED; + } + + rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ? + RTE_ETHER_CRC_LEN : 0); + return 0; fail: rte_free(rx_ring); @@ -554,27 +426,6 @@ fail: return err; } -static int -enetc_rx_queue_setup(struct rte_eth_dev *dev, - uint16_t rx_queue_id, - uint16_t nb_rx_desc, - unsigned int socket_id __rte_unused, - const struct rte_eth_rxconf *rx_conf __rte_unused, - struct rte_mempool *mb_pool) -{ - int err = 0; - - PMD_INIT_FUNC_TRACE(); - if (nb_rx_desc > MAX_BD_COUNT) - return -1; - - err = enetc_alloc_rx_resources(dev, rx_queue_id, - nb_rx_desc, - mb_pool); - - return err; -} - static void enetc_rx_queue_release(void *rxq) { @@ -649,6 +500,370 @@ enetc_stats_reset(struct rte_eth_dev *dev) enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS); } +static void +enetc_dev_close(struct rte_eth_dev *dev) +{ + uint16_t i; + + PMD_INIT_FUNC_TRACE(); + enetc_dev_stop(dev); + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + enetc_rx_queue_release(dev->data->rx_queues[i]); + dev->data->rx_queues[i] = NULL; + } + dev->data->nb_rx_queues = 0; + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + enetc_tx_queue_release(dev->data->tx_queues[i]); + dev->data->tx_queues[i] = NULL; + } + dev->data->nb_tx_queues = 0; +} + +static void +enetc_promiscuous_enable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); + + /* Setting to enable promiscuous mode*/ + psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); +} + +static void +enetc_promiscuous_disable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + /* Setting to disable promiscuous mode for SI0*/ + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); + psipmr &= (~ENETC_PSIPMR_SET_UP(0)); + + if (dev->data->all_multicast == 0) + psipmr &= (~ENETC_PSIPMR_SET_MP(0)); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); +} + +static void +enetc_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); + + /* Setting to enable allmulticast mode for SI0*/ + psipmr |= ENETC_PSIPMR_SET_MP(0); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); +} + +static void +enetc_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t psipmr = 0; + + if (dev->data->promiscuous == 1) + return; /* must remain in all_multicast mode */ + + /* Setting to disable all multicast mode for SI0*/ + psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) & + ~(ENETC_PSIPMR_SET_MP(0)); + + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); +} + +static int +enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; + + /* check that mtu is within the allowed range */ + if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE) + return -EINVAL; + + /* + * Refuse mtu that requires the support of scattered packets + * when this feature has not been enabled before. + */ + if (dev->data->min_rx_buf_size && + !dev->data->scattered_rx && frame_size > + dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { + ENETC_PMD_ERR("SG not enabled, will not fit in one buffer"); + return -EINVAL; + } + + if (frame_size > RTE_ETHER_MAX_LEN) + dev->data->dev_conf.rxmode.offloads &= + DEV_RX_OFFLOAD_JUMBO_FRAME; + else + dev->data->dev_conf.rxmode.offloads &= + ~DEV_RX_OFFLOAD_JUMBO_FRAME; + + enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE); + enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE); + + dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + + /*setting the MTU*/ + enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) | + ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE)); + + return 0; +} + +static int +enetc_dev_configure(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; + struct rte_eth_conf *eth_conf = &dev->data->dev_conf; + uint64_t rx_offloads = eth_conf->rxmode.offloads; + uint32_t checksum = L3_CKSUM | L4_CKSUM; + + PMD_INIT_FUNC_TRACE(); + + if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { + uint32_t max_len; + + max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; + + enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, + ENETC_SET_MAXFRM(max_len)); + enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), + ENETC_MAC_MAXFRM_SIZE); + enetc_port_wr(enetc_hw, ENETC_PTXMBAR, + 2 * ENETC_MAC_MAXFRM_SIZE); + dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN - + RTE_ETHER_CRC_LEN; + } + + if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) { + int config; + + config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + config |= ENETC_PM0_CRC; + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config); + } + + if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) + checksum &= ~L3_CKSUM; + + if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM)) + checksum &= ~L4_CKSUM; + + enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum); + + + return 0; +} + +static int +enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *rx_ring; + uint32_t rx_data; + + rx_ring = dev->data->rx_queues[qidx]; + if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) { + rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index, + ENETC_RBMR); + rx_data = rx_data | ENETC_RBMR_EN; + enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR, + rx_data); + dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; + } + + return 0; +} + +static int +enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *rx_ring; + uint32_t rx_data; + + rx_ring = dev->data->rx_queues[qidx]; + if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) { + rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index, + ENETC_RBMR); + rx_data = rx_data & (~ENETC_RBMR_EN); + enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR, + rx_data); + dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; + } + + return 0; +} + +static int +enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *tx_ring; + uint32_t tx_data; + + tx_ring = dev->data->tx_queues[qidx]; + if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) { + tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index, + ENETC_TBMR); + tx_data = tx_data | ENETC_TBMR_EN; + enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR, + tx_data); + dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; + } + + return 0; +} + +static int +enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) +{ + struct enetc_eth_adapter *priv = + ENETC_DEV_PRIVATE(dev->data->dev_private); + struct enetc_bdr *tx_ring; + uint32_t tx_data; + + tx_ring = dev->data->tx_queues[qidx]; + if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) { + tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index, + ENETC_TBMR); + tx_data = tx_data & (~ENETC_TBMR_EN); + enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR, + tx_data); + dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; + } + + return 0; +} + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_enetc_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +/* Features supported by this driver */ +static const struct eth_dev_ops enetc_ops = { + .dev_configure = enetc_dev_configure, + .dev_start = enetc_dev_start, + .dev_stop = enetc_dev_stop, + .dev_close = enetc_dev_close, + .link_update = enetc_link_update, + .stats_get = enetc_stats_get, + .stats_reset = enetc_stats_reset, + .promiscuous_enable = enetc_promiscuous_enable, + .promiscuous_disable = enetc_promiscuous_disable, + .allmulticast_enable = enetc_allmulticast_enable, + .allmulticast_disable = enetc_allmulticast_disable, + .dev_infos_get = enetc_dev_infos_get, + .mtu_set = enetc_mtu_set, + .rx_queue_setup = enetc_rx_queue_setup, + .rx_queue_start = enetc_rx_queue_start, + .rx_queue_stop = enetc_rx_queue_stop, + .rx_queue_release = enetc_rx_queue_release, + .tx_queue_setup = enetc_tx_queue_setup, + .tx_queue_start = enetc_tx_queue_start, + .tx_queue_stop = enetc_tx_queue_stop, + .tx_queue_release = enetc_tx_queue_release, + .dev_supported_ptypes_get = enetc_supported_ptypes_get, +}; + +/** + * Initialisation of the enetc device + * + * @param eth_dev + * - Pointer to the structure rte_eth_dev + * + * @return + * - On success, zero. + * - On failure, negative value. + */ +static int +enetc_dev_init(struct rte_eth_dev *eth_dev) +{ + int error = 0; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + eth_dev->dev_ops = &enetc_ops; + eth_dev->rx_pkt_burst = &enetc_recv_pkts; + eth_dev->tx_pkt_burst = &enetc_xmit_pkts; + + /* Retrieving and storing the HW base address of device */ + hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; + hw->device_id = pci_dev->id.device_id; + + error = enetc_hardware_init(hw); + if (error != 0) { + ENETC_PMD_ERR("Hardware initialization failed"); + return -1; + } + + /* Allocate memory for storing MAC addresses */ + eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", + RTE_ETHER_ADDR_LEN, 0); + if (!eth_dev->data->mac_addrs) { + ENETC_PMD_ERR("Failed to allocate %d bytes needed to " + "store MAC addresses", + RTE_ETHER_ADDR_LEN * 1); + error = -ENOMEM; + return -1; + } + + /* Copy the permanent MAC address */ + rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, + ð_dev->data->mac_addrs[0]); + + /* Set MTU */ + enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM, + ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN)); + eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN - + RTE_ETHER_CRC_LEN; + + ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x", + eth_dev->data->port_id, pci_dev->id.vendor_id, + pci_dev->id.device_id); + return 0; +} + +static int +enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); + return 0; +} + static int enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev)