X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fi40e%2Fi40e_ethdev_vf.c;h=7869b9b32440ac3bcd89c6322ee236bda50878aa;hb=0880c40113ef2d69b6433d7dfa0b4032cc378b0d;hp=90d1cbbc14f94cd919cd73850739549a3e45b6d1;hpb=37d7b38b51fe2af61ed219fe5dbc156cfdf66608;p=dpdk.git diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 90d1cbbc14..7869b9b324 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -1,7 +1,7 @@ /*- * BSD LICENSE * - * Copyright(c) 2010-2015 Intel Corporation. All rights reserved. + * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -67,7 +67,8 @@ #include "i40e_rxtx.h" #include "i40e_ethdev.h" #include "i40e_pf.h" -#define I40EVF_VSI_DEFAULT_MSIX_INTR 1 +#define I40EVF_VSI_DEFAULT_MSIX_INTR 1 +#define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0 /* busy wait delay in msec */ #define I40EVF_BUSY_WAIT_DELAY 10 @@ -100,9 +101,6 @@ enum i40evf_aq_result { I40EVF_MSG_CMD, /* Read async command result */ }; -/* A share buffer to store the command result from PF driver */ -static uint8_t cmd_result_buffer[I40E_AQ_BUF_SZ]; - static int i40evf_dev_configure(struct rte_eth_dev *dev); static int i40evf_dev_start(struct rte_eth_dev *dev); static void i40evf_dev_stop(struct rte_eth_dev *dev); @@ -112,6 +110,12 @@ static int i40evf_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete); static void i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); +static int i40evf_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *xstats, unsigned n); +static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + unsigned limit); +static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev); static int i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask); @@ -122,8 +126,6 @@ static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev); static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev); static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev); static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev); -static int i40evf_get_link_status(struct rte_eth_dev *dev, - struct rte_eth_link *link); static int i40evf_init_vlan(struct rte_eth_dev *dev); static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); @@ -133,6 +135,11 @@ static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); +static void i40evf_add_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *addr, + uint32_t index, + uint32_t pool); +static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index); static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); @@ -144,10 +151,41 @@ static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf); +static int +i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id); +static int +i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id); +static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev, + uint8_t *msg, + uint16_t msglen); /* Default hash key buffer for RSS */ static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1]; +struct rte_i40evf_xstats_name_off { + char name[RTE_ETH_XSTATS_NAME_SIZE]; + unsigned offset; +}; + +static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = { + {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)}, + {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)}, + {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)}, + {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)}, + {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)}, + {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats, + rx_unknown_protocol)}, + {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)}, + {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)}, + {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)}, + {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)}, + {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)}, + {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)}, +}; + +#define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \ + sizeof(rte_i40evf_stats_strings[0])) + static const struct eth_dev_ops i40evf_eth_dev_ops = { .dev_configure = i40evf_dev_configure, .dev_start = i40evf_dev_start, @@ -158,8 +196,12 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = { .allmulticast_disable = i40evf_dev_allmulticast_disable, .link_update = i40evf_dev_link_update, .stats_get = i40evf_dev_stats_get, + .xstats_get = i40evf_dev_xstats_get, + .xstats_get_names = i40evf_dev_xstats_get_names, + .xstats_reset = i40evf_dev_xstats_reset, .dev_close = i40evf_dev_close, .dev_infos_get = i40evf_dev_info_get, + .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get, .vlan_filter_set = i40evf_vlan_filter_set, .vlan_offload_set = i40evf_vlan_offload_set, .vlan_pvid_set = i40evf_vlan_pvid_set, @@ -169,64 +211,60 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = { .tx_queue_stop = i40evf_dev_tx_queue_stop, .rx_queue_setup = i40e_dev_rx_queue_setup, .rx_queue_release = i40e_dev_rx_queue_release, + .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable, + .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable, + .rx_descriptor_done = i40e_dev_rx_descriptor_done, .tx_queue_setup = i40e_dev_tx_queue_setup, .tx_queue_release = i40e_dev_tx_queue_release, + .rx_queue_count = i40e_dev_rx_queue_count, + .rxq_info_get = i40e_rxq_info_get, + .txq_info_get = i40e_txq_info_get, + .mac_addr_add = i40evf_add_mac_addr, + .mac_addr_remove = i40evf_del_mac_addr, .reta_update = i40evf_dev_rss_reta_update, .reta_query = i40evf_dev_rss_reta_query, .rss_hash_update = i40evf_dev_rss_hash_update, .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get, }; -static int -i40evf_set_mac_type(struct i40e_hw *hw) -{ - int status = I40E_ERR_DEVICE_NOT_SUPPORTED; - - if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { - switch (hw->device_id) { - case I40E_DEV_ID_VF: - case I40E_DEV_ID_VF_HV: - hw->mac.type = I40E_MAC_VF; - status = I40E_SUCCESS; - break; - default: - ; - } - } - - return status; -} - /* - * Parse admin queue message. - * - * return value: - * < 0: meet error - * 0: read sys msg - * > 0: read cmd result + * Read data in admin queue to get msg from pf driver */ static enum i40evf_aq_result -i40evf_parse_pfmsg(struct i40e_vf *vf, - struct i40e_arq_event_info *event, - struct i40evf_arq_msg_info *data) +i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data) { - enum i40e_virtchnl_ops opcode = (enum i40e_virtchnl_ops)\ - rte_le_to_cpu_32(event->desc.cookie_high); - enum i40e_status_code retval = (enum i40e_status_code)\ - rte_le_to_cpu_32(event->desc.cookie_low); - enum i40evf_aq_result ret = I40EVF_MSG_CMD; + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct i40e_arq_event_info event; + enum i40e_virtchnl_ops opcode; + enum i40e_status_code retval; + int ret; + enum i40evf_aq_result result = I40EVF_MSG_NON; + + event.buf_len = data->buf_len; + event.msg_buf = data->msg; + ret = i40e_clean_arq_element(hw, &event, NULL); + /* Can't read any msg from adminQ */ + if (ret) { + if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK) + result = I40EVF_MSG_ERR; + return result; + } + opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high); + retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low); /* pf sys event */ if (opcode == I40E_VIRTCHNL_OP_EVENT) { struct i40e_virtchnl_pf_event *vpe = - (struct i40e_virtchnl_pf_event *)event->msg_buf; + (struct i40e_virtchnl_pf_event *)event.msg_buf; - /* Initialize ret to sys event */ - ret = I40EVF_MSG_SYS; + result = I40EVF_MSG_SYS; switch (vpe->event) { case I40E_VIRTCHNL_EVENT_LINK_CHANGE: vf->link_up = vpe->event_data.link_event.link_status; + vf->link_speed = + vpe->event_data.link_event.link_speed; vf->pend_msg |= PFMSG_LINK_CHANGE; PMD_DRV_LOG(INFO, "Link status update:%s", vf->link_up ? "up" : "down"); @@ -247,74 +285,17 @@ i40evf_parse_pfmsg(struct i40e_vf *vf, } } else { /* async reply msg on command issued by vf previously */ - ret = I40EVF_MSG_CMD; + result = I40EVF_MSG_CMD; /* Actual data length read from PF */ - data->msg_len = event->msg_len; + data->msg_len = event.msg_len; } - /* fill the ops and result to notify VF */ + data->result = retval; data->ops = opcode; - return ret; -} - -/* - * Read data in admin queue to get msg from pf driver - */ -static enum i40evf_aq_result -i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data) -{ - struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); - struct i40e_arq_event_info event; - int ret; - enum i40evf_aq_result result = I40EVF_MSG_NON; - - event.buf_len = data->buf_len; - event.msg_buf = data->msg; - ret = i40e_clean_arq_element(hw, &event, NULL); - /* Can't read any msg from adminQ */ - if (ret) { - if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) - result = I40EVF_MSG_NON; - else - result = I40EVF_MSG_ERR; - return result; - } - - /* Parse the event */ - result = i40evf_parse_pfmsg(vf, &event, data); - return result; } -/* - * Polling read until command result return from pf driver or meet error. - */ -static int -i40evf_wait_cmd_done(struct rte_eth_dev *dev, - struct i40evf_arq_msg_info *data) -{ - int i = 0; - enum i40evf_aq_result ret; - -#define MAX_TRY_TIMES 20 -#define ASQ_DELAY_MS 100 - do { - /* Delay some time first */ - rte_delay_ms(ASQ_DELAY_MS); - ret = i40evf_read_pfmsg(dev, data); - if (ret == I40EVF_MSG_CMD) - return 0; - else if (ret == I40EVF_MSG_ERR) - return -1; - - /* If don't read msg or read sys event, continue */ - } while(i++ < MAX_TRY_TIMES); - - return -1; -} - /** * clear current command. Only call in case execute * _atomic_set_cmd successfully. @@ -341,13 +322,17 @@ _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops) return !ret; } +#define MAX_TRY_TIMES 200 +#define ASQ_DELAY_MS 10 + static int i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args) { struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); - int err = -1; struct i40evf_arq_msg_info info; + enum i40evf_aq_result ret; + int err, i = 0; if (_atomic_set_cmd(vf, args->ops)) return -1; @@ -361,20 +346,47 @@ i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args) args->in_args, args->in_args_size, NULL); if (err) { PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops); + _clear_cmd(vf); return err; } - err = i40evf_wait_cmd_done(dev, &info); - /* read message and it's expected one */ - if (!err && args->ops == info.ops) + switch (args->ops) { + case I40E_VIRTCHNL_OP_RESET_VF: + /*no need to process in this function */ + err = 0; + break; + case I40E_VIRTCHNL_OP_VERSION: + case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: + /* for init adminq commands, need to poll the response */ + err = -1; + do { + ret = i40evf_read_pfmsg(dev, &info); + if (ret == I40EVF_MSG_CMD) { + err = 0; + break; + } else if (ret == I40EVF_MSG_ERR) + break; + rte_delay_ms(ASQ_DELAY_MS); + /* If don't read msg or read sys event, continue */ + } while (i++ < MAX_TRY_TIMES); _clear_cmd(vf); - else if (err) - PMD_DRV_LOG(ERR, "Failed to read message from AdminQ"); - else if (args->ops != info.ops) - PMD_DRV_LOG(ERR, "command mismatch, expect %u, get %u", - args->ops, info.ops); + break; + + default: + /* for other adminq in running time, waiting the cmd done flag */ + err = -1; + do { + if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) { + err = 0; + break; + } + rte_delay_ms(ASQ_DELAY_MS); + /* If don't read msg or read sys event, continue */ + } while (i++ < MAX_TRY_TIMES); + break; + } - return (err | info.result); + return err | vf->cmd_retval; } /* @@ -394,7 +406,7 @@ i40evf_check_api_version(struct rte_eth_dev *dev) args.ops = I40E_VIRTCHNL_OP_VERSION; args.in_args = (uint8_t *)&version; args.in_args_size = sizeof(version); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); @@ -409,7 +421,7 @@ i40evf_check_api_version(struct rte_eth_dev *dev) if (vf->version_major == I40E_DPDK_VERSION_MAJOR) PMD_DRV_LOG(INFO, "Peer is DPDK PF host"); else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && - (vf->version_minor == I40E_VIRTCHNL_VERSION_MINOR)) + (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) PMD_DRV_LOG(INFO, "Peer is Linux PF host"); else { PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)", @@ -429,14 +441,23 @@ i40evf_get_vf_resource(struct rte_eth_dev *dev) struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); int err; struct vf_cmd_info args; - uint32_t len; + uint32_t caps, len; args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES; - args.in_args = NULL; - args.in_args_size = 0; - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; - + if (PF_IS_V11(vf)) { + caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 | + I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ | + I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG | + I40E_VIRTCHNL_VF_OFFLOAD_VLAN | + I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING; + args.in_args = (uint8_t *)∩︀ + args.in_args_size = sizeof(caps); + } else { + args.in_args = NULL; + args.in_args_size = 0; + } err = i40evf_execute_vf_cmd(dev, &args); if (err) { @@ -476,7 +497,7 @@ i40evf_config_promisc(struct rte_eth_dev *dev, args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE; args.in_args = (uint8_t *)&promisc; args.in_args_size = sizeof(promisc); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); @@ -503,7 +524,7 @@ i40evf_config_vlan_offload(struct rte_eth_dev *dev, args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD; args.in_args = (uint8_t *)&offload; args.in_args_size = sizeof(offload); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); @@ -522,7 +543,7 @@ i40evf_config_vlan_pvid(struct rte_eth_dev *dev, struct vf_cmd_info args; struct i40e_virtchnl_pvid_info tpid_info; - if (dev == NULL || info == NULL) { + if (info == NULL) { PMD_DRV_LOG(ERR, "invalid parameters"); return I40E_ERR_PARAM; } @@ -534,7 +555,7 @@ i40evf_config_vlan_pvid(struct rte_eth_dev *dev, args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID; args.in_args = (uint8_t *)&tpid_info; args.in_args_size = sizeof(tpid_info); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); @@ -613,7 +634,7 @@ i40evf_configure_vsi_queues(struct rte_eth_dev *dev) args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES; args.in_args = (uint8_t *)vc_vqci; args.in_args_size = size; - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; ret = i40evf_execute_vf_cmd(dev, &args); if (ret) @@ -666,7 +687,7 @@ i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev) (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT; args.in_args = (uint8_t *)vc_vqcei; args.in_args_size = size; - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; ret = i40evf_execute_vf_cmd(dev, &args); if (ret) @@ -697,24 +718,38 @@ i40evf_config_irq_map(struct rte_eth_dev *dev) uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \ sizeof(struct i40e_virtchnl_vector_map)]; struct i40e_virtchnl_irq_map_info *map_info; + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + uint32_t vector_id; int i, err; + + if (rte_intr_allow_others(intr_handle)) { + if (vf->version_major == I40E_DPDK_VERSION_MAJOR) + vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR; + else + vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX; + } else { + vector_id = I40E_MISC_VEC_ID; + } + map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer; map_info->num_vectors = 1; - map_info->vecmap[0].rxitr_idx = RTE_LIBRTE_I40E_ITR_INTERVAL / 2; - map_info->vecmap[0].txitr_idx = RTE_LIBRTE_I40E_ITR_INTERVAL / 2; + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT; map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id; /* Alway use default dynamic MSIX interrupt */ - map_info->vecmap[0].vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR; + map_info->vecmap[0].vector_id = vector_id; /* Don't map any tx queue */ map_info->vecmap[0].txq_map = 0; map_info->vecmap[0].rxq_map = 0; - for (i = 0; i < dev->data->nb_rx_queues; i++) + for (i = 0; i < dev->data->nb_rx_queues; i++) { map_info->vecmap[0].rxq_map |= 1 << i; + if (rte_intr_dp_is_en(intr_handle)) + intr_handle->intr_vec[i] = vector_id; + } args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP; args.in_args = (u8 *)cmd_buffer; args.in_args_size = sizeof(cmd_buffer); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) @@ -745,7 +780,7 @@ i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid, args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES; args.in_args = (u8 *)&queue_select; args.in_args_size = sizeof(queue_select); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) @@ -794,7 +829,7 @@ i40evf_stop_queues(struct rte_eth_dev *dev) /* Stop TX queues first */ for (i = 0; i < dev->data->nb_tx_queues; i++) { if (i40evf_dev_tx_queue_stop(dev, i) != 0) { - PMD_DRV_LOG(ERR, "Fail to start queue %u", i); + PMD_DRV_LOG(ERR, "Fail to stop queue %u", i); return -1; } } @@ -802,7 +837,7 @@ i40evf_stop_queues(struct rte_eth_dev *dev) /* Then stop RX queues */ for (i = 0; i < dev->data->nb_rx_queues; i++) { if (i40evf_dev_rx_queue_stop(dev, i) != 0) { - PMD_DRV_LOG(ERR, "Fail to start queue %u", i); + PMD_DRV_LOG(ERR, "Fail to stop queue %u", i); return -1; } } @@ -810,8 +845,11 @@ i40evf_stop_queues(struct rte_eth_dev *dev) return 0; } -static int -i40evf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) +static void +i40evf_add_mac_addr(struct rte_eth_dev *dev, + struct ether_addr *addr, + __rte_unused uint32_t index, + __rte_unused uint32_t pool) { struct i40e_virtchnl_ether_addr_list *list; struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); @@ -825,7 +863,7 @@ i40evf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) addr->addr_bytes[0], addr->addr_bytes[1], addr->addr_bytes[2], addr->addr_bytes[3], addr->addr_bytes[4], addr->addr_bytes[5]); - return -1; + return; } list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer; @@ -837,32 +875,36 @@ i40evf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS; args.in_args = cmd_buffer; args.in_args_size = sizeof(cmd_buffer); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) PMD_DRV_LOG(ERR, "fail to execute command " "OP_ADD_ETHER_ADDRESS"); - return err; + return; } -static int -i40evf_del_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) +static void +i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index) { struct i40e_virtchnl_ether_addr_list *list; struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct rte_eth_dev_data *data = dev->data; + struct ether_addr *addr; uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \ sizeof(struct i40e_virtchnl_ether_addr)]; int err; struct vf_cmd_info args; + addr = &(data->mac_addrs[index]); + if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) { PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x", addr->addr_bytes[0], addr->addr_bytes[1], addr->addr_bytes[2], addr->addr_bytes[3], addr->addr_bytes[4], addr->addr_bytes[5]); - return -1; + return; } list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer; @@ -874,22 +916,20 @@ i40evf_del_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS; args.in_args = cmd_buffer; args.in_args_size = sizeof(cmd_buffer); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) PMD_DRV_LOG(ERR, "fail to execute command " "OP_DEL_ETHER_ADDRESS"); - - return err; + return; } static int -i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats) { struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); struct i40e_virtchnl_queue_select q_stats; - struct i40e_eth_stats *pstats; int err; struct vf_cmd_info args; @@ -898,15 +938,29 @@ i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats) args.ops = I40E_VIRTCHNL_OP_GET_STATS; args.in_args = (u8 *)&q_stats; args.in_args_size = sizeof(q_stats); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) { PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS"); + *pstats = NULL; return err; } - pstats = (struct i40e_eth_stats *)args.out_buffer; + *pstats = (struct i40e_eth_stats *)args.out_buffer; + return 0; +} + +static int +i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + int ret; + struct i40e_eth_stats *pstats = NULL; + + ret = i40evf_update_stats(dev, &pstats); + if (ret != 0) + return 0; + stats->ipackets = pstats->rx_unicast + pstats->rx_multicast + pstats->rx_broadcast; stats->opackets = pstats->tx_broadcast + pstats->tx_multicast + @@ -919,6 +973,61 @@ i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats) return 0; } +static void +i40evf_dev_xstats_reset(struct rte_eth_dev *dev) +{ + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct i40e_eth_stats *pstats = NULL; + + /* read stat values to clear hardware registers */ + i40evf_update_stats(dev, &pstats); + + /* set stats offset base on current values */ + vf->vsi.eth_stats_offset = vf->vsi.eth_stats; +} + +static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, + struct rte_eth_xstat_name *xstats_names, + __rte_unused unsigned limit) +{ + unsigned i; + + if (xstats_names != NULL) + for (i = 0; i < I40EVF_NB_XSTATS; i++) { + snprintf(xstats_names[i].name, + sizeof(xstats_names[i].name), + "%s", rte_i40evf_stats_strings[i].name); + } + return I40EVF_NB_XSTATS; +} + +static int i40evf_dev_xstats_get(struct rte_eth_dev *dev, + struct rte_eth_xstat *xstats, unsigned n) +{ + int ret; + unsigned i; + struct i40e_eth_stats *pstats = NULL; + + if (n < I40EVF_NB_XSTATS) + return I40EVF_NB_XSTATS; + + ret = i40evf_update_stats(dev, &pstats); + if (ret != 0) + return 0; + + if (!xstats) + return 0; + + /* loop over xstats array and values from pstats */ + for (i = 0; i < I40EVF_NB_XSTATS; i++) { + xstats[i].id = i; + xstats[i].value = *(uint64_t *)(((char *)pstats) + + rte_i40evf_stats_strings[i].offset); + } + + return I40EVF_NB_XSTATS; +} + static int i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid) { @@ -937,7 +1046,7 @@ i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid) args.ops = I40E_VIRTCHNL_OP_ADD_VLAN; args.in_args = (u8 *)&cmd_buffer; args.in_args_size = sizeof(cmd_buffer); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) @@ -964,7 +1073,7 @@ i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid) args.ops = I40E_VIRTCHNL_OP_DEL_VLAN; args.in_args = (u8 *)&cmd_buffer; args.in_args_size = sizeof(cmd_buffer); - args.out_buffer = cmd_result_buffer; + args.out_buffer = vf->aq_resp; args.out_size = I40E_AQ_BUF_SZ; err = i40evf_execute_vf_cmd(dev, &args); if (err) @@ -973,34 +1082,13 @@ i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid) return err; } -static int -i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link) -{ - int err; - struct vf_cmd_info args; - struct rte_eth_link *new_link; - - args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT; - args.in_args = NULL; - args.in_args_size = 0; - args.out_buffer = cmd_result_buffer; - args.out_size = I40E_AQ_BUF_SZ; - err = i40evf_execute_vf_cmd(dev, &args); - if (err) { - PMD_DRV_LOG(ERR, "fail to execute command OP_GET_LINK_STAT"); - return err; - } - - new_link = (struct rte_eth_link *)args.out_buffer; - (void)rte_memcpy(link, new_link, sizeof(*link)); - - return 0; -} - static const struct rte_pci_id pci_id_i40evf_map[] = { -#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)}, -#include "rte_pci_dev_ids.h" -{ .vendor_id = 0, /* sentinel */ }, + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) }, + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) }, + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) }, + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) }, + { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) }, + { .vendor_id = 0, /* sentinel */ }, }; static inline int @@ -1017,6 +1105,38 @@ i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev, return 0; } +/* Disable IRQ0 */ +static inline void +i40evf_disable_irq0(struct i40e_hw *hw) +{ + /* Disable all interrupt types */ + I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0); + I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, + I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); + I40EVF_WRITE_FLUSH(hw); +} + +/* Enable IRQ0 */ +static inline void +i40evf_enable_irq0(struct i40e_hw *hw) +{ + /* Enable admin queue interrupt trigger */ + uint32_t val; + + i40evf_disable_irq0(hw); + val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1); + val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK | + I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK; + I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val); + + I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, + I40E_VFINT_DYN_CTL01_INTENA_MASK | + I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | + I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); + + I40EVF_WRITE_FLUSH(hw); +} + static int i40evf_reset_vf(struct i40e_hw *hw) { @@ -1061,10 +1181,13 @@ i40evf_init_vf(struct rte_eth_dev *dev) int i, err, bufsz; struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct ether_addr *p_mac_addr; + uint16_t interval = + i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX); vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); vf->dev_data = dev->data; - err = i40evf_set_mac_type(hw); + err = i40e_set_mac_type(hw); if (err) { PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err); goto err; @@ -1077,7 +1200,6 @@ i40evf_init_vf(struct rte_eth_dev *dev) goto err; } - /* Reset VF and wait until it's complete */ if (i40evf_reset_vf(hw)) { PMD_INIT_LOG(ERR, "reset NIC failed"); @@ -1095,6 +1217,11 @@ i40evf_init_vf(struct rte_eth_dev *dev) PMD_INIT_LOG(ERR, "init_adminq failed"); return -1; } + vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0); + if (!vf->aq_resp) { + PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory"); + goto err_aq; + } if (i40evf_check_api_version(dev) != 0) { PMD_INIT_LOG(ERR, "check_api version failed"); goto err_aq; @@ -1123,17 +1250,29 @@ i40evf_init_vf(struct rte_eth_dev *dev) goto err_alloc; } + if (hw->mac.type == I40E_MAC_X722_VF) + vf->flags = I40E_FLAG_RSS_AQ_CAPABLE; vf->vsi.vsi_id = vf->vsi_res->vsi_id; vf->vsi.type = vf->vsi_res->vsi_type; vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs; + vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); - /* check mac addr, if it's not valid, genrate one */ - if (I40E_SUCCESS != i40e_validate_mac_addr(\ - vf->vsi_res->default_mac_addr)) - eth_random_addr(vf->vsi_res->default_mac_addr); - - ether_addr_copy((struct ether_addr *)vf->vsi_res->default_mac_addr, - (struct ether_addr *)hw->mac.addr); + /* Store the MAC address configured by host, or generate random one */ + p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr); + if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */ + ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr); + else + eth_random_addr(hw->mac.addr); /* Generate a random one */ + + /* If the PF host is not DPDK, set the interval of ITR0 to max*/ + if (vf->version_major != I40E_DPDK_VERSION_MAJOR) { + I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, + (I40E_ITR_INDEX_DEFAULT << + I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) | + (interval << + I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)); + I40EVF_WRITE_FLUSH(hw); + } return 0; @@ -1157,15 +1296,150 @@ i40evf_uninit_vf(struct rte_eth_dev *dev) i40evf_dev_close(dev); rte_free(vf->vf_res); vf->vf_res = NULL; + rte_free(vf->aq_resp); + vf->aq_resp = NULL; return 0; } +static void +i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev, + uint8_t *msg, + __rte_unused uint16_t msglen) +{ + struct i40e_virtchnl_pf_event *pf_msg = + (struct i40e_virtchnl_pf_event *)msg; + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + + switch (pf_msg->event) { + case I40E_VIRTCHNL_EVENT_RESET_IMPENDING: + PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n"); + _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL); + break; + case I40E_VIRTCHNL_EVENT_LINK_CHANGE: + PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n"); + vf->link_up = pf_msg->event_data.link_event.link_status; + vf->link_speed = pf_msg->event_data.link_event.link_speed; + break; + case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE: + PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n"); + break; + default: + PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event); + break; + } +} + +static void +i40evf_handle_aq_msg(struct rte_eth_dev *dev) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct i40e_arq_event_info info; + struct i40e_virtchnl_msg *v_msg; + uint16_t pending, opcode; + int ret; + + info.buf_len = I40E_AQ_BUF_SZ; + if (!vf->aq_resp) { + PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL"); + return; + } + info.msg_buf = vf->aq_resp; + v_msg = (struct i40e_virtchnl_msg *)&info.desc; + + pending = 1; + while (pending) { + ret = i40e_clean_arq_element(hw, &info, &pending); + + if (ret != I40E_SUCCESS) { + PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ," + "ret: %d", ret); + break; + } + opcode = rte_le_to_cpu_16(info.desc.opcode); + + switch (opcode) { + case i40e_aqc_opc_send_msg_to_vf: + if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT) + /* process event*/ + i40evf_handle_pf_event(dev, info.msg_buf, + info.msg_len); + else { + /* read message and it's expected one */ + if (v_msg->v_opcode == vf->pend_cmd) { + vf->cmd_retval = v_msg->v_retval; + /* prevent compiler reordering */ + rte_compiler_barrier(); + _clear_cmd(vf); + } else + PMD_DRV_LOG(ERR, "command mismatch," + "expect %u, get %u", + vf->pend_cmd, v_msg->v_opcode); + PMD_DRV_LOG(DEBUG, "adminq response is received," + " opcode = %d\n", v_msg->v_opcode); + } + break; + default: + PMD_DRV_LOG(ERR, "Request %u is not supported yet", + opcode); + break; + } + } +} + +/** + * Interrupt handler triggered by NIC for handling + * specific interrupt. Only adminq interrupt is processed in VF. + * + * @param handle + * Pointer to interrupt handle. + * @param param + * The address of parameter (struct rte_eth_dev *) regsitered before. + * + * @return + * void + */ +static void +i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle, + void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t icr0; + + i40evf_disable_irq0(hw); + + /* read out interrupt causes */ + icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01); + + /* No interrupt event indicated */ + if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) { + PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n"); + goto done; + } + + if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) { + PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n"); + i40evf_handle_aq_msg(dev); + } + + /* Link Status Change interrupt */ + if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK) + PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported," + " do nothing\n"); + +done: + i40evf_enable_irq0(hw); + rte_intr_enable(&dev->pci_dev->intr_handle); +} + static int i40evf_dev_init(struct rte_eth_dev *eth_dev) { struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\ eth_dev->data->dev_private); + struct rte_pci_device *pci_dev = eth_dev->pci_dev; PMD_INIT_FUNC_TRACE(); @@ -1179,11 +1453,13 @@ i40evf_dev_init(struct rte_eth_dev *eth_dev) * has already done this work. */ if (rte_eal_process_type() != RTE_PROC_PRIMARY){ - if (eth_dev->data->scattered_rx) - eth_dev->rx_pkt_burst = i40e_recv_scattered_pkts; + i40e_set_rx_function(eth_dev); + i40e_set_tx_function(eth_dev); return 0; } + rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev); + hw->vendor_id = eth_dev->pci_dev->id.vendor_id; hw->device_id = eth_dev->pci_dev->id.device_id; hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id; @@ -1198,16 +1474,28 @@ i40evf_dev_init(struct rte_eth_dev *eth_dev) return -1; } + /* register callback func to eal lib */ + rte_intr_callback_register(&pci_dev->intr_handle, + i40evf_dev_interrupt_handler, (void *)eth_dev); + + /* enable uio intr after callback register */ + rte_intr_enable(&pci_dev->intr_handle); + + /* configure and enable device interrupt */ + i40evf_enable_irq0(hw); + /* copy mac addr */ eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac", - ETHER_ADDR_LEN, 0); + ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX, + 0); if (eth_dev->data->mac_addrs == NULL) { - PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to " - "store MAC addresses", ETHER_ADDR_LEN); + PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to" + " store MAC addresses", + ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX); return -ENOMEM; } ether_addr_copy((struct ether_addr *)hw->mac.addr, - (struct ether_addr *)eth_dev->data->mac_addrs); + ð_dev->data->mac_addrs[0]); return 0; } @@ -1239,41 +1527,49 @@ i40evf_dev_uninit(struct rte_eth_dev *eth_dev) */ static struct eth_driver rte_i40evf_pmd = { .pci_drv = { - .name = "rte_i40evf_pmd", .id_table = pci_id_i40evf_map, .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE, + .probe = rte_eth_dev_pci_probe, + .remove = rte_eth_dev_pci_remove, }, .eth_dev_init = i40evf_dev_init, .eth_dev_uninit = i40evf_dev_uninit, - .dev_private_size = sizeof(struct i40e_vf), + .dev_private_size = sizeof(struct i40e_adapter), }; -/* - * VF Driver initialization routine. - * Invoked one at EAL init time. - * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices. - */ +RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv); +RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map); +RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio"); + static int -rte_i40evf_pmd_init(const char *name __rte_unused, - const char *params __rte_unused) +i40evf_dev_configure(struct rte_eth_dev *dev) { - PMD_INIT_FUNC_TRACE(); + struct i40e_adapter *ad = + I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct rte_eth_conf *conf = &dev->data->dev_conf; + struct i40e_vf *vf; - rte_eth_driver_register(&rte_i40evf_pmd); - - return 0; -} - -static struct rte_driver rte_i40evf_driver = { - .type = PMD_PDEV, - .init = rte_i40evf_pmd_init, -}; + /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk + * allocation or vector Rx preconditions we will reset it. + */ + ad->rx_bulk_alloc_allowed = true; + ad->rx_vec_allowed = true; + ad->tx_simple_allowed = true; + ad->tx_vec_allowed = true; -PMD_REGISTER_DRIVER(rte_i40evf_driver); + /* For non-DPDK PF drivers, VF has no ability to disable HW + * CRC strip, and is implicitly enabled by the PF. + */ + if (!conf->rxmode.hw_strip_crc) { + vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && + (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) { + /* Peer is running non-DPDK PF driver. */ + PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip"); + return -EINVAL; + } + } -static int -i40evf_dev_configure(struct rte_eth_dev *dev) -{ return i40evf_init_vlan(dev); } @@ -1370,6 +1666,8 @@ i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (err) PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on", rx_queue_id); + else + dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; } return err; @@ -1394,6 +1692,7 @@ i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) i40e_rx_queue_release_mbufs(rxq); i40e_reset_rx_queue(rxq); + dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; } return 0; @@ -1414,6 +1713,8 @@ i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (err) PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on", tx_queue_id); + else + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; } return err; @@ -1431,13 +1732,14 @@ i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE); if (err) { - PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of", + PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", tx_queue_id); return err; } i40e_tx_queue_release_mbufs(txq); i40e_reset_tx_queue(txq); + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; } return 0; @@ -1505,7 +1807,6 @@ i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq) if (dev_data->dev_conf.rxmode.enable_scatter || (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) { dev_data->scattered_rx = 1; - dev->rx_pkt_burst = i40e_recv_scattered_pkts; } return 0; @@ -1516,16 +1817,22 @@ i40evf_rx_init(struct rte_eth_dev *dev) { struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); uint16_t i; + int ret = I40E_SUCCESS; struct i40e_rx_queue **rxq = (struct i40e_rx_queue **)dev->data->rx_queues; i40evf_config_rss(vf); for (i = 0; i < dev->data->nb_rx_queues; i++) { - if (i40evf_rxq_init(dev, rxq[i]) < 0) - return -EFAULT; + if (!rxq[i] || !rxq[i]->q_set) + continue; + ret = i40evf_rxq_init(dev, rxq[i]); + if (ret != I40E_SUCCESS) + break; } + if (ret == I40E_SUCCESS) + i40e_set_rx_function(dev); - return 0; + return ret; } static void @@ -1538,21 +1845,180 @@ i40evf_tx_init(struct rte_eth_dev *dev) for (i = 0; i < dev->data->nb_tx_queues; i++) txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i); + + i40e_set_tx_function(dev); } static inline void -i40evf_enable_queues_intr(struct i40e_hw *hw) +i40evf_enable_queues_intr(struct rte_eth_dev *dev) { - I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1), + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + + if (!rte_intr_allow_others(intr_handle)) { + I40E_WRITE_REG(hw, + I40E_VFINT_DYN_CTL01, + I40E_VFINT_DYN_CTL01_INTENA_MASK | + I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | + I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); + I40EVF_WRITE_FLUSH(hw); + return; + } + + if (vf->version_major == I40E_DPDK_VERSION_MAJOR) + /* To support DPDK PF host */ + I40E_WRITE_REG(hw, + I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1), I40E_VFINT_DYN_CTLN1_INTENA_MASK | I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); + /* If host driver is kernel driver, do nothing. + * Interrupt 0 is used for rx packets, but don't set + * I40E_VFINT_DYN_CTL01, + * because it is already done in i40evf_enable_irq0. + */ + + I40EVF_WRITE_FLUSH(hw); } static inline void -i40evf_disable_queues_intr(struct i40e_hw *hw) +i40evf_disable_queues_intr(struct rte_eth_dev *dev) +{ + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + + if (!rte_intr_allow_others(intr_handle)) { + I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, + I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); + I40EVF_WRITE_FLUSH(hw); + return; + } + + if (vf->version_major == I40E_DPDK_VERSION_MAJOR) + I40E_WRITE_REG(hw, + I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR + - 1), + 0); + /* If host driver is kernel driver, do nothing. + * Interrupt 0 is used for rx packets, but don't zero + * I40E_VFINT_DYN_CTL01, + * because interrupt 0 is also used for adminq processing. + */ + + I40EVF_WRITE_FLUSH(hw); +} + +static int +i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) { - I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1), - 0); + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint16_t interval = + i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL); + uint16_t msix_intr; + + msix_intr = intr_handle->intr_vec[queue_id]; + if (msix_intr == I40E_MISC_VEC_ID) + I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, + I40E_VFINT_DYN_CTL01_INTENA_MASK | + I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | + (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) | + (interval << + I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)); + else + I40E_WRITE_REG(hw, + I40E_VFINT_DYN_CTLN1(msix_intr - + I40E_RX_VEC_START), + I40E_VFINT_DYN_CTLN1_INTENA_MASK | + I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK | + (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | + (interval << + I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)); + + I40EVF_WRITE_FLUSH(hw); + + rte_intr_enable(&dev->pci_dev->intr_handle); + + return 0; +} + +static int +i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) +{ + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint16_t msix_intr; + + msix_intr = intr_handle->intr_vec[queue_id]; + if (msix_intr == I40E_MISC_VEC_ID) + I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0); + else + I40E_WRITE_REG(hw, + I40E_VFINT_DYN_CTLN1(msix_intr - + I40E_RX_VEC_START), + 0); + + I40EVF_WRITE_FLUSH(hw); + + return 0; +} + +static void +i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add) +{ + struct i40e_virtchnl_ether_addr_list *list; + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + int err, i, j; + int next_begin = 0; + int begin = 0; + uint32_t len; + struct ether_addr *addr; + struct vf_cmd_info args; + + do { + j = 0; + len = sizeof(struct i40e_virtchnl_ether_addr_list); + for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) { + if (is_zero_ether_addr(&dev->data->mac_addrs[i])) + continue; + len += sizeof(struct i40e_virtchnl_ether_addr); + if (len >= I40E_AQ_BUF_SZ) { + next_begin = i + 1; + break; + } + } + + list = rte_zmalloc("i40evf_del_mac_buffer", len, 0); + + for (i = begin; i < next_begin; i++) { + addr = &dev->data->mac_addrs[i]; + if (is_zero_ether_addr(addr)) + continue; + (void)rte_memcpy(list->list[j].addr, addr->addr_bytes, + sizeof(addr->addr_bytes)); + PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x", + addr->addr_bytes[0], addr->addr_bytes[1], + addr->addr_bytes[2], addr->addr_bytes[3], + addr->addr_bytes[4], addr->addr_bytes[5]); + j++; + } + list->vsi_id = vf->vsi_res->vsi_id; + list->num_elements = j; + args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS : + I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS; + args.in_args = (uint8_t *)list; + args.in_args_size = len; + args.out_buffer = vf->aq_resp; + args.out_size = I40E_AQ_BUF_SZ; + err = i40evf_execute_vf_cmd(dev, &args); + if (err) + PMD_DRV_LOG(ERR, "fail to execute command %s", + add ? "OP_ADD_ETHER_ADDRESS" : + "OP_DEL_ETHER_ADDRESS"); + rte_free(list); + begin = next_begin; + } while (begin < I40E_NUM_MACADDR_MAX); } static int @@ -1560,7 +2026,8 @@ i40evf_dev_start(struct rte_eth_dev *dev) { struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - struct ether_addr mac_addr; + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + uint32_t intr_vector = 0; PMD_INIT_FUNC_TRACE(); @@ -1570,6 +2037,24 @@ i40evf_dev_start(struct rte_eth_dev *dev) vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues, dev->data->nb_tx_queues); + /* check and configure queue intr-vector mapping */ + if (dev->data->dev_conf.intr_conf.rxq != 0) { + intr_vector = dev->data->nb_rx_queues; + if (rte_intr_efd_enable(intr_handle, intr_vector)) + return -1; + } + + if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { + intr_handle->intr_vec = + rte_zmalloc("intr_vec", + dev->data->nb_rx_queues * sizeof(int), 0); + if (!intr_handle->intr_vec) { + PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" + " intr_vec\n", dev->data->nb_rx_queues); + return -ENOMEM; + } + } + if (i40evf_rx_init(dev) != 0){ PMD_DRV_LOG(ERR, "failed to do RX init"); return -1; @@ -1586,24 +2071,19 @@ i40evf_dev_start(struct rte_eth_dev *dev) goto err_queue; } - /* Set mac addr */ - (void)rte_memcpy(mac_addr.addr_bytes, hw->mac.addr, - sizeof(mac_addr.addr_bytes)); - if (i40evf_add_mac_addr(dev, &mac_addr)) { - PMD_DRV_LOG(ERR, "Failed to add mac addr"); - goto err_queue; - } + /* Set all mac addrs */ + i40evf_add_del_all_mac_addr(dev, TRUE); if (i40evf_start_queues(dev) != 0) { PMD_DRV_LOG(ERR, "enable queues failed"); goto err_mac; } - i40evf_enable_queues_intr(hw); + i40evf_enable_queues_intr(dev); return 0; err_mac: - i40evf_del_mac_addr(dev, &mac_addr); + i40evf_add_del_all_mac_addr(dev, FALSE); err_queue: return -1; } @@ -1611,12 +2091,23 @@ err_queue: static void i40evf_dev_stop(struct rte_eth_dev *dev) { - struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; PMD_INIT_FUNC_TRACE(); - i40evf_disable_queues_intr(hw); i40evf_stop_queues(dev); + i40evf_disable_queues_intr(dev); + i40e_dev_clear_queues(dev); + + /* Clean datapath event and queue/vec mapping */ + rte_intr_efd_disable(intr_handle); + if (intr_handle->intr_vec) { + rte_free(intr_handle->intr_vec); + intr_handle->intr_vec = NULL; + } + /* remove all mac addrs */ + i40evf_add_del_all_mac_addr(dev, FALSE); + } static int @@ -1629,14 +2120,33 @@ i40evf_dev_link_update(struct rte_eth_dev *dev, * DPDK pf host provide interfacet to acquire link status * while Linux driver does not */ - if (vf->version_major == I40E_DPDK_VERSION_MAJOR) - i40evf_get_link_status(dev, &new_link); - else { - /* Always assume it's up, for Linux driver PF host */ - new_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX; - new_link.link_speed = ETH_LINK_SPEED_10000; - new_link.link_status = 1; + + /* Linux driver PF host */ + switch (vf->link_speed) { + case I40E_LINK_SPEED_100MB: + new_link.link_speed = ETH_SPEED_NUM_100M; + break; + case I40E_LINK_SPEED_1GB: + new_link.link_speed = ETH_SPEED_NUM_1G; + break; + case I40E_LINK_SPEED_10GB: + new_link.link_speed = ETH_SPEED_NUM_10G; + break; + case I40E_LINK_SPEED_20GB: + new_link.link_speed = ETH_SPEED_NUM_20G; + break; + case I40E_LINK_SPEED_40GB: + new_link.link_speed = ETH_SPEED_NUM_40G; + break; + default: + new_link.link_speed = ETH_SPEED_NUM_100M; + break; } + /* full duplex only */ + new_link.link_duplex = ETH_LINK_FULL_DUPLEX; + new_link.link_status = vf->link_up ? ETH_LINK_UP : + ETH_LINK_DOWN; + i40evf_dev_atomic_write_link_status(dev, &new_link); return 0; @@ -1715,6 +2225,7 @@ i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); dev_info->reta_size = ETH_RSS_RETA_SIZE_64; dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL; + dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX; dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | DEV_RX_OFFLOAD_QINQ_STRIP | @@ -1750,6 +2261,18 @@ i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS, }; + + dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = I40E_MAX_RING_DESC, + .nb_min = I40E_MIN_RING_DESC, + .nb_align = I40E_ALIGN_RING_DESC, + }; + + dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = I40E_MAX_RING_DESC, + .nb_min = I40E_MIN_RING_DESC, + .nb_align = I40E_ALIGN_RING_DESC, + }; } static void @@ -1763,11 +2286,80 @@ static void i40evf_dev_close(struct rte_eth_dev *dev) { struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev = dev->pci_dev; i40evf_dev_stop(dev); hw->adapter_stopped = 1; + i40e_dev_free_queues(dev); i40evf_reset_vf(hw); i40e_shutdown_adminq(hw); + /* disable uio intr before callback unregister */ + rte_intr_disable(&pci_dev->intr_handle); + + /* unregister callback func from eal lib */ + rte_intr_callback_unregister(&pci_dev->intr_handle, + i40evf_dev_interrupt_handler, (void *)dev); + i40evf_disable_irq0(hw); +} + +static int +i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) +{ + struct i40e_vf *vf = I40E_VSI_TO_VF(vsi); + struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); + int ret; + + if (!lut) + return -EINVAL; + + if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { + ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE, + lut, lut_size); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to get RSS lookup table"); + return ret; + } + } else { + uint32_t *lut_dw = (uint32_t *)lut; + uint16_t i, lut_size_dw = lut_size / 4; + + for (i = 0; i < lut_size_dw; i++) + lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i)); + } + + return 0; +} + +static int +i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size) +{ + struct i40e_vf *vf; + struct i40e_hw *hw; + int ret; + + if (!vsi || !lut) + return -EINVAL; + + vf = I40E_VSI_TO_VF(vsi); + hw = I40E_VSI_TO_HW(vsi); + + if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { + ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE, + lut, lut_size); + if (ret) { + PMD_DRV_LOG(ERR, "Failed to set RSS lookup table"); + return ret; + } + } else { + uint32_t *lut_dw = (uint32_t *)lut; + uint16_t i, lut_size_dw = lut_size / 4; + + for (i = 0; i < lut_size_dw; i++) + I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]); + I40EVF_WRITE_FLUSH(hw); + } + + return 0; } static int @@ -1775,11 +2367,10 @@ i40evf_dev_rss_reta_update(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size) { - struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t lut, l; - uint16_t i, j; - uint16_t idx, shift; - uint8_t mask; + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + uint8_t *lut; + uint16_t i, idx, shift; + int ret; if (reta_size != ETH_RSS_RETA_SIZE_64) { PMD_DRV_LOG(ERR, "The size of hash lookup table configured " @@ -1788,29 +2379,26 @@ i40evf_dev_rss_reta_update(struct rte_eth_dev *dev, return -EINVAL; } - for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) { + lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); + if (!lut) { + PMD_DRV_LOG(ERR, "No memory can be allocated"); + return -ENOMEM; + } + ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size); + if (ret) + goto out; + for (i = 0; i < reta_size; i++) { idx = i / RTE_RETA_GROUP_SIZE; shift = i % RTE_RETA_GROUP_SIZE; - mask = (uint8_t)((reta_conf[idx].mask >> shift) & - I40E_4_BIT_MASK); - if (!mask) - continue; - if (mask == I40E_4_BIT_MASK) - l = 0; - else - l = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2)); - - for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) { - if (mask & (0x1 << j)) - lut |= reta_conf[idx].reta[shift + j] << - (CHAR_BIT * j); - else - lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j)); - } - I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut); + if (reta_conf[idx].mask & (1ULL << shift)) + lut[i] = reta_conf[idx].reta[shift]; } + ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size); - return 0; +out: + rte_free(lut); + + return ret; } static int @@ -1818,11 +2406,10 @@ i40evf_dev_rss_reta_query(struct rte_eth_dev *dev, struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size) { - struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t lut; - uint16_t i, j; - uint16_t idx, shift; - uint8_t mask; + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); + uint16_t i, idx, shift; + uint8_t *lut; + int ret; if (reta_size != ETH_RSS_RETA_SIZE_64) { PMD_DRV_LOG(ERR, "The size of hash lookup table configured " @@ -1831,50 +2418,115 @@ i40evf_dev_rss_reta_query(struct rte_eth_dev *dev, return -EINVAL; } - for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) { + lut = rte_zmalloc("i40e_rss_lut", reta_size, 0); + if (!lut) { + PMD_DRV_LOG(ERR, "No memory can be allocated"); + return -ENOMEM; + } + + ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size); + if (ret) + goto out; + for (i = 0; i < reta_size; i++) { idx = i / RTE_RETA_GROUP_SIZE; shift = i % RTE_RETA_GROUP_SIZE; - mask = (uint8_t)((reta_conf[idx].mask >> shift) & - I40E_4_BIT_MASK); - if (!mask) - continue; + if (reta_conf[idx].mask & (1ULL << shift)) + reta_conf[idx].reta[shift] = lut[i]; + } - lut = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2)); - for (j = 0; j < I40E_4_BIT_WIDTH; j++) { - if (mask & (0x1 << j)) - reta_conf[idx].reta[shift + j] = - ((lut >> (CHAR_BIT * j)) & - I40E_8_BIT_MASK); - } +out: + rte_free(lut); + + return ret; +} + +static int +i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len) +{ + struct i40e_vf *vf = I40E_VSI_TO_VF(vsi); + struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); + int ret = 0; + + if (!key || key_len == 0) { + PMD_DRV_LOG(DEBUG, "No key to be configured"); + return 0; + } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) * + sizeof(uint32_t)) { + PMD_DRV_LOG(ERR, "Invalid key length %u", key_len); + return -EINVAL; } - return 0; + if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { + struct i40e_aqc_get_set_rss_key_data *key_dw = + (struct i40e_aqc_get_set_rss_key_data *)key; + + ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw); + if (ret) + PMD_INIT_LOG(ERR, "Failed to configure RSS key " + "via AQ"); + } else { + uint32_t *hash_key = (uint32_t *)key; + uint16_t i; + + for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) + i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]); + I40EVF_WRITE_FLUSH(hw); + } + + return ret; } static int -i40evf_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf) +i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len) { - uint32_t *hash_key; - uint8_t hash_key_len; - uint64_t rss_hf, hena; + struct i40e_vf *vf = I40E_VSI_TO_VF(vsi); + struct i40e_hw *hw = I40E_VSI_TO_HW(vsi); + int ret; - hash_key = (uint32_t *)(rss_conf->rss_key); - hash_key_len = rss_conf->rss_key_len; - if (hash_key != NULL && hash_key_len >= - (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { + if (!key || !key_len) + return -EINVAL; + + if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) { + ret = i40e_aq_get_rss_key(hw, vsi->vsi_id, + (struct i40e_aqc_get_set_rss_key_data *)key); + if (ret) { + PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ"); + return ret; + } + } else { + uint32_t *key_dw = (uint32_t *)key; uint16_t i; for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) - I40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]); + key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i)); } + *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t); + + return 0; +} + +static int +i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf) +{ + struct i40e_hw *hw = I40E_VF_TO_HW(vf); + uint64_t rss_hf, hena; + int ret; + + ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key, + rss_conf->rss_key_len); + if (ret) + return ret; rss_hf = rss_conf->rss_hf; - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; - hena &= ~I40E_RSS_HENA_ALL; - hena |= i40e_config_hena(rss_hf); - I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena); - I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; + if (hw->mac.type == I40E_MAC_X722) + hena &= ~I40E_RSS_HENA_ALL_X722; + else + hena &= ~I40E_RSS_HENA_ALL; + hena |= i40e_config_hena(rss_hf, hw->mac.type); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); I40EVF_WRITE_FLUSH(hw); return 0; @@ -1886,11 +2538,14 @@ i40evf_disable_rss(struct i40e_vf *vf) struct i40e_hw *hw = I40E_VF_TO_HW(vf); uint64_t hena; - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; - hena &= ~I40E_RSS_HENA_ALL; - I40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena); - I40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; + if (hw->mac.type == I40E_MAC_X722) + hena &= ~I40E_RSS_HENA_ALL_X722; + else + hena &= ~I40E_RSS_HENA_ALL; + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena); + i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32)); I40EVF_WRITE_FLUSH(hw); } @@ -1900,6 +2555,7 @@ i40evf_config_rss(struct i40e_vf *vf) struct i40e_hw *hw = I40E_VF_TO_HW(vf); struct rte_eth_rss_conf rss_conf; uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4; + uint16_t num; if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { i40evf_disable_rss(vf); @@ -1907,9 +2563,10 @@ i40evf_config_rss(struct i40e_vf *vf) return 0; } + num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF); /* Fill out the look up table */ for (i = 0, j = 0; i < nb_q; i++, j++) { - if (j >= vf->num_queue_pairs) + if (j >= num) j = 0; lut = (lut << 8) | j; if ((i & 3) == 3) @@ -1923,28 +2580,33 @@ i40evf_config_rss(struct i40e_vf *vf) return 0; } - if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < nb_q) { + if (rss_conf.rss_key == NULL || rss_conf.rss_key_len < + (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) { /* Calculate the default hash key */ for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) rss_key_default[i] = (uint32_t)rte_rand(); rss_conf.rss_key = (uint8_t *)rss_key_default; - rss_conf.rss_key_len = nb_q; + rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * + sizeof(uint32_t); } - return i40evf_hw_rss_hash_set(hw, &rss_conf); + return i40evf_hw_rss_hash_set(vf, &rss_conf); } static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf) { + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL; uint64_t hena; - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; - if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */ + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; + if (!(hena & ((hw->mac.type == I40E_MAC_X722) + ? I40E_RSS_HENA_ALL_X722 + : I40E_RSS_HENA_ALL))) { /* RSS disabled */ if (rss_hf != 0) /* Enable RSS */ return -EINVAL; return 0; @@ -1954,25 +2616,22 @@ i40evf_dev_rss_hash_update(struct rte_eth_dev *dev, if (rss_hf == 0) /* Disable RSS */ return -EINVAL; - return i40evf_hw_rss_hash_set(hw, rss_conf); + return i40evf_hw_rss_hash_set(vf, rss_conf); } static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, struct rte_eth_rss_conf *rss_conf) { + struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private); struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key); uint64_t hena; - uint16_t i; - if (hash_key) { - for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) - hash_key[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i)); - rss_conf->rss_key_len = i * sizeof(uint32_t); - } - hena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0)); - hena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32; + i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key, + &rss_conf->rss_key_len); + + hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0)); + hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32; rss_conf->rss_hf = i40e_parse_hena(hena); return 0;