X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fmlx5%2Fmlx5_defs.h;h=e5f7acc40c672b5a7903812871d2a46f998bd429;hb=a0bfe9d56f746c749ff4cf275e88469fd952b01c;hp=51124cdcc5cd2349e7e88862ebe87cc1a91edd83;hpb=7d6bf6b866b8c25ec06539b3eeed1db4f785577c;p=dpdk.git diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h index 51124cdcc5..e5f7acc40c 100644 --- a/drivers/net/mlx5/mlx5_defs.h +++ b/drivers/net/mlx5/mlx5_defs.h @@ -7,20 +7,13 @@ #define RTE_PMD_MLX5_DEFS_H_ #include +#include #include "mlx5_autoconf.h" /* Reported driver name. */ #define MLX5_DRIVER_NAME "net_mlx5" -/* Maximum number of simultaneous unicast MAC addresses. */ -#define MLX5_MAX_UC_MAC_ADDRESSES 128 -/* Maximum number of simultaneous Multicast MAC addresses. */ -#define MLX5_MAX_MC_MAC_ADDRESSES 128 -/* Maximum number of simultaneous MAC addresses. */ -#define MLX5_MAX_MAC_ADDRESSES \ - (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) - /* Maximum number of simultaneous VLAN filters. */ #define MLX5_MAX_VLAN_IDS 128 @@ -28,7 +21,7 @@ * Request TX completion every time descriptors reach this threshold since * the previous request. Must be a power of two for performance reasons. */ -#define MLX5_TX_COMP_THRESH 32 +#define MLX5_TX_COMP_THRESH 32u /* * Request TX completion every time the total number of WQEBBs used for inlining @@ -37,6 +30,13 @@ */ #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) +/* + * Maximal amount of normal completion CQEs + * processed in one call of tx_burst() routine. + */ +#define MLX5_TX_COMP_MAX_CQE 2u + + /* Size of per-queue MR cache array for linear search. */ #define MLX5_MR_CACHE_N 8 @@ -51,6 +51,10 @@ #define MLX5_PMD_SOFT_COUNTERS 1 #endif +/* Switch port ID parameters for bonding configurations. */ +#define MLX5_PORT_ID_BONDING_PF_MASK 0xf +#define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf + /* Alarm timeout. */ #define MLX5_ALARM_TIMEOUT_US 100000 @@ -58,45 +62,89 @@ #define MLX5_MAX_XSTATS 32 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ -#define MLX5_MAX_TSO_HEADER 192 - -/* Default minimum number of Tx queues for vectorized Tx. */ -#define MLX5_VPMD_MIN_TXQS 4 +#define MLX5_MAX_TSO_HEADER (128u + 34u) + +/* Inline data size required by NICs. */ +#define MLX5_INLINE_HSIZE_NONE 0 +#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_vlan_hdr)) +#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ + sizeof(struct rte_ipv6_hdr)) +#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ + sizeof(struct rte_tcp_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ + sizeof(struct rte_udp_hdr) + \ + sizeof(struct rte_vxlan_hdr) + \ + sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_vlan_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ + sizeof(struct rte_ipv6_hdr)) +#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ + sizeof(struct rte_tcp_hdr)) /* Threshold of buffer replenishment for vectorized Rx. */ -#define MLX5_VPMD_RXQ_RPLNSH_THRESH 64U +#define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ + (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2)) /* Maximum size of burst for vectorized Rx. */ -#define MLX5_VPMD_RX_MAX_BURST MLX5_VPMD_RXQ_RPLNSH_THRESH +#define MLX5_VPMD_RX_MAX_BURST 64U -/* - * Maximum size of burst for vectorized Tx. This is related to the maximum size - * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW. - * Careful when changing, large value can cause WQE DS to overlap. - */ -#define MLX5_VPMD_TX_MAX_BURST 32U +/* Recommended optimal burst size. */ +#define MLX5_RX_DEFAULT_BURST 64U +#define MLX5_TX_DEFAULT_BURST 64U /* Number of packets vectorized Rx can simultaneously process in a loop. */ #define MLX5_VPMD_DESCS_PER_LOOP 4 +/* Mask of RSS on source only or destination only. */ +#define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \ + ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY) + /* Supported RSS */ -#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP)) +#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ + MLX5_RSS_SRC_DST_ONLY)) /* Timeout in seconds to get a valid link status. */ #define MLX5_LINK_STATUS_TIMEOUT 10 -/* Reserved address space for UAR mapping. */ -#define MLX5_UAR_SIZE (1ULL << 32) - -/* Offset of reserved UAR address space to hugepage memory. Offset is used here - * to minimize possibility of address next to hugepage being used by other code - * in either primary or secondary process, failing to map TX UAR would make TX - * packets invisible to HW. +/* Number of times to retry retrieving the physical link information. */ +#define MLX5_GET_LINK_STATUS_RETRY_COUNT 3 + +/* Maximum number of UAR pages used by a port, + * These are the size and mask for an array of mutexes used to synchronize + * the access to port's UARs on platforms that do not support 64 bit writes. + * In such systems it is possible to issue the 64 bits DoorBells through two + * consecutive writes, each write 32 bits. The access to a UAR page (which can + * be accessible by all threads in the process) must be synchronized + * (for example, using a semaphore). Such a synchronization is not required + * when ringing DoorBells on different UAR pages. + * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared + * among the ports. */ -#define MLX5_UAR_OFFSET (1ULL << 32) +#define MLX5_UAR_PAGE_NUM_MAX 64 +#define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) + +/* Fields of memory mapping type in offset parameter of mmap() */ +#define MLX5_UAR_MMAP_CMD_SHIFT 8 +#define MLX5_UAR_MMAP_CMD_MASK 0xff + +/* Environment variable to control the doorbell register mapping. */ +#define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" +#if defined(RTE_ARCH_ARM64) +#define MLX5_SHUT_UP_BF_DEFAULT "0" +#else +#define MLX5_SHUT_UP_BF_DEFAULT "1" +#endif + +#ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD +#define MLX5_MMAP_GET_NC_PAGES_CMD 3 +#endif /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ -#define MLX5_MPRQ_STRIDE_NUM_N 4U +#define MLX5_MPRQ_STRIDE_NUM_N 6U + +/* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ +#define MLX5_MPRQ_STRIDE_SIZE_N 11U /* Two-byte shift is disabled for Multi-Packet RQ. */ #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 @@ -111,6 +159,52 @@ #define MLX5_MPRQ_MIN_RXQS 12 /* Cache size of mempool for Multi-Packet RQ. */ -#define MLX5_MPRQ_MP_CACHE_SZ 32 +#define MLX5_MPRQ_MP_CACHE_SZ 32U + +/* MLX5_DV_XMETA_EN supported values. */ +#define MLX5_XMETA_MODE_LEGACY 0 +#define MLX5_XMETA_MODE_META16 1 +#define MLX5_XMETA_MODE_META32 2 + +/* MLX5_TX_DB_NC supported values. */ +#define MLX5_TXDB_CACHED 0 +#define MLX5_TXDB_NCACHED 1 +#define MLX5_TXDB_HEURISTIC 2 + +/* Tx accurate scheduling on timestamps parameters. */ +#define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ +#define MLX5_TXPP_CLKQ_SIZE 1 +#define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) +#define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ + MLX5_TXPP_REARM) * 2) +#define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) +/* The minimal size test packet to put into one WQE, padded by HW. */ +#define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ + sizeof(struct rte_ipv4_hdr)) + +/* Size of the simple hash table for metadata register table. */ +#define MLX5_FLOW_MREG_HTABLE_SZ 4096 +#define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" +#define MLX5_DEFAULT_COPY_ID UINT32_MAX + +/* Hairpin TX/RX queue configuration parameters. */ +#define MLX5_HAIRPIN_QUEUE_STRIDE 6 +#define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) + +/* Definition of static_assert found in /usr/include/assert.h */ +#ifndef HAVE_STATIC_ASSERT +#define static_assert _Static_assert +#endif + +/* + * Defines the amount of retries to allocate the first UAR in the page. + * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as + * UAR base address if UAR was not the first object in the UAR page. + * It caused the PMD failure and we should try to get another UAR + * till we get the first one with non-NULL base address returned. + * Should follow the rdma_core internal (not exported) definition + * MLX5_NUM_NON_FP_BFREGS_PER_UAR. + */ +#define MLX5_ALLOC_UAR_RETRY 2 #endif /* RTE_PMD_MLX5_DEFS_H_ */