X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=examples%2Fvmdq_dcb%2Fmain.c;h=3c7f2b381d059bf44df6a96e1ac7875c6fe955df;hb=ea0c20ea95fd5d71a10757e6598ac66233ea1495;hp=2f708a1543bbbb1d1d0427c66d4b5cc66c038fc6;hpb=3031749c2df04a63cdcef186dcce3781e61436e8;p=dpdk.git diff --git a/examples/vmdq_dcb/main.c b/examples/vmdq_dcb/main.c index 2f708a1543..3c7f2b381d 100644 --- a/examples/vmdq_dcb/main.c +++ b/examples/vmdq_dcb/main.c @@ -48,7 +48,6 @@ #include #include #include -#include #include #include #include @@ -70,14 +69,12 @@ #include #include -#include "main.h" - /* basic constants used in application */ #define NUM_QUEUES 128 #define NUM_MBUFS 64*1024 #define MBUF_CACHE_SIZE 64 -#define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM) +#define MBUF_DATA_SIZE (2048 + RTE_PKTMBUF_HEADROOM) #define INVALID_PORT_ID 0xFF @@ -87,36 +84,6 @@ static uint32_t enabled_port_mask = 0; /* number of pools (if user does not specify any, 16 by default */ static enum rte_eth_nb_pools num_pools = ETH_16_POOLS; -/* - * RX and TX Prefetch, Host, and Write-back threshold values should be - * carefully set for optimal performance. Consult the network - * controller's datasheet and supporting DPDK documentation for guidance - * on how these parameters should be set. - */ -/* Default configuration for rx and tx thresholds etc. */ -static const struct rte_eth_rxconf rx_conf_default = { - .rx_thresh = { - .pthresh = 8, - .hthresh = 8, - .wthresh = 4, - }, -}; - -/* - * These default values are optimized for use with the Intel(R) 82599 10 GbE - * Controller and the DPDK ixgbe PMD. Consider using other values for other - * network controllers and/or network drivers. - */ -static const struct rte_eth_txconf tx_conf_default = { - .tx_thresh = { - .pthresh = 36, - .hthresh = 0, - .wthresh = 0, - }, - .tx_free_thresh = 0, /* Use PMD default values */ - .tx_rs_thresh = 0, /* Use PMD default values */ -}; - /* empty vmdq+dcb configuration structure. Filled in programatically */ static const struct rte_eth_conf vmdq_dcb_conf_default = { .rxmode = { @@ -212,7 +179,8 @@ port_init(uint8_t port, struct rte_mempool *mbuf_pool) for (q = 0; q < rxRings; q ++) { retval = rte_eth_rx_queue_setup(port, q, rxRingSize, - rte_eth_dev_socket_id(port), &rx_conf_default, + rte_eth_dev_socket_id(port), + NULL, mbuf_pool); if (retval < 0) return retval; @@ -220,7 +188,8 @@ port_init(uint8_t port, struct rte_mempool *mbuf_pool) for (q = 0; q < txRings; q ++) { retval = rte_eth_tx_queue_setup(port, q, txRingSize, - rte_eth_dev_socket_id(port), &tx_conf_default); + rte_eth_dev_socket_id(port), + NULL); if (retval < 0) return retval; } @@ -341,7 +310,6 @@ vmdq_parse_args(int argc, char **argv) } -#ifndef RTE_EXEC_ENV_BAREMETAL /* When we receive a HUP signal, print out our stats */ static void sighup_handler(int signum) @@ -354,7 +322,6 @@ sighup_handler(int signum) } printf("\nFinished handling signal %d\n", signum); } -#endif /* * Main thread that does the work, reading from INPUT_PORT @@ -429,7 +396,7 @@ static unsigned check_ports_num(unsigned nb_ports) /* Main function, does initialisation and calls the per-lcore functions */ int -MAIN(int argc, char *argv[]) +main(int argc, char *argv[]) { unsigned cores; struct rte_mempool *mbuf_pool; @@ -439,9 +406,7 @@ MAIN(int argc, char *argv[]) unsigned nb_ports, valid_num_ports; uint8_t portid; -#ifndef RTE_EXEC_ENV_BAREMETAL signal(SIGHUP, sighup_handler); -#endif /* init EAL */ ret = rte_eal_init(argc, argv); @@ -476,12 +441,8 @@ MAIN(int argc, char *argv[]) rte_exit(EXIT_FAILURE, "Error with valid ports number is not even or less than 2\n"); } - mbuf_pool = rte_mempool_create("MBUF_POOL", NUM_MBUFS * nb_ports, - MBUF_SIZE, MBUF_CACHE_SIZE, - sizeof(struct rte_pktmbuf_pool_private), - rte_pktmbuf_pool_init, NULL, - rte_pktmbuf_init, NULL, - rte_socket_id(), 0); + mbuf_pool = rte_pktmbuf_pool_create("MBUF_POOL", NUM_MBUFS * nb_ports, + MBUF_CACHE_SIZE, 0, MBUF_DATA_SIZE, rte_socket_id()); if (mbuf_pool == NULL) rte_exit(EXIT_FAILURE, "Cannot create mbuf pool\n");