X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_eal%2Flinuxapp%2Feal%2Feal_timer.c;h=169c6e11e58359f810d58a8828fba9dd46dce72d;hb=ff708facfcbf42f3dcb3c62d82ecd93e7b8c2506;hp=1d10457b8d7b47efb3b234ff8b5743292af794c1;hpb=da6fd0759cbeb5fc14991a79e40105b9f6b99059;p=dpdk.git

diff --git a/lib/librte_eal/linuxapp/eal/eal_timer.c b/lib/librte_eal/linuxapp/eal/eal_timer.c
index 1d10457b8d..169c6e11e5 100644
--- a/lib/librte_eal/linuxapp/eal/eal_timer.c
+++ b/lib/librte_eal/linuxapp/eal/eal_timer.c
@@ -1,14 +1,14 @@
 /*-
  *   BSD LICENSE
- * 
+ *
  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
  *   Copyright(c) 2012-2013 6WIND S.A.
  *   All rights reserved.
- * 
+ *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
- * 
+ *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
@@ -18,7 +18,7 @@
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
@@ -47,7 +47,6 @@
 #include <rte_common.h>
 #include <rte_log.h>
 #include <rte_cycles.h>
-#include <rte_tailq.h>
 #include <rte_memory.h>
 #include <rte_memzone.h>
 #include <rte_eal.h>
@@ -71,8 +70,6 @@ static uint64_t eal_tsc_resolution_hz = 0;
 /* General capabilities register */
 #define CLK_PERIOD_SHIFT     32 /* Clock period shift. */
 #define CLK_PERIOD_MASK      0xffffffff00000000ULL /* Clock period mask. */
-#define COUNT_SIZE_CAP_SHIFT 13 /* Count size capa. shift. */
-#define COUNT_SIZE_CAP_MASK 0x0000000000002000ULL /* Count size capa. mask. */
 
 /**
  * HPET timer registers. From the Intel IA-PC HPET (High Precision Event
@@ -278,35 +275,6 @@ check_tsc_flags(void)
 	fclose(stream);
 }
 
-static int
-set_tsc_freq_from_cpuinfo(void)
-{
-	char line[256];
-	FILE *stream;
-	double dmhz;
-
-	stream = fopen("/proc/cpuinfo", "r");
-	if (!stream) {
-		RTE_LOG(WARNING, EAL, "WARNING: Unable to open /proc/cpuinfo\n");
-		return -1;
-	}
-
-	while (fgets(line, sizeof line, stream)) {
-		if (sscanf(line, "cpu MHz\t: %lf", &dmhz) == 1) {
-			eal_tsc_resolution_hz = (uint64_t)(dmhz * 1000000UL);
-			break;
-		}
-	}
-
-	fclose(stream);
-
-	if (!eal_tsc_resolution_hz) {
-		RTE_LOG(WARNING, EAL, "WARNING: Cannot read CPU clock from cpuinfo\n");
-		return -1;
-	}
-	return 0;
-}
-
 static int
 set_tsc_freq_from_clock(void)
 {
@@ -355,9 +323,8 @@ set_tsc_freq_fallback(void)
 static void
 set_tsc_freq(void)
 {
-	if (set_tsc_freq_from_cpuinfo() < 0 &&
-	    set_tsc_freq_from_clock() < 0)
-	    set_tsc_freq_fallback();
+	if (set_tsc_freq_from_clock() < 0)
+		set_tsc_freq_fallback();
 
 	RTE_LOG(INFO, EAL, "TSC frequency is ~%"PRIu64" KHz\n",
 			eal_tsc_resolution_hz/1000);