X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=lib%2Flibrte_pmd_e1000%2Figb_ethdev.c;h=77244e60c1ac51381a16ca6c1d16617373afd18e;hb=e9d48c0072d36eb6423b45fba4ec49d0def6c36f;hp=a2727adcc22e4ad3e8757a2ac89201e36dc0d5c1;hpb=b967915a0380a418f2716c6dae3f64ed3d844636;p=dpdk.git

diff --git a/lib/librte_pmd_e1000/igb_ethdev.c b/lib/librte_pmd_e1000/igb_ethdev.c
index a2727adcc2..77244e60c1 100644
--- a/lib/librte_pmd_e1000/igb_ethdev.c
+++ b/lib/librte_pmd_e1000/igb_ethdev.c
@@ -1,7 +1,7 @@
 /*-
  *   BSD LICENSE
  * 
- *   Copyright(c) 2010-2013 Intel Corporation. All rights reserved.
+ *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
  *   All rights reserved.
  * 
  *   Redistribution and use in source and binary forms, with or without
@@ -471,6 +471,18 @@ eth_igbvf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
 	PMD_INIT_LOG(DEBUG, "eth_igbvf_dev_init");
 
 	eth_dev->dev_ops = &igbvf_eth_dev_ops;
+	eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
+	eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
+
+	/* for secondary processes, we don't initialise any further as primary
+	 * has already done this work. Only check we don't need a different
+	 * RX function */
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY){
+		if (eth_dev->data->scattered_rx)
+			eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
+		return 0;
+	}
+
 	pci_dev = eth_dev->pci_dev;
 
 	hw->device_id = pci_dev->id.device_id;
@@ -551,6 +563,17 @@ rte_igb_pmd_init(void)
 	return 0;
 }
 
+static void
+igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
+{
+	struct e1000_hw *hw =
+		E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	/* RCTL: enable VLAN filter since VMDq always use VLAN filter */
+	uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
+	rctl |= E1000_RCTL_VFE;
+	E1000_WRITE_REG(hw, E1000_RCTL, rctl);
+}
+
 /*
  * VF Driver initialization routine.
  * Invoked one at EAL init time.
@@ -647,6 +670,11 @@ eth_igb_start(struct rte_eth_dev *dev)
 			ETH_VLAN_EXTEND_MASK;
 	eth_igb_vlan_offload_set(dev, mask);
 
+	if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
+		/* Enable VLAN filter since VMDq always use VLAN filter */
+		igb_vmdq_vlan_hw_filter_enable(dev);
+	}
+		
 	/*
 	 * Configure the Interrupt Moderation register (EITR) with the maximum
 	 * possible value (0xFFFF) to minimize "System Partial Write" issued by
@@ -1106,19 +1134,28 @@ eth_igb_infos_get(struct rte_eth_dev *dev,
 	case e1000_82575:
 		dev_info->max_rx_queues = 4;
 		dev_info->max_tx_queues = 4;
+		dev_info->max_vmdq_pools = 0;
 		break;
 
 	case e1000_82576:
 		dev_info->max_rx_queues = 16;
 		dev_info->max_tx_queues = 16;
+		dev_info->max_vmdq_pools = ETH_8_POOLS;
 		break;
 
 	case e1000_82580:
 		dev_info->max_rx_queues = 8;
 		dev_info->max_tx_queues = 8;
+		dev_info->max_vmdq_pools = ETH_8_POOLS;
 		break;
 
 	case e1000_i350:
+		dev_info->max_rx_queues = 8;
+		dev_info->max_tx_queues = 8;
+		dev_info->max_vmdq_pools = ETH_8_POOLS;
+		break;
+
+	case e1000_i354:
 		dev_info->max_rx_queues = 8;
 		dev_info->max_tx_queues = 8;
 		break;
@@ -1126,22 +1163,26 @@ eth_igb_infos_get(struct rte_eth_dev *dev,
 	case e1000_i210:
 		dev_info->max_rx_queues = 4;
 		dev_info->max_tx_queues = 4;
+		dev_info->max_vmdq_pools = 0;
 		break;
 
 	case e1000_vfadapt:
 		dev_info->max_rx_queues = 2;
 		dev_info->max_tx_queues = 2;
+		dev_info->max_vmdq_pools = 0;
 		break;
 
 	case e1000_vfadapt_i350:
 		dev_info->max_rx_queues = 1;
 		dev_info->max_tx_queues = 1;
+		dev_info->max_vmdq_pools = 0;
 		break;
 
 	default:
 		/* Should not happen */
 		dev_info->max_rx_queues = 0;
 		dev_info->max_tx_queues = 0;
+		dev_info->max_vmdq_pools = 0;
 	}
 }
 
@@ -1686,6 +1727,7 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 	};
 	uint32_t rx_buf_size;
 	uint32_t max_high_water;
+	uint32_t rctl;
 
 	hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	rx_buf_size = igb_get_rx_buffer_size(hw);
@@ -1708,6 +1750,21 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
 
 	err = e1000_setup_link_generic(hw);
 	if (err == E1000_SUCCESS) {
+
+		/* check if we want to forward MAC frames - driver doesn't have native
+		 * capability to do that, so we'll write the registers ourselves */
+
+		rctl = E1000_READ_REG(hw, E1000_RCTL);
+
+		/* set or clear MFLCN.PMCF bit depending on configuration */
+		if (fc_conf->mac_ctrl_frame_fwd != 0)
+			rctl |= E1000_RCTL_PMCF;
+		else
+			rctl &= ~E1000_RCTL_PMCF;
+
+		E1000_WRITE_REG(hw, E1000_RCTL, rctl);
+		E1000_WRITE_FLUSH(hw);
+
 		return 0;
 	}