From e290ccf8c6b0ce99c4642123e7693112a51e4246 Mon Sep 17 00:00:00 2001 From: Rasesh Mody Date: Sat, 29 Sep 2018 08:14:35 +0000 Subject: [PATCH] net/qede/base: add RL update params Add 'rl_bc_stage_th','rl_timer_stage_th' and 'dcqcn_reset_alpha_on_idle' to RL update param as well as logs. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/ecore_sp_commands.c | 8 +++++++- drivers/net/qede/base/ecore_sp_commands.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c index b43baf9d0c..49a5ff5523 100644 --- a/drivers/net/qede/base/ecore_sp_commands.c +++ b/drivers/net/qede/base/ecore_sp_commands.c @@ -515,6 +515,10 @@ enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn, rl_update->rl_id_first = params->rl_id_first; rl_update->rl_id_last = params->rl_id_last; rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg; + rl_update->dcqcn_reset_alpha_on_idle = + params->dcqcn_reset_alpha_on_idle; + rl_update->rl_bc_stage_th = params->rl_bc_stage_th; + rl_update->rl_timer_stage_th = params->rl_timer_stage_th; rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate); rl_update->rl_max_rate = OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_max_rate)); @@ -529,12 +533,14 @@ enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn, OSAL_CPU_TO_LE32(params->dcqcn_timeuot_us); rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us); - DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n", + DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x,dcqcn_reset_alpha_on_idle %x, rl_bc_stage_th %x, rl_timer_stage_th %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n", rl_update->qcn_update_param_flg, rl_update->dcqcn_update_param_flg, rl_update->rl_init_flg, rl_update->rl_start_flg, rl_update->rl_stop_flg, rl_update->rl_id_first, rl_update->rl_id_last, rl_update->rl_dc_qcn_flg, + rl_update->dcqcn_reset_alpha_on_idle, + rl_update->rl_bc_stage_th, rl_update->rl_timer_stage_th, rl_update->rl_bc_rate, rl_update->rl_max_rate, rl_update->rl_r_ai, rl_update->rl_r_hai, rl_update->dcqcn_g, rl_update->dcqcn_k_us, diff --git a/drivers/net/qede/base/ecore_sp_commands.h b/drivers/net/qede/base/ecore_sp_commands.h index e57414cfc5..524fe57a14 100644 --- a/drivers/net/qede/base/ecore_sp_commands.h +++ b/drivers/net/qede/base/ecore_sp_commands.h @@ -119,6 +119,9 @@ struct ecore_rl_update_params { u8 rl_stop_flg; u8 rl_id_first; u8 rl_id_last; + u8 dcqcn_reset_alpha_on_idle; + u8 rl_bc_stage_th; + u8 rl_timer_stage_th; u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */ u32 rl_bc_rate; /* Byte Counter Limit */ u32 rl_max_rate; /* Maximum rate in Mbps resolution */ -- 2.20.1