/* * Copyright Droids Corporation, Microb Technology, Eirbot (2009) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * Revision : $Id $ * */ /* WARNING : this file is automatically generated by scripts. * You should not edit it. If you find something wrong in it, * write to zer0@droids-corp.org */ /* prescalers timer 0 */ #define TIMER0_PRESCALER_DIV_0 0 #define TIMER0_PRESCALER_DIV_1 1 #define TIMER0_PRESCALER_DIV_8 2 #define TIMER0_PRESCALER_DIV_64 3 #define TIMER0_PRESCALER_DIV_256 4 #define TIMER0_PRESCALER_DIV_1024 5 #define TIMER0_PRESCALER_DIV_FALL 6 #define TIMER0_PRESCALER_DIV_RISE 7 #define TIMER0_PRESCALER_REG_0 0 #define TIMER0_PRESCALER_REG_1 1 #define TIMER0_PRESCALER_REG_2 8 #define TIMER0_PRESCALER_REG_3 64 #define TIMER0_PRESCALER_REG_4 256 #define TIMER0_PRESCALER_REG_5 1024 #define TIMER0_PRESCALER_REG_6 -1 #define TIMER0_PRESCALER_REG_7 -2 /* prescalers timer 1 */ #define TIMER1_PRESCALER_DIV_0 0 #define TIMER1_PRESCALER_DIV_1 1 #define TIMER1_PRESCALER_DIV_8 2 #define TIMER1_PRESCALER_DIV_64 3 #define TIMER1_PRESCALER_DIV_256 4 #define TIMER1_PRESCALER_DIV_1024 5 #define TIMER1_PRESCALER_DIV_FALL 6 #define TIMER1_PRESCALER_DIV_RISE 7 #define TIMER1_PRESCALER_REG_0 0 #define TIMER1_PRESCALER_REG_1 1 #define TIMER1_PRESCALER_REG_2 8 #define TIMER1_PRESCALER_REG_3 64 #define TIMER1_PRESCALER_REG_4 256 #define TIMER1_PRESCALER_REG_5 1024 #define TIMER1_PRESCALER_REG_6 -1 #define TIMER1_PRESCALER_REG_7 -2 /* prescalers timer 2 */ #define TIMER2_PRESCALER_DIV_0 0 #define TIMER2_PRESCALER_DIV_1 1 #define TIMER2_PRESCALER_DIV_8 2 #define TIMER2_PRESCALER_DIV_32 3 #define TIMER2_PRESCALER_DIV_64 4 #define TIMER2_PRESCALER_DIV_128 5 #define TIMER2_PRESCALER_DIV_256 6 #define TIMER2_PRESCALER_DIV_1024 7 #define TIMER2_PRESCALER_REG_0 0 #define TIMER2_PRESCALER_REG_1 1 #define TIMER2_PRESCALER_REG_2 8 #define TIMER2_PRESCALER_REG_3 32 #define TIMER2_PRESCALER_REG_4 64 #define TIMER2_PRESCALER_REG_5 128 #define TIMER2_PRESCALER_REG_6 256 #define TIMER2_PRESCALER_REG_7 1024 /* prescalers timer 3 */ #define TIMER3_PRESCALER_DIV_0 0 #define TIMER3_PRESCALER_DIV_1 1 #define TIMER3_PRESCALER_DIV_8 2 #define TIMER3_PRESCALER_DIV_64 3 #define TIMER3_PRESCALER_DIV_256 4 #define TIMER3_PRESCALER_DIV_1024 5 #define TIMER3_PRESCALER_DIV_FALL 6 #define TIMER3_PRESCALER_DIV_RISE 7 #define TIMER3_PRESCALER_REG_0 0 #define TIMER3_PRESCALER_REG_1 1 #define TIMER3_PRESCALER_REG_2 8 #define TIMER3_PRESCALER_REG_3 64 #define TIMER3_PRESCALER_REG_4 256 #define TIMER3_PRESCALER_REG_5 1024 #define TIMER3_PRESCALER_REG_6 -1 #define TIMER3_PRESCALER_REG_7 -2 /* prescalers timer 4 */ #define TIMER4_PRESCALER_DIV_0 0 #define TIMER4_PRESCALER_DIV_1 1 #define TIMER4_PRESCALER_DIV_8 2 #define TIMER4_PRESCALER_DIV_64 3 #define TIMER4_PRESCALER_DIV_256 4 #define TIMER4_PRESCALER_DIV_1024 5 #define TIMER4_PRESCALER_DIV_FALL 6 #define TIMER4_PRESCALER_DIV_RISE 7 #define TIMER4_PRESCALER_REG_0 0 #define TIMER4_PRESCALER_REG_1 1 #define TIMER4_PRESCALER_REG_2 8 #define TIMER4_PRESCALER_REG_3 64 #define TIMER4_PRESCALER_REG_4 256 #define TIMER4_PRESCALER_REG_5 1024 #define TIMER4_PRESCALER_REG_6 -1 #define TIMER4_PRESCALER_REG_7 -2 /* prescalers timer 5 */ #define TIMER5_PRESCALER_DIV_0 0 #define TIMER5_PRESCALER_DIV_1 1 #define TIMER5_PRESCALER_DIV_8 2 #define TIMER5_PRESCALER_DIV_64 3 #define TIMER5_PRESCALER_DIV_256 4 #define TIMER5_PRESCALER_DIV_1024 5 #define TIMER5_PRESCALER_DIV_FALL 6 #define TIMER5_PRESCALER_DIV_RISE 7 #define TIMER5_PRESCALER_REG_0 0 #define TIMER5_PRESCALER_REG_1 1 #define TIMER5_PRESCALER_REG_2 8 #define TIMER5_PRESCALER_REG_3 64 #define TIMER5_PRESCALER_REG_4 256 #define TIMER5_PRESCALER_REG_5 1024 #define TIMER5_PRESCALER_REG_6 -1 #define TIMER5_PRESCALER_REG_7 -2 /* available timers */ #define TIMER0_AVAILABLE #define TIMER0A_AVAILABLE #define TIMER0B_AVAILABLE #define TIMER1_AVAILABLE #define TIMER1A_AVAILABLE #define TIMER1B_AVAILABLE #define TIMER1C_AVAILABLE #define TIMER2_AVAILABLE #define TIMER2A_AVAILABLE #define TIMER2B_AVAILABLE #define TIMER3_AVAILABLE #define TIMER3A_AVAILABLE #define TIMER3B_AVAILABLE #define TIMER3C_AVAILABLE #define TIMER4_AVAILABLE #define TIMER4A_AVAILABLE #define TIMER4B_AVAILABLE #define TIMER4C_AVAILABLE #define TIMER5_AVAILABLE #define TIMER5A_AVAILABLE #define TIMER5B_AVAILABLE #define TIMER5C_AVAILABLE /* overflow interrupt number */ #define SIG_OVERFLOW0_NUM 0 #define SIG_OVERFLOW1_NUM 1 #define SIG_OVERFLOW2_NUM 2 #define SIG_OVERFLOW3_NUM 3 #define SIG_OVERFLOW4_NUM 4 #define SIG_OVERFLOW5_NUM 5 #define SIG_OVERFLOW_TOTAL_NUM 6 /* output compare interrupt number */ #define SIG_OUTPUT_COMPARE0A_NUM 0 #define SIG_OUTPUT_COMPARE0B_NUM 1 #define SIG_OUTPUT_COMPARE1A_NUM 2 #define SIG_OUTPUT_COMPARE1B_NUM 3 #define SIG_OUTPUT_COMPARE1C_NUM 4 #define SIG_OUTPUT_COMPARE2A_NUM 5 #define SIG_OUTPUT_COMPARE2B_NUM 6 #define SIG_OUTPUT_COMPARE3A_NUM 7 #define SIG_OUTPUT_COMPARE3B_NUM 8 #define SIG_OUTPUT_COMPARE3C_NUM 9 #define SIG_OUTPUT_COMPARE4A_NUM 10 #define SIG_OUTPUT_COMPARE4B_NUM 11 #define SIG_OUTPUT_COMPARE4C_NUM 12 #define SIG_OUTPUT_COMPARE5A_NUM 13 #define SIG_OUTPUT_COMPARE5B_NUM 14 #define SIG_OUTPUT_COMPARE5C_NUM 15 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 16 /* Pwm nums */ #define PWM0A_NUM 0 #define PWM0B_NUM 1 #define PWM1A_NUM 2 #define PWM1B_NUM 3 #define PWM1C_NUM 4 #define PWM2A_NUM 5 #define PWM2B_NUM 6 #define PWM3A_NUM 7 #define PWM3B_NUM 8 #define PWM3C_NUM 9 #define PWM4A_NUM 10 #define PWM4B_NUM 11 #define PWM4C_NUM 12 #define PWM5A_NUM 13 #define PWM5B_NUM 14 #define PWM5C_NUM 15 #define PWM_TOTAL_NUM 16 /* input capture interrupt number */ #define SIG_INPUT_CAPTURE1_NUM 0 #define SIG_INPUT_CAPTURE3_NUM 1 #define SIG_INPUT_CAPTURE4_NUM 2 #define SIG_INPUT_CAPTURE5_NUM 3 #define SIG_INPUT_CAPTURE_TOTAL_NUM 4 /* OCR0A */ #define OCROA_0_REG OCR0A #define OCROA_1_REG OCR0A #define OCROA_2_REG OCR0A #define OCROA_3_REG OCR0A #define OCROA_4_REG OCR0A #define OCROA_5_REG OCR0A #define OCROA_6_REG OCR0A #define OCROA_7_REG OCR0A /* ADMUX */ #define MUX0_REG ADMUX #define MUX1_REG ADMUX #define MUX2_REG ADMUX #define MUX3_REG ADMUX #define MUX4_REG ADMUX #define ADLAR_REG ADMUX #define REFS0_REG ADMUX #define REFS1_REG ADMUX /* WDTCSR */ #define WDP0_REG WDTCSR #define WDP1_REG WDTCSR #define WDP2_REG WDTCSR #define WDE_REG WDTCSR #define WDCE_REG WDTCSR #define WDP3_REG WDTCSR #define WDIE_REG WDTCSR #define WDIF_REG WDTCSR /* EEDR */ #define EEDR0_REG EEDR #define EEDR1_REG EEDR #define EEDR2_REG EEDR #define EEDR3_REG EEDR #define EEDR4_REG EEDR #define EEDR5_REG EEDR #define EEDR6_REG EEDR #define EEDR7_REG EEDR /* ACSR */ #define ACIS0_REG ACSR #define ACIS1_REG ACSR #define ACIC_REG ACSR #define ACIE_REG ACSR #define ACI_REG ACSR #define ACO_REG ACSR #define ACBG_REG ACSR #define ACD_REG ACSR /* RAMPZ */ #define RAMPZ0_REG RAMPZ #define RAMPZ1_REG RAMPZ /* OCR2B */ #define OCR2B_0_REG OCR2B #define OCR2B_1_REG OCR2B #define OCR2B_2_REG OCR2B #define OCR2B_3_REG OCR2B #define OCR2B_4_REG OCR2B #define OCR2B_5_REG OCR2B #define OCR2B_6_REG OCR2B #define OCR2B_7_REG OCR2B /* OCR2A */ #define OCR2A_0_REG OCR2A #define OCR2A_1_REG OCR2A #define OCR2A_2_REG OCR2A #define OCR2A_3_REG OCR2A #define OCR2A_4_REG OCR2A #define OCR2A_5_REG OCR2A #define OCR2A_6_REG OCR2A #define OCR2A_7_REG OCR2A /* SPDR */ #define SPDR0_REG SPDR #define SPDR1_REG SPDR #define SPDR2_REG SPDR #define SPDR3_REG SPDR #define SPDR4_REG SPDR #define SPDR5_REG SPDR #define SPDR6_REG SPDR #define SPDR7_REG SPDR /* SPSR */ #define SPI2X_REG SPSR #define WCOL_REG SPSR #define SPIF_REG SPSR /* ICR1H */ #define ICR1H0_REG ICR1H #define ICR1H1_REG ICR1H #define ICR1H2_REG ICR1H #define ICR1H3_REG ICR1H #define ICR1H4_REG ICR1H #define ICR1H5_REG ICR1H #define ICR1H6_REG ICR1H #define ICR1H7_REG ICR1H /* ICR1L */ #define ICR1L0_REG ICR1L #define ICR1L1_REG ICR1L #define ICR1L2_REG ICR1L #define ICR1L3_REG ICR1L #define ICR1L4_REG ICR1L #define ICR1L5_REG ICR1L #define ICR1L6_REG ICR1L #define ICR1L7_REG ICR1L /* EEARH */ #define EEAR8_REG EEARH #define EEAR9_REG EEARH #define EEAR10_REG EEARH #define EEAR11_REG EEARH /* TCNT1L */ #define TCNT1L0_REG TCNT1L #define TCNT1L1_REG TCNT1L #define TCNT1L2_REG TCNT1L #define TCNT1L3_REG TCNT1L #define TCNT1L4_REG TCNT1L #define TCNT1L5_REG TCNT1L #define TCNT1L6_REG TCNT1L #define TCNT1L7_REG TCNT1L /* PORTG */ #define PORTG0_REG PORTG #define PORTG1_REG PORTG #define PORTG2_REG PORTG #define PORTG3_REG PORTG #define PORTG4_REG PORTG #define PORTG5_REG PORTG /* UCSR0C */ #define UCPOL0_REG UCSR0C #define UCSZ00_REG UCSR0C #define UCSZ01_REG UCSR0C #define USBS0_REG UCSR0C #define UPM00_REG UCSR0C #define UPM01_REG UCSR0C #define UMSEL00_REG UCSR0C #define UMSEL01_REG UCSR0C /* UCSR0B */ #define TXB80_REG UCSR0B #define RXB80_REG UCSR0B #define UCSZ02_REG UCSR0B #define TXEN0_REG UCSR0B #define RXEN0_REG UCSR0B #define UDRIE0_REG UCSR0B #define TXCIE0_REG UCSR0B #define RXCIE0_REG UCSR0B /* TCNT1H */ #define TCNT1H0_REG TCNT1H #define TCNT1H1_REG TCNT1H #define TCNT1H2_REG TCNT1H #define TCNT1H3_REG TCNT1H #define TCNT1H4_REG TCNT1H #define TCNT1H5_REG TCNT1H #define TCNT1H6_REG TCNT1H #define TCNT1H7_REG TCNT1H /* PORTC */ #define PORTC0_REG PORTC #define PORTC1_REG PORTC #define PORTC2_REG PORTC #define PORTC3_REG PORTC #define PORTC4_REG PORTC #define PORTC5_REG PORTC #define PORTC6_REG PORTC #define PORTC7_REG PORTC /* PORTA */ #define PORTA0_REG PORTA #define PORTA1_REG PORTA #define PORTA2_REG PORTA #define PORTA3_REG PORTA #define PORTA4_REG PORTA #define PORTA5_REG PORTA #define PORTA6_REG PORTA #define PORTA7_REG PORTA /* GPIOR1 */ #define GPIOR10_REG GPIOR1 #define GPIOR11_REG GPIOR1 #define GPIOR12_REG GPIOR1 #define GPIOR13_REG GPIOR1 #define GPIOR14_REG GPIOR1 #define GPIOR15_REG GPIOR1 #define GPIOR16_REG GPIOR1 #define GPIOR17_REG GPIOR1 /* EIMSK */ #define INT0_REG EIMSK #define INT1_REG EIMSK #define INT2_REG EIMSK #define INT3_REG EIMSK #define INT4_REG EIMSK #define INT5_REG EIMSK #define INT6_REG EIMSK #define INT7_REG EIMSK /* UDR1 */ #define UDR1_0_REG UDR1 #define UDR1_1_REG UDR1 #define UDR1_2_REG UDR1 #define UDR1_3_REG UDR1 #define UDR1_4_REG UDR1 #define UDR1_5_REG UDR1 #define UDR1_6_REG UDR1 #define UDR1_7_REG UDR1 /* UDR0 */ #define UDR0_0_REG UDR0 #define UDR0_1_REG UDR0 #define UDR0_2_REG UDR0 #define UDR0_3_REG UDR0 #define UDR0_4_REG UDR0 #define UDR0_5_REG UDR0 #define UDR0_6_REG UDR0 #define UDR0_7_REG UDR0 /* EICRB */ #define ISC40_REG EICRB #define ISC41_REG EICRB #define ISC50_REG EICRB #define ISC51_REG EICRB #define ISC60_REG EICRB #define ISC61_REG EICRB #define ISC70_REG EICRB #define ISC71_REG EICRB /* EICRA */ #define ISC00_REG EICRA #define ISC01_REG EICRA #define ISC10_REG EICRA #define ISC11_REG EICRA #define ISC20_REG EICRA #define ISC21_REG EICRA #define ISC30_REG EICRA #define ISC31_REG EICRA /* DIDR0 */ #define ADC0D_REG DIDR0 #define ADC1D_REG DIDR0 #define ADC2D_REG DIDR0 #define ADC3D_REG DIDR0 #define ADC4D_REG DIDR0 #define ADC5D_REG DIDR0 #define ADC6D_REG DIDR0 #define ADC7D_REG DIDR0 /* DIDR1 */ #define AIN0D_REG DIDR1 #define AIN1D_REG DIDR1 /* DIDR2 */ #define ADC8D_REG DIDR2 #define ADC9D_REG DIDR2 #define ADC10D_REG DIDR2 #define ADC11D_REG DIDR2 #define ADC12D_REG DIDR2 #define ADC13D_REG DIDR2 #define ADC14D_REG DIDR2 #define ADC15D_REG DIDR2 /* DDRF */ #define DDF0_REG DDRF #define DDF1_REG DDRF #define DDF2_REG DDRF #define DDF3_REG DDRF #define DDF4_REG DDRF #define DDF5_REG DDRF #define DDF6_REG DDRF #define DDF7_REG DDRF /* ASSR */ #define TCR2BUB_REG ASSR #define TCR2AUB_REG ASSR #define OCR2BUB_REG ASSR #define OCR2AUB_REG ASSR #define TCN2UB_REG ASSR #define AS2_REG ASSR #define EXCLK_REG ASSR /* CLKPR */ #define CLKPS0_REG CLKPR #define CLKPS1_REG CLKPR #define CLKPS2_REG CLKPR #define CLKPS3_REG CLKPR #define CLKPCE_REG CLKPR /* OCR0B */ #define OCR0B_0_REG OCR0B #define OCR0B_1_REG OCR0B #define OCR0B_2_REG OCR0B #define OCR0B_3_REG OCR0B #define OCR0B_4_REG OCR0B #define OCR0B_5_REG OCR0B #define OCR0B_6_REG OCR0B #define OCR0B_7_REG OCR0B /* SREG */ #define C_REG SREG #define Z_REG SREG #define N_REG SREG #define V_REG SREG #define S_REG SREG #define H_REG SREG #define T_REG SREG #define I_REG SREG /* UBRR1L */ #define UBRR_0_REG UBRR1L #define UBRR_1_REG UBRR1L #define UBRR_2_REG UBRR1L #define UBRR_3_REG UBRR1L #define UBRR_4_REG UBRR1L #define UBRR_5_REG UBRR1L #define UBRR_6_REG UBRR1L #define UBRR_7_REG UBRR1L /* DDRC */ #define DDC0_REG DDRC #define DDC1_REG DDRC #define DDC2_REG DDRC #define DDC3_REG DDRC #define DDC4_REG DDRC #define DDC5_REG DDRC #define DDC6_REG DDRC #define DDC7_REG DDRC /* OCR3AL */ #define OCR3AL0_REG OCR3AL #define OCR3AL1_REG OCR3AL #define OCR3AL2_REG OCR3AL #define OCR3AL3_REG OCR3AL #define OCR3AL4_REG OCR3AL #define OCR3AL5_REG OCR3AL #define OCR3AL6_REG OCR3AL #define OCR3AL7_REG OCR3AL /* DDRA */ #define DDA0_REG DDRA #define DDA1_REG DDRA #define DDA2_REG DDRA #define DDA3_REG DDRA #define DDA4_REG DDRA #define DDA5_REG DDRA #define DDA6_REG DDRA #define DDA7_REG DDRA /* UBRR1H */ #define UBRR_8_REG UBRR1H #define UBRR_9_REG UBRR1H #define UBRR_10_REG UBRR1H #define UBRR_11_REG UBRR1H /* DDRG */ #define DDG0_REG DDRG #define DDG1_REG DDRG #define DDG2_REG DDRG #define DDG3_REG DDRG #define DDG4_REG DDRG #define DDG5_REG DDRG /* OCR3AH */ #define OCR3AH0_REG OCR3AH #define OCR3AH1_REG OCR3AH #define OCR3AH2_REG OCR3AH #define OCR3AH3_REG OCR3AH #define OCR3AH4_REG OCR3AH #define OCR3AH5_REG OCR3AH #define OCR3AH6_REG OCR3AH #define OCR3AH7_REG OCR3AH /* TCCR1B */ #define CS10_REG TCCR1B #define CS11_REG TCCR1B #define CS12_REG TCCR1B #define WGM12_REG TCCR1B #define WGM13_REG TCCR1B #define ICES1_REG TCCR1B #define ICNC1_REG TCCR1B /* OSCCAL */ #define CAL0_REG OSCCAL #define CAL1_REG OSCCAL #define CAL2_REG OSCCAL #define CAL3_REG OSCCAL #define CAL4_REG OSCCAL #define CAL5_REG OSCCAL #define CAL6_REG OSCCAL #define CAL7_REG OSCCAL /* DDRD */ #define DDD0_REG DDRD #define DDD1_REG DDRD #define DDD2_REG DDRD #define DDD3_REG DDRD #define DDD4_REG DDRD #define DDD5_REG DDRD #define DDD6_REG DDRD #define DDD7_REG DDRD /* TCNT5H */ #define TCNT5H0_REG TCNT5H #define TCNT5H1_REG TCNT5H #define TCNT5H2_REG TCNT5H #define TCNT5H3_REG TCNT5H #define TCNT5H4_REG TCNT5H #define TCNT5H5_REG TCNT5H #define TCNT5H6_REG TCNT5H #define TCNT5H7_REG TCNT5H /* GPIOR0 */ #define GPIOR00_REG GPIOR0 #define GPIOR01_REG GPIOR0 #define GPIOR02_REG GPIOR0 #define GPIOR03_REG GPIOR0 #define GPIOR04_REG GPIOR0 #define GPIOR05_REG GPIOR0 #define GPIOR06_REG GPIOR0 #define GPIOR07_REG GPIOR0 /* GPIOR2 */ #define GPIOR20_REG GPIOR2 #define GPIOR21_REG GPIOR2 #define GPIOR22_REG GPIOR2 #define GPIOR23_REG GPIOR2 #define GPIOR24_REG GPIOR2 #define GPIOR25_REG GPIOR2 #define GPIOR26_REG GPIOR2 #define GPIOR27_REG GPIOR2 /* TCNT5L */ #define TCNT5L0_REG TCNT5L #define TCNT5L1_REG TCNT5L #define TCNT5L2_REG TCNT5L #define TCNT5L3_REG TCNT5L #define TCNT5L4_REG TCNT5L #define TCNT5L5_REG TCNT5L #define TCNT5L6_REG TCNT5L #define TCNT5L7_REG TCNT5L /* PCICR */ #define PCIE0_REG PCICR #define PCIE1_REG PCICR #define PCIE2_REG PCICR /* TCNT2 */ #define TCNT2_0_REG TCNT2 #define TCNT2_1_REG TCNT2 #define TCNT2_2_REG TCNT2 #define TCNT2_3_REG TCNT2 #define TCNT2_4_REG TCNT2 #define TCNT2_5_REG TCNT2 #define TCNT2_6_REG TCNT2 #define TCNT2_7_REG TCNT2 /* TCNT0 */ #define TCNT0_0_REG TCNT0 #define TCNT0_1_REG TCNT0 #define TCNT0_2_REG TCNT0 #define TCNT0_3_REG TCNT0 #define TCNT0_4_REG TCNT0 #define TCNT0_5_REG TCNT0 #define TCNT0_6_REG TCNT0 #define TCNT0_7_REG TCNT0 /* TWAR */ #define TWGCE_REG TWAR #define TWA0_REG TWAR #define TWA1_REG TWAR #define TWA2_REG TWAR #define TWA3_REG TWAR #define TWA4_REG TWAR #define TWA5_REG TWAR #define TWA6_REG TWAR /* TCCR0B */ #define CS00_REG TCCR0B #define CS01_REG TCCR0B #define CS02_REG TCCR0B #define WGM02_REG TCCR0B #define FOC0B_REG TCCR0B #define FOC0A_REG TCCR0B /* TCCR0A */ #define WGM00_REG TCCR0A #define WGM01_REG TCCR0A #define COM0B0_REG TCCR0A #define COM0B1_REG TCCR0A #define COM0A0_REG TCCR0A #define COM0A1_REG TCCR0A /* TIFR4 */ #define TOV4_REG TIFR4 #define OCF4A_REG TIFR4 #define OCF4B_REG TIFR4 #define OCF4C_REG TIFR4 #define ICF4_REG TIFR4 /* TIFR5 */ #define TOV5_REG TIFR5 #define OCF5A_REG TIFR5 #define OCF5B_REG TIFR5 #define OCF5C_REG TIFR5 #define ICF5_REG TIFR5 /* TIFR2 */ #define TOV2_REG TIFR2 #define OCF2A_REG TIFR2 #define OCF2B_REG TIFR2 /* TIFR3 */ #define TOV3_REG TIFR3 #define OCF3A_REG TIFR3 #define OCF3B_REG TIFR3 #define OCF3C_REG TIFR3 #define ICF3_REG TIFR3 /* SPCR */ #define SPR0_REG SPCR #define SPR1_REG SPCR #define CPHA_REG SPCR #define CPOL_REG SPCR #define MSTR_REG SPCR #define DORD_REG SPCR #define SPE_REG SPCR #define SPIE_REG SPCR /* TIFR1 */ #define TOV1_REG TIFR1 #define OCF1A_REG TIFR1 #define OCF1B_REG TIFR1 #define OCF1C_REG TIFR1 #define ICF1_REG TIFR1 /* OCR4AH */ #define OCR4AH0_REG OCR4AH #define OCR4AH1_REG OCR4AH #define OCR4AH2_REG OCR4AH #define OCR4AH3_REG OCR4AH #define OCR4AH4_REG OCR4AH #define OCR4AH5_REG OCR4AH #define OCR4AH6_REG OCR4AH #define OCR4AH7_REG OCR4AH /* OCR5CH */ #define OCR5CH0_REG OCR5CH #define OCR5CH1_REG OCR5CH #define OCR5CH2_REG OCR5CH #define OCR5CH3_REG OCR5CH #define OCR5CH4_REG OCR5CH #define OCR5CH5_REG OCR5CH #define OCR5CH6_REG OCR5CH #define OCR5CH7_REG OCR5CH /* OCR4AL */ #define OCR4AL0_REG OCR4AL #define OCR4AL1_REG OCR4AL #define OCR4AL2_REG OCR4AL #define OCR4AL3_REG OCR4AL #define OCR4AL4_REG OCR4AL #define OCR4AL5_REG OCR4AL #define OCR4AL6_REG OCR4AL #define OCR4AL7_REG OCR4AL /* OCR5CL */ #define OCR5CL0_REG OCR5CL #define OCR5CL1_REG OCR5CL #define OCR5CL2_REG OCR5CL #define OCR5CL3_REG OCR5CL #define OCR5CL4_REG OCR5CL #define OCR5CL5_REG OCR5CL #define OCR5CL6_REG OCR5CL #define OCR5CL7_REG OCR5CL /* OCR3CH */ #define OCR3CH0_REG OCR3CH #define OCR3CH1_REG OCR3CH #define OCR3CH2_REG OCR3CH #define OCR3CH3_REG OCR3CH #define OCR3CH4_REG OCR3CH #define OCR3CH5_REG OCR3CH #define OCR3CH6_REG OCR3CH #define OCR3CH7_REG OCR3CH /* OCR3CL */ #define OCR3CL0_REG OCR3CL #define OCR3CL1_REG OCR3CL #define OCR3CL2_REG OCR3CL #define OCR3CL3_REG OCR3CL #define OCR3CL4_REG OCR3CL #define OCR3CL5_REG OCR3CL #define OCR3CL6_REG OCR3CL #define OCR3CL7_REG OCR3CL /* GTCCR */ #define PSRSYNC_REG GTCCR #define TSM_REG GTCCR #define PSRASY_REG GTCCR /* TWBR */ #define TWBR0_REG TWBR #define TWBR1_REG TWBR #define TWBR2_REG TWBR #define TWBR3_REG TWBR #define TWBR4_REG TWBR #define TWBR5_REG TWBR #define TWBR6_REG TWBR #define TWBR7_REG TWBR /* SPH */ #define SP8_REG SPH #define SP9_REG SPH #define SP10_REG SPH #define SP11_REG SPH #define SP12_REG SPH #define SP13_REG SPH #define SP14_REG SPH #define SP15_REG SPH /* TCCR3C */ #define FOC3C_REG TCCR3C #define FOC3B_REG TCCR3C #define FOC3A_REG TCCR3C /* TCCR3B */ #define CS30_REG TCCR3B #define CS31_REG TCCR3B #define CS32_REG TCCR3B #define WGM32_REG TCCR3B #define WGM33_REG TCCR3B #define ICES3_REG TCCR3B #define ICNC3_REG TCCR3B /* TCCR3A */ #define WGM30_REG TCCR3A #define WGM31_REG TCCR3A #define COM3C0_REG TCCR3A #define COM3C1_REG TCCR3A #define COM3B0_REG TCCR3A #define COM3B1_REG TCCR3A #define COM3A0_REG TCCR3A #define COM3A1_REG TCCR3A /* PORTF */ #define PORTF0_REG PORTF #define PORTF1_REG PORTF #define PORTF2_REG PORTF #define PORTF3_REG PORTF #define PORTF4_REG PORTF #define PORTF5_REG PORTF #define PORTF6_REG PORTF #define PORTF7_REG PORTF /* PCMSK1 */ #define PCINT8_REG PCMSK1 #define PCINT9_REG PCMSK1 #define PCINT10_REG PCMSK1 #define PCINT11_REG PCMSK1 #define PCINT12_REG PCMSK1 #define PCINT13_REG PCMSK1 #define PCINT14_REG PCMSK1 #define PCINT15_REG PCMSK1 /* OCR1BL */ #define OCR1BL0_REG OCR1BL #define OCR1BL1_REG OCR1BL #define OCR1BL2_REG OCR1BL #define OCR1BL3_REG OCR1BL #define OCR1BL4_REG OCR1BL #define OCR1BL5_REG OCR1BL #define OCR1BL6_REG OCR1BL #define OCR1BL7_REG OCR1BL /* TCNT3H */ #define TCNT3H0_REG TCNT3H #define TCNT3H1_REG TCNT3H #define TCNT3H2_REG TCNT3H #define TCNT3H3_REG TCNT3H #define TCNT3H4_REG TCNT3H #define TCNT3H5_REG TCNT3H #define TCNT3H6_REG TCNT3H #define TCNT3H7_REG TCNT3H /* OCR1BH */ #define OCR1BH0_REG OCR1BH #define OCR1BH1_REG OCR1BH #define OCR1BH2_REG OCR1BH #define OCR1BH3_REG OCR1BH #define OCR1BH4_REG OCR1BH #define OCR1BH5_REG OCR1BH #define OCR1BH6_REG OCR1BH #define OCR1BH7_REG OCR1BH /* TCNT3L */ #define TCNT3L0_REG TCNT3L #define TCNT3L1_REG TCNT3L #define TCNT3L2_REG TCNT3L #define TCNT3L3_REG TCNT3L #define TCNT3L4_REG TCNT3L #define TCNT3L5_REG TCNT3L #define TCNT3L6_REG TCNT3L #define TCNT3L7_REG TCNT3L /* ICR5L */ #define ICR5L0_REG ICR5L #define ICR5L1_REG ICR5L #define ICR5L2_REG ICR5L #define ICR5L3_REG ICR5L #define ICR5L4_REG ICR5L #define ICR5L5_REG ICR5L #define ICR5L6_REG ICR5L #define ICR5L7_REG ICR5L /* SPL */ #define SP0_REG SPL #define SP1_REG SPL #define SP2_REG SPL #define SP3_REG SPL #define SP4_REG SPL #define SP5_REG SPL #define SP6_REG SPL #define SP7_REG SPL /* ICR5H */ #define ICR5H0_REG ICR5H #define ICR5H1_REG ICR5H #define ICR5H2_REG ICR5H #define ICR5H3_REG ICR5H #define ICR5H4_REG ICR5H #define ICR5H5_REG ICR5H #define ICR5H6_REG ICR5H #define ICR5H7_REG ICR5H /* MCUSR */ #define JTRF_REG MCUSR #define PORF_REG MCUSR #define EXTRF_REG MCUSR #define BORF_REG MCUSR #define WDRF_REG MCUSR /* EECR */ #define EERE_REG EECR #define EEPE_REG EECR #define EEMPE_REG EECR #define EERIE_REG EECR #define EEPM0_REG EECR #define EEPM1_REG EECR /* SMCR */ #define SE_REG SMCR #define SM0_REG SMCR #define SM1_REG SMCR #define SM2_REG SMCR /* TWCR */ #define TWIE_REG TWCR #define TWEN_REG TWCR #define TWWC_REG TWCR #define TWSTO_REG TWCR #define TWSTA_REG TWCR #define TWEA_REG TWCR #define TWINT_REG TWCR /* PCIFR */ #define PCIF0_REG PCIFR #define PCIF1_REG PCIFR #define PCIF2_REG PCIFR /* TCCR2A */ #define WGM20_REG TCCR2A #define WGM21_REG TCCR2A #define COM2B0_REG TCCR2A #define COM2B1_REG TCCR2A #define COM2A0_REG TCCR2A #define COM2A1_REG TCCR2A /* TCCR2B */ #define CS20_REG TCCR2B #define CS21_REG TCCR2B #define CS22_REG TCCR2B #define WGM22_REG TCCR2B #define FOC2B_REG TCCR2B #define FOC2A_REG TCCR2B /* UBRR0H */ #define UBRR8_REG UBRR0H #define UBRR9_REG UBRR0H #define UBRR10_REG UBRR0H #define UBRR11_REG UBRR0H /* PING */ #define PING0_REG PING #define PING1_REG PING #define PING2_REG PING #define PING3_REG PING #define PING4_REG PING #define PING5_REG PING /* UBRR0L */ #define UBRR0_REG UBRR0L #define UBRR1_REG UBRR0L #define UBRR2_REG UBRR0L #define UBRR3_REG UBRR0L #define UBRR4_REG UBRR0L #define UBRR5_REG UBRR0L #define UBRR6_REG UBRR0L #define UBRR7_REG UBRR0L /* TWSR */ #define TWPS0_REG TWSR #define TWPS1_REG TWSR #define TWS3_REG TWSR #define TWS4_REG TWSR #define TWS5_REG TWSR #define TWS6_REG TWSR #define TWS7_REG TWSR /* ICR4H */ #define ICR4H0_REG ICR4H #define ICR4H1_REG ICR4H #define ICR4H2_REG ICR4H #define ICR4H3_REG ICR4H #define ICR4H4_REG ICR4H #define ICR4H5_REG ICR4H #define ICR4H6_REG ICR4H #define ICR4H7_REG ICR4H /* EEARL */ #define EEAR0_REG EEARL #define EEAR1_REG EEARL #define EEAR2_REG EEARL #define EEAR3_REG EEARL #define EEAR4_REG EEARL #define EEAR5_REG EEARL #define EEAR6_REG EEARL #define EEAR7_REG EEARL /* PCMSK2 */ #define PCINT16_REG PCMSK2 #define PCINT17_REG PCMSK2 #define PCINT18_REG PCMSK2 #define PCINT19_REG PCMSK2 #define PCINT20_REG PCMSK2 #define PCINT21_REG PCMSK2 #define PCINT22_REG PCMSK2 #define PCINT23_REG PCMSK2 /* ICR4L */ #define ICR4L0_REG ICR4L #define ICR4L1_REG ICR4L #define ICR4L2_REG ICR4L #define ICR4L3_REG ICR4L #define ICR4L4_REG ICR4L #define ICR4L5_REG ICR4L #define ICR4L6_REG ICR4L #define ICR4L7_REG ICR4L /* MCUCR */ #define JTD_REG MCUCR #define IVCE_REG MCUCR #define IVSEL_REG MCUCR #define PUD_REG MCUCR /* PINC */ #define PINC0_REG PINC #define PINC1_REG PINC #define PINC2_REG PINC #define PINC3_REG PINC #define PINC4_REG PINC #define PINC5_REG PINC #define PINC6_REG PINC #define PINC7_REG PINC /* OCR1CL */ #define OCR1CL0_REG OCR1CL #define OCR1CL1_REG OCR1CL #define OCR1CL2_REG OCR1CL #define OCR1CL3_REG OCR1CL #define OCR1CL4_REG OCR1CL #define OCR1CL5_REG OCR1CL #define OCR1CL6_REG OCR1CL #define OCR1CL7_REG OCR1CL /* TCNT4L */ #define TCNT4L0_REG TCNT4L #define TCNT4L1_REG TCNT4L #define TCNT4L2_REG TCNT4L #define TCNT4L3_REG TCNT4L #define TCNT4L4_REG TCNT4L #define TCNT4L5_REG TCNT4L #define TCNT4L6_REG TCNT4L #define TCNT4L7_REG TCNT4L /* OCR1CH */ #define OCR1CH0_REG OCR1CH #define OCR1CH1_REG OCR1CH #define OCR1CH2_REG OCR1CH #define OCR1CH3_REG OCR1CH #define OCR1CH4_REG OCR1CH #define OCR1CH5_REG OCR1CH #define OCR1CH6_REG OCR1CH #define OCR1CH7_REG OCR1CH /* TCNT4H */ #define TCNT4H0_REG TCNT4H #define TCNT4H1_REG TCNT4H #define TCNT4H2_REG TCNT4H #define TCNT4H3_REG TCNT4H #define TCNT4H4_REG TCNT4H #define TCNT4H5_REG TCNT4H #define TCNT4H6_REG TCNT4H #define TCNT4H7_REG TCNT4H /* OCDR */ #define OCDR0_REG OCDR #define OCDR1_REG OCDR #define OCDR2_REG OCDR #define OCDR3_REG OCDR #define OCDR4_REG OCDR #define OCDR5_REG OCDR #define OCDR6_REG OCDR #define OCDR7_REG OCDR /* PINA */ #define PINA0_REG PINA #define PINA1_REG PINA #define PINA2_REG PINA #define PINA3_REG PINA #define PINA4_REG PINA #define PINA5_REG PINA #define PINA6_REG PINA #define PINA7_REG PINA /* UCSR1B */ #define TXB81_REG UCSR1B #define RXB81_REG UCSR1B #define UCSZ12_REG UCSR1B #define TXEN1_REG UCSR1B #define RXEN1_REG UCSR1B #define UDRIE1_REG UCSR1B #define TXCIE1_REG UCSR1B #define RXCIE1_REG UCSR1B /* UCSR1C */ #define UCPOL1_REG UCSR1C #define UCSZ10_REG UCSR1C #define UCSZ11_REG UCSR1C #define USBS1_REG UCSR1C #define UPM10_REG UCSR1C #define UPM11_REG UCSR1C #define UMSEL10_REG UCSR1C #define UMSEL11_REG UCSR1C /* UCSR1A */ #define MPCM1_REG UCSR1A #define U2X1_REG UCSR1A #define UPE1_REG UCSR1A #define DOR1_REG UCSR1A #define FE1_REG UCSR1A #define UDRE1_REG UCSR1A #define TXC1_REG UCSR1A #define RXC1_REG UCSR1A /* DDRB */ #define DDB0_REG DDRB #define DDB1_REG DDRB #define DDB2_REG DDRB #define DDB3_REG DDRB #define DDB4_REG DDRB #define DDB5_REG DDRB #define DDB6_REG DDRB #define DDB7_REG DDRB /* TWDR */ #define TWD0_REG TWDR #define TWD1_REG TWDR #define TWD2_REG TWDR #define TWD3_REG TWDR #define TWD4_REG TWDR #define TWD5_REG TWDR #define TWD6_REG TWDR #define TWD7_REG TWDR /* TCCR5A */ #define WGM50_REG TCCR5A #define WGM51_REG TCCR5A #define COM5C0_REG TCCR5A #define COM5C1_REG TCCR5A #define COM5B0_REG TCCR5A #define COM5B1_REG TCCR5A #define COM5A0_REG TCCR5A #define COM5A1_REG TCCR5A /* TWAMR */ #define TWAM0_REG TWAMR #define TWAM1_REG TWAMR #define TWAM2_REG TWAMR #define TWAM3_REG TWAMR #define TWAM4_REG TWAMR #define TWAM5_REG TWAMR #define TWAM6_REG TWAMR /* TCCR5C */ #define FOC5C_REG TCCR5C #define FOC5B_REG TCCR5C #define FOC5A_REG TCCR5C /* TCCR5B */ #define CS50_REG TCCR5B #define CS51_REG TCCR5B #define CS52_REG TCCR5B #define WGM52_REG TCCR5B #define WGM53_REG TCCR5B #define ICES5_REG TCCR5B #define ICNC5_REG TCCR5B /* ADCSRA */ #define ADPS0_REG ADCSRA #define ADPS1_REG ADCSRA #define ADPS2_REG ADCSRA #define ADIE_REG ADCSRA #define ADIF_REG ADCSRA #define ADATE_REG ADCSRA #define ADSC_REG ADCSRA #define ADEN_REG ADCSRA /* ADCSRB */ #define ACME_REG ADCSRB #define ADTS0_REG ADCSRB #define ADTS1_REG ADCSRB #define ADTS2_REG ADCSRB #define MUX5_REG ADCSRB /* OCR5AL */ #define OCR5AL0_REG OCR5AL #define OCR5AL1_REG OCR5AL #define OCR5AL2_REG OCR5AL #define OCR5AL3_REG OCR5AL #define OCR5AL4_REG OCR5AL #define OCR5AL5_REG OCR5AL #define OCR5AL6_REG OCR5AL #define OCR5AL7_REG OCR5AL /* TCCR1A */ #define WGM10_REG TCCR1A #define WGM11_REG TCCR1A #define COM1C0_REG TCCR1A #define COM1C1_REG TCCR1A #define COM1B0_REG TCCR1A #define COM1B1_REG TCCR1A #define COM1A0_REG TCCR1A #define COM1A1_REG TCCR1A /* OCR4CH */ #define OCR4CH0_REG OCR4CH #define OCR4CH1_REG OCR4CH #define OCR4CH2_REG OCR4CH #define OCR4CH3_REG OCR4CH #define OCR4CH4_REG OCR4CH #define OCR4CH5_REG OCR4CH #define OCR4CH6_REG OCR4CH #define OCR4CH7_REG OCR4CH /* OCR5AH */ #define OCR5AH0_REG OCR5AH #define OCR5AH1_REG OCR5AH #define OCR5AH2_REG OCR5AH #define OCR5AH3_REG OCR5AH #define OCR5AH4_REG OCR5AH #define OCR5AH5_REG OCR5AH #define OCR5AH6_REG OCR5AH #define OCR5AH7_REG OCR5AH /* OCR4CL */ #define OCR4CL0_REG OCR4CL #define OCR4CL1_REG OCR4CL #define OCR4CL2_REG OCR4CL #define OCR4CL3_REG OCR4CL #define OCR4CL4_REG OCR4CL #define OCR4CL5_REG OCR4CL #define OCR4CL6_REG OCR4CL #define OCR4CL7_REG OCR4CL /* UCSR0A */ #define MPCM0_REG UCSR0A #define U2X0_REG UCSR0A #define UPE0_REG UCSR0A #define DOR0_REG UCSR0A #define FE0_REG UCSR0A #define UDRE0_REG UCSR0A #define TXC0_REG UCSR0A #define RXC0_REG UCSR0A /* TCCR1C */ #define FOC1C_REG TCCR1C #define FOC1B_REG TCCR1C #define FOC1A_REG TCCR1C /* ICR3H */ #define ICR3H0_REG ICR3H #define ICR3H1_REG ICR3H #define ICR3H2_REG ICR3H #define ICR3H3_REG ICR3H #define ICR3H4_REG ICR3H #define ICR3H5_REG ICR3H #define ICR3H6_REG ICR3H #define ICR3H7_REG ICR3H /* DDRE */ #define DDE0_REG DDRE #define DDE1_REG DDRE #define DDE2_REG DDRE #define DDE3_REG DDRE #define DDE4_REG DDRE #define DDE5_REG DDRE #define DDE6_REG DDRE #define DDE7_REG DDRE /* PORTD */ #define PORTD0_REG PORTD #define PORTD1_REG PORTD #define PORTD2_REG PORTD #define PORTD3_REG PORTD #define PORTD4_REG PORTD #define PORTD5_REG PORTD #define PORTD6_REG PORTD #define PORTD7_REG PORTD /* ICR3L */ #define ICR3L0_REG ICR3L #define ICR3L1_REG ICR3L #define ICR3L2_REG ICR3L #define ICR3L3_REG ICR3L #define ICR3L4_REG ICR3L #define ICR3L5_REG ICR3L #define ICR3L6_REG ICR3L #define ICR3L7_REG ICR3L /* PORTE */ #define PORTE0_REG PORTE #define PORTE1_REG PORTE #define PORTE2_REG PORTE #define PORTE3_REG PORTE #define PORTE4_REG PORTE #define PORTE5_REG PORTE #define PORTE6_REG PORTE #define PORTE7_REG PORTE /* SPMCSR */ #define SPMEN_REG SPMCSR #define PGERS_REG SPMCSR #define PGWRT_REG SPMCSR #define BLBSET_REG SPMCSR #define RWWSRE_REG SPMCSR #define SIGRD_REG SPMCSR #define RWWSB_REG SPMCSR #define SPMIE_REG SPMCSR /* PORTB */ #define PORTB0_REG PORTB #define PORTB1_REG PORTB #define PORTB2_REG PORTB #define PORTB3_REG PORTB #define PORTB4_REG PORTB #define PORTB5_REG PORTB #define PORTB6_REG PORTB #define PORTB7_REG PORTB /* ADCL */ #define ADCL0_REG ADCL #define ADCL1_REG ADCL #define ADCL2_REG ADCL #define ADCL3_REG ADCL #define ADCL4_REG ADCL #define ADCL5_REG ADCL #define ADCL6_REG ADCL #define ADCL7_REG ADCL /* ADCH */ #define ADCH0_REG ADCH #define ADCH1_REG ADCH #define ADCH2_REG ADCH #define ADCH3_REG ADCH #define ADCH4_REG ADCH #define ADCH5_REG ADCH #define ADCH6_REG ADCH #define ADCH7_REG ADCH /* OCR5BH */ #define OCR5BH0_REG OCR5BH #define OCR5BH1_REG OCR5BH #define OCR5BH2_REG OCR5BH #define OCR5BH3_REG OCR5BH #define OCR5BH4_REG OCR5BH #define OCR5BH5_REG OCR5BH #define OCR5BH6_REG OCR5BH #define OCR5BH7_REG OCR5BH /* OCR3BL */ #define OCR3BL0_REG OCR3BL #define OCR3BL1_REG OCR3BL #define OCR3BL2_REG OCR3BL #define OCR3BL3_REG OCR3BL #define OCR3BL4_REG OCR3BL #define OCR3BL5_REG OCR3BL #define OCR3BL6_REG OCR3BL #define OCR3BL7_REG OCR3BL /* OCR5BL */ #define OCR5BL0_REG OCR5BL #define OCR5BL1_REG OCR5BL #define OCR5BL2_REG OCR5BL #define OCR5BL3_REG OCR5BL #define OCR5BL4_REG OCR5BL #define OCR5BL5_REG OCR5BL #define OCR5BL6_REG OCR5BL #define OCR5BL7_REG OCR5BL /* OCR3BH */ #define OCR3BH0_REG OCR3BH #define OCR3BH1_REG OCR3BH #define OCR3BH2_REG OCR3BH #define OCR3BH3_REG OCR3BH #define OCR3BH4_REG OCR3BH #define OCR3BH5_REG OCR3BH #define OCR3BH6_REG OCR3BH #define OCR3BH7_REG OCR3BH /* TIMSK2 */ #define TOIE2_REG TIMSK2 #define OCIE2A_REG TIMSK2 #define OCIE2B_REG TIMSK2 /* TIMSK3 */ #define TOIE3_REG TIMSK3 #define OCIE3A_REG TIMSK3 #define OCIE3B_REG TIMSK3 #define OCIE3C_REG TIMSK3 #define ICIE3_REG TIMSK3 /* TIMSK0 */ #define TOIE0_REG TIMSK0 #define OCIE0A_REG TIMSK0 #define OCIE0B_REG TIMSK0 /* TIMSK1 */ #define TOIE1_REG TIMSK1 #define OCIE1A_REG TIMSK1 #define OCIE1B_REG TIMSK1 #define OCIE1C_REG TIMSK1 #define ICIE1_REG TIMSK1 /* TIMSK4 */ #define TOIE4_REG TIMSK4 #define OCIE4A_REG TIMSK4 #define OCIE4B_REG TIMSK4 #define OCIE4C_REG TIMSK4 #define ICIE4_REG TIMSK4 /* TIMSK5 */ #define TOIE5_REG TIMSK5 #define OCIE5A_REG TIMSK5 #define OCIE5B_REG TIMSK5 #define OCIE5C_REG TIMSK5 #define ICIE5_REG TIMSK5 /* TCCR4B */ #define CS40_REG TCCR4B #define CS41_REG TCCR4B #define CS42_REG TCCR4B #define WGM42_REG TCCR4B #define WGM43_REG TCCR4B #define ICES4_REG TCCR4B #define ICNC4_REG TCCR4B /* TCCR4C */ #define FOC4C_REG TCCR4C #define FOC4B_REG TCCR4C #define FOC4A_REG TCCR4C /* TCCR4A */ #define WGM40_REG TCCR4A #define WGM41_REG TCCR4A #define COM4C0_REG TCCR4A #define COM4C1_REG TCCR4A #define COM4B0_REG TCCR4A #define COM4B1_REG TCCR4A #define COM4A0_REG TCCR4A #define COM4A1_REG TCCR4A /* PCMSK0 */ #define PCINT0_REG PCMSK0 #define PCINT1_REG PCMSK0 #define PCINT2_REG PCMSK0 #define PCINT3_REG PCMSK0 #define PCINT4_REG PCMSK0 #define PCINT5_REG PCMSK0 #define PCINT6_REG PCMSK0 #define PCINT7_REG PCMSK0 /* XMCRB */ #define XMM0_REG XMCRB #define XMM1_REG XMCRB #define XMM2_REG XMCRB #define XMBK_REG XMCRB /* XMCRA */ #define SRW00_REG XMCRA #define SRW01_REG XMCRA #define SRW10_REG XMCRA #define SRW11_REG XMCRA #define SRL0_REG XMCRA #define SRL1_REG XMCRA #define SRL2_REG XMCRA #define SRE_REG XMCRA /* OCR4BL */ #define OCR4BL0_REG OCR4BL #define OCR4BL1_REG OCR4BL #define OCR4BL2_REG OCR4BL #define OCR4BL3_REG OCR4BL #define OCR4BL4_REG OCR4BL #define OCR4BL5_REG OCR4BL #define OCR4BL6_REG OCR4BL #define OCR4BL7_REG OCR4BL /* PINB */ #define PINB0_REG PINB #define PINB1_REG PINB #define PINB2_REG PINB #define PINB3_REG PINB #define PINB4_REG PINB #define PINB5_REG PINB #define PINB6_REG PINB #define PINB7_REG PINB /* EIFR */ #define INTF0_REG EIFR #define INTF1_REG EIFR #define INTF2_REG EIFR #define INTF3_REG EIFR #define INTF4_REG EIFR #define INTF5_REG EIFR #define INTF6_REG EIFR #define INTF7_REG EIFR /* OCR4BH */ #define OCR4BH0_REG OCR4BH #define OCR4BH1_REG OCR4BH #define OCR4BH2_REG OCR4BH #define OCR4BH3_REG OCR4BH #define OCR4BH4_REG OCR4BH #define OCR4BH5_REG OCR4BH #define OCR4BH6_REG OCR4BH #define OCR4BH7_REG OCR4BH /* PINF */ #define PINF0_REG PINF #define PINF1_REG PINF #define PINF2_REG PINF #define PINF3_REG PINF #define PINF4_REG PINF #define PINF5_REG PINF #define PINF6_REG PINF #define PINF7_REG PINF /* PINE */ #define PINE0_REG PINE #define PINE1_REG PINE #define PINE2_REG PINE #define PINE3_REG PINE #define PINE4_REG PINE #define PINE5_REG PINE #define PINE6_REG PINE #define PINE7_REG PINE /* PIND */ #define PIND0_REG PIND #define PIND1_REG PIND #define PIND2_REG PIND #define PIND3_REG PIND #define PIND4_REG PIND #define PIND5_REG PIND #define PIND6_REG PIND #define PIND7_REG PIND /* OCR1AH */ #define OCR1AH0_REG OCR1AH #define OCR1AH1_REG OCR1AH #define OCR1AH2_REG OCR1AH #define OCR1AH3_REG OCR1AH #define OCR1AH4_REG OCR1AH #define OCR1AH5_REG OCR1AH #define OCR1AH6_REG OCR1AH #define OCR1AH7_REG OCR1AH /* PRR0 */ #define PRADC_REG PRR0 #define PRUSART0_REG PRR0 #define PRSPI_REG PRR0 #define PRTIM1_REG PRR0 #define PRTIM0_REG PRR0 #define PRTIM2_REG PRR0 #define PRTWI_REG PRR0 /* OCR1AL */ #define OCR1AL0_REG OCR1AL #define OCR1AL1_REG OCR1AL #define OCR1AL2_REG OCR1AL #define OCR1AL3_REG OCR1AL #define OCR1AL4_REG OCR1AL #define OCR1AL5_REG OCR1AL #define OCR1AL6_REG OCR1AL #define OCR1AL7_REG OCR1AL /* TIFR0 */ #define TOV0_REG TIFR0 #define OCF0A_REG TIFR0 #define OCF0B_REG TIFR0 /* PRR1 */ #define PRUSART1_REG PRR1 #define PRUSART2_REG PRR1 #define PRUSART3_REG PRR1 #define PRTIM3_REG PRR1 #define PRTIM4_REG PRR1 #define PRTIM5_REG PRR1 /* pins mapping */ #define AD0_PORT PORTA #define AD0_BIT 0 #define AD1_PORT PORTA #define AD1_BIT 1 #define AD2_PORT PORTA #define AD2_BIT 2 #define AD3_PORT PORTA #define AD3_BIT 3 #define AD4_PORT PORTA #define AD4_BIT 4 #define AD5_PORT PORTA #define AD5_BIT 5 #define AD6_PORT PORTA #define AD6_BIT 6 #define AD7_PORT PORTA #define AD7_BIT 7 #define SS_PORT PORTB #define SS_BIT 0 #define PCINT0_PORT PORTB #define PCINT0_BIT 0 #define SCK_PORT PORTB #define SCK_BIT 1 #define PCINT1_PORT PORTB #define PCINT1_BIT 1 #define MOSI_PORT PORTB #define MOSI_BIT 2 #define PCINT2_PORT PORTB #define PCINT2_BIT 2 #define MISO_PORT PORTB #define MISO_BIT 3 #define PCINT3_PORT PORTB #define PCINT3_BIT 3 #define OC2_PORT PORTB #define OC2_BIT 4 #define PCINT4_PORT PORTB #define PCINT4_BIT 4 #define OC1A_PORT PORTB #define OC1A_BIT 5 #define PCINT5_PORT PORTB #define PCINT5_BIT 5 #define OC1B_PORT PORTB #define OC1B_BIT 6 #define PCINT6_PORT PORTB #define PCINT6_BIT 6 #define OC0A_PORT PORTB #define OC0A_BIT 7 #define OC1C_PORT PORTB #define OC1C_BIT 7 #define PCINT7_PORT PORTB #define PCINT7_BIT 7 #define A8_PORT PORTC #define A8_BIT 0 #define A9_PORT PORTC #define A9_BIT 1 #define A10_PORT PORTC #define A10_BIT 2 #define A11_PORT PORTC #define A11_BIT 3 #define A12_PORT PORTC #define A12_BIT 4 #define A13_PORT PORTC #define A13_BIT 5 #define A14_PORT PORTC #define A14_BIT 6 #define A15_PORT PORTC #define A15_BIT 7 #define SCL_PORT PORTD #define SCL_BIT 0 #define INT0_PORT PORTD #define INT0_BIT 0 #define SDA_PORT PORTD #define SDA_BIT 1 #define INT1_PORT PORTD #define INT1_BIT 1 #define RXD1_PORT PORTD #define RXD1_BIT 2 #define INT2_PORT PORTD #define INT2_BIT 2 #define TXD1_PORT PORTD #define TXD1_BIT 3 #define INT3_PORT PORTD #define INT3_BIT 3 #define ICP1_PORT PORTD #define ICP1_BIT 4 #define XCK1_PORT PORTD #define XCK1_BIT 5 #define T1_PORT PORTD #define T1_BIT 6 #define T0_PORT PORTD #define T0_BIT 7 #define RXD0_PORT PORTE #define RXD0_BIT 0 #define PDI_PORT PORTE #define PDI_BIT 0 #define PCINT8_PORT PORTE #define PCINT8_BIT 0 #define TXD0_PORT PORTE #define TXD0_BIT 1 #define PDO_PORT PORTE #define PDO_BIT 1 #define XCK0_PORT PORTE #define XCK0_BIT 2 #define AIN0_PORT PORTE #define AIN0_BIT 2 #define OC3A_PORT PORTE #define OC3A_BIT 3 #define AIN1_PORT PORTE #define AIN1_BIT 3 #define OC3B_PORT PORTE #define OC3B_BIT 4 #define INT4_PORT PORTE #define INT4_BIT 4 #define OC3C_PORT PORTE #define OC3C_BIT 5 #define INT5_PORT PORTE #define INT5_BIT 5 #define T3_PORT PORTE #define T3_BIT 6 #define INT6_PORT PORTE #define INT6_BIT 6 #define ICP3_PORT PORTE #define ICP3_BIT 7 #define INT7_PORT PORTE #define INT7_BIT 7 #define CLKO_PORT PORTE #define CLKO_BIT 7 #define ADC0_PORT PORTF #define ADC0_BIT 0 #define ADC1_PORT PORTF #define ADC1_BIT 1 #define ADC2_PORT PORTF #define ADC2_BIT 2 #define ADC3_PORT PORTF #define ADC3_BIT 3 #define ADC4_PORT PORTF #define ADC4_BIT 4 #define TCK_PORT PORTF #define TCK_BIT 4 #define ADC5_PORT PORTF #define ADC5_BIT 5 #define TMS_PORT PORTF #define TMS_BIT 5 #define ADC6_PORT PORTF #define ADC6_BIT 6 #define TD0_PORT PORTF #define TD0_BIT 6 #define ADC7_PORT PORTF #define ADC7_BIT 7 #define TDI_PORT PORTF #define TDI_BIT 7 #define WR_PORT PORTG #define WR_BIT 0 #define RD_PORT PORTG #define RD_BIT 1 #define ALE_PORT PORTG #define ALE_BIT 2 #define TOSC2_PORT PORTG #define TOSC2_BIT 3 #define TOSC1_PORT PORTG #define TOSC1_BIT 4 #define OC0B_PORT PORTG #define OC0B_BIT 5