/* * Copyright Droids Corporation, Microb Technology, Eirbot (2009) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * * Revision : $Id $ * */ /* WARNING : this file is automatically generated by scripts. * You should not edit it. If you find something wrong in it, * write to zer0@droids-corp.org */ /* prescalers timer 0 */ #define TIMER0_PRESCALER_DIV_0 0 #define TIMER0_PRESCALER_DIV_1 1 #define TIMER0_PRESCALER_DIV_8 2 #define TIMER0_PRESCALER_DIV_64 3 #define TIMER0_PRESCALER_DIV_256 4 #define TIMER0_PRESCALER_DIV_1024 5 #define TIMER0_PRESCALER_DIV_FALL 6 #define TIMER0_PRESCALER_DIV_RISE 7 #define TIMER0_PRESCALER_REG_0 0 #define TIMER0_PRESCALER_REG_1 1 #define TIMER0_PRESCALER_REG_2 8 #define TIMER0_PRESCALER_REG_3 64 #define TIMER0_PRESCALER_REG_4 256 #define TIMER0_PRESCALER_REG_5 1024 #define TIMER0_PRESCALER_REG_6 -1 #define TIMER0_PRESCALER_REG_7 -2 /* available timers */ /* overflow interrupt number */ #define SIG_OVERFLOW_TOTAL_NUM 0 /* output compare interrupt number */ #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 /* Pwm nums */ #define PWM_TOTAL_NUM 0 /* input capture interrupt number */ #define SIG_INPUT_CAPTURE_TOTAL_NUM 0 /* CLKPR */ #define CLKPS0_REG CLKPR #define CLKPS1_REG CLKPR #define CLKPS2_REG CLKPR #define CLKPS3_REG CLKPR #define CLKPCE_REG CLKPR /* WDTCR */ #define WDP0_REG WDTCR #define WDP1_REG WDTCR #define WDP2_REG WDTCR #define WDE_REG WDTCR #define WDCE_REG WDTCR #define WDP3_REG WDTCR #define WDTIE_REG WDTCR #define WDTIF_REG WDTCR /* GIMSK */ #define PCIE_REG GIMSK #define INT0_REG GIMSK /* ADMUX */ #define MUX0_REG ADMUX #define MUX1_REG ADMUX #define ADLAR_REG ADMUX #define REFS0_REG ADMUX /* SREG */ #define C_REG SREG #define Z_REG SREG #define N_REG SREG #define V_REG SREG #define S_REG SREG #define H_REG SREG #define T_REG SREG #define I_REG SREG /* DDRB */ #define DDB0_REG DDRB #define DDB1_REG DDRB #define DDB2_REG DDRB #define DDB3_REG DDRB #define DDB4_REG DDRB #define DDB5_REG DDRB /* EEDR */ #define EEDR0_REG EEDR #define EEDR1_REG EEDR #define EEDR2_REG EEDR #define EEDR3_REG EEDR #define EEDR4_REG EEDR #define EEDR5_REG EEDR #define EEDR6_REG EEDR #define EEDR7_REG EEDR /* ACSR */ #define ACIS0_REG ACSR #define ACIS1_REG ACSR #define ACIE_REG ACSR #define ACI_REG ACSR #define ACO_REG ACSR #define ACBG_REG ACSR #define ACD_REG ACSR /* GTCCR */ #define PSR10_REG GTCCR #define TSM_REG GTCCR /* GIFR */ #define PCIF_REG GIFR #define INTF0_REG GIFR /* OSCCAL */ #define CAL0_REG OSCCAL #define CAL1_REG OSCCAL #define CAL2_REG OSCCAL #define CAL3_REG OSCCAL #define CAL4_REG OSCCAL #define CAL5_REG OSCCAL #define CAL6_REG OSCCAL /* ADCSRA */ #define ADPS0_REG ADCSRA #define ADPS1_REG ADCSRA #define ADPS2_REG ADCSRA #define ADIE_REG ADCSRA #define ADIF_REG ADCSRA #define ADATE_REG ADCSRA #define ADSC_REG ADCSRA #define ADEN_REG ADCSRA /* ADCSRB */ #define ADTS0_REG ADCSRB #define ADTS1_REG ADCSRB #define ADTS2_REG ADCSRB #define ACME_REG ADCSRB /* OCR0A */ #define OCR0A_0_REG OCR0A #define OCR0A_1_REG OCR0A #define OCR0A_2_REG OCR0A #define OCR0A_3_REG OCR0A #define OCR0A_4_REG OCR0A #define OCR0A_5_REG OCR0A #define OCR0A_6_REG OCR0A #define OCR0A_7_REG OCR0A /* OCR0B */ #define OCR0B_0_REG OCR0B #define OCR0B_1_REG OCR0B #define OCR0B_2_REG OCR0B #define OCR0B_3_REG OCR0B #define OCR0B_4_REG OCR0B #define OCR0B_5_REG OCR0B #define OCR0B_6_REG OCR0B #define OCR0B_7_REG OCR0B /* SPL */ #define SP0_REG SPL #define SP1_REG SPL #define SP2_REG SPL #define SP3_REG SPL #define SP4_REG SPL #define SP5_REG SPL #define SP6_REG SPL #define SP7_REG SPL /* MCUSR */ #define PORF_REG MCUSR #define EXTRF_REG MCUSR #define BORF_REG MCUSR #define WDRF_REG MCUSR /* EECR */ #define EERE_REG EECR #define EEWE_REG EECR #define EEMWE_REG EECR #define EERIE_REG EECR #define EEPM0_REG EECR #define EEPM1_REG EECR /* PCMSK */ #define PCINT0_REG PCMSK #define PCINT1_REG PCMSK #define PCINT2_REG PCMSK #define PCINT3_REG PCMSK #define PCINT4_REG PCMSK #define PCINT5_REG PCMSK /* SPMCSR */ #define SPMEN_REG SPMCSR #define PGERS_REG SPMCSR #define PGWRT_REG SPMCSR #define RFLB_REG SPMCSR #define CTPB_REG SPMCSR /* ADCL */ #define ADCL0_REG ADCL #define ADCL1_REG ADCL #define ADCL2_REG ADCL #define ADCL3_REG ADCL #define ADCL4_REG ADCL #define ADCL5_REG ADCL #define ADCL6_REG ADCL #define ADCL7_REG ADCL /* EEAR */ #define EEAR0_REG EEAR #define EEAR1_REG EEAR #define EEAR2_REG EEAR #define EEAR3_REG EEAR #define EEAR4_REG EEAR #define EEAR5_REG EEAR /* PORTB */ #define PORTB0_REG PORTB #define PORTB1_REG PORTB #define PORTB2_REG PORTB #define PORTB3_REG PORTB #define PORTB4_REG PORTB #define PORTB5_REG PORTB /* ADCH */ #define ADCH0_REG ADCH #define ADCH1_REG ADCH #define ADCH2_REG ADCH #define ADCH3_REG ADCH #define ADCH4_REG ADCH #define ADCH5_REG ADCH #define ADCH6_REG ADCH #define ADCH7_REG ADCH /* TCNT0 */ #define TCNT0_0_REG TCNT0 #define TCNT0_1_REG TCNT0 #define TCNT0_2_REG TCNT0 #define TCNT0_3_REG TCNT0 #define TCNT0_4_REG TCNT0 #define TCNT0_5_REG TCNT0 #define TCNT0_6_REG TCNT0 #define TCNT0_7_REG TCNT0 /* TIMSK0 */ #define TOIE0_REG TIMSK0 #define OCIE0A_REG TIMSK0 #define OCIE0B_REG TIMSK0 /* TCCR0B */ #define CS00_REG TCCR0B #define CS01_REG TCCR0B #define CS02_REG TCCR0B #define WGM02_REG TCCR0B #define FOC0B_REG TCCR0B #define FOC0A_REG TCCR0B /* TCCR0A */ #define WGM00_REG TCCR0A #define WGM01_REG TCCR0A #define COM0B0_REG TCCR0A #define COM0B1_REG TCCR0A #define COM0A0_REG TCCR0A #define COM0A1_REG TCCR0A /* DWDR */ #define DWDR0_REG DWDR #define DWDR1_REG DWDR #define DWDR2_REG DWDR #define DWDR3_REG DWDR #define DWDR4_REG DWDR #define DWDR5_REG DWDR #define DWDR6_REG DWDR #define DWDR7_REG DWDR /* DIDR0 */ #define ADC1D_REG DIDR0 #define ADC3D_REG DIDR0 #define ADC2D_REG DIDR0 #define ADC0D_REG DIDR0 #define AIN0D_REG DIDR0 #define AIN1D_REG DIDR0 /* MCUCR */ #define ISC00_REG MCUCR #define ISC01_REG MCUCR #define SM0_REG MCUCR #define SM1_REG MCUCR #define SE_REG MCUCR #define PUD_REG MCUCR /* PINB */ #define PINB0_REG PINB #define PINB1_REG PINB #define PINB2_REG PINB #define PINB3_REG PINB #define PINB4_REG PINB #define PINB5_REG PINB /* TIFR0 */ #define TOV0_REG TIFR0 #define OCF0A_REG TIFR0 #define OCF0B_REG TIFR0 /* pins mapping */ #define MOSI_PORT PORTB #define MOSI_BIT 0 #define AIN0_PORT PORTB #define AIN0_BIT 0 #define OC0A_PORT PORTB #define OC0A_BIT 0 #define TXD_PORT PORTB #define TXD_BIT 0 #define PCINT0_PORT PORTB #define PCINT0_BIT 0 #define MISO_PORT PORTB #define MISO_BIT 1 #define INT0_PORT PORTB #define INT0_BIT 1 #define AIN1_PORT PORTB #define AIN1_BIT 1 #define OC0B_PORT PORTB #define OC0B_BIT 1 #define INT0_PORT PORTB #define INT0_BIT 1 #define RXD_PORT PORTB #define RXD_BIT 1 #define PCINT1_PORT PORTB #define PCINT1_BIT 1 #define SCK_PORT PORTB #define SCK_BIT 2 #define ADC1_PORT PORTB #define ADC1_BIT 2 #define T0_PORT PORTB #define T0_BIT 2 #define PCINT2_PORT PORTB #define PCINT2_BIT 2