From: Harman Kalra <hkalra@marvell.com>
Date: Mon, 16 Nov 2020 14:41:55 +0000 (+0530)
Subject: common/octeontx2: fix mbox response by syncing data types
X-Git-Url: http://git.droids-corp.org/?p=dpdk.git;a=commitdiff_plain;h=023b46db5466133647dad4d1ce7dd139ee8a0866

common/octeontx2: fix mbox response by syncing data types

Syncing the data types of msix offset mbox response structure
fields wrt rvu_pfvf structure as in msix offset mbox handler,
respective block LFs response field is initialised with rvu_pfvf
and mismatch in the data types of respective fields may lead
to issues.

This mismatch in data types resulted in a bug where no sso msix
offsets are returned. For 256 SSO hwgrps, 256 msix offsets
are required, but since num of sso lf field (rsp->sso) in
response structure is u8 and is initialised with same field
in pfvf structure viz u16, value 256 corresponds to 0 hence
no sso_msixoff.
Similar mbox changes are required in kernel side also which are
available in marvell SDK version SDK-11.0.

Fixes: 2b71657c8660 ("common/octeontx2: add mbox request and response definition")
Cc: stable@dpdk.org

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
---

diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 9a1e8a7eac..f6d884c198 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -90,7 +90,7 @@ struct mbox_msghdr {
 #define OTX2_MBOX_RSP_SIG (0xbeef)
 	/* Signature, for validating corrupted msgs */
 	uint16_t __otx2_io sig;
-#define OTX2_MBOX_VERSION (0x0009)
+#define OTX2_MBOX_VERSION (0x000a)
 	/* Version of msg's structure for this ID */
 	uint16_t __otx2_io ver;
 	/* Offset of next msg within mailbox region */
@@ -454,17 +454,17 @@ struct msix_offset_rsp {
 	struct mbox_msghdr hdr;
 	uint16_t __otx2_io npa_msixoff;
 	uint16_t __otx2_io nix_msixoff;
-	uint8_t __otx2_io sso;
-	uint8_t __otx2_io ssow;
-	uint8_t __otx2_io timlfs;
-	uint8_t __otx2_io cptlfs;
+	uint16_t __otx2_io sso;
+	uint16_t __otx2_io ssow;
+	uint16_t __otx2_io timlfs;
+	uint16_t __otx2_io cptlfs;
 	uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
 	uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
 	uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
 	uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
-	uint8_t __otx2_io cpt1_lfs;
-	uint8_t __otx2_io ree0_lfs;
-	uint8_t __otx2_io ree1_lfs;
+	uint16_t __otx2_io cpt1_lfs;
+	uint16_t __otx2_io ree0_lfs;
+	uint16_t __otx2_io ree1_lfs;
 	uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
 	uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
 	uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];