From 41f24863e050810539f3a58ef901d23dddde0117 Mon Sep 17 00:00:00 2001 From: Viacheslav Ovsiienko Date: Thu, 20 Feb 2020 12:44:37 +0000 Subject: [PATCH] doc: clarify memory write combining in mlx5 guide Just add the words about write combining attribute. Signed-off-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 5ab7c07165..dd2fbde605 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -568,16 +568,17 @@ Run-time configuration The rdma core library can map doorbell register in two ways, depending on the environment variable "MLX5_SHUT_UP_BF": - - As regular cached memory, if the variable is either missing or set to zero. + - As regular cached memory (usually with write combining attribute), if the + variable is either missing or set to zero. - As non-cached memory, if the variable is present and set to not "0" value. The type of mapping may slightly affect the Tx performance, the optimal choice is strongly relied on the host architecture and should be deduced practically. If ``tx_db_nc`` is set to zero, the doorbell is forced to be mapped to regular - memory, the PMD will perform the extra write memory barrier after writing to - doorbell, it might increase the needed CPU clocks per packet to send, but - latency might be improved. + memory (with write combining), the PMD will perform the extra write memory barrier + after writing to doorbell, it might increase the needed CPU clocks per packet + to send, but latency might be improved. If ``tx_db_nc`` is set to one, the doorbell is forced to be mapped to non cached memory, the PMD will not perform the extra write memory barrier -- 2.20.1