timer_prescaler.h

   1 /*
   2  *  Copyright Droids Corporation, Microb Technology, Eirbot (2006)
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, write to the Free Software
  16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  *
  18  *  Revision : $Id: timer_prescaler.h,v 1.1.2.4 2009-01-30 20:18:36 zer0 Exp $
  19  *
  20  */
  21
  22 #ifndef _TIMER_PRESCALER_H_
  23 #define _TIMER_PRESCALER_H_
  24
  25 /* return <0 on error, else return reg value */
  26 /* This static inline function is very optimized if div is
  27  * a constant */
  28 static inline int16_t __timer0_div_to_reg(uint16_t div)
  29 {
  30         switch(div) {
  31 #if defined TIMER0_PRESCALER_REG_0 && TIMER0_PRESCALER_REG_0 >= 0
  32         case TIMER0_PRESCALER_REG_0:
  33                 return 0;
  34 #endif
  35
  36 #if defined TIMER0_PRESCALER_REG_1 && TIMER0_PRESCALER_REG_1 >= 0
  37         case TIMER0_PRESCALER_REG_1:
  38                 return 1;
  39 #endif
  40
  41 #if defined TIMER0_PRESCALER_REG_2 && TIMER0_PRESCALER_REG_2 >= 0
  42         case TIMER0_PRESCALER_REG_2:
  43                 return 2;
  44 #endif
  45
  46 #if defined TIMER0_PRESCALER_REG_3 && TIMER0_PRESCALER_REG_3 >= 0
  47         case TIMER0_PRESCALER_REG_3:
  48                 return 3;
  49 #endif
  50
  51 #if defined TIMER0_PRESCALER_REG_4 && TIMER0_PRESCALER_REG_4 >= 0
  52         case TIMER0_PRESCALER_REG_4:
  53                 return 4;
  54 #endif
  55
  56 #if defined TIMER0_PRESCALER_REG_5 && TIMER0_PRESCALER_REG_5 >= 0
  57         case TIMER0_PRESCALER_REG_5:
  58                 return 5;
  59 #endif
  60
  61 #if defined TIMER0_PRESCALER_REG_6 && TIMER0_PRESCALER_REG_6 >= 0
  62         case TIMER0_PRESCALER_REG_6:
  63                 return 6;
  64 #endif
  65
  66 #if defined TIMER0_PRESCALER_REG_7 && TIMER0_PRESCALER_REG_7 >= 0
  67         case TIMER0_PRESCALER_REG_7:
  68                 return 7;
  69 #endif
  70
  71 #if defined TIMER0_PRESCALER_REG_8 && TIMER0_PRESCALER_REG_8 >= 0
  72         case TIMER0_PRESCALER_REG_8:
  73                 return 8;
  74 #endif
  75
  76 #if defined TIMER0_PRESCALER_REG_9 && TIMER0_PRESCALER_REG_9 >= 0
  77         case TIMER0_PRESCALER_REG_9:
  78                 return 9;
  79 #endif
  80
  81 #if defined TIMER0_PRESCALER_REG_10 && TIMER0_PRESCALER_REG_10 >= 0
  82         case TIMER0_PRESCALER_REG_10:
  83                 return 10;
  84 #endif
  85
  86 #if defined TIMER0_PRESCALER_REG_11 && TIMER0_PRESCALER_REG_11 >= 0
  87         case TIMER0_PRESCALER_REG_11:
  88                 return 11;
  89 #endif
  90
  91 #if defined TIMER0_PRESCALER_REG_12 && TIMER0_PRESCALER_REG_12 >= 0
  92         case TIMER0_PRESCALER_REG_12:
  93                 return 12;
  94 #endif
  95
  96 #if defined TIMER0_PRESCALER_REG_13 && TIMER0_PRESCALER_REG_13 >= 0
  97         case TIMER0_PRESCALER_REG_13:
  98                 return 13;
  99 #endif
 100
 101 #if defined TIMER0_PRESCALER_REG_14 && TIMER0_PRESCALER_REG_14 >= 0
 102         case TIMER0_PRESCALER_REG_14:
 103                 return 14;
 104 #endif
 105
 106 #if defined TIMER0_PRESCALER_REG_15 && TIMER0_PRESCALER_REG_15 >= 0
 107         case TIMER0_PRESCALER_REG_15:
 108                 return 15;
 109 #endif
 110         default:
 111                 return -1;
 112         }
 113 }
 114
 115 /* return <0 on error, else return div value */
 116 /* This static inline function is very optimized if reg is
 117  * a constant */
 118 static inline int16_t __timer0_reg_to_div(uint8_t reg)
 119 {
 120         switch(reg) {
 121 #if defined TIMER0_PRESCALER_DIV_0
 122         case TIMER0_PRESCALER_DIV_0:
 123                 return 0;
 124 #endif
 125
 126 #if defined TIMER0_PRESCALER_DIV_1
 127         case TIMER0_PRESCALER_DIV_1:
 128                 return 1;
 129 #endif
 130
 131 #if defined TIMER0_PRESCALER_DIV_2
 132         case TIMER0_PRESCALER_DIV_2:
 133                 return 2;
 134 #endif
 135
 136 #if defined TIMER0_PRESCALER_DIV_4
 137         case TIMER0_PRESCALER_DIV_4:
 138                 return 4;
 139 #endif
 140
 141 #if defined TIMER0_PRESCALER_DIV_8
 142         case TIMER0_PRESCALER_DIV_8:
 143                 return 8;
 144 #endif
 145
 146 #if defined TIMER0_PRESCALER_DIV_16
 147         case TIMER0_PRESCALER_DIV_16:
 148                 return 16;
 149 #endif
 150
 151 #if defined TIMER0_PRESCALER_DIV_32
 152         case TIMER0_PRESCALER_DIV_32:
 153                 return 32;
 154 #endif
 155
 156 #if defined TIMER0_PRESCALER_DIV_64
 157         case TIMER0_PRESCALER_DIV_64:
 158                 return 64;
 159 #endif
 160
 161 #if defined TIMER0_PRESCALER_DIV_128
 162         case TIMER0_PRESCALER_DIV_128:
 163                 return 128;
 164 #endif
 165
 166 #if defined TIMER0_PRESCALER_DIV_256
 167         case TIMER0_PRESCALER_DIV_256:
 168                 return 256;
 169 #endif
 170
 171 #if defined TIMER0_PRESCALER_DIV_512
 172         case TIMER0_PRESCALER_DIV_512:
 173                 return 512;
 174 #endif
 175
 176 #if defined TIMER0_PRESCALER_DIV_1024
 177         case TIMER0_PRESCALER_DIV_1024:
 178                 return 1024;
 179 #endif
 180
 181 #if defined TIMER0_PRESCALER_DIV_2048
 182         case TIMER0_PRESCALER_DIV_2048:
 183                 return 2048;
 184 #endif
 185
 186 #if defined TIMER0_PRESCALER_DIV_4096
 187         case TIMER0_PRESCALER_DIV_4096:
 188                 return 4096;
 189 #endif
 190
 191 #if defined TIMER0_PRESCALER_DIV_8192
 192         case TIMER0_PRESCALER_DIV_8192:
 193                 return 8192;
 194 #endif
 195
 196 #if defined TIMER0_PRESCALER_DIV_16384
 197         case TIMER0_PRESCALER_DIV_16384:
 198                 return 16384;
 199 #endif
 200
 201         default:
 202                 return -1;
 203         }
 204 }
 205
 206
 207 /* return <0 on error, else return reg value */
 208 /* This static inline function is very optimized if div is
 209  * a constant */
 210 static inline int16_t __timer1_div_to_reg(uint16_t div)
 211 {
 212         switch(div) {
 213 #if defined TIMER1_PRESCALER_REG_0 && TIMER1_PRESCALER_REG_0 >= 0
 214         case TIMER1_PRESCALER_REG_0:
 215                 return 0;
 216 #endif
 217
 218 #if defined TIMER1_PRESCALER_REG_1 && TIMER1_PRESCALER_REG_1 >= 0
 219         case TIMER1_PRESCALER_REG_1:
 220                 return 1;
 221 #endif
 222
 223 #if defined TIMER1_PRESCALER_REG_2 && TIMER1_PRESCALER_REG_2 >= 0
 224         case TIMER1_PRESCALER_REG_2:
 225                 return 2;
 226 #endif
 227
 228 #if defined TIMER1_PRESCALER_REG_3 && TIMER1_PRESCALER_REG_3 >= 0
 229         case TIMER1_PRESCALER_REG_3:
 230                 return 3;
 231 #endif
 232
 233 #if defined TIMER1_PRESCALER_REG_4 && TIMER1_PRESCALER_REG_4 >= 0
 234         case TIMER1_PRESCALER_REG_4:
 235                 return 4;
 236 #endif
 237
 238 #if defined TIMER1_PRESCALER_REG_5 && TIMER1_PRESCALER_REG_5 >= 0
 239         case TIMER1_PRESCALER_REG_5:
 240                 return 5;
 241 #endif
 242
 243 #if defined TIMER1_PRESCALER_REG_6 && TIMER1_PRESCALER_REG_6 >= 0
 244         case TIMER1_PRESCALER_REG_6:
 245                 return 6;
 246 #endif
 247
 248 #if defined TIMER1_PRESCALER_REG_7 && TIMER1_PRESCALER_REG_7 >= 0
 249         case TIMER1_PRESCALER_REG_7:
 250                 return 7;
 251 #endif
 252
 253 #if defined TIMER1_PRESCALER_REG_8 && TIMER1_PRESCALER_REG_8 >= 0
 254         case TIMER1_PRESCALER_REG_8:
 255                 return 8;
 256 #endif
 257
 258 #if defined TIMER1_PRESCALER_REG_9 && TIMER1_PRESCALER_REG_9 >= 0
 259         case TIMER1_PRESCALER_REG_9:
 260                 return 9;
 261 #endif
 262
 263 #if defined TIMER1_PRESCALER_REG_10 && TIMER1_PRESCALER_REG_10 >= 0
 264         case TIMER1_PRESCALER_REG_10:
 265                 return 10;
 266 #endif
 267
 268 #if defined TIMER1_PRESCALER_REG_11 && TIMER1_PRESCALER_REG_11 >= 0
 269         case TIMER1_PRESCALER_REG_11:
 270                 return 11;
 271 #endif
 272
 273 #if defined TIMER1_PRESCALER_REG_12 && TIMER1_PRESCALER_REG_12 >= 0
 274         case TIMER1_PRESCALER_REG_12:
 275                 return 12;
 276 #endif
 277
 278 #if defined TIMER1_PRESCALER_REG_13 && TIMER1_PRESCALER_REG_13 >= 0
 279         case TIMER1_PRESCALER_REG_13:
 280                 return 13;
 281 #endif
 282
 283 #if defined TIMER1_PRESCALER_REG_14 && TIMER1_PRESCALER_REG_14 >= 0
 284         case TIMER1_PRESCALER_REG_14:
 285                 return 14;
 286 #endif
 287
 288 #if defined TIMER1_PRESCALER_REG_15 && TIMER1_PRESCALER_REG_15 >= 0
 289         case TIMER1_PRESCALER_REG_15:
 290                 return 15;
 291 #endif
 292         default:
 293                 return -1;
 294         }
 295 }
 296
 297 /* return <0 on error, else return div value */
 298 /* This static inline function is very optimized if reg is
 299  * a constant */
 300 static inline int16_t __timer1_reg_to_div(uint8_t reg)
 301 {
 302         switch(reg) {
 303 #if defined TIMER1_PRESCALER_DIV_0
 304         case TIMER1_PRESCALER_DIV_0:
 305                 return 0;
 306 #endif
 307
 308 #if defined TIMER1_PRESCALER_DIV_1
 309         case TIMER1_PRESCALER_DIV_1:
 310                 return 1;
 311 #endif
 312
 313 #if defined TIMER1_PRESCALER_DIV_2
 314         case TIMER1_PRESCALER_DIV_2:
 315                 return 2;
 316 #endif
 317
 318 #if defined TIMER1_PRESCALER_DIV_4
 319         case TIMER1_PRESCALER_DIV_4:
 320                 return 4;
 321 #endif
 322
 323 #if defined TIMER1_PRESCALER_DIV_8
 324         case TIMER1_PRESCALER_DIV_8:
 325                 return 8;
 326 #endif
 327
 328 #if defined TIMER1_PRESCALER_DIV_16
 329         case TIMER1_PRESCALER_DIV_16:
 330                 return 16;
 331 #endif
 332
 333 #if defined TIMER1_PRESCALER_DIV_32
 334         case TIMER1_PRESCALER_DIV_32:
 335                 return 32;
 336 #endif
 337
 338 #if defined TIMER1_PRESCALER_DIV_64
 339         case TIMER1_PRESCALER_DIV_64:
 340                 return 64;
 341 #endif
 342
 343 #if defined TIMER1_PRESCALER_DIV_128
 344         case TIMER1_PRESCALER_DIV_128:
 345                 return 128;
 346 #endif
 347
 348 #if defined TIMER1_PRESCALER_DIV_256
 349         case TIMER1_PRESCALER_DIV_256:
 350                 return 256;
 351 #endif
 352
 353 #if defined TIMER1_PRESCALER_DIV_512
 354         case TIMER1_PRESCALER_DIV_512:
 355                 return 512;
 356 #endif
 357
 358 #if defined TIMER1_PRESCALER_DIV_1024
 359         case TIMER1_PRESCALER_DIV_1024:
 360                 return 1024;
 361 #endif
 362
 363 #if defined TIMER1_PRESCALER_DIV_2048
 364         case TIMER1_PRESCALER_DIV_2048:
 365                 return 2048;
 366 #endif
 367
 368 #if defined TIMER1_PRESCALER_DIV_4096
 369         case TIMER1_PRESCALER_DIV_4096:
 370                 return 4096;
 371 #endif
 372
 373 #if defined TIMER1_PRESCALER_DIV_8192
 374         case TIMER1_PRESCALER_DIV_8192:
 375                 return 8192;
 376 #endif
 377
 378 #if defined TIMER1_PRESCALER_DIV_16384
 379         case TIMER1_PRESCALER_DIV_16384:
 380                 return 16384;
 381 #endif
 382
 383         default:
 384                 return -1;
 385         }
 386 }
 387
 388
 389
 390 /* return <0 on error, else return reg value */
 391 /* This static inline function is very optimized if div is
 392  * a constant */
 393 static inline int16_t __timer2_div_to_reg(uint16_t div)
 394 {
 395         switch(div) {
 396 #if defined TIMER2_PRESCALER_REG_0 && TIMER2_PRESCALER_REG_0 >= 0
 397         case TIMER2_PRESCALER_REG_0:
 398                 return 0;
 399 #endif
 400
 401 #if defined TIMER2_PRESCALER_REG_1 && TIMER2_PRESCALER_REG_1 >= 0
 402         case TIMER2_PRESCALER_REG_1:
 403                 return 1;
 404 #endif
 405
 406 #if defined TIMER2_PRESCALER_REG_2 && TIMER2_PRESCALER_REG_2 >= 0
 407         case TIMER2_PRESCALER_REG_2:
 408                 return 2;
 409 #endif
 410
 411 #if defined TIMER2_PRESCALER_REG_3 && TIMER2_PRESCALER_REG_3 >= 0
 412         case TIMER2_PRESCALER_REG_3:
 413                 return 3;
 414 #endif
 415
 416 #if defined TIMER2_PRESCALER_REG_4 && TIMER2_PRESCALER_REG_4 >= 0
 417         case TIMER2_PRESCALER_REG_4:
 418                 return 4;
 419 #endif
 420
 421 #if defined TIMER2_PRESCALER_REG_5 && TIMER2_PRESCALER_REG_5 >= 0
 422         case TIMER2_PRESCALER_REG_5:
 423                 return 5;
 424 #endif
 425
 426 #if defined TIMER2_PRESCALER_REG_6 && TIMER2_PRESCALER_REG_6 >= 0
 427         case TIMER2_PRESCALER_REG_6:
 428                 return 6;
 429 #endif
 430
 431 #if defined TIMER2_PRESCALER_REG_7 && TIMER2_PRESCALER_REG_7 >= 0
 432         case TIMER2_PRESCALER_REG_7:
 433                 return 7;
 434 #endif
 435
 436 #if defined TIMER2_PRESCALER_REG_8 && TIMER2_PRESCALER_REG_8 >= 0
 437         case TIMER2_PRESCALER_REG_8:
 438                 return 8;
 439 #endif
 440
 441 #if defined TIMER2_PRESCALER_REG_9 && TIMER2_PRESCALER_REG_9 >= 0
 442         case TIMER2_PRESCALER_REG_9:
 443                 return 9;
 444 #endif
 445
 446 #if defined TIMER2_PRESCALER_REG_10 && TIMER2_PRESCALER_REG_10 >= 0
 447         case TIMER2_PRESCALER_REG_10:
 448                 return 10;
 449 #endif
 450
 451 #if defined TIMER2_PRESCALER_REG_11 && TIMER2_PRESCALER_REG_11 >= 0
 452         case TIMER2_PRESCALER_REG_11:
 453                 return 11;
 454 #endif
 455
 456 #if defined TIMER2_PRESCALER_REG_12 && TIMER2_PRESCALER_REG_12 >= 0
 457         case TIMER2_PRESCALER_REG_12:
 458                 return 12;
 459 #endif
 460
 461 #if defined TIMER2_PRESCALER_REG_13 && TIMER2_PRESCALER_REG_13 >= 0
 462         case TIMER2_PRESCALER_REG_13:
 463                 return 13;
 464 #endif
 465
 466 #if defined TIMER2_PRESCALER_REG_14 && TIMER2_PRESCALER_REG_14 >= 0
 467         case TIMER2_PRESCALER_REG_14:
 468                 return 14;
 469 #endif
 470
 471 #if defined TIMER2_PRESCALER_REG_15 && TIMER2_PRESCALER_REG_15 >= 0
 472         case TIMER2_PRESCALER_REG_15:
 473                 return 15;
 474 #endif
 475         default:
 476                 return -1;
 477         }
 478 }
 479
 480 /* return <0 on error, else return div value */
 481 /* This static inline function is very optimized if reg is
 482  * a constant */
 483 static inline int16_t __timer2_reg_to_div(uint8_t reg)
 484 {
 485         switch(reg) {
 486 #if defined TIMER2_PRESCALER_DIV_0
 487         case TIMER2_PRESCALER_DIV_0:
 488                 return 0;
 489 #endif
 490
 491 #if defined TIMER2_PRESCALER_DIV_1
 492         case TIMER2_PRESCALER_DIV_1:
 493                 return 1;
 494 #endif
 495
 496 #if defined TIMER2_PRESCALER_DIV_2
 497         case TIMER2_PRESCALER_DIV_2:
 498                 return 2;
 499 #endif
 500
 501 #if defined TIMER2_PRESCALER_DIV_4
 502         case TIMER2_PRESCALER_DIV_4:
 503                 return 4;
 504 #endif
 505
 506 #if defined TIMER2_PRESCALER_DIV_8
 507         case TIMER2_PRESCALER_DIV_8:
 508                 return 8;
 509 #endif
 510
 511 #if defined TIMER2_PRESCALER_DIV_16
 512         case TIMER2_PRESCALER_DIV_16:
 513                 return 16;
 514 #endif
 515
 516 #if defined TIMER2_PRESCALER_DIV_32
 517         case TIMER2_PRESCALER_DIV_32:
 518                 return 32;
 519 #endif
 520
 521 #if defined TIMER2_PRESCALER_DIV_64
 522         case TIMER2_PRESCALER_DIV_64:
 523                 return 64;
 524 #endif
 525
 526 #if defined TIMER2_PRESCALER_DIV_128
 527         case TIMER2_PRESCALER_DIV_128:
 528                 return 128;
 529 #endif
 530
 531 #if defined TIMER2_PRESCALER_DIV_256
 532         case TIMER2_PRESCALER_DIV_256:
 533                 return 256;
 534 #endif
 535
 536 #if defined TIMER2_PRESCALER_DIV_512
 537         case TIMER2_PRESCALER_DIV_512:
 538                 return 512;
 539 #endif
 540
 541 #if defined TIMER2_PRESCALER_DIV_1024
 542         case TIMER2_PRESCALER_DIV_1024:
 543                 return 1024;
 544 #endif
 545
 546 #if defined TIMER2_PRESCALER_DIV_2048
 547         case TIMER2_PRESCALER_DIV_2048:
 548                 return 2048;
 549 #endif
 550
 551 #if defined TIMER2_PRESCALER_DIV_4096
 552         case TIMER2_PRESCALER_DIV_4096:
 553                 return 4096;
 554 #endif
 555
 556 #if defined TIMER2_PRESCALER_DIV_8192
 557         case TIMER2_PRESCALER_DIV_8192:
 558                 return 8192;
 559 #endif
 560
 561 #if defined TIMER2_PRESCALER_DIV_16384
 562         case TIMER2_PRESCALER_DIV_16384:
 563                 return 16384;
 564 #endif
 565
 566         default:
 567                 return -1;
 568         }
 569 }
 570
 571
 572
 573 /* return <0 on error, else return reg value */
 574 /* This static inline function is very optimized if div is
 575  * a constant */
 576 static inline int16_t __timer3_div_to_reg(uint16_t div)
 577 {
 578         switch(div) {
 579 #if defined TIMER3_PRESCALER_REG_0 && TIMER3_PRESCALER_REG_0 >= 0
 580         case TIMER3_PRESCALER_REG_0:
 581                 return 0;
 582 #endif
 583
 584 #if defined TIMER3_PRESCALER_REG_1 && TIMER3_PRESCALER_REG_1 >= 0
 585         case TIMER3_PRESCALER_REG_1:
 586                 return 1;
 587 #endif
 588
 589 #if defined TIMER3_PRESCALER_REG_2 && TIMER3_PRESCALER_REG_2 >= 0
 590         case TIMER3_PRESCALER_REG_2:
 591                 return 2;
 592 #endif
 593
 594 #if defined TIMER3_PRESCALER_REG_3 && TIMER3_PRESCALER_REG_3 >= 0
 595         case TIMER3_PRESCALER_REG_3:
 596                 return 3;
 597 #endif
 598
 599 #if defined TIMER3_PRESCALER_REG_4 && TIMER3_PRESCALER_REG_4 >= 0
 600         case TIMER3_PRESCALER_REG_4:
 601                 return 4;
 602 #endif
 603
 604 #if defined TIMER3_PRESCALER_REG_5 && TIMER3_PRESCALER_REG_5 >= 0
 605         case TIMER3_PRESCALER_REG_5:
 606                 return 5;
 607 #endif
 608
 609 #if defined TIMER3_PRESCALER_REG_6 && TIMER3_PRESCALER_REG_6 >= 0
 610         case TIMER3_PRESCALER_REG_6:
 611                 return 6;
 612 #endif
 613
 614 #if defined TIMER3_PRESCALER_REG_7 && TIMER3_PRESCALER_REG_7 >= 0
 615         case TIMER3_PRESCALER_REG_7:
 616                 return 7;
 617 #endif
 618
 619 #if defined TIMER3_PRESCALER_REG_8 && TIMER3_PRESCALER_REG_8 >= 0
 620         case TIMER3_PRESCALER_REG_8:
 621                 return 8;
 622 #endif
 623
 624 #if defined TIMER3_PRESCALER_REG_9 && TIMER3_PRESCALER_REG_9 >= 0
 625         case TIMER3_PRESCALER_REG_9:
 626                 return 9;
 627 #endif
 628
 629 #if defined TIMER3_PRESCALER_REG_10 && TIMER3_PRESCALER_REG_10 >= 0
 630         case TIMER3_PRESCALER_REG_10:
 631                 return 10;
 632 #endif
 633
 634 #if defined TIMER3_PRESCALER_REG_11 && TIMER3_PRESCALER_REG_11 >= 0
 635         case TIMER3_PRESCALER_REG_11:
 636                 return 11;
 637 #endif
 638
 639 #if defined TIMER3_PRESCALER_REG_12 && TIMER3_PRESCALER_REG_12 >= 0
 640         case TIMER3_PRESCALER_REG_12:
 641                 return 12;
 642 #endif
 643
 644 #if defined TIMER3_PRESCALER_REG_13 && TIMER3_PRESCALER_REG_13 >= 0
 645         case TIMER3_PRESCALER_REG_13:
 646                 return 13;
 647 #endif
 648 #if defined TIMER3_PRESCALER_REG_14 && TIMER3_PRESCALER_REG_14 >= 0
 649         case TIMER3_PRESCALER_REG_14:
 650                 return 14;
 651 #endif
 652
 653 #if defined TIMER3_PRESCALER_REG_15 && TIMER3_PRESCALER_REG_15 >= 0
 654         case TIMER3_PRESCALER_REG_15:
 655                 return 15;
 656 #endif
 657         default:
 658                 return -1;
 659         }
 660 }
 661
 662 /* return <0 on error, else return div value */
 663 /* This static inline function is very optimized if reg is
 664  * a constant */
 665 static inline int16_t __timer3_reg_to_div(uint8_t reg)
 666 {
 667         switch(reg) {
 668 #if defined TIMER3_PRESCALER_DIV_0
 669         case TIMER3_PRESCALER_DIV_0:
 670                 return 0;
 671 #endif
 672
 673 #if defined TIMER3_PRESCALER_DIV_1
 674         case TIMER3_PRESCALER_DIV_1:
 675                 return 1;
 676 #endif
 677
 678 #if defined TIMER3_PRESCALER_DIV_2
 679         case TIMER3_PRESCALER_DIV_2:
 680                 return 2;
 681 #endif
 682
 683 #if defined TIMER3_PRESCALER_DIV_4
 684         case TIMER3_PRESCALER_DIV_4:
 685                 return 4;
 686 #endif
 687
 688 #if defined TIMER3_PRESCALER_DIV_8
 689         case TIMER3_PRESCALER_DIV_8:
 690                 return 8;
 691 #endif
 692
 693 #if defined TIMER3_PRESCALER_DIV_16
 694         case TIMER3_PRESCALER_DIV_16:
 695                 return 16;
 696 #endif
 697
 698 #if defined TIMER3_PRESCALER_DIV_32
 699         case TIMER3_PRESCALER_DIV_32:
 700                 return 32;
 701 #endif
 702
 703 #if defined TIMER3_PRESCALER_DIV_64
 704         case TIMER3_PRESCALER_DIV_64:
 705                 return 64;
 706 #endif
 707
 708 #if defined TIMER3_PRESCALER_DIV_128
 709         case TIMER3_PRESCALER_DIV_128:
 710                 return 128;
 711 #endif
 712
 713 #if defined TIMER3_PRESCALER_DIV_256
 714         case TIMER3_PRESCALER_DIV_256:
 715                 return 256;
 716 #endif
 717
 718 #if defined TIMER3_PRESCALER_DIV_512
 719         case TIMER3_PRESCALER_DIV_512:
 720                 return 512;
 721 #endif
 722
 723 #if defined TIMER3_PRESCALER_DIV_1024
 724         case TIMER3_PRESCALER_DIV_1024:
 725                 return 1024;
 726 #endif
 727
 728 #if defined TIMER3_PRESCALER_DIV_2048
 729         case TIMER3_PRESCALER_DIV_2048:
 730                 return 2048;
 731 #endif
 732
 733 #if defined TIMER3_PRESCALER_DIV_4096
 734         case TIMER3_PRESCALER_DIV_4096:
 735                 return 4096;
 736 #endif
 737
 738 #if defined TIMER3_PRESCALER_DIV_8192
 739         case TIMER3_PRESCALER_DIV_8192:
 740                 return 8192;
 741 #endif
 742
 743 #if defined TIMER3_PRESCALER_DIV_16384
 744         case TIMER3_PRESCALER_DIV_16384:
 745                 return 16384;
 746 #endif
 747
 748         default:
 749                 return -1;
 750         }
 751 }
 752
 753 /* return <0 on error, else return reg value */
 754 /* This static inline function is very optimized if div is
 755  * a constant */
 756 static inline int16_t __timer4_div_to_reg(uint16_t div)
 757 {
 758         switch(div) {
 759 #if defined TIMER4_PRESCALER_REG_0 && TIMER4_PRESCALER_REG_0 >= 0
 760         case TIMER4_PRESCALER_REG_0:
 761                 return 0;
 762 #endif
 763
 764 #if defined TIMER4_PRESCALER_REG_1 && TIMER4_PRESCALER_REG_1 >= 0
 765         case TIMER4_PRESCALER_REG_1:
 766                 return 1;
 767 #endif
 768
 769 #if defined TIMER4_PRESCALER_REG_2 && TIMER4_PRESCALER_REG_2 >= 0
 770         case TIMER4_PRESCALER_REG_2:
 771                 return 2;
 772 #endif
 773
 774 #if defined TIMER4_PRESCALER_REG_3 && TIMER4_PRESCALER_REG_3 >= 0
 775         case TIMER4_PRESCALER_REG_3:
 776                 return 3;
 777 #endif
 778
 779 #if defined TIMER4_PRESCALER_REG_4 && TIMER4_PRESCALER_REG_4 >= 0
 780         case TIMER4_PRESCALER_REG_4:
 781                 return 4;
 782 #endif
 783
 784 #if defined TIMER4_PRESCALER_REG_5 && TIMER4_PRESCALER_REG_5 >= 0
 785         case TIMER4_PRESCALER_REG_5:
 786                 return 5;
 787 #endif
 788
 789 #if defined TIMER4_PRESCALER_REG_6 && TIMER4_PRESCALER_REG_6 >= 0
 790         case TIMER4_PRESCALER_REG_6:
 791                 return 6;
 792 #endif
 793
 794 #if defined TIMER4_PRESCALER_REG_7 && TIMER4_PRESCALER_REG_7 >= 0
 795         case TIMER4_PRESCALER_REG_7:
 796                 return 7;
 797 #endif
 798
 799 #if defined TIMER4_PRESCALER_REG_8 && TIMER4_PRESCALER_REG_8 >= 0
 800         case TIMER4_PRESCALER_REG_8:
 801                 return 8;
 802 #endif
 803
 804 #if defined TIMER4_PRESCALER_REG_9 && TIMER4_PRESCALER_REG_9 >= 0
 805         case TIMER4_PRESCALER_REG_9:
 806                 return 9;
 807 #endif
 808
 809 #if defined TIMER4_PRESCALER_REG_10 && TIMER4_PRESCALER_REG_10 >= 0
 810         case TIMER4_PRESCALER_REG_10:
 811                 return 10;
 812 #endif
 813
 814 #if defined TIMER4_PRESCALER_REG_11 && TIMER4_PRESCALER_REG_11 >= 0
 815         case TIMER4_PRESCALER_REG_11:
 816                 return 11;
 817 #endif
 818
 819 #if defined TIMER4_PRESCALER_REG_12 && TIMER4_PRESCALER_REG_12 >= 0
 820         case TIMER4_PRESCALER_REG_12:
 821                 return 12;
 822 #endif
 823
 824 #if defined TIMER4_PRESCALER_REG_13 && TIMER4_PRESCALER_REG_13 >= 0
 825         case TIMER4_PRESCALER_REG_13:
 826                 return 13;
 827 #endif
 828 #if defined TIMER4_PRESCALER_REG_14 && TIMER4_PRESCALER_REG_14 >= 0
 829         case TIMER4_PRESCALER_REG_14:
 830                 return 14;
 831 #endif
 832
 833 #if defined TIMER4_PRESCALER_REG_15 && TIMER4_PRESCALER_REG_15 >= 0
 834         case TIMER4_PRESCALER_REG_15:
 835                 return 15;
 836 #endif
 837         default:
 838                 return -1;
 839         }
 840 }
 841
 842 /* return <0 on error, else return div value */
 843 /* This static inline function is very optimized if reg is
 844  * a constant */
 845 static inline int16_t __timer4_reg_to_div(uint8_t reg)
 846 {
 847         switch(reg) {
 848 #if defined TIMER4_PRESCALER_DIV_0
 849         case TIMER4_PRESCALER_DIV_0:
 850                 return 0;
 851 #endif
 852
 853 #if defined TIMER4_PRESCALER_DIV_1
 854         case TIMER4_PRESCALER_DIV_1:
 855                 return 1;
 856 #endif
 857
 858 #if defined TIMER4_PRESCALER_DIV_2
 859         case TIMER4_PRESCALER_DIV_2:
 860                 return 2;
 861 #endif
 862
 863 #if defined TIMER4_PRESCALER_DIV_4
 864         case TIMER4_PRESCALER_DIV_4:
 865                 return 4;
 866 #endif
 867
 868 #if defined TIMER4_PRESCALER_DIV_8
 869         case TIMER4_PRESCALER_DIV_8:
 870                 return 8;
 871 #endif
 872
 873 #if defined TIMER4_PRESCALER_DIV_16
 874         case TIMER4_PRESCALER_DIV_16:
 875                 return 16;
 876 #endif
 877
 878 #if defined TIMER4_PRESCALER_DIV_32
 879         case TIMER4_PRESCALER_DIV_32:
 880                 return 32;
 881 #endif
 882
 883 #if defined TIMER4_PRESCALER_DIV_64
 884         case TIMER4_PRESCALER_DIV_64:
 885                 return 64;
 886 #endif
 887
 888 #if defined TIMER4_PRESCALER_DIV_128
 889         case TIMER4_PRESCALER_DIV_128:
 890                 return 128;
 891 #endif
 892
 893 #if defined TIMER4_PRESCALER_DIV_256
 894         case TIMER4_PRESCALER_DIV_256:
 895                 return 256;
 896 #endif
 897
 898 #if defined TIMER4_PRESCALER_DIV_512
 899         case TIMER4_PRESCALER_DIV_512:
 900                 return 512;
 901 #endif
 902
 903 #if defined TIMER4_PRESCALER_DIV_1024
 904         case TIMER4_PRESCALER_DIV_1024:
 905                 return 1024;
 906 #endif
 907
 908 #if defined TIMER4_PRESCALER_DIV_2048
 909         case TIMER4_PRESCALER_DIV_2048:
 910                 return 2048;
 911 #endif
 912
 913 #if defined TIMER4_PRESCALER_DIV_4096
 914         case TIMER4_PRESCALER_DIV_4096:
 915                 return 4096;
 916 #endif
 917
 918 #if defined TIMER4_PRESCALER_DIV_8192
 919         case TIMER4_PRESCALER_DIV_8192:
 920                 return 8192;
 921 #endif
 922
 923 #if defined TIMER4_PRESCALER_DIV_16384
 924         case TIMER4_PRESCALER_DIV_16384:
 925                 return 16384;
 926 #endif
 927
 928         default:
 929                 return -1;
 930         }
 931 }
 932
 933 /* return <0 on error, else return reg value */
 934 /* This static inline function is very optimized if div is
 935  * a constant */
 936 static inline int16_t __timer5_div_to_reg(uint16_t div)
 937 {
 938         switch(div) {
 939 #if defined TIMER5_PRESCALER_REG_0 && TIMER5_PRESCALER_REG_0 >= 0
 940         case TIMER5_PRESCALER_REG_0:
 941                 return 0;
 942 #endif
 943
 944 #if defined TIMER5_PRESCALER_REG_1 && TIMER5_PRESCALER_REG_1 >= 0
 945         case TIMER5_PRESCALER_REG_1:
 946                 return 1;
 947 #endif
 948
 949 #if defined TIMER5_PRESCALER_REG_2 && TIMER5_PRESCALER_REG_2 >= 0
 950         case TIMER5_PRESCALER_REG_2:
 951                 return 2;
 952 #endif
 953
 954 #if defined TIMER5_PRESCALER_REG_3 && TIMER5_PRESCALER_REG_3 >= 0
 955         case TIMER5_PRESCALER_REG_3:
 956                 return 3;
 957 #endif
 958
 959 #if defined TIMER5_PRESCALER_REG_4 && TIMER5_PRESCALER_REG_4 >= 0
 960         case TIMER5_PRESCALER_REG_4:
 961                 return 4;
 962 #endif
 963
 964 #if defined TIMER5_PRESCALER_REG_5 && TIMER5_PRESCALER_REG_5 >= 0
 965         case TIMER5_PRESCALER_REG_5:
 966                 return 5;
 967 #endif
 968
 969 #if defined TIMER5_PRESCALER_REG_6 && TIMER5_PRESCALER_REG_6 >= 0
 970         case TIMER5_PRESCALER_REG_6:
 971                 return 6;
 972 #endif
 973
 974 #if defined TIMER5_PRESCALER_REG_7 && TIMER5_PRESCALER_REG_7 >= 0
 975         case TIMER5_PRESCALER_REG_7:
 976                 return 7;
 977 #endif
 978
 979 #if defined TIMER5_PRESCALER_REG_8 && TIMER5_PRESCALER_REG_8 >= 0
 980         case TIMER5_PRESCALER_REG_8:
 981                 return 8;
 982 #endif
 983
 984 #if defined TIMER5_PRESCALER_REG_9 && TIMER5_PRESCALER_REG_9 >= 0
 985         case TIMER5_PRESCALER_REG_9:
 986                 return 9;
 987 #endif
 988
 989 #if defined TIMER5_PRESCALER_REG_10 && TIMER5_PRESCALER_REG_10 >= 0
 990         case TIMER5_PRESCALER_REG_10:
 991                 return 10;
 992 #endif
 993
 994 #if defined TIMER5_PRESCALER_REG_11 && TIMER5_PRESCALER_REG_11 >= 0
 995         case TIMER5_PRESCALER_REG_11:
 996                 return 11;
 997 #endif
 998
 999 #if defined TIMER5_PRESCALER_REG_12 && TIMER5_PRESCALER_REG_12 >= 0
1000         case TIMER5_PRESCALER_REG_12:
1001                 return 12;
1002 #endif
1003
1004 #if defined TIMER5_PRESCALER_REG_13 && TIMER5_PRESCALER_REG_13 >= 0
1005         case TIMER5_PRESCALER_REG_13:
1006                 return 13;
1007 #endif
1008 #if defined TIMER5_PRESCALER_REG_14 && TIMER5_PRESCALER_REG_14 >= 0
1009         case TIMER5_PRESCALER_REG_14:
1010                 return 14;
1011 #endif
1012
1013 #if defined TIMER5_PRESCALER_REG_15 && TIMER5_PRESCALER_REG_15 >= 0
1014         case TIMER5_PRESCALER_REG_15:
1015                 return 15;
1016 #endif
1017         default:
1018                 return -1;
1019         }
1020 }
1021
1022 /* return <0 on error, else return div value */
1023 /* This static inline function is very optimized if reg is
1024  * a constant */
1025 static inline int16_t __timer5_reg_to_div(uint8_t reg)
1026 {
1027         switch(reg) {
1028 #if defined TIMER5_PRESCALER_DIV_0
1029         case TIMER5_PRESCALER_DIV_0:
1030                 return 0;
1031 #endif
1032
1033 #if defined TIMER5_PRESCALER_DIV_1
1034         case TIMER5_PRESCALER_DIV_1:
1035                 return 1;
1036 #endif
1037
1038 #if defined TIMER5_PRESCALER_DIV_2
1039         case TIMER5_PRESCALER_DIV_2:
1040                 return 2;
1041 #endif
1042
1043 #if defined TIMER5_PRESCALER_DIV_4
1044         case TIMER5_PRESCALER_DIV_4:
1045                 return 4;
1046 #endif
1047
1048 #if defined TIMER5_PRESCALER_DIV_8
1049         case TIMER5_PRESCALER_DIV_8:
1050                 return 8;
1051 #endif
1052
1053 #if defined TIMER5_PRESCALER_DIV_16
1054         case TIMER5_PRESCALER_DIV_16:
1055                 return 16;
1056 #endif
1057
1058 #if defined TIMER5_PRESCALER_DIV_32
1059         case TIMER5_PRESCALER_DIV_32:
1060                 return 32;
1061 #endif
1062
1063 #if defined TIMER5_PRESCALER_DIV_64
1064         case TIMER5_PRESCALER_DIV_64:
1065                 return 64;
1066 #endif
1067
1068 #if defined TIMER5_PRESCALER_DIV_128
1069         case TIMER5_PRESCALER_DIV_128:
1070                 return 128;
1071 #endif
1072
1073 #if defined TIMER5_PRESCALER_DIV_256
1074         case TIMER5_PRESCALER_DIV_256:
1075                 return 256;
1076 #endif
1077
1078 #if defined TIMER5_PRESCALER_DIV_512
1079         case TIMER5_PRESCALER_DIV_512:
1080                 return 512;
1081 #endif
1082
1083 #if defined TIMER5_PRESCALER_DIV_1024
1084         case TIMER5_PRESCALER_DIV_1024:
1085                 return 1024;
1086 #endif
1087
1088 #if defined TIMER5_PRESCALER_DIV_2048
1089         case TIMER5_PRESCALER_DIV_2048:
1090                 return 2048;
1091 #endif
1092
1093 #if defined TIMER5_PRESCALER_DIV_4096
1094         case TIMER5_PRESCALER_DIV_4096:
1095                 return 4096;
1096 #endif
1097
1098 #if defined TIMER5_PRESCALER_DIV_8192
1099         case TIMER5_PRESCALER_DIV_8192:
1100                 return 8192;
1101 #endif
1102
1103 #if defined TIMER5_PRESCALER_DIV_16384
1104         case TIMER5_PRESCALER_DIV_16384:
1105                 return 16384;
1106 #endif
1107
1108         default:
1109                 return -1;
1110         }
1111 }
1112
1113 #endif