From: Fabrice Desclaux Date: Tue, 26 Jun 2012 17:49:13 +0000 (+0200) Subject: first version of mainboard X-Git-Tag: v2~14 X-Git-Url: http://git.droids-corp.org/?p=protos%2Fxbee-elec.git;a=commitdiff_plain;h=a8c4d1a6bf76c08fd4263c8832584071a739ba76 first version of mainboard --- diff --git a/gschem-sym/ATmega168-TQFP-1.sym b/gschem-sym/ATmega168-TQFP-1.sym new file mode 100644 index 0000000..6578062 --- /dev/null +++ b/gschem-sym/ATmega168-TQFP-1.sym @@ -0,0 +1,379 @@ +v 20060113 1 +P 3700 8100 3400 8100 1 0 0 +{ +T 3500 8150 5 8 1 1 0 0 1 +pinnumber=12 +T 3500 8050 5 8 0 1 0 2 1 +pinseq=12 +T 3350 8100 9 8 1 1 0 6 1 +pinlabel=(PCINT0/CLKO/ICP1) PB0 +T 3350 8100 5 8 0 1 0 8 1 +pintype=io +} +P 3700 7700 3400 7700 1 0 0 +{ +T 3500 7750 5 8 1 1 0 0 1 +pinnumber=13 +T 3500 7650 5 8 0 1 0 2 1 +pinseq=13 +T 3350 7700 9 8 1 1 0 6 1 +pinlabel=(PCINT1/OC1A) PB1 +T 3350 7700 5 8 0 1 0 8 1 +pintype=io +} +P 3700 7300 3400 7300 1 0 0 +{ +T 3500 7350 5 8 1 1 0 0 1 +pinnumber=14 +T 3500 7250 5 8 0 1 0 2 1 +pinseq=14 +T 3350 7300 9 8 1 1 0 6 1 +pinlabel=(PCINT2/\_SS\_/OC1B) PB2 +T 3350 7300 5 8 0 1 0 8 1 +pintype=io +} +P 3700 6900 3400 6900 1 0 0 +{ +T 3500 6950 5 8 1 1 0 0 1 +pinnumber=15 +T 3500 6850 5 8 0 1 0 2 1 +pinseq=15 +T 3350 6900 9 8 1 1 0 6 1 +pinlabel=(PCINT3/OC2A/MOSI) PB3 +T 3350 6900 5 8 0 1 0 8 1 +pintype=io +} +P 3700 6500 3400 6500 1 0 0 +{ +T 3500 6550 5 8 1 1 0 0 1 +pinnumber=16 +T 3500 6450 5 8 0 1 0 2 1 +pinseq=16 +T 3350 6500 9 8 1 1 0 6 1 +pinlabel=(PCINT4/MISO) PB4 +T 3350 6500 5 8 0 1 0 8 1 +pintype=io +} +P 3700 6100 3400 6100 1 0 0 +{ +T 3500 6150 5 8 1 1 0 0 1 +pinnumber=17 +T 3500 6050 5 8 0 1 0 2 1 +pinseq=17 +T 3350 6100 9 8 1 1 0 6 1 +pinlabel=(SCK/PCINT5) PB5 +T 3350 6100 5 8 0 1 0 8 1 +pintype=io +} +P 3700 5700 3400 5700 1 0 0 +{ +T 3500 5750 5 8 1 1 0 0 1 +pinnumber=23 +T 3500 5650 5 8 0 1 0 2 1 +pinseq=23 +T 3350 5700 9 8 1 1 0 6 1 +pinlabel=(ADC0/PCINT8) PC0 +T 3350 5700 5 8 0 1 0 8 1 +pintype=io +} +P 3700 5300 3400 5300 1 0 0 +{ +T 3500 5350 5 8 1 1 0 0 1 +pinnumber=24 +T 3500 5250 5 8 0 1 0 2 1 +pinseq=24 +T 3350 5300 9 8 1 1 0 6 1 +pinlabel=(ADC1/PCINT9) PC1 +T 3350 5300 5 8 0 1 0 8 1 +pintype=io +} +P 3700 4900 3400 4900 1 0 0 +{ +T 3500 4950 5 8 1 1 0 0 1 +pinnumber=25 +T 3500 4850 5 8 0 1 0 2 1 +pinseq=25 +T 3350 4900 9 8 1 1 0 6 1 +pinlabel=(ADC2/PCINT10) PC2 +T 3350 4900 5 8 0 1 0 8 1 +pintype=io +} +P 3700 4500 3400 4500 1 0 0 +{ +T 3500 4550 5 8 1 1 0 0 1 +pinnumber=26 +T 3500 4450 5 8 0 1 0 2 1 +pinseq=26 +T 3350 4500 9 8 1 1 0 6 1 +pinlabel=(ADC3/PCINT11) PC3 +T 3350 4500 5 8 0 1 0 8 1 +pintype=io +} +P 3700 4100 3400 4100 1 0 0 +{ +T 3500 4150 5 8 1 1 0 0 1 +pinnumber=27 +T 3500 4050 5 8 0 1 0 2 1 +pinseq=27 +T 3350 4100 9 8 1 1 0 6 1 +pinlabel=(ADC4/SDA/PCINT12) PC4 +T 3350 4100 5 8 0 1 0 8 1 +pintype=io +} +P 3700 3700 3400 3700 1 0 0 +{ +T 3500 3750 5 8 1 1 0 0 1 +pinnumber=28 +T 3500 3650 5 8 0 1 0 2 1 +pinseq=28 +T 3350 3700 9 8 1 1 0 6 1 +pinlabel=(ADC5/SCL/PCINT13) PC5 +T 3350 3700 5 8 0 1 0 8 1 +pintype=io +} +P 3700 3300 3400 3300 1 0 0 +{ +T 3500 3350 5 8 1 1 0 0 1 +pinnumber=30 +T 3500 3250 5 8 0 1 0 2 1 +pinseq=30 +T 3350 3300 9 8 1 1 0 6 1 +pinlabel=(RXD/PCINT16) PD0 +T 3350 3300 5 8 0 1 0 8 1 +pintype=io +} +P 3700 2900 3400 2900 1 0 0 +{ +T 3500 2950 5 8 1 1 0 0 1 +pinnumber=31 +T 3500 2850 5 8 0 1 0 2 1 +pinseq=31 +T 3350 2900 9 8 1 1 0 6 1 +pinlabel=(TXD/PCINT17) PD1 +T 3350 2900 5 8 0 1 0 8 1 +pintype=io +} +P 3700 2500 3400 2500 1 0 0 +{ +T 3500 2550 5 8 1 1 0 0 1 +pinnumber=32 +T 3500 2450 5 8 0 1 0 2 1 +pinseq=32 +T 3350 2500 9 8 1 1 0 6 1 +pinlabel=(INT0/PCINT18) PD2 +T 3350 2500 5 8 0 1 0 8 1 +pintype=io +} +P 3700 2100 3400 2100 1 0 0 +{ +T 3500 2150 5 8 1 1 0 0 1 +pinnumber=1 +T 3500 2050 5 8 0 1 0 2 1 +pinseq=1 +T 3350 2100 9 8 1 1 0 6 1 +pinlabel=(PCINT19/OC2B/INT1) PD3 +T 3350 2100 5 8 0 1 0 8 1 +pintype=io +} +P 3700 1700 3400 1700 1 0 0 +{ +T 3500 1750 5 8 1 1 0 0 1 +pinnumber=2 +T 3500 1650 5 8 0 1 0 2 1 +pinseq=2 +T 3350 1700 9 8 1 1 0 6 1 +pinlabel=(PCINT20/XCK/T0) PD4 +T 3350 1700 5 8 0 1 0 8 1 +pintype=io +} +P 3700 1300 3400 1300 1 0 0 +{ +T 3500 1350 5 8 1 1 0 0 1 +pinnumber=9 +T 3500 1250 5 8 0 1 0 2 1 +pinseq=9 +T 3350 1300 9 8 1 1 0 6 1 +pinlabel=(PCINT21/OC0B/T1) PD5 +T 3350 1300 5 8 0 1 0 8 1 +pintype=io +} +P 3700 900 3400 900 1 0 0 +{ +T 3500 950 5 8 1 1 0 0 1 +pinnumber=10 +T 3500 850 5 8 0 1 0 2 1 +pinseq=10 +T 3350 900 9 8 1 1 0 6 1 +pinlabel=(PCINT22/OC0A/AIN0) PD6 +T 3350 900 5 8 0 1 0 8 1 +pintype=io +} +P 3700 500 3400 500 1 0 0 +{ +T 3500 550 5 8 1 1 0 0 1 +pinnumber=11 +T 3500 450 5 8 0 1 0 2 1 +pinseq=11 +T 3350 500 9 8 1 1 0 6 1 +pinlabel=(PCINT23/AIN1) PD7 +T 3350 500 5 8 0 1 0 8 1 +pintype=io +} +P 100 8100 400 8100 1 0 0 +{ +T 300 8150 5 8 1 1 0 6 1 +pinnumber=19 +T 300 8050 5 8 0 1 0 8 1 +pinseq=19 +T 450 8100 9 8 1 1 0 0 1 +pinlabel=ADC6 +T 450 8100 5 8 0 1 0 2 1 +pintype=in +} +P 100 7700 400 7700 1 0 0 +{ +T 300 7750 5 8 1 1 0 6 1 +pinnumber=22 +T 300 7650 5 8 0 1 0 8 1 +pinseq=22 +T 450 7700 9 8 1 1 0 0 1 +pinlabel=ADC7 +T 450 7700 5 8 0 1 0 2 1 +pintype=in +} +P 100 7300 400 7300 1 0 0 +{ +T 300 7350 5 8 1 1 0 6 1 +pinnumber=20 +T 300 7250 5 8 0 1 0 8 1 +pinseq=20 +T 450 7300 9 8 1 1 0 0 1 +pinlabel=AREF +T 450 7300 5 8 0 1 0 2 1 +pintype=in +} +P 100 6900 400 6900 1 0 0 +{ +T 300 6950 5 8 1 1 0 6 1 +pinnumber=18 +T 300 6850 5 8 0 1 0 8 1 +pinseq=18 +T 450 6900 9 8 1 1 0 0 1 +pinlabel=AVCC +T 450 6900 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 6500 400 6500 1 0 0 +{ +T 300 6550 5 8 1 1 0 6 1 +pinnumber=3 +T 300 6450 5 8 0 1 0 8 1 +pinseq=3 +T 450 6500 9 8 1 1 0 0 1 +pinlabel=GND +T 450 6500 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 6100 400 6100 1 0 0 +{ +T 300 6150 5 8 1 1 0 6 1 +pinnumber=5 +T 300 6050 5 8 0 1 0 8 1 +pinseq=5 +T 450 6100 9 8 1 1 0 0 1 +pinlabel=GND +T 450 6100 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 5700 400 5700 1 0 0 +{ +T 300 5750 5 8 1 1 0 6 1 +pinnumber=21 +T 300 5650 5 8 0 1 0 8 1 +pinseq=21 +T 450 5700 9 8 1 1 0 0 1 +pinlabel=GND +T 450 5700 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 5300 400 5300 1 0 0 +{ +T 300 5350 5 8 1 1 0 6 1 +pinnumber=7 +T 300 5250 5 8 0 1 0 8 1 +pinseq=7 +T 525 5300 9 8 1 1 0 0 1 +pinlabel=PB6 (PCINT6/XTAL1/TOSC1) +T 525 5300 5 8 0 1 0 2 1 +pintype=clk +} +L 500 5300 400 5375 3 0 0 0 -1 -1 +L 500 5300 400 5225 3 0 0 0 -1 -1 +P 100 4900 400 4900 1 0 0 +{ +T 300 4950 5 8 1 1 0 6 1 +pinnumber=8 +T 300 4850 5 8 0 1 0 8 1 +pinseq=8 +T 525 4900 9 8 1 1 0 0 1 +pinlabel=PB7 (PCINT7/XTAL2/TOSC2) +T 525 4900 5 8 0 1 0 2 1 +pintype=clk +} +L 500 4900 400 4975 3 0 0 0 -1 -1 +L 500 4900 400 4825 3 0 0 0 -1 -1 +P 100 4500 300 4500 1 0 0 +{ +T 300 4550 5 8 1 1 0 6 1 +pinnumber=29 +T 300 4450 5 8 0 1 0 8 1 +pinseq=29 +T 450 4500 9 8 1 1 0 0 1 +pinlabel=PC6 (\_RESET\_/PCINT14) +T 450 4500 5 8 0 1 0 2 1 +pintype=in +} +V 350 4500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 4100 400 4100 1 0 0 +{ +T 300 4150 5 8 1 1 0 6 1 +pinnumber=4 +T 300 4050 5 8 0 1 0 8 1 +pinseq=4 +T 450 4100 9 8 1 1 0 0 1 +pinlabel=VCC +T 450 4100 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 3700 400 3700 1 0 0 +{ +T 300 3750 5 8 1 1 0 6 1 +pinnumber=6 +T 300 3650 5 8 0 1 0 8 1 +pinseq=6 +T 450 3700 9 8 1 1 0 0 1 +pinlabel=VCC +T 450 3700 5 8 0 1 0 2 1 +pintype=pwr +} +B 400 100 3000 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 3400 8600 8 10 1 1 0 6 1 +refdes=U? +T 400 8600 9 10 1 0 0 0 1 +ATmega168 TQFP +T 400 8800 5 10 0 0 0 0 1 +device=ATMEGA168 +T 400 9000 5 10 0 0 0 0 1 +footprint=TQFP32 +T 400 9200 5 10 0 0 0 0 1 +author=Dan Fekete +T 400 9400 5 10 0 0 0 0 1 +documentation=http://www.atmel.com/dyn/resources/prod_documents/doc8271.pdf +T 400 9600 5 10 0 0 0 0 1 +description=8 bit Atmel MicroController +T 400 9800 5 10 0 0 0 0 1 +numslots=0 +T 400 10000 5 10 0 0 0 0 1 +dist-license=GNU GPL +T 400 10200 5 10 0 0 0 0 1 +use-license=Unlimited diff --git a/gschem-sym/ATmega168-TQFP-arduino-1.sym b/gschem-sym/ATmega168-TQFP-arduino-1.sym new file mode 100644 index 0000000..5cf9de0 --- /dev/null +++ b/gschem-sym/ATmega168-TQFP-arduino-1.sym @@ -0,0 +1,379 @@ +v 20100214 2 +P 2800 4800 2500 4800 1 0 0 +{ +T 2550 4850 5 8 1 1 0 0 1 +pinnumber=23 +T 2600 4750 5 8 0 1 0 2 1 +pinseq=23 +T 2450 4800 9 8 1 1 0 6 1 +pinlabel=(PC0) A0 +T 2450 4800 5 8 0 1 0 8 1 +pintype=io +} +P 2800 4600 2500 4600 1 0 0 +{ +T 2550 4650 5 8 1 1 0 0 1 +pinnumber=24 +T 2600 4550 5 8 0 1 0 2 1 +pinseq=24 +T 2450 4600 9 8 1 1 0 6 1 +pinlabel=(PC1) A1 +T 2450 4600 5 8 0 1 0 8 1 +pintype=io +} +P 2800 4400 2500 4400 1 0 0 +{ +T 2550 4450 5 8 1 1 0 0 1 +pinnumber=25 +T 2600 4350 5 8 0 1 0 2 1 +pinseq=25 +T 2450 4400 9 8 1 1 0 6 1 +pinlabel=(PC2) A2 +T 2450 4400 5 8 0 1 0 8 1 +pintype=io +} +P 2800 4200 2500 4200 1 0 0 +{ +T 2550 4250 5 8 1 1 0 0 1 +pinnumber=26 +T 2600 4150 5 8 0 1 0 2 1 +pinseq=26 +T 2450 4200 9 8 1 1 0 6 1 +pinlabel=(PC3) A3 +T 2450 4200 5 8 0 1 0 8 1 +pintype=io +} +P 2800 4000 2500 4000 1 0 0 +{ +T 2550 4050 5 8 1 1 0 0 1 +pinnumber=27 +T 2600 3950 5 8 0 1 0 2 1 +pinseq=27 +T 2450 4000 9 8 1 1 0 6 1 +pinlabel=(PC4/SDA) A4 +T 2450 4000 5 8 0 1 0 8 1 +pintype=io +} +P 2800 3800 2500 3800 1 0 0 +{ +T 2550 3850 5 8 1 1 0 0 1 +pinnumber=28 +T 2600 3750 5 8 0 1 0 2 1 +pinseq=28 +T 2450 3800 9 8 1 1 0 6 1 +pinlabel=(PC5/SCL) A5 +T 2450 3800 5 8 0 1 0 8 1 +pintype=io +} +P 2800 3600 2500 3600 1 0 0 +{ +T 2550 3650 5 8 1 1 0 0 1 +pinnumber=19 +T 2600 3550 5 8 0 1 0 2 1 +pinseq=19 +T 2450 3600 9 8 1 1 0 6 1 +pinlabel=(ADC6) A6 +T 2450 3600 5 8 0 1 0 8 1 +pintype=in +} +P 2800 3400 2500 3400 1 0 0 +{ +T 2550 3450 5 8 1 1 0 0 1 +pinnumber=22 +T 2600 3350 5 8 0 1 0 2 1 +pinseq=22 +T 2450 3400 9 8 1 1 0 6 1 +pinlabel=(ADC7) A7 +T 2450 3400 5 8 0 1 0 8 1 +pintype=in +} +P 2800 3000 2500 3000 1 0 0 +{ +T 2550 3050 5 8 1 1 0 0 1 +pinnumber=30 +T 2600 2950 5 8 0 1 0 2 1 +pinseq=30 +T 2450 3000 9 8 1 1 0 6 1 +pinlabel=(PD0/RXD) D0 +T 2450 3000 5 8 0 1 0 8 1 +pintype=io +} +P 2800 2800 2500 2800 1 0 0 +{ +T 2550 2850 5 8 1 1 0 0 1 +pinnumber=31 +T 2600 2750 5 8 0 1 0 2 1 +pinseq=31 +T 2450 2800 9 8 1 1 0 6 1 +pinlabel=(PD1/TXD) D1 +T 2450 2800 5 8 0 1 0 8 1 +pintype=io +} +P 2800 2600 2500 2600 1 0 0 +{ +T 2550 2650 5 8 1 1 0 0 1 +pinnumber=32 +T 2600 2550 5 8 0 1 0 2 1 +pinseq=32 +T 2450 2600 9 8 1 1 0 6 1 +pinlabel=(PD2/INT0) D2 +T 2450 2600 5 8 0 1 0 8 1 +pintype=io +} +P 2800 2400 2500 2400 1 0 0 +{ +T 2550 2450 5 8 1 1 0 0 1 +pinnumber=1 +T 2600 2350 5 8 0 1 0 2 1 +pinseq=1 +T 2450 2400 9 8 1 1 0 6 1 +pinlabel=(PD3/INT1) D3 +T 2450 2400 5 8 0 1 0 8 1 +pintype=io +} +P 2800 2200 2500 2200 1 0 0 +{ +T 2550 2250 5 8 1 1 0 0 1 +pinnumber=2 +T 2600 2150 5 8 0 1 0 2 1 +pinseq=2 +T 2450 2200 9 8 1 1 0 6 1 +pinlabel=(PD4) D4 +T 2450 2200 5 8 0 1 0 8 1 +pintype=io +} +P 2800 2000 2500 2000 1 0 0 +{ +T 2550 2050 5 8 1 1 0 0 1 +pinnumber=9 +T 2600 1950 5 8 0 1 0 2 1 +pinseq=9 +T 2450 2000 9 8 1 1 0 6 1 +pinlabel=(PD5) D5 +T 2450 2000 5 8 0 1 0 8 1 +pintype=io +} +P 2800 1800 2500 1800 1 0 0 +{ +T 2550 1850 5 8 1 1 0 0 1 +pinnumber=10 +T 2600 1750 5 8 0 1 0 2 1 +pinseq=10 +T 2450 1800 9 8 1 1 0 6 1 +pinlabel=(PD6/AIN0) D6 +T 2450 1800 5 8 0 1 0 8 1 +pintype=io +} +P 2800 1600 2500 1600 1 0 0 +{ +T 2550 1650 5 8 1 1 0 0 1 +pinnumber=11 +T 2600 1550 5 8 0 1 0 2 1 +pinseq=11 +T 2450 1600 9 8 1 1 0 6 1 +pinlabel=(PD7/AIN1) D7 +T 2450 1600 5 8 0 1 0 8 1 +pintype=io +} +P 2800 1400 2500 1400 1 0 0 +{ +T 2550 1450 5 8 1 1 0 0 1 +pinnumber=12 +T 2600 1350 5 8 0 1 0 2 1 +pinseq=12 +T 2450 1400 9 8 1 1 0 6 1 +pinlabel=(PB0/ICP1) D8 +T 2450 1400 5 8 0 1 0 8 1 +pintype=io +} +P 2800 1200 2500 1200 1 0 0 +{ +T 2550 1250 5 8 1 1 0 0 1 +pinnumber=13 +T 2600 1150 5 8 0 1 0 2 1 +pinseq=13 +T 2450 1200 9 8 1 1 0 6 1 +pinlabel=(PB1) D9 +T 2450 1200 5 8 0 1 0 8 1 +pintype=io +} +P 2800 1000 2500 1000 1 0 0 +{ +T 2550 1050 5 8 1 1 0 0 1 +pinnumber=14 +T 2600 950 5 8 0 1 0 2 1 +pinseq=14 +T 2450 1000 9 8 1 1 0 6 1 +pinlabel=(PB2/\_SS\_) D10 +T 2450 1000 5 8 0 1 0 8 1 +pintype=io +} +P 2800 800 2500 800 1 0 0 +{ +T 2550 850 5 8 1 1 0 0 1 +pinnumber=15 +T 2600 750 5 8 0 1 0 2 1 +pinseq=15 +T 2450 800 9 8 1 1 0 6 1 +pinlabel=(PB3/MOSI) D11 +T 2450 800 5 8 0 1 0 8 1 +pintype=io +} +P 2800 600 2500 600 1 0 0 +{ +T 2550 650 5 8 1 1 0 0 1 +pinnumber=16 +T 2600 550 5 8 0 1 0 2 1 +pinseq=16 +T 2450 600 9 8 1 1 0 6 1 +pinlabel=(PB4/MISO) D12 +T 2450 600 5 8 0 1 0 8 1 +pintype=io +} +P 2800 400 2500 400 1 0 0 +{ +T 2550 450 5 8 1 1 0 0 1 +pinnumber=17 +T 2600 350 5 8 0 1 0 2 1 +pinseq=17 +T 2450 400 9 8 1 1 0 6 1 +pinlabel=(PB5/SCK) D13 +T 2450 400 5 8 0 1 0 8 1 +pintype=io +} +P 0 2800 300 2800 1 0 0 +{ +T 250 2850 5 8 1 1 0 6 1 +pinnumber=20 +T 200 2750 5 8 0 1 0 8 1 +pinseq=20 +T 350 2800 9 8 1 1 0 0 1 +pinlabel=AREF +T 350 2800 5 8 0 1 0 2 1 +pintype=in +} +P 0 4000 300 4000 1 0 0 +{ +T 250 4050 5 8 1 1 0 6 1 +pinnumber=18 +T 200 3950 5 8 0 1 0 8 1 +pinseq=18 +T 350 4000 9 8 1 1 0 0 1 +pinlabel=AVCC +T 350 4000 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 1000 300 1000 1 0 0 +{ +T 250 1050 5 8 1 1 0 6 1 +pinnumber=3 +T 200 950 5 8 0 1 0 8 1 +pinseq=3 +T 350 1000 9 8 1 1 0 0 1 +pinlabel=GND +T 350 1000 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 800 300 800 1 0 0 +{ +T 250 850 5 8 1 1 0 6 1 +pinnumber=5 +T 200 750 5 8 0 1 0 8 1 +pinseq=5 +T 350 800 9 8 1 1 0 0 1 +pinlabel=GND +T 350 800 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 600 300 600 1 0 0 +{ +T 250 650 5 8 1 1 0 6 1 +pinnumber=21 +T 200 550 5 8 0 1 0 8 1 +pinseq=21 +T 350 600 9 8 1 1 0 0 1 +pinlabel=GND +T 350 600 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 4800 200 4800 1 0 0 +{ +T 250 4850 5 8 1 1 0 6 1 +pinnumber=29 +T 200 4750 5 8 0 1 0 8 1 +pinseq=29 +T 350 4800 9 8 1 1 0 0 1 +pinlabel=\_RESET\_ (PC6) +T 350 4800 5 8 0 1 0 2 1 +pintype=in +} +V 250 4800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 0 3800 300 3800 1 0 0 +{ +T 250 3850 5 8 1 1 0 6 1 +pinnumber=4 +T 200 3750 5 8 0 1 0 8 1 +pinseq=4 +T 350 3800 9 8 1 1 0 0 1 +pinlabel=VCC +T 350 3800 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 3600 300 3600 1 0 0 +{ +T 250 3650 5 8 1 1 0 6 1 +pinnumber=6 +T 200 3550 5 8 0 1 0 8 1 +pinseq=6 +T 350 3600 9 8 1 1 0 0 1 +pinlabel=VCC +T 350 3600 5 8 0 1 0 2 1 +pintype=pwr +} +P 0 2000 300 2000 1 0 0 +{ +T 250 2050 5 8 1 1 0 6 1 +pinnumber=7 +T 200 1950 5 8 0 1 0 8 1 +pinseq=7 +T 425 2000 9 8 1 1 0 0 1 +pinlabel=XTAL1 (PB6) +T 425 2000 5 8 0 1 0 2 1 +pintype=clk +} +L 400 2000 300 2075 3 0 0 0 -1 -1 +L 400 2000 300 1925 3 0 0 0 -1 -1 +P 0 1800 300 1800 1 0 0 +{ +T 250 1850 5 8 1 1 0 6 1 +pinnumber=8 +T 200 1750 5 8 0 1 0 8 1 +pinseq=8 +T 425 1800 9 8 1 1 0 0 1 +pinlabel=XTAL2 (PB7) +T 425 1800 5 8 0 1 0 2 1 +pintype=clk +} +L 400 1800 300 1875 3 0 0 0 -1 -1 +L 400 1800 300 1725 3 0 0 0 -1 -1 +B 300 200 2200 5000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 2500 5250 8 10 1 1 0 6 1 +refdes=U? +T 300 150 9 10 1 0 0 2 1 +ATmega168 TQFP Arduino +T 300 7400 5 10 0 0 0 0 1 +device=ATMEGA168 +T 300 7200 5 10 0 0 0 0 1 +footprint=TQFP32 +T 300 6400 5 10 0 0 0 0 1 +author=Dan Fekete +T 300 6800 5 10 0 0 0 0 1 +documentation=http://www.atmel.com/dyn/resources/prod_documents/doc8271.pdf +T 300 7000 5 10 0 0 0 0 1 +description=8 bit Atmel MicroController +T 300 5600 5 10 0 0 0 0 1 +numslots=0 +T 300 6000 5 10 0 0 0 0 1 +dist-license=GNU GPL +T 300 6200 5 10 0 0 0 0 1 +use-license=Unlimited diff --git a/gschem-sym/ATmega168_TQFP.sym b/gschem-sym/ATmega168_TQFP.sym new file mode 100644 index 0000000..096302f --- /dev/null +++ b/gschem-sym/ATmega168_TQFP.sym @@ -0,0 +1,476 @@ +v 20110115 2 +T 3000 8900 8 10 1 1 0 6 1 +refdes=U? +T 400 9050 5 10 0 0 0 0 1 +device=ATmega168_TQFP +T 400 9250 5 10 0 0 0 0 1 +footprint=TQFP44 +P 2300 100 2300 300 1 0 0 +{ +T 2350 200 5 8 1 1 0 0 1 +pinnumber=4 +T 2350 200 5 8 0 1 0 2 1 +pinseq=4 +T 2300 450 9 8 1 1 0 3 1 +pinlabel=Reset +T 2300 600 5 8 0 1 0 3 1 +pintype=in +} +L 2108 574 2492 574 3 0 0 0 -1 -1 +V 2300 350 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1700 100 1700 400 1 0 0 +{ +T 1750 200 5 8 1 1 0 0 1 +pinnumber=7 +T 1750 200 5 8 0 1 0 2 1 +pinseq=7 +T 1700 450 9 8 1 1 0 3 1 +pinlabel=XTAL2 +T 1700 600 5 8 0 1 0 3 1 +pintype=out +} +P 1100 100 1100 400 1 0 0 +{ +T 1150 200 5 8 1 1 0 0 1 +pinnumber=8 +T 1150 200 5 8 0 1 0 2 1 +pinseq=8 +T 1100 450 9 8 1 1 0 3 1 +pinlabel=XTAL1 +T 1100 600 5 8 0 1 0 3 1 +pintype=in +} +P 100 2200 400 2200 1 0 0 +{ +T 300 2250 5 8 1 1 0 6 1 +pinnumber=16 +T 300 2150 5 8 0 1 0 8 1 +pinseq=16 +T 450 2200 9 8 1 1 0 0 1 +pinlabel=PD7 (OC2) +T 450 2200 5 8 0 1 0 2 1 +pintype=io +} +P 100 2600 400 2600 1 0 0 +{ +T 300 2650 5 8 1 1 0 6 1 +pinnumber=15 +T 300 2550 5 8 0 1 0 8 1 +pinseq=15 +T 450 2600 9 8 1 1 0 0 1 +pinlabel=PD6 (ICP1) +T 450 2600 5 8 0 1 0 2 1 +pintype=io +} +P 100 3000 400 3000 1 0 0 +{ +T 300 3050 5 8 1 1 0 6 1 +pinnumber=14 +T 300 2950 5 8 0 1 0 8 1 +pinseq=14 +T 450 3000 9 8 1 1 0 0 1 +pinlabel=PD5 (OC1A) +T 450 3000 5 8 0 1 0 2 1 +pintype=io +} +P 100 3400 400 3400 1 0 0 +{ +T 300 3450 5 8 1 1 0 6 1 +pinnumber=13 +T 300 3350 5 8 0 1 0 8 1 +pinseq=13 +T 450 3400 9 8 1 1 0 0 1 +pinlabel=PD4 (OC1B) +T 450 3400 5 8 0 1 0 2 1 +pintype=io +} +P 100 3800 400 3800 1 0 0 +{ +T 300 3850 5 8 1 1 0 6 1 +pinnumber=12 +T 300 3750 5 8 0 1 0 8 1 +pinseq=12 +T 450 3800 9 8 1 1 0 0 1 +pinlabel=PD3 (INT1) +T 450 3800 5 8 0 1 0 2 1 +pintype=io +} +P 100 4200 400 4200 1 0 0 +{ +T 300 4250 5 8 1 1 0 6 1 +pinnumber=11 +T 300 4150 5 8 0 1 0 8 1 +pinseq=11 +T 450 4200 9 8 1 1 0 0 1 +pinlabel=PD2 (INT0) +T 450 4200 5 8 0 1 0 2 1 +pintype=io +} +P 100 4600 400 4600 1 0 0 +{ +T 300 4650 5 8 1 1 0 6 1 +pinnumber=10 +T 300 4550 5 8 0 1 0 8 1 +pinseq=10 +T 450 4600 9 8 1 1 0 0 1 +pinlabel=PD1 (TXD) +T 450 4600 5 8 0 1 0 2 1 +pintype=io +} +P 100 5000 400 5000 1 0 0 +{ +T 300 5050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 4950 5 8 0 1 0 8 1 +pinseq=9 +T 450 5000 9 8 1 1 0 0 1 +pinlabel=PD0 (RXD) +T 450 5000 5 8 0 1 0 2 1 +pintype=io +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=3 +T 300 5550 5 8 0 1 0 8 1 +pinseq=3 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=PB7 (SCK) +T 450 5600 5 8 0 1 0 2 1 +pintype=io +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=2 +T 300 5950 5 8 0 1 0 8 1 +pinseq=2 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=PB6 (MISO) +T 450 6000 5 8 0 1 0 2 1 +pintype=io +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=1 +T 300 6350 5 8 0 1 0 8 1 +pinseq=1 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=PB5 (MOSI) +T 450 6400 5 8 0 1 0 2 1 +pintype=io +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=44 +T 300 6750 5 8 0 1 0 8 1 +pinseq=44 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=PB4 (SS) +T 450 6800 5 8 0 1 0 2 1 +pintype=io +} +L 862 6924 1062 6924 3 0 0 0 -1 -1 +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=43 +T 300 7150 5 8 0 1 0 8 1 +pinseq=43 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=PB3 (AIN1/OC0) +T 450 7200 5 8 0 1 0 2 1 +pintype=io +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=42 +T 300 7550 5 8 0 1 0 8 1 +pinseq=42 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=PB2 (AIN0/INT2) +T 450 7600 5 8 0 1 0 2 1 +pintype=io +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=41 +T 300 7950 5 8 0 1 0 8 1 +pinseq=41 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=PB1 (T1) +T 450 8000 5 8 0 1 0 2 1 +pintype=io +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=40 +T 300 8350 5 8 0 1 0 8 1 +pinseq=40 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=PB0 (XCK/T0) +T 450 8400 5 8 0 1 0 2 1 +pintype=io +} +P 3300 2200 3000 2200 1 0 0 +{ +T 3100 2250 5 8 1 1 0 0 1 +pinnumber=26 +T 3100 2150 5 8 0 1 0 2 1 +pinseq=26 +T 2950 2200 9 8 1 1 0 6 1 +pinlabel=(TOSC2) PC7 +T 2950 2200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 2600 3000 2600 1 0 0 +{ +T 3100 2650 5 8 1 1 0 0 1 +pinnumber=25 +T 3100 2550 5 8 0 1 0 2 1 +pinseq=25 +T 2950 2600 9 8 1 1 0 6 1 +pinlabel=(TOSC1) PC6 +T 2950 2600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3000 3000 3000 1 0 0 +{ +T 3100 3050 5 8 1 1 0 0 1 +pinnumber=24 +T 3100 2950 5 8 0 1 0 2 1 +pinseq=24 +T 2950 3000 9 8 1 1 0 6 1 +pinlabel=(TDI) PC5 +T 2950 3000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3400 3000 3400 1 0 0 +{ +T 3100 3450 5 8 1 1 0 0 1 +pinnumber=23 +T 3100 3350 5 8 0 1 0 2 1 +pinseq=23 +T 2950 3400 9 8 1 1 0 6 1 +pinlabel=(TDO) PC4 +T 2950 3400 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3800 3000 3800 1 0 0 +{ +T 3100 3850 5 8 1 1 0 0 1 +pinnumber=22 +T 3100 3750 5 8 0 1 0 2 1 +pinseq=22 +T 2950 3800 9 8 1 1 0 6 1 +pinlabel=(TMS) PC3 +T 2950 3800 5 8 0 1 0 8 1 +pintype=io +} +P 3300 4200 3000 4200 1 0 0 +{ +T 3100 4250 5 8 1 1 0 0 1 +pinnumber=21 +T 3100 4150 5 8 0 1 0 2 1 +pinseq=21 +T 2950 4200 9 8 1 1 0 6 1 +pinlabel=(TCK) PC2 +T 2950 4200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 4600 3000 4600 1 0 0 +{ +T 3100 4650 5 8 1 1 0 0 1 +pinnumber=20 +T 3100 4550 5 8 0 1 0 2 1 +pinseq=20 +T 2950 4600 9 8 1 1 0 6 1 +pinlabel=(SDA) PC1 +T 2950 4600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 5000 3000 5000 1 0 0 +{ +T 3100 5050 5 8 1 1 0 0 1 +pinnumber=19 +T 3100 4950 5 8 0 1 0 2 1 +pinseq=19 +T 2950 5000 9 8 1 1 0 6 1 +pinlabel=(SCL) PC0 +T 2950 5000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 5600 3000 5600 1 0 0 +{ +T 3100 5650 5 8 1 1 0 0 1 +pinnumber=30 +T 3100 5550 5 8 0 1 0 2 1 +pinseq=30 +T 2950 5600 9 8 1 1 0 6 1 +pinlabel=(ADC7) PA7 +T 2950 5600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6000 3000 6000 1 0 0 +{ +T 3100 6050 5 8 1 1 0 0 1 +pinnumber=31 +T 3100 5950 5 8 0 1 0 2 1 +pinseq=31 +T 2950 6000 9 8 1 1 0 6 1 +pinlabel=(ADC6) PA6 +T 2950 6000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6400 3000 6400 1 0 0 +{ +T 3100 6450 5 8 1 1 0 0 1 +pinnumber=32 +T 3100 6350 5 8 0 1 0 2 1 +pinseq=32 +T 2950 6400 9 8 1 1 0 6 1 +pinlabel=(ADC5) PA5 +T 2950 6400 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6800 3000 6800 1 0 0 +{ +T 3100 6850 5 8 1 1 0 0 1 +pinnumber=33 +T 3100 6750 5 8 0 1 0 2 1 +pinseq=33 +T 2950 6800 9 8 1 1 0 6 1 +pinlabel=(ADC4) PA4 +T 2950 6800 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7200 3000 7200 1 0 0 +{ +T 3100 7250 5 8 1 1 0 0 1 +pinnumber=34 +T 3100 7150 5 8 0 1 0 2 1 +pinseq=34 +T 2950 7200 9 8 1 1 0 6 1 +pinlabel=(ADC3) PA3 +T 2950 7200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7600 3000 7600 1 0 0 +{ +T 3100 7650 5 8 1 1 0 0 1 +pinnumber=35 +T 3100 7550 5 8 0 1 0 2 1 +pinseq=35 +T 2950 7600 9 8 1 1 0 6 1 +pinlabel=(ADC2) PA2 +T 2950 7600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8000 3000 8000 1 0 0 +{ +T 3100 8050 5 8 1 1 0 0 1 +pinnumber=36 +T 3100 7950 5 8 0 1 0 2 1 +pinseq=36 +T 2950 8000 9 8 1 1 0 6 1 +pinlabel=(ADC1) PA1 +T 2950 8000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8400 3000 8400 1 0 0 +{ +T 3100 8450 5 8 1 1 0 0 1 +pinnumber=37 +T 3100 8350 5 8 0 1 0 2 1 +pinseq=37 +T 2950 8400 9 8 1 1 0 6 1 +pinlabel=(ADC0) PA0 +T 2950 8400 5 8 0 1 0 8 1 +pintype=io +} +B 400 400 2600 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 9850 5 10 0 0 0 0 1 +description=8-bit RISC micro controller (Atmel) +T 400 10050 5 10 0 0 0 0 1 +numslots=0 +T 400 10250 5 10 0 0 0 0 1 +author=Matthijs ten Berge +T 400 8850 9 10 1 0 0 0 1 +ATmega16 +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=27 +T 300 1550 5 8 0 1 0 8 1 +pinseq=27 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=AVCC +T 450 1600 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=29 +T 300 1150 5 8 0 1 0 8 1 +pinseq=29 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=AREF +T 450 1200 5 8 0 1 0 2 1 +pintype=io +} +T 0 0 8 10 0 0 0 0 1 +dist-license=GPL +T 1600 0 8 10 0 0 0 0 1 +use-license=unlimited +T 0 200 8 10 0 0 0 0 1 +comment=Suggested library: micro +P 3300 1800 3000 1800 1 0 0 +{ +T 3100 1850 5 8 1 1 0 0 1 +pinnumber=6 +T 3100 1750 5 8 0 1 0 2 1 +pinseq=6 +T 2950 1800 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 1800 5 8 0 1 0 8 1 +pintype=pwr +} +P 3300 1500 3000 1500 1 0 0 +{ +T 3100 1550 5 8 1 1 0 0 1 +pinnumber=18 +T 3100 1450 5 8 0 1 0 2 1 +pinseq=18 +T 2950 1500 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 1500 5 8 0 1 0 8 1 +pintype=pwr +} +P 3300 1200 3000 1200 1 0 0 +{ +T 3100 1250 5 8 1 1 0 0 1 +pinnumber=28 +T 3100 1150 5 8 0 1 0 2 1 +pinseq=28 +T 2950 1200 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 1200 5 8 0 1 0 8 1 +pintype=pwr +} +P 3300 900 3000 900 1 0 0 +{ +T 3100 950 5 8 1 1 0 0 1 +pinnumber=39 +T 3100 850 5 8 0 1 0 2 1 +pinseq=39 +T 2950 900 9 8 1 1 0 6 1 +pinlabel=GND +T 2950 900 5 8 0 1 0 8 1 +pintype=pwr +} diff --git a/gschem-sym/ATmega16_TQFP.sym b/gschem-sym/ATmega16_TQFP.sym new file mode 100644 index 0000000..8c57aa2 --- /dev/null +++ b/gschem-sym/ATmega16_TQFP.sym @@ -0,0 +1,436 @@ +v 20040111 1 +T 3000 8900 8 10 1 1 0 6 1 +refdes=U? +T 400 9050 5 10 0 0 0 0 1 +device=ATmega16_TQFP +T 400 9250 5 10 0 0 0 0 1 +footprint=TQFP44 +T 400 9450 5 10 0 0 0 0 1 +net=GND:6,18,28,39 +T 400 9650 5 10 0 0 0 0 1 +net=Vcc:5,17,38 +P 2300 100 2300 300 1 0 0 +{ +T 2350 200 5 8 1 1 0 0 1 +pinnumber=4 +T 2350 200 5 8 0 1 0 2 1 +pinseq=4 +T 2300 450 9 8 1 1 0 3 1 +pinlabel=Reset +T 2300 600 5 8 0 1 0 3 1 +pintype=in +} +L 2108 574 2492 574 3 0 0 0 -1 -1 +V 2300 350 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1700 100 1700 400 1 0 0 +{ +T 1750 200 5 8 1 1 0 0 1 +pinnumber=7 +T 1750 200 5 8 0 1 0 2 1 +pinseq=7 +T 1700 450 9 8 1 1 0 3 1 +pinlabel=XTAL2 +T 1700 600 5 8 0 1 0 3 1 +pintype=out +} +P 1100 100 1100 400 1 0 0 +{ +T 1150 200 5 8 1 1 0 0 1 +pinnumber=8 +T 1150 200 5 8 0 1 0 2 1 +pinseq=8 +T 1100 450 9 8 1 1 0 3 1 +pinlabel=XTAL1 +T 1100 600 5 8 0 1 0 3 1 +pintype=in +} +P 100 2200 400 2200 1 0 0 +{ +T 300 2250 5 8 1 1 0 6 1 +pinnumber=16 +T 300 2150 5 8 0 1 0 8 1 +pinseq=16 +T 450 2200 9 8 1 1 0 0 1 +pinlabel=PD7 (OC2) +T 450 2200 5 8 0 1 0 2 1 +pintype=io +} +P 100 2600 400 2600 1 0 0 +{ +T 300 2650 5 8 1 1 0 6 1 +pinnumber=15 +T 300 2550 5 8 0 1 0 8 1 +pinseq=15 +T 450 2600 9 8 1 1 0 0 1 +pinlabel=PD6 (ICP1) +T 450 2600 5 8 0 1 0 2 1 +pintype=io +} +P 100 3000 400 3000 1 0 0 +{ +T 300 3050 5 8 1 1 0 6 1 +pinnumber=14 +T 300 2950 5 8 0 1 0 8 1 +pinseq=14 +T 450 3000 9 8 1 1 0 0 1 +pinlabel=PD5 (OC1A) +T 450 3000 5 8 0 1 0 2 1 +pintype=io +} +P 100 3400 400 3400 1 0 0 +{ +T 300 3450 5 8 1 1 0 6 1 +pinnumber=13 +T 300 3350 5 8 0 1 0 8 1 +pinseq=13 +T 450 3400 9 8 1 1 0 0 1 +pinlabel=PD4 (OC1B) +T 450 3400 5 8 0 1 0 2 1 +pintype=io +} +P 100 3800 400 3800 1 0 0 +{ +T 300 3850 5 8 1 1 0 6 1 +pinnumber=12 +T 300 3750 5 8 0 1 0 8 1 +pinseq=12 +T 450 3800 9 8 1 1 0 0 1 +pinlabel=PD3 (INT1) +T 450 3800 5 8 0 1 0 2 1 +pintype=io +} +P 100 4200 400 4200 1 0 0 +{ +T 300 4250 5 8 1 1 0 6 1 +pinnumber=11 +T 300 4150 5 8 0 1 0 8 1 +pinseq=11 +T 450 4200 9 8 1 1 0 0 1 +pinlabel=PD2 (INT0) +T 450 4200 5 8 0 1 0 2 1 +pintype=io +} +P 100 4600 400 4600 1 0 0 +{ +T 300 4650 5 8 1 1 0 6 1 +pinnumber=10 +T 300 4550 5 8 0 1 0 8 1 +pinseq=10 +T 450 4600 9 8 1 1 0 0 1 +pinlabel=PD1 (TXD) +T 450 4600 5 8 0 1 0 2 1 +pintype=io +} +P 100 5000 400 5000 1 0 0 +{ +T 300 5050 5 8 1 1 0 6 1 +pinnumber=9 +T 300 4950 5 8 0 1 0 8 1 +pinseq=9 +T 450 5000 9 8 1 1 0 0 1 +pinlabel=PD0 (RXD) +T 450 5000 5 8 0 1 0 2 1 +pintype=io +} +P 100 5600 400 5600 1 0 0 +{ +T 300 5650 5 8 1 1 0 6 1 +pinnumber=3 +T 300 5550 5 8 0 1 0 8 1 +pinseq=3 +T 450 5600 9 8 1 1 0 0 1 +pinlabel=PB7 (SCK) +T 450 5600 5 8 0 1 0 2 1 +pintype=io +} +P 100 6000 400 6000 1 0 0 +{ +T 300 6050 5 8 1 1 0 6 1 +pinnumber=2 +T 300 5950 5 8 0 1 0 8 1 +pinseq=2 +T 450 6000 9 8 1 1 0 0 1 +pinlabel=PB6 (MISO) +T 450 6000 5 8 0 1 0 2 1 +pintype=io +} +P 100 6400 400 6400 1 0 0 +{ +T 300 6450 5 8 1 1 0 6 1 +pinnumber=1 +T 300 6350 5 8 0 1 0 8 1 +pinseq=1 +T 450 6400 9 8 1 1 0 0 1 +pinlabel=PB5 (MOSI) +T 450 6400 5 8 0 1 0 2 1 +pintype=io +} +P 100 6800 400 6800 1 0 0 +{ +T 300 6850 5 8 1 1 0 6 1 +pinnumber=44 +T 300 6750 5 8 0 1 0 8 1 +pinseq=44 +T 450 6800 9 8 1 1 0 0 1 +pinlabel=PB4 (SS) +T 450 6800 5 8 0 1 0 2 1 +pintype=io +} +L 862 6924 1062 6924 3 0 0 0 -1 -1 +P 100 7200 400 7200 1 0 0 +{ +T 300 7250 5 8 1 1 0 6 1 +pinnumber=43 +T 300 7150 5 8 0 1 0 8 1 +pinseq=43 +T 450 7200 9 8 1 1 0 0 1 +pinlabel=PB3 (AIN1/OC0) +T 450 7200 5 8 0 1 0 2 1 +pintype=io +} +P 100 7600 400 7600 1 0 0 +{ +T 300 7650 5 8 1 1 0 6 1 +pinnumber=42 +T 300 7550 5 8 0 1 0 8 1 +pinseq=42 +T 450 7600 9 8 1 1 0 0 1 +pinlabel=PB2 (AIN0/INT2) +T 450 7600 5 8 0 1 0 2 1 +pintype=io +} +P 100 8000 400 8000 1 0 0 +{ +T 300 8050 5 8 1 1 0 6 1 +pinnumber=41 +T 300 7950 5 8 0 1 0 8 1 +pinseq=41 +T 450 8000 9 8 1 1 0 0 1 +pinlabel=PB1 (T1) +T 450 8000 5 8 0 1 0 2 1 +pintype=io +} +P 100 8400 400 8400 1 0 0 +{ +T 300 8450 5 8 1 1 0 6 1 +pinnumber=40 +T 300 8350 5 8 0 1 0 8 1 +pinseq=40 +T 450 8400 9 8 1 1 0 0 1 +pinlabel=PB0 (XCK/T0) +T 450 8400 5 8 0 1 0 2 1 +pintype=io +} +P 3300 2200 3000 2200 1 0 0 +{ +T 3100 2250 5 8 1 1 0 0 1 +pinnumber=26 +T 3100 2150 5 8 0 1 0 2 1 +pinseq=26 +T 2950 2200 9 8 1 1 0 6 1 +pinlabel=(TOSC2) PC7 +T 2950 2200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 2600 3000 2600 1 0 0 +{ +T 3100 2650 5 8 1 1 0 0 1 +pinnumber=25 +T 3100 2550 5 8 0 1 0 2 1 +pinseq=25 +T 2950 2600 9 8 1 1 0 6 1 +pinlabel=(TOSC1) PC6 +T 2950 2600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3000 3000 3000 1 0 0 +{ +T 3100 3050 5 8 1 1 0 0 1 +pinnumber=24 +T 3100 2950 5 8 0 1 0 2 1 +pinseq=24 +T 2950 3000 9 8 1 1 0 6 1 +pinlabel=(TDI) PC5 +T 2950 3000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3400 3000 3400 1 0 0 +{ +T 3100 3450 5 8 1 1 0 0 1 +pinnumber=23 +T 3100 3350 5 8 0 1 0 2 1 +pinseq=23 +T 2950 3400 9 8 1 1 0 6 1 +pinlabel=(TDO) PC4 +T 2950 3400 5 8 0 1 0 8 1 +pintype=io +} +P 3300 3800 3000 3800 1 0 0 +{ +T 3100 3850 5 8 1 1 0 0 1 +pinnumber=22 +T 3100 3750 5 8 0 1 0 2 1 +pinseq=22 +T 2950 3800 9 8 1 1 0 6 1 +pinlabel=(TMS) PC3 +T 2950 3800 5 8 0 1 0 8 1 +pintype=io +} +P 3300 4200 3000 4200 1 0 0 +{ +T 3100 4250 5 8 1 1 0 0 1 +pinnumber=21 +T 3100 4150 5 8 0 1 0 2 1 +pinseq=21 +T 2950 4200 9 8 1 1 0 6 1 +pinlabel=(TCK) PC2 +T 2950 4200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 4600 3000 4600 1 0 0 +{ +T 3100 4650 5 8 1 1 0 0 1 +pinnumber=20 +T 3100 4550 5 8 0 1 0 2 1 +pinseq=20 +T 2950 4600 9 8 1 1 0 6 1 +pinlabel=(SDA) PC1 +T 2950 4600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 5000 3000 5000 1 0 0 +{ +T 3100 5050 5 8 1 1 0 0 1 +pinnumber=19 +T 3100 4950 5 8 0 1 0 2 1 +pinseq=19 +T 2950 5000 9 8 1 1 0 6 1 +pinlabel=(SCL) PC0 +T 2950 5000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 5600 3000 5600 1 0 0 +{ +T 3100 5650 5 8 1 1 0 0 1 +pinnumber=30 +T 3100 5550 5 8 0 1 0 2 1 +pinseq=30 +T 2950 5600 9 8 1 1 0 6 1 +pinlabel=(ADC7) PA7 +T 2950 5600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6000 3000 6000 1 0 0 +{ +T 3100 6050 5 8 1 1 0 0 1 +pinnumber=31 +T 3100 5950 5 8 0 1 0 2 1 +pinseq=31 +T 2950 6000 9 8 1 1 0 6 1 +pinlabel=(ADC6) PA6 +T 2950 6000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6400 3000 6400 1 0 0 +{ +T 3100 6450 5 8 1 1 0 0 1 +pinnumber=32 +T 3100 6350 5 8 0 1 0 2 1 +pinseq=32 +T 2950 6400 9 8 1 1 0 6 1 +pinlabel=(ADC5) PA5 +T 2950 6400 5 8 0 1 0 8 1 +pintype=io +} +P 3300 6800 3000 6800 1 0 0 +{ +T 3100 6850 5 8 1 1 0 0 1 +pinnumber=33 +T 3100 6750 5 8 0 1 0 2 1 +pinseq=33 +T 2950 6800 9 8 1 1 0 6 1 +pinlabel=(ADC4) PA4 +T 2950 6800 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7200 3000 7200 1 0 0 +{ +T 3100 7250 5 8 1 1 0 0 1 +pinnumber=34 +T 3100 7150 5 8 0 1 0 2 1 +pinseq=34 +T 2950 7200 9 8 1 1 0 6 1 +pinlabel=(ADC3) PA3 +T 2950 7200 5 8 0 1 0 8 1 +pintype=io +} +P 3300 7600 3000 7600 1 0 0 +{ +T 3100 7650 5 8 1 1 0 0 1 +pinnumber=35 +T 3100 7550 5 8 0 1 0 2 1 +pinseq=35 +T 2950 7600 9 8 1 1 0 6 1 +pinlabel=(ADC2) PA2 +T 2950 7600 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8000 3000 8000 1 0 0 +{ +T 3100 8050 5 8 1 1 0 0 1 +pinnumber=36 +T 3100 7950 5 8 0 1 0 2 1 +pinseq=36 +T 2950 8000 9 8 1 1 0 6 1 +pinlabel=(ADC1) PA1 +T 2950 8000 5 8 0 1 0 8 1 +pintype=io +} +P 3300 8400 3000 8400 1 0 0 +{ +T 3100 8450 5 8 1 1 0 0 1 +pinnumber=37 +T 3100 8350 5 8 0 1 0 2 1 +pinseq=37 +T 2950 8400 9 8 1 1 0 6 1 +pinlabel=(ADC0) PA0 +T 2950 8400 5 8 0 1 0 8 1 +pintype=io +} +B 400 400 2600 8400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 400 9850 5 10 0 0 0 0 1 +description=8-bit RISC micro controller (Atmel) +T 400 10050 5 10 0 0 0 0 1 +numslots=0 +T 400 10250 5 10 0 0 0 0 1 +author=Matthijs ten Berge +T 400 8850 9 10 1 0 0 0 1 +ATmega16 +P 100 1600 400 1600 1 0 0 +{ +T 300 1650 5 8 1 1 0 6 1 +pinnumber=27 +T 300 1550 5 8 0 1 0 8 1 +pinseq=27 +T 450 1600 9 8 1 1 0 0 1 +pinlabel=AVCC +T 450 1600 5 8 0 1 0 2 1 +pintype=pwr +} +P 100 1200 400 1200 1 0 0 +{ +T 300 1250 5 8 1 1 0 6 1 +pinnumber=29 +T 300 1150 5 8 0 1 0 8 1 +pinseq=29 +T 450 1200 9 8 1 1 0 0 1 +pinlabel=AREF +T 450 1200 5 8 0 1 0 2 1 +pintype=io +} +T 0 0 8 10 0 0 0 0 1 +dist-license=GPL +T 1600 0 8 10 0 0 0 0 1 +use-license=unlimited +T 0 200 8 10 0 0 0 0 1 +comment=Suggested library: micro diff --git a/gschem-sym/ATxmega128A3u-AU.sym b/gschem-sym/ATxmega128A3u-AU.sym new file mode 100644 index 0000000..c10443d --- /dev/null +++ b/gschem-sym/ATxmega128A3u-AU.sym @@ -0,0 +1,596 @@ +v 20110115 2 +B 300 4300 4200 10100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 500 15000 9 10 0 0 0 0 1 +distlicense=GPL3 +T 500 15200 9 10 0 0 0 0 1 +uselicense=no restrictions +T 500 15400 9 10 0 0 0 0 1 +author=Kai-Martin Knaak, kmk@lilalaser.de +T 500 15800 9 10 0 0 0 0 1 +description=ATXmegaA1, TQFP-100 +T 500 16000 9 10 0 0 0 0 1 +device=ATXmegaA1 +T 4600 14400 8 8 1 1 0 0 1 +footprint=TQFP64_14 +T 2000 13300 8 36 1 1 270 0 1 +value=ATXmega128A3U-AU +T 4600 14600 8 10 1 1 0 0 1 +refdes=U? +P 200 11700 300 11700 1 0 0 +{ +T 350 11700 9 10 1 1 0 1 1 +pinlabel=PA6 +T 200 11750 5 8 1 1 0 6 1 +pinnumber=4 +T 200 11750 5 8 0 1 0 6 1 +pinseq=4 +} +P 200 11400 300 11400 1 0 0 +{ +T 350 11400 9 10 1 1 0 1 1 +pinlabel=PA7 +T 200 11450 5 8 1 1 0 6 1 +pinnumber=5 +T 200 11450 5 8 0 1 0 6 1 +pinseq=5 +} +P 1400 4200 1400 4300 1 0 0 +{ +T 1400 4350 9 10 1 1 90 1 1 +pinlabel=GND +T 1450 4250 5 8 1 1 0 2 1 +pinnumber=14 +T 1450 4250 5 8 0 1 0 2 1 +pinseq=14 +} +P 200 10900 300 10900 1 0 0 +{ +T 350 10900 9 10 1 1 0 1 1 +pinlabel=PB0 +T 200 10950 5 8 1 1 0 6 1 +pinnumber=6 +T 200 10950 5 8 0 1 0 6 1 +pinseq=6 +} +P 200 10600 300 10600 1 0 0 +{ +T 350 10600 9 10 1 1 0 1 1 +pinlabel=PB1 +T 200 10650 5 8 1 1 0 6 1 +pinnumber=7 +T 200 10650 5 8 0 1 0 6 1 +pinseq=7 +} +P 200 10300 300 10300 1 0 0 +{ +T 350 10300 9 10 1 1 0 1 1 +pinlabel=PB2 +T 200 10350 5 8 1 1 0 6 1 +pinnumber=8 +T 200 10350 5 8 0 1 0 6 1 +pinseq=8 +} +P 200 10000 300 10000 1 0 0 +{ +T 350 10000 9 10 1 1 0 1 1 +pinlabel=PB3 +T 200 10050 5 8 1 1 0 6 1 +pinnumber=9 +T 200 10050 5 8 0 1 0 6 1 +pinseq=9 +} +P 200 9700 300 9700 1 0 0 +{ +T 350 9700 9 10 1 1 0 1 1 +pinlabel=PB4 +T 200 9750 5 8 1 1 0 6 1 +pinnumber=10 +T 200 9750 5 8 0 1 0 6 1 +pinseq=10 +} +P 200 9400 300 9400 1 0 0 +{ +T 350 9400 9 10 1 1 0 1 1 +pinlabel=PB5 +T 200 9450 5 8 1 1 0 6 1 +pinnumber=11 +T 200 9450 5 8 0 1 0 6 1 +pinseq=11 +} +P 200 9100 300 9100 1 0 0 +{ +T 350 9100 9 10 1 1 0 1 1 +pinlabel=PB6 +T 200 9150 5 8 1 1 0 6 1 +pinnumber=12 +T 200 9150 5 8 0 1 0 6 1 +pinseq=12 +} +P 200 8800 300 8800 1 0 0 +{ +T 350 8800 9 10 1 1 0 1 1 +pinlabel=PB7 +T 200 8850 5 8 1 1 0 6 1 +pinnumber=13 +T 200 8850 5 8 0 1 0 6 1 +pinseq=13 +} +P 1800 4200 1800 4300 1 0 0 +{ +T 1800 4350 9 10 1 1 90 1 1 +pinlabel=GND +T 1850 4250 5 8 1 1 0 2 1 +pinnumber=24 +T 1850 4250 5 8 0 1 0 2 1 +pinseq=24 +} +P 1800 14500 1800 14400 1 0 0 +{ +T 1800 14350 9 10 1 1 90 7 1 +pinlabel=VDD +T 1850 14450 5 8 1 1 0 0 1 +pinnumber=15 +T 1850 14450 5 8 0 1 0 0 1 +pinseq=15 +} +P 200 8300 300 8300 1 0 0 +{ +T 350 8300 9 10 1 1 0 1 1 +pinlabel=PC0 +T 200 8350 5 8 1 1 0 6 1 +pinnumber=16 +T 200 8350 5 8 0 1 0 6 1 +pinseq=16 +} +P 200 8000 300 8000 1 0 0 +{ +T 350 8000 9 10 1 1 0 1 1 +pinlabel=PC1 +T 200 8050 5 8 1 1 0 6 1 +pinnumber=17 +T 200 8050 5 8 0 1 0 6 1 +pinseq=17 +} +P 200 7700 300 7700 1 0 0 +{ +T 350 7700 9 10 1 1 0 1 1 +pinlabel=PC2 +T 200 7750 5 8 1 1 0 6 1 +pinnumber=18 +T 200 7750 5 8 0 1 0 6 1 +pinseq=18 +} +P 200 7400 300 7400 1 0 0 +{ +T 350 7400 9 10 1 1 0 1 1 +pinlabel=PC3 +T 200 7450 5 8 1 1 0 6 1 +pinnumber=19 +T 200 7450 5 8 0 1 0 6 1 +pinseq=19 +} +P 200 7100 300 7100 1 0 0 +{ +T 350 7100 9 10 1 1 0 1 1 +pinlabel=PC4 +T 200 7150 5 8 1 1 0 6 1 +pinnumber=20 +T 200 7150 5 8 0 1 0 6 1 +pinseq=20 +} +P 200 6800 300 6800 1 0 0 +{ +T 350 6800 9 10 1 1 0 1 1 +pinlabel=PC5 +T 200 6850 5 8 1 1 0 6 1 +pinnumber=21 +T 200 6850 5 8 0 1 0 6 1 +pinseq=21 +} +P 200 6500 300 6500 1 0 0 +{ +T 350 6500 9 10 1 1 0 1 1 +pinlabel=PC6 +T 200 6550 5 8 1 1 0 6 1 +pinnumber=22 +T 200 6550 5 8 0 1 0 6 1 +pinseq=22 +} +P 200 6200 300 6200 1 0 0 +{ +T 350 6200 9 10 1 1 0 1 1 +pinlabel=PC7 +T 200 6250 5 8 1 1 0 6 1 +pinnumber=23 +T 200 6250 5 8 0 1 0 6 1 +pinseq=23 +} +P 2200 4200 2200 4300 1 0 0 +{ +T 2200 4350 9 10 1 1 90 1 1 +pinlabel=GND +T 2250 4250 5 8 1 1 0 2 1 +pinnumber=34 +T 2250 4250 5 8 0 1 0 2 1 +pinseq=34 +} +P 2200 14500 2200 14400 1 0 0 +{ +T 2200 14350 9 10 1 1 90 7 1 +pinlabel=VDD +T 2250 14450 5 8 1 1 0 0 1 +pinnumber=25 +T 2250 14450 5 8 0 1 0 0 1 +pinseq=25 +} +P 4600 13500 4500 13500 1 0 0 +{ +T 4445 13495 9 10 1 1 0 6 1 +pinlabel=PD0 +T 4595 13545 5 8 1 1 0 0 1 +pinnumber=26 +T 4600 13550 5 8 0 1 0 0 1 +pinseq=26 +} +P 4600 13200 4500 13200 1 0 0 +{ +T 4445 13195 9 10 1 1 0 6 1 +pinlabel=PD1 +T 4595 13245 5 8 1 1 0 0 1 +pinnumber=27 +T 4600 13250 5 8 0 1 0 0 1 +pinseq=27 +} +P 4600 12900 4500 12900 1 0 0 +{ +T 4445 12895 9 10 1 1 0 6 1 +pinlabel=PD2 +T 4595 12945 5 8 1 1 0 0 1 +pinnumber=28 +T 4600 12950 5 8 0 1 0 0 1 +pinseq=28 +} +P 4600 12600 4500 12600 1 0 0 +{ +T 4445 12595 9 10 1 1 0 6 1 +pinlabel=PD3 +T 4595 12645 5 8 1 1 0 0 1 +pinnumber=29 +T 4600 12650 5 8 0 1 0 0 1 +pinseq=29 +} +P 4600 12300 4500 12300 1 0 0 +{ +T 4445 12295 9 10 1 1 0 6 1 +pinlabel=PD4 +T 4595 12345 5 8 1 1 0 0 1 +pinnumber=30 +T 4600 12350 5 8 0 1 0 0 1 +pinseq=30 +} +P 4600 12000 4500 12000 1 0 0 +{ +T 4445 11995 9 10 1 1 0 6 1 +pinlabel=PD5 +T 4595 12045 5 8 1 1 0 0 1 +pinnumber=31 +T 4600 12050 5 8 0 1 0 0 1 +pinseq=31 +} +P 4600 11700 4500 11700 1 0 0 +{ +T 4445 11695 9 10 1 1 0 6 1 +pinlabel=PD6 +T 4595 11745 5 8 1 1 0 0 1 +pinnumber=32 +T 4600 11750 5 8 0 1 0 0 1 +pinseq=32 +} +P 4600 11400 4500 11400 1 0 0 +{ +T 4445 11395 9 10 1 1 0 6 1 +pinlabel=PD7 +T 4595 11445 5 8 1 1 0 0 1 +pinnumber=33 +T 4600 11450 5 8 0 1 0 0 1 +pinseq=33 +} +P 2600 4200 2600 4300 1 0 0 +{ +T 2600 4350 9 10 1 1 90 1 1 +pinlabel=GND +T 2650 4250 5 8 1 1 0 2 1 +pinnumber=44 +T 2650 4250 5 8 0 1 0 2 1 +pinseq=44 +} +P 2600 14500 2600 14400 1 0 0 +{ +T 2600 14350 9 10 1 1 90 7 1 +pinlabel=VCC +T 2650 14450 5 8 1 1 0 0 1 +pinnumber=35 +T 2650 14450 5 8 0 1 0 0 1 +pinseq=35 +} +P 4600 10900 4500 10900 1 0 0 +{ +T 4445 10895 9 10 1 1 0 6 1 +pinlabel=PE0 +T 4595 10945 5 8 1 1 0 0 1 +pinnumber=36 +T 4600 10950 5 8 0 1 0 0 1 +pinseq=36 +} +P 4600 10600 4500 10600 1 0 0 +{ +T 4445 10595 9 10 1 1 0 6 1 +pinlabel=PE1 +T 4595 10645 5 8 1 1 0 0 1 +pinnumber=37 +T 4600 10650 5 8 0 1 0 0 1 +pinseq=37 +} +P 4600 10300 4500 10300 1 0 0 +{ +T 4445 10295 9 10 1 1 0 6 1 +pinlabel=PE2 +T 4595 10345 5 8 1 1 0 0 1 +pinnumber=38 +T 4600 10350 5 8 0 1 0 0 1 +pinseq=38 +} +P 4600 10000 4500 10000 1 0 0 +{ +T 4445 9995 9 10 1 1 0 6 1 +pinlabel=PE3 +T 4595 10045 5 8 1 1 0 0 1 +pinnumber=39 +T 4600 10050 5 8 0 1 0 0 1 +pinseq=39 +} +P 4600 9700 4500 9700 1 0 0 +{ +T 4445 9695 9 10 1 1 0 6 1 +pinlabel=PE4 +T 4595 9745 5 8 1 1 0 0 1 +pinnumber=40 +T 4600 9750 5 8 0 1 0 0 1 +pinseq=40 +} +P 4600 9400 4500 9400 1 0 0 +{ +T 4445 9395 9 10 1 1 0 6 1 +pinlabel=PE5 +T 4595 9445 5 8 1 1 0 0 1 +pinnumber=41 +T 4600 9450 5 8 0 1 0 0 1 +pinseq=41 +} +P 4600 9100 4500 9100 1 0 0 +{ +T 4445 9095 9 10 1 1 0 6 1 +pinlabel=PE6 +T 4595 9145 5 8 1 1 0 0 1 +pinnumber=42 +T 4600 9150 5 8 0 1 0 0 1 +pinseq=42 +} +P 4600 8800 4500 8800 1 0 0 +{ +T 4445 8795 9 10 1 1 0 6 1 +pinlabel=PE7 +T 4595 8845 5 8 1 1 0 0 1 +pinnumber=43 +T 4600 8850 5 8 0 1 0 0 1 +pinseq=43 +} +P 3000 4200 3000 4300 1 0 0 +{ +T 3000 4350 9 10 1 1 90 1 1 +pinlabel=GND +T 3050 4250 5 8 1 1 0 2 1 +pinnumber=52 +T 3050 4250 5 8 0 1 0 2 1 +pinseq=52 +} +P 3000 14500 3000 14400 1 0 0 +{ +T 3000 14350 9 10 1 1 90 7 1 +pinlabel=VCC +T 3050 14450 5 8 1 1 0 0 1 +pinnumber=45 +T 3050 14450 5 8 0 1 0 0 1 +pinseq=45 +} +P 4600 8300 4500 8300 1 0 0 +{ +T 4445 8295 9 10 1 1 0 6 1 +pinlabel=PF0 +T 4595 8345 5 8 1 1 0 0 1 +pinnumber=46 +T 4600 8350 5 8 0 1 0 0 1 +pinseq=46 +} +P 4600 8000 4500 8000 1 0 0 +{ +T 4445 7995 9 10 1 1 0 6 1 +pinlabel=PF1 +T 4595 8045 5 8 1 1 0 0 1 +pinnumber=47 +T 4600 8050 5 8 0 1 0 0 1 +pinseq=47 +} +P 4600 7700 4500 7700 1 0 0 +{ +T 4445 7695 9 10 1 1 0 6 1 +pinlabel=PF2 +T 4595 7745 5 8 1 1 0 0 1 +pinnumber=48 +T 4600 7750 5 8 0 1 0 0 1 +pinseq=48 +} +P 4600 7400 4500 7400 1 0 0 +{ +T 4445 7395 9 10 1 1 0 6 1 +pinlabel=PF3 +T 4595 7445 5 8 1 1 0 0 1 +pinnumber=49 +T 4600 7450 5 8 0 1 0 0 1 +pinseq=49 +} +P 4600 7100 4500 7100 1 0 0 +{ +T 4445 7095 9 10 1 1 0 6 1 +pinlabel=PF4 +T 4595 7145 5 8 1 1 0 0 1 +pinnumber=50 +T 4600 7150 5 8 0 1 0 0 1 +pinseq=50 +} +P 4600 6800 4500 6800 1 0 0 +{ +T 4445 6795 9 10 1 1 0 6 1 +pinlabel=PF5 +T 4595 6845 5 8 1 1 0 0 1 +pinnumber=51 +T 4600 6850 5 8 0 1 0 0 1 +pinseq=51 +} +P 4600 6500 4500 6500 1 0 0 +{ +T 4445 6495 9 10 1 1 0 6 1 +pinlabel=PF6 +T 4595 6545 5 8 1 1 0 0 1 +pinnumber=54 +T 4600 6550 5 8 0 1 0 0 1 +pinseq=54 +} +P 4600 6200 4500 6200 1 0 0 +{ +T 4445 6195 9 10 1 1 0 6 1 +pinlabel=PF7 +T 4595 6245 5 8 1 1 0 0 1 +pinnumber=55 +T 4600 6250 5 8 0 1 0 0 1 +pinseq=55 +} +P 3400 4200 3400 4300 1 0 0 +{ +T 3400 4350 9 10 1 1 90 1 1 +pinlabel=GND +T 3450 4250 5 8 1 1 0 2 1 +pinnumber=60 +T 3450 4250 5 8 0 1 0 2 1 +pinseq=60 +} +P 3400 14500 3400 14400 1 0 0 +{ +T 3400 14350 9 10 1 1 90 7 1 +pinlabel=VCC +T 3450 14450 5 8 1 1 0 0 1 +pinnumber=53 +T 3450 14450 5 8 0 1 0 0 1 +pinseq=53 +} +P 4600 5500 4500 5500 1 0 0 +{ +T 4450 5500 9 10 1 1 0 7 1 +pinlabel=PDI +T 4600 5550 5 8 1 1 0 0 1 +pinnumber=56 +T 4600 5550 5 8 0 1 0 0 1 +pinseq=56 +} +P 4600 5200 4500 5200 1 0 0 +{ +T 4450 5200 9 10 1 1 0 7 1 +pinlabel=RESET +T 4600 5250 5 8 1 1 0 0 1 +pinnumber=57 +T 4600 5250 5 8 0 1 0 0 1 +pinseq=57 +} +P 4600 4900 4500 4900 1 0 0 +{ +T 4450 4900 9 10 1 1 0 7 1 +pinlabel=PR0 +T 4600 4950 5 8 1 1 0 0 1 +pinnumber=58 +T 4600 4950 5 8 0 1 0 0 1 +pinseq=58 +} +P 4600 4600 4500 4600 1 0 0 +{ +T 4450 4600 9 10 1 1 0 7 1 +pinlabel=PR1 +T 4600 4650 5 8 1 1 0 0 1 +pinnumber=59 +T 4600 4650 5 8 0 1 0 0 1 +pinseq=59 +} +P 1400 14500 1400 14400 1 0 0 +{ +T 1400 14350 9 10 1 1 90 7 1 +pinlabel=AVCC +T 1450 14450 5 8 1 1 0 0 1 +pinnumber=61 +T 1450 14450 5 8 0 1 0 0 1 +pinseq=61 +} +P 200 13500 300 13500 1 0 0 +{ +T 350 13500 9 10 1 1 0 1 1 +pinlabel=PA0 +T 200 13550 5 8 1 1 0 6 1 +pinnumber=62 +T 200 13550 5 8 0 1 0 6 1 +pinseq=62 +} +P 200 13200 300 13200 1 0 0 +{ +T 350 13200 9 10 1 1 0 1 1 +pinlabel=PA1 +T 200 13250 5 8 1 1 0 6 1 +pinnumber=63 +T 200 13250 5 8 0 1 0 6 1 +pinseq=63 +} +P 200 12900 300 12900 1 0 0 +{ +T 350 12900 9 10 1 1 0 1 1 +pinlabel=PA2 +T 200 12950 5 8 1 1 0 6 1 +pinnumber=64 +T 200 12950 5 8 0 1 0 6 1 +pinseq=64 +} +P 200 12600 300 12600 1 0 0 +{ +T 350 12600 9 10 1 1 0 1 1 +pinlabel=PA3 +T 200 12650 5 8 1 1 0 6 1 +pinnumber=1 +T 200 12650 5 8 0 1 0 6 1 +pinseq=1 +} +P 200 12300 300 12300 1 0 0 +{ +T 350 12300 9 10 1 1 0 1 1 +pinlabel=PA4 +T 200 12350 5 8 1 1 0 6 1 +pinnumber=2 +T 200 12350 5 8 0 1 0 6 1 +pinseq=2 +} +P 200 12000 300 12000 1 0 0 +{ +T 350 12000 9 10 1 1 0 1 1 +pinlabel=PA5 +T 200 12050 5 8 1 1 0 6 1 +pinnumber=3 +T 200 12050 5 8 0 1 0 6 1 +pinseq=3 +} +T 500 15600 9 10 0 0 0 0 1 +documentation=http://www.atmel.com/Images/doc8386.pdf diff --git a/gschem-sym/MOD__MaxStream_XBee_PRO.fp b/gschem-sym/MOD__MaxStream_XBee_PRO.fp new file mode 100644 index 0000000..c3cf346 --- /dev/null +++ b/gschem-sym/MOD__MaxStream_XBee_PRO.fp @@ -0,0 +1,97 @@ +Element[0x0 "IC" "" "" 0 0 -48992 -62939 0 100 0x0] +( + ElementLine[-48992 65842 -48992 -42133 1000] + ElementLine[-48992 -42133 -20110 -65842 1000] + ElementLine[-20110 -65842 20110 -65842 1000] + ElementLine[20110 -65842 48992 -42133 1000] + ElementLine[48992 -42133 48992 65842 1000] + ElementLine[48992 65842 -48992 65842 1000] + ElementLine[-35433 15748 35433 15748 2000] + ElementLine[-35433 -14763 35433 -14763 2000] + ElementLine[-31496 9842 -22637 984 1000] + ElementLine[-22637 984 -26574 -9842 1000] + ElementLine[-26574 -9842 -18208 -9842 1000] + ElementLine[-18208 -9842 -16732 -4921 1000] + ElementLine[-16732 -4921 -11811 -9842 1000] + ElementLine[-11811 -9842 -6889 -9842 1000] + ElementLine[-6889 -9842 -15748 -1476 1000] + ElementLine[-15748 -1476 -11811 9842 1000] + ElementLine[-11811 9842 -18700 9842 1000] + ElementLine[-18700 9842 -20669 3937 1000] + ElementLine[-20669 3937 -26574 9842 1000] + ElementLine[-26574 9842 -31496 9842 1000] + ElementLine[492 9842 -5019 9842 2000] + ElementLine[-5019 9842 -5019 -3937 2000] + ElementLine[-5019 -3937 492 -3937 2000] + ElementLine[-5019 2952 492 2952 2000] + ElementLine[16486 9842 9596 9842 2000] + ElementLine[9596 9842 9596 -3937 2000] + ElementLine[9596 -3937 16486 -3937 2000] + ElementLine[9596 2952 14763 2952 2000] + ElementLine[29281 9842 22391 9842 2000] + ElementLine[22391 9842 22391 -3937 2000] + ElementLine[22391 -3937 29281 -3937 2000] + ElementLine[22391 2952 27559 2952 2000] + ElementArc[688 -492 3444 3444 90 180 2000] + ElementArc[688 6397 3444 3444 90 180 2000] + Pad[-44682 -39133 -41932 -39133 5500 2000 7500 "" "1" 0x0800] + Pad[-44682 -39133 -41932 -39133 5500 2000 7500 "" "1" 0x0880] + Pin[-43307 -39133 5500 2000 7500 2899 "" "1" 0x01] + Pad[-44682 -31259 -41932 -31259 5500 2000 7500 "" "2" 0x0800] + Pad[-44682 -31259 -41932 -31259 5500 2000 7500 "" "2" 0x0880] + Pin[-43307 -31259 5500 2000 7500 2899 "" "2" 0x01] + Pad[-44682 -23385 -41932 -23385 5500 2000 7500 "" "3" 0x0800] + Pad[-44682 -23385 -41932 -23385 5500 2000 7500 "" "3" 0x0880] + Pin[-43307 -23385 5500 2000 7500 2899 "" "3" 0x01] + Pad[-44682 -15511 -41932 -15511 5500 2000 7500 "" "4" 0x0800] + Pad[-44682 -15511 -41932 -15511 5500 2000 7500 "" "4" 0x0880] + Pin[-43307 -15511 5500 2000 7500 2899 "" "4" 0x01] + Pad[-44682 -7637 -41932 -7637 5500 2000 7500 "" "5" 0x0800] + Pad[-44682 -7637 -41932 -7637 5500 2000 7500 "" "5" 0x0880] + Pin[-43307 -7637 5500 2000 7500 2899 "" "5" 0x01] + Pad[-44682 236 -41932 236 5500 2000 7500 "" "6" 0x0800] + Pad[-44682 236 -41932 236 5500 2000 7500 "" "6" 0x0880] + Pin[-43307 236 5500 2000 7500 2899 "" "6" 0x01] + Pad[-44682 8110 -41932 8110 5500 2000 7500 "" "7" 0x0800] + Pad[-44682 8110 -41932 8110 5500 2000 7500 "" "7" 0x0880] + Pin[-43307 8110 5500 2000 7500 2899 "" "7" 0x01] + Pad[-44682 15984 -41932 15984 5500 2000 7500 "" "8" 0x0800] + Pad[-44682 15984 -41932 15984 5500 2000 7500 "" "8" 0x0880] + Pin[-43307 15984 5500 2000 7500 2899 "" "8" 0x01] + Pad[-44682 23858 -41932 23858 5500 2000 7500 "" "9" 0x0800] + Pad[-44682 23858 -41932 23858 5500 2000 7500 "" "9" 0x0880] + Pin[-43307 23858 5500 2000 7500 2899 "" "9" 0x01] + Pad[-44682 31732 -41932 31732 5500 2000 7500 "" "10" 0x0800] + Pad[-44682 31732 -41932 31732 5500 2000 7500 "" "10" 0x0880] + Pin[-43307 31732 5500 2000 7500 2899 "" "10" 0x01] + Pad[41932 31732 44682 31732 5500 2000 7500 "" "11" 0x0800] + Pad[41932 31732 44682 31732 5500 2000 7500 "" "11" 0x0880] + Pin[43307 31732 5500 2000 7500 2899 "" "11" 0x01] + Pad[41932 23858 44682 23858 5500 2000 7500 "" "12" 0x0800] + Pad[41932 23858 44682 23858 5500 2000 7500 "" "12" 0x0880] + Pin[43307 23858 5500 2000 7500 2899 "" "12" 0x01] + Pad[41932 15984 44682 15984 5500 2000 7500 "" "13" 0x0800] + Pad[41932 15984 44682 15984 5500 2000 7500 "" "13" 0x0880] + Pin[43307 15984 5500 2000 7500 2899 "" "13" 0x01] + Pad[41932 8110 44682 8110 5500 2000 7500 "" "14" 0x0800] + Pad[41932 8110 44682 8110 5500 2000 7500 "" "14" 0x0880] + Pin[43307 8110 5500 2000 7500 2899 "" "14" 0x01] + Pad[41932 236 44682 236 5500 2000 7500 "" "15" 0x0800] + Pad[41932 236 44682 236 5500 2000 7500 "" "15" 0x0880] + Pin[43307 236 5500 2000 7500 2899 "" "15" 0x01] + Pad[41932 -7637 44682 -7637 5500 2000 7500 "" "16" 0x0800] + Pad[41932 -7637 44682 -7637 5500 2000 7500 "" "16" 0x0880] + Pin[43307 -7637 5500 2000 7500 2899 "" "16" 0x01] + Pad[41932 -15511 44682 -15511 5500 2000 7500 "" "17" 0x0800] + Pad[41932 -15511 44682 -15511 5500 2000 7500 "" "17" 0x0880] + Pin[43307 -15511 5500 2000 7500 2899 "" "17" 0x01] + Pad[41932 -23385 44682 -23385 5500 2000 7500 "" "18" 0x0800] + Pad[41932 -23385 44682 -23385 5500 2000 7500 "" "18" 0x0880] + Pin[43307 -23385 5500 2000 7500 2899 "" "18" 0x01] + Pad[41932 -31259 44682 -31259 5500 2000 7500 "" "19" 0x0800] + Pad[41932 -31259 44682 -31259 5500 2000 7500 "" "19" 0x0880] + Pin[43307 -31259 5500 2000 7500 2899 "" "19" 0x01] + Pad[41932 -39133 44682 -39133 5500 2000 7500 "" "20" 0x0800] + Pad[41932 -39133 44682 -39133 5500 2000 7500 "" "20" 0x0880] + Pin[43307 -39133 5500 2000 7500 2899 "" "20" 0x01] +) diff --git a/gschem-sym/atmega168.sym b/gschem-sym/atmega168.sym new file mode 100644 index 0000000..97bd044 --- /dev/null +++ b/gschem-sym/atmega168.sym @@ -0,0 +1,320 @@ +v 20040111 1 +B 1000 1000 3000 5000 3 10 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 1000 6050 8 10 1 1 0 0 1 +refdes=U? +T 1000 1000 9 8 0 1 0 2 1 +value= +T 1000 1000 9 8 0 1 0 2 1 +footprint=DIP-28-300 +T 1000 1000 9 8 0 1 0 2 1 +manufacturer=Atmel +T 1000 1000 9 8 0 1 0 2 1 +manufacturer_part_number=ATmega168-20PU +P 1000 5800 900 5800 1 0 1 +{ +T 950 5850 5 8 1 1 0 6 1 +pinnumber=1 +T 1050 5850 5 8 0 1 0 0 1 +pinseq=1 +T 1050 5750 5 8 0 1 0 2 1 +pintype=in +T 1050 5800 9 8 1 1 0 1 1 +pinlabel=RESET' +} +P 4000 2600 4100 2600 1 0 1 +{ +T 4050 2650 5 8 1 1 0 0 1 +pinnumber=2 +T 3950 2650 5 8 0 1 0 6 1 +pinseq=2 +T 3950 2550 5 8 0 1 0 8 1 +pintype=in +T 3950 2600 9 8 1 1 0 7 1 +pinlabel=PD0/PCINT16/RXD +} +P 4000 2400 4100 2400 1 0 1 +{ +T 4050 2450 5 8 1 1 0 0 1 +pinnumber=3 +T 3950 2450 5 8 0 1 0 6 1 +pinseq=3 +T 3950 2350 5 8 0 1 0 8 1 +pintype=in +T 3950 2400 9 8 1 1 0 7 1 +pinlabel=PD1/PCINT17/TXD +} +P 4000 2200 4100 2200 1 0 1 +{ +T 4050 2250 5 8 1 1 0 0 1 +pinnumber=4 +T 3950 2250 5 8 0 1 0 6 1 +pinseq=4 +T 3950 2150 5 8 0 1 0 8 1 +pintype=in +T 3950 2200 9 8 1 1 0 7 1 +pinlabel=PD2/PCINT18/INT0 +} +P 4000 2000 4100 2000 1 0 1 +{ +T 4050 2050 5 8 1 1 0 0 1 +pinnumber=5 +T 3950 2050 5 8 0 1 0 6 1 +pinseq=5 +T 3950 1950 5 8 0 1 0 8 1 +pintype=in +T 3950 2000 9 8 1 1 0 7 1 +pinlabel=PD3/PCINT19/INT1/OC2B +} +P 4000 1800 4100 1800 1 0 1 +{ +T 4050 1850 5 8 1 1 0 0 1 +pinnumber=6 +T 3950 1850 5 8 0 1 0 6 1 +pinseq=6 +T 3950 1750 5 8 0 1 0 8 1 +pintype=in +T 3950 1800 9 8 1 1 0 7 1 +pinlabel=PD4/PCINT20/XCK/T0 +} +P 1000 3400 900 3400 1 0 1 +{ +T 950 3450 5 8 1 1 0 6 1 +pinnumber=7 +T 1050 3450 5 8 0 1 0 0 1 +pinseq=7 +T 1050 3350 5 8 0 1 0 2 1 +pintype=pwr +T 1050 3400 9 8 1 1 0 1 1 +pinlabel=VCC +} +P 1000 1400 900 1400 1 0 1 +{ +T 950 1450 5 8 1 1 0 6 1 +pinnumber=8 +T 1050 1450 5 8 0 1 0 0 1 +pinseq=8 +T 1050 1350 5 8 0 1 0 2 1 +pintype=pwr +T 1050 1400 9 8 1 1 0 1 1 +pinlabel=GND +} +P 1000 4500 900 4500 1 0 1 +{ +T 950 4550 5 8 1 1 0 6 1 +pinnumber=9 +T 1050 4550 5 8 0 1 0 0 1 +pinseq=9 +T 1050 4450 5 8 0 1 0 2 1 +pintype=in +T 1050 4500 9 8 1 1 0 1 1 +pinlabel=XTAL1 +} +P 1000 3900 900 3900 1 0 1 +{ +T 950 3950 5 8 1 1 0 6 1 +pinnumber=10 +T 1050 3950 5 8 0 1 0 0 1 +pinseq=10 +T 1050 3850 5 8 0 1 0 2 1 +pintype=in +T 1050 3900 9 8 1 1 0 1 1 +pinlabel=XTAL2 +} +P 4000 1600 4100 1600 1 0 1 +{ +T 4050 1650 5 8 1 1 0 0 1 +pinnumber=11 +T 3950 1650 5 8 0 1 0 6 1 +pinseq=11 +T 3950 1550 5 8 0 1 0 8 1 +pintype=in +T 3950 1600 9 8 1 1 0 7 1 +pinlabel=PD5/PCINT21/OC0B/T1 +} +P 4000 1400 4100 1400 1 0 1 +{ +T 4050 1450 5 8 1 1 0 0 1 +pinnumber=12 +T 3950 1450 5 8 0 1 0 6 1 +pinseq=12 +T 3950 1350 5 8 0 1 0 8 1 +pintype=in +T 3950 1400 9 8 1 1 0 7 1 +pinlabel=PD6/PCINT22/OC0A/AIN0 +} +P 4000 1200 4100 1200 1 0 1 +{ +T 4050 1250 5 8 1 1 0 0 1 +pinnumber=13 +T 3950 1250 5 8 0 1 0 6 1 +pinseq=13 +T 3950 1150 5 8 0 1 0 8 1 +pintype=in +T 3950 1200 9 8 1 1 0 7 1 +pinlabel=PD7/PCINT23/AIN1 +} +P 4000 5800 4100 5800 1 0 1 +{ +T 4050 5850 5 8 1 1 0 0 1 +pinnumber=14 +T 3950 5850 5 8 0 1 0 6 1 +pinseq=14 +T 3950 5750 5 8 0 1 0 8 1 +pintype=in +T 3950 5800 9 8 1 1 0 7 1 +pinlabel=PB0/PCINT0/CLKO/ICP1 +} +P 4000 5600 4100 5600 1 0 1 +{ +T 4050 5650 5 8 1 1 0 0 1 +pinnumber=15 +T 3950 5650 5 8 0 1 0 6 1 +pinseq=15 +T 3950 5550 5 8 0 1 0 8 1 +pintype=in +T 3950 5600 9 8 1 1 0 7 1 +pinlabel=PB1/PCINT1/OC1A +} +P 4000 5400 4100 5400 1 0 1 +{ +T 4050 5450 5 8 1 1 0 0 1 +pinnumber=16 +T 3950 5450 5 8 0 1 0 6 1 +pinseq=16 +T 3950 5350 5 8 0 1 0 8 1 +pintype=in +T 3950 5400 9 8 1 1 0 7 1 +pinlabel=PB2/PCINT2/OC1B/SS' +} +P 4000 5200 4100 5200 1 0 1 +{ +T 4050 5250 5 8 1 1 0 0 1 +pinnumber=17 +T 3950 5250 5 8 0 1 0 6 1 +pinseq=17 +T 3950 5150 5 8 0 1 0 8 1 +pintype=in +T 3950 5200 9 8 1 1 0 7 1 +pinlabel=PB3/PCINT3/OC2A/MOSI +} +P 4000 5000 4100 5000 1 0 1 +{ +T 4050 5050 5 8 1 1 0 0 1 +pinnumber=18 +T 3950 5050 5 8 0 1 0 6 1 +pinseq=18 +T 3950 4950 5 8 0 1 0 8 1 +pintype=in +T 3950 5000 9 8 1 1 0 7 1 +pinlabel=PB4/PCINT4/MISO +} +P 4000 4800 4100 4800 1 0 1 +{ +T 4050 4850 5 8 1 1 0 0 1 +pinnumber=19 +T 3950 4850 5 8 0 1 0 6 1 +pinseq=19 +T 3950 4750 5 8 0 1 0 8 1 +pintype=in +T 3950 4800 9 8 1 1 0 7 1 +pinlabel=PB5/PCINT5/SCK +} +P 1000 2400 900 2400 1 0 1 +{ +T 950 2450 5 8 1 1 0 6 1 +pinnumber=20 +T 1050 2450 5 8 0 1 0 0 1 +pinseq=20 +T 1050 2350 5 8 0 1 0 2 1 +pintype=pwr +T 1050 2400 9 8 1 1 0 1 1 +pinlabel=AVCC +} +P 1000 2000 900 2000 1 0 1 +{ +T 950 2050 5 8 1 1 0 6 1 +pinnumber=21 +T 1050 2050 5 8 0 1 0 0 1 +pinseq=21 +T 1050 1950 5 8 0 1 0 2 1 +pintype=in +T 1050 2000 9 8 1 1 0 1 1 +pinlabel=AREF +} +P 1000 1200 900 1200 1 0 1 +{ +T 950 1250 5 8 1 1 0 6 1 +pinnumber=22 +T 1050 1250 5 8 0 1 0 0 1 +pinseq=22 +T 1050 1150 5 8 0 1 0 2 1 +pintype=pwr +T 1050 1200 9 8 1 1 0 1 1 +pinlabel=GND +} +P 4000 4400 4100 4400 1 0 1 +{ +T 4050 4450 5 8 1 1 0 0 1 +pinnumber=23 +T 3950 4450 5 8 0 1 0 6 1 +pinseq=23 +T 3950 4350 5 8 0 1 0 8 1 +pintype=in +T 3950 4400 9 8 1 1 0 7 1 +pinlabel=PC0/PCINT8/ADC0 +} +P 4000 4200 4100 4200 1 0 1 +{ +T 4050 4250 5 8 1 1 0 0 1 +pinnumber=24 +T 3950 4250 5 8 0 1 0 6 1 +pinseq=24 +T 3950 4150 5 8 0 1 0 8 1 +pintype=in +T 3950 4200 9 8 1 1 0 7 1 +pinlabel=PC1/PCINT9/ADC1 +} +P 4000 4000 4100 4000 1 0 1 +{ +T 4050 4050 5 8 1 1 0 0 1 +pinnumber=25 +T 3950 4050 5 8 0 1 0 6 1 +pinseq=25 +T 3950 3950 5 8 0 1 0 8 1 +pintype=in +T 3950 4000 9 8 1 1 0 7 1 +pinlabel=PC2/PCINT10/ADC2 +} +P 4000 3800 4100 3800 1 0 1 +{ +T 4050 3850 5 8 1 1 0 0 1 +pinnumber=26 +T 3950 3850 5 8 0 1 0 6 1 +pinseq=26 +T 3950 3750 5 8 0 1 0 8 1 +pintype=in +T 3950 3800 9 8 1 1 0 7 1 +pinlabel=PC3/PCINT11/ADC3 +} +P 4000 3600 4100 3600 1 0 1 +{ +T 4050 3650 5 8 1 1 0 0 1 +pinnumber=27 +T 3950 3650 5 8 0 1 0 6 1 +pinseq=27 +T 3950 3550 5 8 0 1 0 8 1 +pintype=in +T 3950 3600 9 8 1 1 0 7 1 +pinlabel=PC4/PCINT12/ADC4/SDA +} +P 4000 3400 4100 3400 1 0 1 +{ +T 4050 3450 5 8 1 1 0 0 1 +pinnumber=28 +T 3950 3450 5 8 0 1 0 6 1 +pinseq=28 +T 3950 3350 5 8 0 1 0 8 1 +pintype=in +T 3950 3400 9 8 1 1 0 7 1 +pinlabel=PC5/PCINT13/ADC5/SCL +} diff --git a/gschem-sym/lm1117.sym b/gschem-sym/lm1117.sym new file mode 100644 index 0000000..7a9425b --- /dev/null +++ b/gschem-sym/lm1117.sym @@ -0,0 +1,35 @@ +v 20110115 2 +B 300 300 1400 1000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1700 800 2000 800 1 0 1 +{ +T 1800 1100 5 10 0 0 0 0 1 +pinnumber=2 +T 1800 900 5 10 1 1 0 0 1 +pinseq=2 +T 1600 800 9 10 1 1 0 6 1 +pinlabel=Vout +} +P 0 800 300 800 1 0 0 +{ +T 200 900 5 10 1 1 0 6 1 +pinnumber=3 +T 0 1000 5 10 0 0 0 0 1 +pinseq=3 +T 400 800 9 10 1 1 0 0 1 +pinlabel=Vin +} +P 1000 0 1000 300 1 0 0 +{ +T 1100 100 5 10 1 1 0 0 1 +pinnumber=1 +T 200 100 5 10 0 0 0 0 1 +pinseq=1 +T 1000 400 9 10 1 1 0 3 1 +pinlabel=Ajd +} +T 300 1400 9 10 1 0 0 0 1 +LM1117 +T 300 1700 8 10 0 0 0 0 1 +device=LM317 +T 1700 1400 8 10 1 1 0 6 1 +refdes=U? diff --git a/gschem-sym/xbee.sym b/gschem-sym/xbee.sym new file mode 100644 index 0000000..99bcce6 --- /dev/null +++ b/gschem-sym/xbee.sym @@ -0,0 +1,232 @@ +v 20110115 2 +P 3800 3800 3500 3800 1 0 0 +{ +T 3900 3800 5 10 0 0 0 0 1 +pintype=io +T 3445 3795 9 9 1 1 0 6 1 +pinlabel=AD0 / DIO0 / Commisioning Button +T 3595 3845 5 10 1 1 0 0 1 +pinnumber=20 +T 3900 3800 5 10 0 0 0 0 1 +pinseq=20 +} +P 100 200 400 200 1 0 0 +{ +T -100 200 5 10 0 0 0 0 1 +pintype=pwr +T 455 195 9 9 1 1 0 0 1 +pinlabel=GND +T 305 245 5 10 1 1 0 6 1 +pinnumber=10 +T -100 200 5 10 0 0 0 0 1 +pinseq=10 +} +P 100 600 400 600 1 0 0 +{ +T -100 600 5 10 0 0 0 0 1 +pintype=io +T 455 595 9 9 1 1 0 0 1 +pinlabel=\_DTR\_ / SLEEP_RQ / DIO8 +T 305 645 5 10 1 1 0 6 1 +pinnumber=9 +T -100 600 5 10 0 0 0 0 1 +pinseq=9 +} +P 100 1400 400 1400 1 0 0 +{ +T -100 1400 5 10 0 0 0 0 1 +pintype=io +T 455 1395 9 9 1 1 0 0 1 +pinlabel=DIO11 +T 305 1445 5 10 1 1 0 6 1 +pinnumber=7 +T -100 1400 5 10 0 0 0 0 1 +pinseq=7 +} +P 100 1800 400 1800 1 0 0 +{ +T -100 1800 5 10 0 0 0 0 1 +pintype=io +T 455 1795 9 9 1 1 0 0 1 +pinlabel=RSSI PWM / DIO10 +T 305 1845 5 10 1 1 0 6 1 +pinnumber=6 +T -100 1800 5 10 0 0 0 0 1 +pinseq=6 +} +P 100 2200 400 2200 1 0 0 +{ +T -100 2200 5 10 0 0 0 0 1 +pintype=in +T 455 2195 9 9 1 1 0 0 1 +pinlabel=\_RESET\_ +T 305 2245 5 10 1 1 0 6 1 +pinnumber=5 +T -100 2200 5 10 0 0 0 0 1 +pinseq=5 +} +P 100 2600 400 2600 1 0 0 +{ +T -100 2600 5 10 0 0 0 0 1 +pintype=io +T 455 2595 9 9 1 1 0 0 1 +pinlabel=DIO12 +T 305 2645 5 10 1 1 0 6 1 +pinnumber=4 +T -100 2600 5 10 0 0 0 0 1 +pinseq=4 +} +P 100 1000 400 1000 1 0 0 +{ +T -100 1000 5 10 0 0 0 0 1 +pintype=pas +T 455 995 9 9 1 1 0 0 1 +pinlabel=RESERVED +T 305 1045 5 10 1 1 0 6 1 +pinnumber=8 +T -100 1000 5 10 0 0 0 0 1 +pinseq=8 +} +B 400 100 3100 3900 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 100 3000 400 3000 1 0 0 +{ +T -100 3000 5 10 0 0 0 0 1 +pintype=in +T 455 2995 9 9 1 1 0 0 1 +pinlabel=DIN / \_CONFIG\_ +T 305 3045 5 10 1 1 0 6 1 +pinnumber=3 +T -100 3000 5 10 0 0 0 0 1 +pinseq=3 +} +P 100 3400 400 3400 1 0 0 +{ +T -100 3400 5 10 0 0 0 0 1 +pintype=out +T 455 3395 9 9 1 1 0 0 1 +pinlabel=DOUT +T 305 3445 5 10 1 1 0 6 1 +pinnumber=2 +T -100 3400 5 10 0 0 0 0 1 +pinseq=2 +} +P 100 3800 400 3800 1 0 0 +{ +T -100 3800 5 10 0 0 0 0 1 +pintype=pwr +T 455 3795 9 9 1 1 0 0 1 +pinlabel=VCC +T 305 3845 5 10 1 1 0 6 1 +pinnumber=1 +T -100 3800 5 10 0 0 0 0 1 +pinseq=1 +} +P 3800 3400 3500 3400 1 0 0 +{ +T 3900 3400 5 10 0 0 0 0 1 +pintype=io +T 3445 3395 9 9 1 1 0 6 1 +pinlabel=AD1 / DIO1 +T 3595 3445 5 10 1 1 0 0 1 +pinnumber=19 +T 3900 3400 5 10 0 0 0 0 1 +pinseq=19 +} +P 3800 3000 3500 3000 1 0 0 +{ +T 3900 3000 5 10 0 0 0 0 1 +pintype=io +T 3445 2995 9 9 1 1 0 6 1 +pinlabel=AD2 / DIO2 +T 3595 3045 5 10 1 1 0 0 1 +pinnumber=18 +T 3900 3000 5 10 0 0 0 0 1 +pinseq=18 +} +P 3800 2600 3500 2600 1 0 0 +{ +T 3900 2600 5 10 0 0 0 0 1 +pintype=io +T 3445 2595 9 9 1 1 0 6 1 +pinlabel=AD3 / DIO3 +T 3595 2645 5 10 1 1 0 0 1 +pinnumber=17 +T 3900 2600 5 10 0 0 0 0 1 +pinseq=17 +} +P 3800 2200 3500 2200 1 0 0 +{ +T 3900 2200 5 10 0 0 0 0 1 +pintype=io +T 3445 2195 9 9 1 1 0 6 1 +pinlabel=\_RTS\_ / DIO6 +T 3595 2245 5 10 1 1 0 0 1 +pinnumber=16 +T 3900 2200 5 10 0 0 0 0 1 +pinseq=16 +} +P 3800 1800 3500 1800 1 0 0 +{ +T 3900 1800 5 10 0 0 0 0 1 +pintype=io +T 3445 1795 9 9 1 1 0 6 1 +pinlabel=Associate / DIO5 +T 3595 1845 5 10 1 1 0 0 1 +pinnumber=15 +T 3900 1800 5 10 0 0 0 0 1 +pinseq=15 +} +P 3800 1400 3500 1400 1 0 0 +{ +T 3900 1400 5 10 0 0 0 0 1 +pintype=io +T 3445 1395 9 9 1 1 0 6 1 +pinlabel=VREF +T 3595 1445 5 10 1 1 0 0 1 +pinnumber=14 +T 3900 1400 5 10 0 0 0 0 1 +pinseq=14 +} +P 3800 200 3500 200 1 0 0 +{ +T 3900 200 5 10 0 0 0 0 1 +pintype=io +T 3445 195 9 9 1 1 0 6 1 +pinlabel=DIO4 +T 3595 245 5 10 1 1 0 0 1 +pinnumber=11 +T 3900 200 5 10 0 0 0 0 1 +pinseq=11 +} +P 3800 600 3500 600 1 0 0 +{ +T 3900 600 5 10 0 0 0 0 1 +pintype=io +T 3445 595 9 9 1 1 0 6 1 +pinlabel=\_CTS\_ / DIO7 +T 3595 645 5 10 1 1 0 0 1 +pinnumber=12 +T 3900 600 5 10 0 0 0 0 1 +pinseq=12 +} +P 3800 1000 3500 1000 1 0 0 +{ +T 3900 1000 5 10 0 0 0 0 1 +pintype=out +T 3445 995 9 9 1 1 0 6 1 +pinlabel=ON / \_SLEEP\_ +T 3595 1045 5 10 1 1 0 0 1 +pinnumber=13 +T 3900 1000 5 10 0 0 0 0 1 +pinseq=13 +} +T 3295 4100 8 10 1 1 0 0 1 +refdes=U? +T 400 4100 9 10 1 0 0 0 1 +XBEE +T 95 100 8 10 0 1 0 0 1 +author=Nicholas De Cicco velociostrich@gmail.com +T 95 100 8 10 0 1 0 0 1 +dist-license=GPLv3 +T 95 100 8 10 0 1 0 0 1 +use-license=unlimited diff --git a/mainboard/gafrc b/mainboard/gafrc new file mode 100644 index 0000000..f3dd10c --- /dev/null +++ b/mainboard/gafrc @@ -0,0 +1 @@ +(component-library "../gschem-sym") diff --git a/mainboard/mainboard.sch b/mainboard/mainboard.sch new file mode 100644 index 0000000..c92859d --- /dev/null +++ b/mainboard/mainboard.sch @@ -0,0 +1,1304 @@ +v 20110115 2 +C 43400 37500 1 0 0 ATxmega128A3u-AU.sym +{ +T 43900 53500 5 10 0 0 0 0 1 +device=ATXmegaA1 +T 47300 52000 5 8 1 1 0 0 1 +footprint=TQFP64_14 +T 45400 50800 5 36 1 1 270 0 1 +value=ATXmega128A3U-AU +T 47300 52200 5 10 1 1 0 0 1 +refdes=U1 +} +C 44600 53000 1 0 0 3.3V-plus-1.sym +C 44700 40600 1 0 0 gnd-1.sym +N 44800 53000 44800 52000 4 +N 44800 52500 46800 52500 4 +N 45200 52500 45200 52000 4 +N 45600 52500 45600 52000 4 +N 46000 52500 46000 52000 4 +N 46400 52500 46400 52000 4 +N 46800 52500 46800 52000 4 +N 44800 40900 44800 41700 4 +N 40800 40900 46800 40900 4 +N 45200 40900 45200 41700 4 +N 45600 40900 45600 41700 4 +N 46000 40900 46000 41700 4 +N 46400 40900 46400 41700 4 +N 46800 40900 46800 41700 4 +C 40600 42200 1 270 0 capacitor-1.sym +{ +T 41300 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 40900 42100 5 10 1 1 270 0 1 +refdes=C? +T 41500 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 40600 42400 5 10 1 1 270 0 1 +value=100nF +} +C 41100 42200 1 270 0 capacitor-1.sym +{ +T 41800 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 41400 42100 5 10 1 1 270 0 1 +refdes=C? +T 42000 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 41100 42400 5 10 1 1 270 0 1 +value=100nF +} +C 41600 42200 1 270 0 capacitor-1.sym +{ +T 42300 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 41900 42100 5 10 1 1 270 0 1 +refdes=C? +T 42500 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 41600 42400 5 10 1 1 270 0 1 +value=100nF +} +C 42100 42200 1 270 0 capacitor-1.sym +{ +T 42800 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 42400 42100 5 10 1 1 270 0 1 +refdes=C? +T 43000 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 42100 42400 5 10 1 1 270 0 1 +value=100nF +} +C 42600 42200 1 270 0 capacitor-1.sym +{ +T 43300 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 42900 42100 5 10 1 1 270 0 1 +refdes=C? +T 43500 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 42600 42400 5 10 1 1 270 0 1 +value=100nF +} +C 43100 42200 1 270 0 capacitor-1.sym +{ +T 43800 42000 5 10 0 0 270 0 1 +device=CAPACITOR +T 43400 42100 5 10 1 1 270 0 1 +refdes=C? +T 44000 42000 5 10 0 0 270 0 1 +symversion=0.1 +T 43100 42400 5 10 1 1 270 0 1 +value=100nF +} +N 40800 40900 40800 41300 4 +N 41300 41300 41300 40900 4 +N 41800 41300 41800 40900 4 +N 42300 41300 42300 40900 4 +N 42800 41300 42800 40900 4 +N 43300 41300 43300 40900 4 +N 40800 42200 40800 42800 4 +N 41300 42200 41300 42600 4 +N 40800 42600 43300 42600 4 +N 41800 42200 41800 42600 4 +N 42300 42200 42300 42600 4 +N 42800 42200 42800 42600 4 +N 43300 42200 43300 42600 4 +C 52000 57300 1 0 0 5V-plus-1.sym +C 40600 42800 1 0 0 3.3V-plus-1.sym +C 61800 41900 1 0 0 xbee.sym +{ +T 65095 46000 5 10 1 1 0 0 1 +refdes=U3 +} +C 61100 46100 1 0 0 3.3V-plus-1.sym +N 61900 45700 61300 45700 4 +N 61900 45300 60700 45300 4 +{ +T 60700 45400 5 10 1 1 0 0 1 +netname=TX_XBEE +} +N 61900 44900 60700 44900 4 +{ +T 60700 45000 5 10 1 1 0 0 1 +netname=RX_XBEE +} +N 61900 42500 60900 42500 4 +{ +T 60900 42600 5 10 1 1 0 0 1 +netname=DTR_XBEE +} +N 65600 42500 66800 42500 4 +{ +T 65900 42600 5 10 1 1 0 0 1 +netname=CTS_XBEE +} +N 65600 44100 66800 44100 4 +{ +T 65900 44200 5 10 1 1 0 0 1 +netname=RTS_XBEE +} +C 61600 41400 1 0 0 gnd-1.sym +N 61300 45700 61300 46100 4 +C 60600 41900 1 0 0 capacitor-1.sym +{ +T 60800 42600 5 10 0 0 0 0 1 +device=CAPACITOR +T 60700 42200 5 10 1 1 0 0 1 +refdes=C? +T 60800 42800 5 10 0 0 0 0 1 +symversion=0.1 +T 60400 41900 5 10 1 1 0 0 1 +value=100nF +} +N 60300 42100 60300 42400 4 +C 60100 42400 1 0 0 3.3V-plus-1.sym +N 61900 42100 61500 42100 4 +N 61700 42100 61700 41700 4 +N 60300 42100 60600 42100 4 +N 43600 45200 42300 45200 4 +{ +T 42300 45300 5 10 1 1 0 0 1 +netname=TX_XBEE +} +N 43600 44900 42300 44900 4 +{ +T 42300 45000 5 10 1 1 0 0 1 +netname=RX_XBEE +} +C 52900 53100 1 0 0 ATmega168-TQFP-1.sym +{ +T 56300 61700 5 10 1 1 0 6 1 +refdes=U2 +T 53300 61900 5 10 0 0 0 0 1 +device=ATMEGA168 +T 53300 62100 5 10 0 0 0 0 1 +footprint=TQFP32 +} +C 52600 58500 1 0 0 gnd-1.sym +N 53000 58800 52700 58800 4 +N 52700 58800 52700 59600 4 +N 53000 59200 52700 59200 4 +N 53000 59600 52700 59600 4 +N 53000 57200 52200 57200 4 +N 52200 56800 52200 57300 4 +N 53000 56800 52200 56800 4 +N 70900 55600 71900 55600 4 +N 71900 55200 70600 55200 4 +C 71900 49200 1 0 0 connector16-2.sym +{ +T 72600 56100 5 10 1 1 0 6 1 +refdes=CONN? +T 72200 56050 5 10 0 0 0 0 1 +device=CONNECTOR_16 +T 72200 56250 5 10 0 0 0 0 1 +footprint=SIP16N +} +C 70700 55600 1 0 0 3.3V-plus-1.sym +C 70500 54900 1 0 0 gnd-1.sym +N 71900 54800 71000 54800 4 +{ +T 71000 54900 5 10 1 1 0 0 1 +netname=PDI_DATA +} +N 71900 54400 71000 54400 4 +{ +T 70600 54500 5 10 1 1 0 0 1 +netname=PDI_CLK_RESET +} +N 71900 54000 71000 54000 4 +{ +T 71000 54100 5 10 1 1 0 0 1 +netname=TMS_XMEGA +} +N 71900 53600 71000 53600 4 +{ +T 71000 53700 5 10 1 1 0 0 1 +netname=TDI_XMEGA +} +N 71900 53200 71000 53200 4 +{ +T 71000 53300 5 10 1 1 0 0 1 +netname=TCK_XMEGA +} +N 71900 52800 71000 52800 4 +{ +T 71000 52900 5 10 1 1 0 0 1 +netname=TDO_XMEGA +} +N 71900 52400 70600 52400 4 +C 70500 52100 1 0 0 gnd-1.sym +N 71900 52000 71000 52000 4 +{ +T 71000 52100 5 10 1 1 0 0 1 +netname=TX_XMEGA +} +N 71900 51600 71000 51600 4 +{ +T 71000 51700 5 10 1 1 0 0 1 +netname=RX_XMEGA +} +T 40600 59800 9 10 1 0 0 0 3 +tx/rx atxmega replaçable +picots de test +carte debug: pin1, alim 3 ou 5 ? +N 43600 44000 42300 44000 4 +{ +T 42300 44100 5 10 1 1 0 0 1 +netname=RX_XMEGA +} +N 43600 43700 42300 43700 4 +{ +T 42300 43800 5 10 1 1 0 0 1 +netname=TX_XMEGA +} +T 71100 50400 9 10 1 0 0 0 1 +No SPI +N 71900 49600 70600 49600 4 +C 70500 49300 1 0 0 gnd-1.sym +N 48900 43000 48000 43000 4 +{ +T 48200 43100 5 10 1 1 0 0 1 +netname=PDI_DATA +} +N 48900 42700 48000 42700 4 +{ +T 48200 42800 5 10 1 1 0 0 1 +netname=PDI_CLK_RESET +} +N 43600 47200 42300 47200 4 +{ +T 42200 47300 5 10 1 1 0 0 1 +netname=TMS_XMEGA +} +N 43600 46900 42300 46900 4 +{ +T 42200 47000 5 10 1 1 0 0 1 +netname=TDI_XMEGA +} +N 43600 46600 42300 46600 4 +{ +T 42200 46700 5 10 1 1 0 0 1 +netname=TCK_XMEGA +} +N 43600 46300 42300 46300 4 +{ +T 42200 46400 5 10 1 1 0 0 1 +netname=TDO_XMEGA +} +N 70900 48100 71900 48100 4 +N 71900 47700 70600 47700 4 +C 71900 41700 1 0 0 connector16-2.sym +{ +T 72600 48600 5 10 1 1 0 6 1 +refdes=CONN? +T 72200 48550 5 10 0 0 0 0 1 +device=CONNECTOR_16 +T 72200 48750 5 10 0 0 0 0 1 +footprint=SIP16N +} +C 70500 47400 1 0 0 gnd-1.sym +N 71900 44900 70200 44900 4 +C 70100 44600 1 0 0 gnd-1.sym +N 71900 44500 71000 44500 4 +{ +T 71000 44600 5 10 1 1 0 0 1 +netname=TX_MEGA +} +N 71900 44100 71000 44100 4 +{ +T 71000 44200 5 10 1 1 0 0 1 +netname=RX_MEGA +} +N 71900 42100 70600 42100 4 +C 70500 41800 1 0 0 gnd-1.sym +T 71100 46900 9 10 1 0 0 0 1 +No PDI +T 71100 45900 9 10 1 0 0 0 1 +No jtag +N 70900 43300 70000 43300 4 +{ +T 69800 43400 5 10 1 1 0 0 1 +netname=MOSI_MEGA +} +N 71900 42900 70000 42900 4 +{ +T 69800 43000 5 10 1 1 0 0 1 +netname=MISO_MEGA +} +N 70900 42500 70000 42500 4 +{ +T 69800 42600 5 10 1 1 0 0 1 +netname=SCK_MEGA +} +N 71900 43700 70600 43700 4 +N 71900 51200 70600 51200 4 +N 57500 56000 56600 56000 4 +{ +T 56600 56100 5 10 1 1 0 0 1 +netname=TX_MEGA +} +N 57500 56400 56600 56400 4 +{ +T 56600 56500 5 10 1 1 0 0 1 +netname=RX_MEGA +} +N 57500 60000 56600 60000 4 +{ +T 56600 60100 5 10 1 1 0 0 1 +netname=MOSI_MEGA +} +N 57500 59600 56600 59600 4 +{ +T 56600 59700 5 10 1 1 0 0 1 +netname=MISO_MEGA +} +N 57500 59200 56600 59200 4 +{ +T 56600 59300 5 10 1 1 0 0 1 +netname=SCK_MEGA +} +N 71900 47300 71000 47300 4 +{ +T 71000 47400 5 10 1 1 0 0 1 +netname=RESET +} +N 53000 57600 52600 57600 4 +{ +T 52400 57700 5 10 1 1 0 0 1 +netname=RESET +} +C 51900 60300 1 0 0 gnd-1.sym +C 50800 61900 1 270 0 capacitor-1.sym +{ +T 51500 61700 5 10 0 0 270 0 1 +device=CAPACITOR +T 51100 61800 5 10 1 1 270 0 1 +refdes=C? +T 51700 61700 5 10 0 0 270 0 1 +symversion=0.1 +T 50800 62100 5 10 1 1 270 0 1 +value=100nF +} +C 51300 61900 1 270 0 capacitor-1.sym +{ +T 52000 61700 5 10 0 0 270 0 1 +device=CAPACITOR +T 51600 61800 5 10 1 1 270 0 1 +refdes=C? +T 52200 61700 5 10 0 0 270 0 1 +symversion=0.1 +T 51300 62100 5 10 1 1 270 0 1 +value=100nF +} +N 51000 60600 51000 61000 4 +N 51500 61000 51500 60600 4 +N 51000 61900 51000 62500 4 +N 51500 61900 51500 62300 4 +N 51500 62300 51000 62300 4 +N 51000 60600 52000 60600 4 +C 50800 62500 1 0 0 5V-plus-1.sym +C 47400 54800 1 0 0 3.3V-plus-1.sym +C 46400 53200 1 0 0 gnd-1.sym +C 46700 53600 1 90 0 capacitor-1.sym +{ +T 46000 53800 5 10 0 0 90 0 1 +device=CAPACITOR +T 46200 53800 5 10 1 1 90 0 1 +refdes=C? +T 45800 53800 5 10 0 0 90 0 1 +symversion=0.1 +} +C 46700 54500 1 0 0 resistor-2.sym +{ +T 47100 54850 5 10 0 0 0 0 1 +device=RESISTOR +T 46900 54800 5 10 1 1 0 0 1 +refdes=R? +} +N 46000 54600 46700 54600 4 +{ +T 45300 54700 5 10 1 1 0 0 1 +netname=PDI_CLK_RESET +} +N 46500 53500 46500 53600 4 +C 51300 53400 1 0 0 gnd-1.sym +C 51600 53800 1 90 0 capacitor-1.sym +{ +T 50900 54000 5 10 0 0 90 0 1 +device=CAPACITOR +T 51100 54000 5 10 1 1 90 0 1 +refdes=C? +T 50700 54000 5 10 0 0 90 0 1 +symversion=0.1 +} +C 51600 54700 1 0 0 resistor-2.sym +{ +T 52000 55050 5 10 0 0 0 0 1 +device=RESISTOR +T 51800 55000 5 10 1 1 0 0 1 +refdes=R? +} +N 51400 53700 51400 53800 4 +N 50600 54800 51600 54800 4 +{ +T 50600 54900 5 10 1 1 0 0 1 +netname=RESET +} +C 52300 55000 1 0 0 5V-plus-1.sym +N 46500 54600 46500 54500 4 +N 47600 54800 47600 54600 4 +N 51400 54800 51400 54700 4 +N 52500 54800 52500 55000 4 +C 44000 62300 1 0 0 5V-plus-1.sym +C 44700 61200 1 0 0 lm1117.sym +{ +T 45000 62900 5 10 0 0 0 0 1 +device=LM317 +T 46400 62600 5 10 1 1 0 6 1 +refdes=U4 +} +C 47000 62300 1 0 0 3.3V-plus-1.sym +C 45600 60700 1 0 0 gnd-1.sym +N 44200 62300 44200 62000 4 +N 44200 62000 44700 62000 4 +N 47200 62300 47200 62000 4 +N 47200 62000 46700 62000 4 +N 45700 61200 45700 61000 4 +N 45700 61100 44200 61100 4 +N 45700 61100 47200 61100 4 +C 44000 62000 1 270 0 capacitor-2.sym +{ +T 44700 61800 5 10 0 0 270 0 1 +device=POLARIZED_CAPACITOR +T 44000 61900 5 10 1 1 270 0 1 +refdes=C? +T 44900 61800 5 10 0 0 270 0 1 +symversion=0.1 +T 43800 61200 5 10 1 1 0 0 1 +value=10u +} +C 47000 62000 1 270 0 capacitor-2.sym +{ +T 47700 61800 5 10 0 0 270 0 1 +device=POLARIZED_CAPACITOR +T 47000 61900 5 10 1 1 270 0 1 +refdes=C? +T 47900 61800 5 10 0 0 270 0 1 +symversion=0.1 +T 46800 61200 5 10 1 1 0 0 1 +value=10u +} +C 50600 50900 1 0 1 resistor-2.sym +{ +T 50200 51250 5 10 0 0 0 6 1 +device=RESISTOR +T 50400 50900 5 10 1 1 0 6 1 +refdes=R? +} +N 49700 51000 49300 51000 4 +C 51100 50600 1 0 1 gnd-1.sym +N 50600 51000 51000 51000 4 +N 51000 50900 51000 52500 4 +N 48400 51000 48000 51000 4 +C 48400 50900 1 0 0 led-2.sym +{ +T 49000 51100 5 10 1 1 0 0 1 +refdes=D? +T 48500 51500 5 10 0 0 0 0 1 +device=LED +} +C 50600 50600 1 0 1 resistor-2.sym +{ +T 50200 50950 5 10 0 0 0 6 1 +device=RESISTOR +T 50400 50600 5 10 1 1 0 6 1 +refdes=R? +} +N 49700 50700 49300 50700 4 +N 48400 50700 48000 50700 4 +C 48400 50600 1 0 0 led-2.sym +{ +T 49000 50800 5 10 1 1 0 0 1 +refdes=D? +T 48500 51200 5 10 0 0 0 0 1 +device=LED +} +C 50600 50300 1 0 1 resistor-2.sym +{ +T 50200 50650 5 10 0 0 0 6 1 +device=RESISTOR +T 50400 50300 5 10 1 1 0 6 1 +refdes=R? +} +N 49700 50400 49300 50400 4 +N 48400 50400 48000 50400 4 +C 48400 50300 1 0 0 led-2.sym +{ +T 49000 50500 5 10 1 1 0 0 1 +refdes=D? +T 48500 50900 5 10 0 0 0 0 1 +device=LED +} +N 50600 50400 50600 51000 4 +C 48700 41600 1 0 0 crystal-1.sym +{ +T 48900 42100 5 10 0 0 0 0 1 +device=CRYSTAL +T 48900 41900 5 10 1 1 0 0 1 +refdes=U? +T 48900 42300 5 10 0 0 0 0 1 +symversion=0.1 +} +N 48000 42100 48700 42100 4 +N 48700 42100 48700 41400 4 +N 48000 42400 49400 42400 4 +N 49400 42400 49400 41400 4 +C 48900 40500 1 90 0 capacitor-1.sym +{ +T 48200 40700 5 10 0 0 90 0 1 +device=CAPACITOR +T 48400 40700 5 10 1 1 90 0 1 +refdes=C? +T 48000 40700 5 10 0 0 90 0 1 +symversion=0.1 +} +C 49600 40500 1 90 0 capacitor-1.sym +{ +T 48900 40700 5 10 0 0 90 0 1 +device=CAPACITOR +T 49100 40700 5 10 1 1 90 0 1 +refdes=C? +T 48700 40700 5 10 0 0 90 0 1 +symversion=0.1 +} +N 48700 40500 49400 40500 4 +C 49000 40200 1 0 0 gnd-1.sym +C 51000 57600 1 0 0 crystal-1.sym +{ +T 51200 58100 5 10 0 0 0 0 1 +device=CRYSTAL +T 51200 57900 5 10 1 1 0 0 1 +refdes=U? +T 51200 58300 5 10 0 0 0 0 1 +symversion=0.1 +} +N 51000 58400 51000 57400 4 +N 51700 58000 51700 57400 4 +C 51200 56500 1 90 0 capacitor-1.sym +{ +T 50500 56700 5 10 0 0 90 0 1 +device=CAPACITOR +T 50700 56700 5 10 1 1 90 0 1 +refdes=C? +T 50300 56700 5 10 0 0 90 0 1 +symversion=0.1 +} +C 51900 56500 1 90 0 capacitor-1.sym +{ +T 51200 56700 5 10 0 0 90 0 1 +device=CAPACITOR +T 51400 56700 5 10 1 1 90 0 1 +refdes=C? +T 51000 56700 5 10 0 0 90 0 1 +symversion=0.1 +} +N 51000 56500 51700 56500 4 +C 51300 56200 1 0 0 gnd-1.sym +N 53000 58400 51000 58400 4 +N 53000 58000 51700 58000 4 +C 50600 52400 1 0 1 resistor-2.sym +{ +T 50200 52750 5 10 0 0 0 6 1 +device=RESISTOR +T 50100 52700 5 10 1 1 0 6 1 +refdes=R? +} +N 49700 52500 49300 52500 4 +N 50600 52500 51000 52500 4 +C 48400 52400 1 0 0 led-2.sym +{ +T 49000 52600 5 10 1 1 0 0 1 +refdes=D? +T 48500 53000 5 10 0 0 0 0 1 +device=LED +} +N 48400 52500 47900 52500 4 +{ +T 48600 52600 5 10 1 1 0 6 1 +netname=LED_AT168 +} +N 56600 60800 57500 60800 4 +{ +T 56800 60900 5 10 1 1 0 0 1 +netname=LED_AT168 +} +C 62700 48900 1 0 0 74126-1.sym +{ +T 64800 50440 5 10 0 0 0 0 1 +device=74126 +T 64800 50240 5 10 0 0 0 0 1 +footprint=DIP14 +T 64400 49900 5 10 1 1 0 6 1 +refdes=U5 +T 62700 48900 5 10 0 0 0 0 1 +slot=1 +T 62700 48900 5 10 0 0 0 0 1 +net=+3.3V:14 +} +C 62700 47600 1 0 0 74126-1.sym +{ +T 64800 49140 5 10 0 0 0 0 1 +device=74126 +T 64800 48940 5 10 0 0 0 0 1 +footprint=DIP14 +T 64400 48600 5 10 1 1 0 6 1 +refdes=U5 +T 62700 47600 5 10 0 0 0 0 1 +slot=2 +T 62700 47600 5 10 0 0 0 0 1 +net=+3.3V:14 +} +N 62700 47800 62000 47800 4 +{ +T 62000 47900 5 10 1 1 0 0 1 +netname=RESET +} +N 62700 49100 62000 49100 4 +{ +T 62000 49200 5 10 1 1 0 0 1 +netname=RESET +} +N 62000 49500 62700 49500 4 +{ +T 61600 49600 5 10 1 1 0 0 1 +netname=MOSI_XMEGA +} +N 62000 48200 62700 48200 4 +{ +T 61600 48300 5 10 1 1 0 0 1 +netname=SCK_XMEGA +} +N 65600 49500 64700 49500 4 +{ +T 64700 49600 5 10 1 1 0 0 1 +netname=MOSI_MEGA +} +N 65600 48200 64700 48200 4 +{ +T 64700 48300 5 10 1 1 0 0 1 +netname=SCK_MEGA +} +C 70900 43200 1 0 0 resistor-2.sym +{ +T 71300 43550 5 10 0 0 0 0 1 +device=RESISTOR +T 71500 43000 5 10 1 1 0 0 1 +refdes=R? +} +C 70900 42400 1 0 0 resistor-2.sym +{ +T 71300 42750 5 10 0 0 0 0 1 +device=RESISTOR +T 71500 42200 5 10 1 1 0 0 1 +refdes=R? +} +N 71800 42500 71900 42500 4 +N 71900 43300 71800 43300 4 +C 71700 59500 1 0 0 connector6-2.sym +{ +T 72400 62400 5 10 1 1 0 6 1 +refdes=CONN? +T 72000 62350 5 10 0 0 0 0 1 +device=CONNECTOR_6 +T 72000 62550 5 10 0 0 0 0 1 +footprint=SIP6N +} +C 69800 59900 1 0 0 connector4-2.sym +{ +T 70500 62000 5 10 1 1 0 6 1 +refdes=CONN? +T 70100 61950 5 10 0 0 0 0 1 +device=CONNECTOR_4 +T 70100 62150 5 10 0 0 0 0 1 +footprint=SIP4N +} +C 71300 59600 1 0 0 gnd-1.sym +C 69400 60000 1 0 0 gnd-1.sym +N 69500 61600 69500 61500 4 +N 69500 61500 69800 61500 4 +N 69500 60300 69800 60300 4 +N 71400 59900 71700 59900 4 +N 71400 62000 71400 61900 4 +N 71400 61900 71700 61900 4 +N 69800 61100 69300 61100 4 +{ +T 69200 61200 5 10 1 1 0 0 1 +netname=SCL +} +N 69800 60700 69300 60700 4 +{ +T 69200 60800 5 10 1 1 0 0 1 +netname=SDA +} +N 71700 61500 71200 61500 4 +{ +T 71100 61600 5 10 1 1 0 0 1 +netname=GPIO1 +} +N 71700 61100 71200 61100 4 +{ +T 71100 61200 5 10 1 1 0 0 1 +netname=GPIO2 +} +C 71200 62000 1 0 0 5V-plus-1.sym +C 69300 61600 1 0 0 3.3V-plus-1.sym +N 71700 60700 71200 60700 4 +{ +T 71100 60800 5 10 1 1 0 0 1 +netname=GPIO3 +} +N 71700 60300 71200 60300 4 +{ +T 71100 60400 5 10 1 1 0 0 1 +netname=GPIO4 +} +N 43600 48400 42300 48400 4 +{ +T 42200 48500 5 10 1 1 0 0 1 +netname=GPIO1 +} +N 43600 48100 42300 48100 4 +{ +T 42200 48200 5 10 1 1 0 0 1 +netname=GPIO2 +} +N 43600 47800 42300 47800 4 +{ +T 42200 47900 5 10 1 1 0 0 1 +netname=GPIO3 +} +N 43600 47500 42300 47500 4 +{ +T 42200 47600 5 10 1 1 0 0 1 +netname=GPIO4 +} +N 40700 45500 43600 45500 4 +{ +T 42300 45600 5 10 1 1 0 0 1 +netname=SCL +} +N 41100 45800 43600 45800 4 +{ +T 42300 45900 5 10 1 1 0 0 1 +netname=SDA +} +C 40800 45600 1 90 0 resistor-2.sym +{ +T 40450 46000 5 10 0 0 90 0 1 +device=RESISTOR +T 40800 45800 5 10 1 1 90 0 1 +refdes=R? +} +C 41200 45900 1 90 0 resistor-2.sym +{ +T 40850 46300 5 10 0 0 90 0 1 +device=RESISTOR +T 41200 46100 5 10 1 1 90 0 1 +refdes=R? +} +N 40700 45500 40700 45600 4 +N 41100 45900 41100 45800 4 +N 41100 46800 40700 46800 4 +N 40700 46500 40700 47100 4 +C 40500 47100 1 0 0 3.3V-plus-1.sym +N 70600 43700 70600 44900 4 +C 70500 50900 1 0 0 gnd-1.sym +C 70700 48100 1 0 0 5V-plus-1.sym +C 40100 39900 0 0 0 title-A1.sym +C 43000 61500 1 0 1 connector2-1.sym +{ +T 42800 62500 5 10 0 0 0 6 1 +device=CONNECTOR_2 +T 43000 62300 5 10 1 1 0 6 1 +refdes=CONN? +} +N 41300 62000 40600 62000 4 +C 40400 62000 1 0 0 5V-plus-1.sym +C 40500 61400 1 0 0 gnd-1.sym +N 41300 61700 40600 61700 4 +C 66300 60900 1 0 1 connector3-1.sym +{ +T 64500 61800 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 66300 62000 5 10 1 1 0 6 1 +refdes=CONN? +} +C 66300 59500 1 0 1 connector3-1.sym +{ +T 64500 60400 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 66300 60600 5 10 1 1 0 6 1 +refdes=CONN? +} +C 66300 58100 1 0 1 connector3-1.sym +{ +T 64500 59000 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 66300 59200 5 10 1 1 0 6 1 +refdes=CONN? +} +C 66300 56700 1 0 1 connector3-1.sym +{ +T 64500 57600 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 66300 57800 5 10 1 1 0 6 1 +refdes=CONN? +} +C 66300 55300 1 0 1 connector3-1.sym +{ +T 64500 56200 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 66300 56400 5 10 1 1 0 6 1 +refdes=CONN? +} +C 66300 53900 1 0 1 connector3-1.sym +{ +T 64500 54800 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 66300 55000 5 10 1 1 0 6 1 +refdes=CONN? +} +T 70000 59000 9 16 1 0 0 0 1 +BUS connector +T 68000 52300 9 16 1 0 0 0 2 +DEBUG connector +ATxmega +T 68400 45800 9 16 1 0 0 0 2 +DEBUG connector +ATmega +T 63500 41200 9 16 1 0 0 0 1 +Xbee +T 53400 62500 9 16 1 0 0 0 1 +ATmega (servo) +T 41600 53900 9 16 1 0 0 0 2 +ATxmega (main +program) +T 62400 50400 9 16 1 0 0 0 2 +ATmega spi multiplexer +(3.3V) +N 64600 61700 64100 61700 4 +{ +T 64200 61800 5 10 1 1 0 0 1 +netname=S_IN1_PPM +} +N 64600 61400 63600 61400 4 +N 64600 61100 64100 61100 4 +C 64000 60800 1 0 0 gnd-1.sym +C 63400 61400 1 0 0 5V-plus-1.sym +N 64600 60300 64100 60300 4 +{ +T 64200 60400 5 10 1 1 0 0 1 +netname=S_IN2 +} +N 64600 60000 63600 60000 4 +N 64600 59700 64100 59700 4 +C 64000 59400 1 0 0 gnd-1.sym +C 63400 60000 1 0 0 5V-plus-1.sym +N 64600 58900 64100 58900 4 +{ +T 64200 59000 5 10 1 1 0 0 1 +netname=S_IN3 +} +N 64600 58600 63600 58600 4 +N 64600 58300 64100 58300 4 +C 64000 58000 1 0 0 gnd-1.sym +C 63400 58600 1 0 0 5V-plus-1.sym +N 64600 57500 64100 57500 4 +{ +T 64200 57600 5 10 1 1 0 0 1 +netname=S_IN4 +} +N 64600 57200 63600 57200 4 +N 64600 56900 64100 56900 4 +C 64000 56600 1 0 0 gnd-1.sym +C 63400 57200 1 0 0 5V-plus-1.sym +N 64600 56100 64100 56100 4 +{ +T 64200 56200 5 10 1 1 0 0 1 +netname=S_IN5 +} +N 64600 55800 63600 55800 4 +N 64600 55500 64100 55500 4 +C 64000 55200 1 0 0 gnd-1.sym +C 63400 55800 1 0 0 5V-plus-1.sym +N 64600 54700 64100 54700 4 +{ +T 64200 54800 5 10 1 1 0 0 1 +netname=S_IN6 +} +N 64600 54400 63600 54400 4 +N 64600 54100 64100 54100 4 +C 64000 53800 1 0 0 gnd-1.sym +C 63400 54400 1 0 0 5V-plus-1.sym +C 62500 60900 1 0 1 connector3-1.sym +{ +T 60700 61800 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 62500 62000 5 10 1 1 0 6 1 +refdes=CONN? +} +C 62500 59500 1 0 1 connector3-1.sym +{ +T 60700 60400 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 62500 60600 5 10 1 1 0 6 1 +refdes=CONN? +} +C 62500 58100 1 0 1 connector3-1.sym +{ +T 60700 59000 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 62500 59200 5 10 1 1 0 6 1 +refdes=CONN? +} +C 62500 56700 1 0 1 connector3-1.sym +{ +T 60700 57600 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 62500 57800 5 10 1 1 0 6 1 +refdes=CONN? +} +C 62500 55300 1 0 1 connector3-1.sym +{ +T 60700 56200 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 62500 56400 5 10 1 1 0 6 1 +refdes=CONN? +} +C 62500 53900 1 0 1 connector3-1.sym +{ +T 60700 54800 5 10 0 0 0 6 1 +device=CONNECTOR_3 +T 62500 55000 5 10 1 1 0 6 1 +refdes=CONN? +} +N 60800 61700 60300 61700 4 +{ +T 60400 61800 5 10 1 1 0 0 1 +netname=S_OUT1 +} +N 60800 61400 59800 61400 4 +N 60800 61100 60300 61100 4 +C 60200 60800 1 0 0 gnd-1.sym +C 59600 61400 1 0 0 5V-plus-1.sym +N 60800 60300 60300 60300 4 +{ +T 60400 60400 5 10 1 1 0 0 1 +netname=S_OUT2 +} +N 60800 60000 59800 60000 4 +N 60800 59700 60300 59700 4 +C 60200 59400 1 0 0 gnd-1.sym +C 59600 60000 1 0 0 5V-plus-1.sym +N 60800 58900 60300 58900 4 +{ +T 60400 59000 5 10 1 1 0 0 1 +netname=S_OUT3 +} +N 60800 58600 59800 58600 4 +N 60800 58300 60300 58300 4 +C 60200 58000 1 0 0 gnd-1.sym +C 59600 58600 1 0 0 5V-plus-1.sym +N 60800 57500 60300 57500 4 +{ +T 60400 57600 5 10 1 1 0 0 1 +netname=S_OUT4 +} +N 60800 57200 59800 57200 4 +N 60800 56900 60300 56900 4 +C 60200 56600 1 0 0 gnd-1.sym +C 59600 57200 1 0 0 5V-plus-1.sym +N 60800 56100 60300 56100 4 +{ +T 60400 56200 5 10 1 1 0 0 1 +netname=S_OUT5 +} +N 60800 55800 59800 55800 4 +N 60800 55500 60300 55500 4 +C 60200 55200 1 0 0 gnd-1.sym +C 59600 55800 1 0 0 5V-plus-1.sym +N 60800 54700 60300 54700 4 +{ +T 60400 54800 5 10 1 1 0 0 1 +netname=S_OUT6 +} +N 60800 54400 59800 54400 4 +N 60800 54100 60300 54100 4 +C 60200 53800 1 0 0 gnd-1.sym +C 59600 54400 1 0 0 5V-plus-1.sym +T 64000 52900 9 16 1 0 0 0 1 +Servo input +T 60200 53000 9 16 1 0 0 0 1 +Servo output +N 57500 58800 56600 58800 4 +{ +T 56900 58900 5 10 1 1 0 0 1 +netname=S_IN1_PPM +} +N 57500 58400 56600 58400 4 +{ +T 56900 58500 5 10 1 1 0 0 1 +netname=S_IN2 +} +N 57500 58000 56600 58000 4 +{ +T 56900 58100 5 10 1 1 0 0 1 +netname=S_IN3 +} +N 57500 57600 56600 57600 4 +{ +T 56900 57700 5 10 1 1 0 0 1 +netname=S_IN4 +} +N 57500 57200 56600 57200 4 +{ +T 56900 57300 5 10 1 1 0 0 1 +netname=S_IN5 +} +N 57500 56800 56600 56800 4 +{ +T 56900 56900 5 10 1 1 0 0 1 +netname=S_IN6 +} +N 57500 55600 56600 55600 4 +{ +T 56700 55700 5 10 1 1 0 0 1 +netname=S_OUT1 +} +N 57500 55200 56600 55200 4 +{ +T 56700 55300 5 10 1 1 0 0 1 +netname=S_OUT2 +} +N 57500 54800 56600 54800 4 +{ +T 56700 54900 5 10 1 1 0 0 1 +netname=S_OUT3 +} +N 57500 54400 56600 54400 4 +{ +T 56700 54500 5 10 1 1 0 0 1 +netname=S_OUT4 +} +N 57500 54000 56600 54000 4 +{ +T 56700 54100 5 10 1 1 0 0 1 +netname=S_OUT5 +} +N 57500 53600 56600 53600 4 +{ +T 56700 53700 5 10 1 1 0 0 1 +netname=S_OUT6 +} +C 51100 41000 1 0 0 connector10-2.sym +{ +T 51800 45500 5 10 1 1 0 6 1 +refdes=CONN? +T 51400 45450 5 10 0 0 0 0 1 +device=CONNECTOR_10 +T 51400 45650 5 10 0 0 0 0 1 +footprint=SIP10N +} +C 51100 45800 1 0 0 connector10-2.sym +{ +T 51800 50300 5 10 1 1 0 6 1 +refdes=CONN? +T 51400 50250 5 10 0 0 0 0 1 +device=CONNECTOR_10 +T 51400 50450 5 10 0 0 0 0 1 +footprint=SIP10N +} +C 41200 48100 1 0 1 connector10-2.sym +{ +T 40500 52600 5 10 1 1 0 0 1 +refdes=CONN? +T 40900 52550 5 10 0 0 0 6 1 +device=CONNECTOR_10 +T 40900 52750 5 10 0 0 0 6 1 +footprint=SIP10N +} +N 43600 51000 43400 51000 4 +N 43400 51000 43400 52100 4 +N 43400 52100 41200 52100 4 +N 41200 51700 43200 51700 4 +N 43200 51700 43200 50700 4 +N 43200 50700 43600 50700 4 +N 43600 50400 43000 50400 4 +N 43000 50400 43000 51300 4 +N 43000 51300 41200 51300 4 +N 41200 50900 42800 50900 4 +N 42800 50900 42800 50100 4 +N 42800 50100 43600 50100 4 +N 43600 49800 42600 49800 4 +N 42600 49800 42600 50500 4 +N 42600 50500 41200 50500 4 +N 41200 50100 42400 50100 4 +N 42400 50100 42400 49500 4 +N 42400 49500 43600 49500 4 +N 43600 49200 42200 49200 4 +N 42200 49200 42200 49700 4 +N 42200 49700 41200 49700 4 +N 41200 49300 42000 49300 4 +N 42000 49300 42000 48900 4 +N 42000 48900 43600 48900 4 +C 41900 48800 1 0 1 3.3V-plus-1.sym +C 41600 48200 1 0 1 gnd-1.sym +N 41200 48900 41500 48900 4 +N 41500 48900 41500 48800 4 +N 41500 48800 41700 48800 4 +N 41200 48500 41500 48500 4 +N 48000 48400 49700 48400 4 +N 48000 48100 49800 48100 4 +N 48000 47500 50000 47500 4 +N 48000 47200 50100 47200 4 +N 48000 46900 50200 46900 4 +N 48000 46600 50300 46600 4 +N 48000 46300 50400 46300 4 +C 50500 46500 1 0 0 3.3V-plus-1.sym +C 50800 45900 1 0 0 gnd-1.sym +N 51100 46600 50900 46600 4 +N 50900 46600 50900 46500 4 +N 50900 46500 50700 46500 4 +N 51100 46200 50900 46200 4 +C 50400 41700 1 0 0 3.3V-plus-1.sym +C 50700 41100 1 0 0 gnd-1.sym +N 51100 41800 50800 41800 4 +N 50800 41800 50800 41700 4 +N 50800 41700 50600 41700 4 +N 51100 41400 50800 41400 4 +N 48000 45800 50600 45800 4 +N 50600 45800 50600 45000 4 +N 51100 44600 50500 44600 4 +N 50500 44600 50500 45500 4 +N 50500 45500 48000 45500 4 +N 51100 44200 50400 44200 4 +N 50400 44200 50400 45200 4 +N 50400 45200 48000 45200 4 +N 51100 43800 50300 43800 4 +N 50300 43800 50300 44900 4 +N 50300 44900 48000 44900 4 +N 51100 43400 50200 43400 4 +N 50200 43400 50200 44600 4 +N 50200 44600 48000 44600 4 +N 51100 43000 50100 43000 4 +N 50100 43000 50100 44300 4 +N 50100 44300 48000 44300 4 +N 51100 42600 50000 42600 4 +N 50000 42600 50000 44000 4 +N 50000 44000 48000 44000 4 +N 51100 42200 49900 42200 4 +N 49900 42200 49900 43700 4 +N 49900 43700 48000 43700 4 +N 57500 61200 56600 61200 4 +{ +T 56900 61300 5 10 1 1 0 0 1 +netname=S_IN1_PPM +} +N 50400 46300 50400 47000 4 +N 50400 47000 51100 47000 4 +N 50300 46600 50300 47400 4 +N 50300 47400 51100 47400 4 +N 50200 46900 50200 47800 4 +N 50200 47800 51100 47800 4 +N 50100 47200 50100 48200 4 +N 50100 48200 51100 48200 4 +N 50000 47500 50000 48600 4 +N 50000 48600 51100 48600 4 +N 48000 47800 49900 47800 4 +N 49900 47800 49900 49000 4 +N 49900 49000 51100 49000 4 +N 49800 48100 49800 49400 4 +N 49800 49400 51100 49400 4 +N 49700 48400 49700 49800 4 +N 49700 49800 51100 49800 4 +N 48000 50100 49200 50100 4 +{ +T 48300 50200 5 10 1 1 0 0 1 +netname=RTS_XBEE +} +N 48000 49800 49200 49800 4 +{ +T 48300 49900 5 10 1 1 0 0 1 +netname=CTS_XBEE +} +N 48000 49500 49200 49500 4 +{ +T 48300 49600 5 10 1 1 0 0 1 +netname=DTR_XBEE +} +N 50600 45000 51100 45000 4 +C 44400 57200 1 0 0 connector1-2.sym +{ +T 45100 58100 5 10 1 1 0 6 1 +refdes=CONN? +T 44700 58050 5 10 0 0 0 0 1 +device=CONNECTOR_1 +T 44700 58250 5 10 0 0 0 0 1 +footprint=SIP1N +} +N 44400 57600 43700 57600 4 +C 43500 57600 1 0 0 5V-plus-1.sym +C 43600 56000 1 0 0 gnd-1.sym +C 44400 55900 1 0 0 connector1-2.sym +{ +T 45100 56800 5 10 1 1 0 6 1 +refdes=CONN? +T 44700 56750 5 10 0 0 0 0 1 +device=CONNECTOR_1 +T 44700 56950 5 10 0 0 0 0 1 +footprint=SIP1N +} +N 44400 56300 43700 56300 4 +C 47300 56200 1 0 0 connector1-2.sym +{ +T 48000 57100 5 10 1 1 0 6 1 +refdes=CONN? +T 47600 57050 5 10 0 0 0 0 1 +device=CONNECTOR_1 +T 47600 57250 5 10 0 0 0 0 1 +footprint=SIP1N +} +N 45900 56600 47300 56600 4 +{ +T 45900 56700 5 10 1 1 0 0 1 +netname=SCK_XMEGA +} +C 47300 57500 1 0 0 connector1-2.sym +{ +T 48000 58400 5 10 1 1 0 6 1 +refdes=CONN? +T 47600 58350 5 10 0 0 0 0 1 +device=CONNECTOR_1 +T 47600 58550 5 10 0 0 0 0 1 +footprint=SIP1N +} +N 45900 57900 47300 57900 4 +{ +T 45900 58000 5 10 1 1 0 0 1 +netname=MOSI_XMEGA +} +C 44400 58500 1 0 0 connector1-2.sym +{ +T 45100 59400 5 10 1 1 0 6 1 +refdes=CONN? +T 44700 59350 5 10 0 0 0 0 1 +device=CONNECTOR_1 +T 44700 59550 5 10 0 0 0 0 1 +footprint=SIP1N +} +N 44400 58900 43700 58900 4 +C 43500 58900 1 0 0 3.3V-plus-1.sym +T 45600 58800 9 16 1 0 0 0 1 +test pins