2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_32 3
51 #define TIMER1_PRESCALER_DIV_64 4
52 #define TIMER1_PRESCALER_DIV_128 5
53 #define TIMER1_PRESCALER_DIV_256 6
54 #define TIMER1_PRESCALER_DIV_1024 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 32
60 #define TIMER1_PRESCALER_REG_4 64
61 #define TIMER1_PRESCALER_REG_5 128
62 #define TIMER1_PRESCALER_REG_6 256
63 #define TIMER1_PRESCALER_REG_7 1024
66 /* available timers */
68 /* overflow interrupt number */
69 #define SIG_OVERFLOW_TOTAL_NUM 0
71 /* output compare interrupt number */
72 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
75 #define PWM_TOTAL_NUM 0
77 /* input capture interrupt number */
78 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
82 #define CADAC16_REG CADAC2
83 #define CADAC17_REG CADAC2
84 #define CADAC18_REG CADAC2
85 #define CADAC19_REG CADAC2
86 #define CADAC20_REG CADAC2
87 #define CADAC21_REG CADAC2
88 #define CADAC22_REG CADAC2
89 #define CADAC23_REG CADAC2
92 #define CADAC24_REG CADAC3
93 #define CADAC25_REG CADAC3
94 #define CADAC26_REG CADAC3
95 #define CADAC27_REG CADAC3
96 #define CADAC28_REG CADAC3
97 #define CADAC29_REG CADAC3
98 #define CADAC30_REG CADAC3
99 #define CADAC31_REG CADAC3
102 #define CADAC00_REG CADAC0
103 #define CADAC01_REG CADAC0
104 #define CADAC02_REG CADAC0
105 #define CADAC03_REG CADAC0
106 #define CADAC04_REG CADAC0
107 #define CADAC05_REG CADAC0
108 #define CADAC06_REG CADAC0
109 #define CADAC07_REG CADAC0
112 #define CADAC08_REG CADAC1
113 #define CADAC09_REG CADAC1
114 #define CADAC10_REG CADAC1
115 #define CADAC11_REG CADAC1
116 #define CADAC12_REG CADAC1
117 #define CADAC13_REG CADAC1
118 #define CADAC14_REG CADAC1
119 #define CADAC15_REG CADAC1
122 #define EERE_REG EECR
123 #define EEPE_REG EECR
124 #define EEMPE_REG EECR
125 #define EERIE_REG EECR
126 #define EEPM0_REG EECR
127 #define EEPM1_REG EECR
130 #define PCIF0_REG PCIFR
131 #define PCIF1_REG PCIFR
134 #define WUTP0_REG WUTCSR
135 #define WUTP1_REG WUTCSR
136 #define WUTP2_REG WUTCSR
137 #define WUTE_REG WUTCSR
138 #define WUTR_REG WUTCSR
139 #define WUTCF_REG WUTCSR
140 #define WUTIE_REG WUTCSR
141 #define WUTIF_REG WUTCSR
154 #define PCIE0_REG PCICR
155 #define PCIE1_REG PCICR
158 #define DDB0_REG DDRB
159 #define DDB1_REG DDRB
160 #define DDB2_REG DDRB
161 #define DDB3_REG DDRB
162 #define DDB4_REG DDRB
163 #define DDB5_REG DDRB
164 #define DDB6_REG DDRB
165 #define DDB7_REG DDRB
171 #define DUVD_REG BPCR
174 #define WDP0_REG WDTCSR
175 #define WDP1_REG WDTCSR
176 #define WDP2_REG WDTCSR
177 #define WDE_REG WDTCSR
178 #define WDCE_REG WDTCSR
179 #define WDP3_REG WDTCSR
180 #define WDIE_REG WDTCSR
181 #define WDIF_REG WDTCSR
184 #define EEDR0_REG EEDR
185 #define EEDR1_REG EEDR
186 #define EEDR2_REG EEDR
187 #define EEDR3_REG EEDR
188 #define EEDR4_REG EEDR
189 #define EEDR5_REG EEDR
190 #define EEDR6_REG EEDR
191 #define EEDR7_REG EEDR
194 #define TWD0_REG TWDR
195 #define TWD1_REG TWDR
196 #define TWD2_REG TWDR
197 #define TWD3_REG TWDR
198 #define TWD4_REG TWDR
199 #define TWD5_REG TWDR
200 #define TWD6_REG TWDR
201 #define TWD7_REG TWDR
204 #define PIND0_REG PIND
205 #define PIND1_REG PIND
208 #define PSRSYNC_REG GTCCR
209 #define TSM_REG GTCCR
212 #define TWBR0_REG TWBR
213 #define TWBR1_REG TWBR
214 #define TWBR2_REG TWBR
215 #define TWBR3_REG TWBR
216 #define TWBR4_REG TWBR
217 #define TWBR5_REG TWBR
218 #define TWBR6_REG TWBR
219 #define TWBR7_REG TWBR
222 #define BGCR0_REG BGCRR
223 #define BGCR1_REG BGCRR
224 #define BGCR2_REG BGCRR
225 #define BGCR3_REG BGCRR
226 #define BGCR4_REG BGCRR
227 #define BGCR5_REG BGCRR
228 #define BGCR6_REG BGCRR
229 #define BGCR7_REG BGCRR
232 #define DDA0_REG DDRA
233 #define DDA1_REG DDRA
234 #define DDA2_REG DDRA
235 #define DDA3_REG DDRA
236 #define DDA4_REG DDRA
237 #define DDA5_REG DDRA
238 #define DDA6_REG DDRA
239 #define DDA7_REG DDRA
242 #define INT0_REG EIMSK
243 #define INT1_REG EIMSK
244 #define INT2_REG EIMSK
245 #define INT3_REG EIMSK
248 #define PRVADC_REG PRR0
249 #define PRTIM0_REG PRR0
250 #define PRTIM1_REG PRR0
251 #define PRTWI_REG PRR0
254 #define PCINT8_REG PCMSK1
255 #define PCINT9_REG PCMSK1
256 #define PCINT10_REG PCMSK1
257 #define PCINT11_REG PCMSK1
258 #define PCINT12_REG PCMSK1
259 #define PCINT13_REG PCMSK1
260 #define PCINT14_REG PCMSK1
261 #define PCINT15_REG PCMSK1
264 #define OCR0A0_REG OCR0A
265 #define OCR0A1_REG OCR0A
266 #define OCR0A2_REG OCR0A
267 #define OCR0A3_REG OCR0A
268 #define OCR0A4_REG OCR0A
269 #define OCR0A5_REG OCR0A
270 #define OCR0A6_REG OCR0A
271 #define OCR0A7_REG OCR0A
274 #define CCDL0_REG BPOCD
275 #define CCDL1_REG BPOCD
276 #define CCDL2_REG BPOCD
277 #define CCDL3_REG BPOCD
278 #define DCDL0_REG BPOCD
279 #define DCDL1_REG BPOCD
280 #define DCDL2_REG BPOCD
281 #define DCDL3_REG BPOCD
284 #define DDD0_REG DDRD
285 #define DDD1_REG DDRD
288 #define OCR0B0_REG OCR0B
289 #define OCR0B1_REG OCR0B
290 #define OCR0B2_REG OCR0B
291 #define OCR0B3_REG OCR0B
292 #define OCR0B4_REG OCR0B
293 #define OCR0B5_REG OCR0B
294 #define OCR0B6_REG OCR0B
295 #define OCR0B7_REG OCR0B
312 #define CADICH0_REG CADICH
313 #define CADICH1_REG CADICH
314 #define CADICH2_REG CADICH
315 #define CADICH3_REG CADICH
316 #define CADICH4_REG CADICH
317 #define CADICH5_REG CADICH
318 #define CADICH6_REG CADICH
319 #define CADICH7_REG CADICH
326 #define PWMOPC_REG FCSR
327 #define PWMOC_REG FCSR
340 #define CADICIF_REG CADCSRB
341 #define CADRCIF_REG CADCSRB
342 #define CADACIF_REG CADCSRB
343 #define CADICIE_REG CADCSRB
344 #define CADRCIE_REG CADCSRB
345 #define CADACIE_REG CADCSRB
348 #define CADICL0_REG CADICL
349 #define CADICL1_REG CADICL
350 #define CADICL2_REG CADICL
351 #define CADICL3_REG CADICL
352 #define CADICL4_REG CADICL
353 #define CADICL5_REG CADICL
354 #define CADICL6_REG CADICL
355 #define CADICL7_REG CADICL
358 #define SCIE_REG BPIR
359 #define DOCIE_REG BPIR
360 #define COCIE_REG BPIR
361 #define DUVIE_REG BPIR
362 #define SCIF_REG BPIR
363 #define DOCIF_REG BPIR
364 #define COCIF_REG BPIR
365 #define DUVIF_REG BPIR
368 #define GPIOR10_REG GPIOR1
369 #define GPIOR11_REG GPIOR1
370 #define GPIOR12_REG GPIOR1
371 #define GPIOR13_REG GPIOR1
372 #define GPIOR14_REG GPIOR1
373 #define GPIOR15_REG GPIOR1
374 #define GPIOR16_REG GPIOR1
375 #define GPIOR17_REG GPIOR1
378 #define BPPL_REG BPPLR
379 #define BPPLE_REG BPPLR
382 #define CS10_REG TCCR1B
383 #define CS11_REG TCCR1B
384 #define CS12_REG TCCR1B
385 #define CTC1_REG TCCR1B
388 #define PORF_REG MCUSR
389 #define EXTRF_REG MCUSR
390 #define BODRF_REG MCUSR
391 #define WDRF_REG MCUSR
392 #define JTRF_REG MCUSR
395 #define EEAR8_REG EEARH
398 #define OCPT0_REG CBPTR
399 #define OCPT1_REG CBPTR
400 #define OCPT2_REG CBPTR
401 #define OCPT3_REG CBPTR
402 #define SCPT0_REG CBPTR
403 #define SCPT1_REG CBPTR
404 #define SCPT2_REG CBPTR
405 #define SCPT3_REG CBPTR
408 #define SPMEN_REG SPMCSR
409 #define PGERS_REG SPMCSR
410 #define PGWRT_REG SPMCSR
411 #define BLBSET_REG SPMCSR
412 #define RWWSRE_REG SPMCSR
413 #define SIGRD_REG SPMCSR
414 #define RWWSB_REG SPMCSR
415 #define SPMIE_REG SPMCSR
418 #define CADSE_REG CADCSRA
419 #define CADSI0_REG CADCSRA
420 #define CADSI1_REG CADCSRA
421 #define CADAS0_REG CADCSRA
422 #define CADAS1_REG CADCSRA
423 #define CADUB_REG CADCSRA
424 #define CADEN_REG CADCSRA
427 #define DUDL0_REG BPDUV
428 #define DUDL1_REG BPDUV
429 #define DUDL2_REG BPDUV
430 #define DUDL3_REG BPDUV
431 #define DUVT0_REG BPDUV
432 #define DUVT1_REG BPDUV
435 #define CADRDC0_REG CADRDC
436 #define CADRDC1_REG CADRDC
437 #define CADRDC2_REG CADRDC
438 #define CADRDC3_REG CADRDC
439 #define CADRDC4_REG CADRDC
440 #define CADRDC5_REG CADRDC
441 #define CADRDC6_REG CADRDC
442 #define CADRDC7_REG CADRDC
445 #define TCNT1L0_REG TCNT1L
446 #define TCNT1L1_REG TCNT1L
447 #define TCNT1L2_REG TCNT1L
448 #define TCNT1L3_REG TCNT1L
449 #define TCNT1L4_REG TCNT1L
450 #define TCNT1L5_REG TCNT1L
451 #define TCNT1L6_REG TCNT1L
452 #define TCNT1L7_REG TCNT1L
455 #define PORTB0_REG PORTB
456 #define PORTB1_REG PORTB
457 #define PORTB2_REG PORTB
458 #define PORTB3_REG PORTB
459 #define PORTB4_REG PORTB
460 #define PORTB5_REG PORTB
461 #define PORTB6_REG PORTB
462 #define PORTB7_REG PORTB
465 #define PORTD0_REG PORTD
466 #define PORTD1_REG PORTD
475 #define TCNT1H0_REG TCNT1H
476 #define TCNT1H1_REG TCNT1H
477 #define TCNT1H2_REG TCNT1H
478 #define TCNT1H3_REG TCNT1H
479 #define TCNT1H4_REG TCNT1H
480 #define TCNT1H5_REG TCNT1H
481 #define TCNT1H6_REG TCNT1H
482 #define TCNT1H7_REG TCNT1H
485 #define PORTC0_REG PORTC
488 #define TWAM0_REG TWAMR
489 #define TWAM1_REG TWAMR
490 #define TWAM2_REG TWAMR
491 #define TWAM3_REG TWAMR
492 #define TWAM4_REG TWAMR
493 #define TWAM5_REG TWAMR
494 #define TWAM6_REG TWAMR
497 #define PORTA0_REG PORTA
498 #define PORTA1_REG PORTA
499 #define PORTA2_REG PORTA
500 #define PORTA3_REG PORTA
501 #define PORTA4_REG PORTA
502 #define PORTA5_REG PORTA
503 #define PORTA6_REG PORTA
504 #define PORTA7_REG PORTA
507 #define TWIE_REG TWCR
508 #define TWEN_REG TWCR
509 #define TWWC_REG TWCR
510 #define TWSTO_REG TWCR
511 #define TWSTA_REG TWCR
512 #define TWEA_REG TWCR
513 #define TWINT_REG TWCR
516 #define SCDL0_REG BPSCD
517 #define SCDL1_REG BPSCD
518 #define SCDL2_REG BPSCD
519 #define SCDL3_REG BPSCD
522 #define TCNT00_REG TCNT0
523 #define TCNT01_REG TCNT0
524 #define TCNT02_REG TCNT0
525 #define TCNT03_REG TCNT0
526 #define TCNT04_REG TCNT0
527 #define TCNT05_REG TCNT0
528 #define TCNT06_REG TCNT0
529 #define TCNT07_REG TCNT0
532 #define PINA0_REG PINA
533 #define PINA1_REG PINA
534 #define PINA2_REG PINA
535 #define PINA3_REG PINA
536 #define PINA4_REG PINA
537 #define PINA5_REG PINA
538 #define PINA6_REG PINA
539 #define PINA7_REG PINA
542 #define OCR1AH0_REG OCR1AH
543 #define OCR1AH1_REG OCR1AH
544 #define OCR1AH2_REG OCR1AH
545 #define OCR1AH3_REG OCR1AH
546 #define OCR1AH4_REG OCR1AH
547 #define OCR1AH5_REG OCR1AH
548 #define OCR1AH6_REG OCR1AH
549 #define OCR1AH7_REG OCR1AH
552 #define TWGCE_REG TWAR
553 #define TWA0_REG TWAR
554 #define TWA1_REG TWAR
555 #define TWA2_REG TWAR
556 #define TWA3_REG TWAR
557 #define TWA4_REG TWAR
558 #define TWA5_REG TWAR
559 #define TWA6_REG TWAR
562 #define GPIOR00_REG GPIOR0
563 #define GPIOR01_REG GPIOR0
564 #define GPIOR02_REG GPIOR0
565 #define GPIOR03_REG GPIOR0
566 #define GPIOR04_REG GPIOR0
567 #define GPIOR05_REG GPIOR0
568 #define GPIOR06_REG GPIOR0
569 #define GPIOR07_REG GPIOR0
572 #define EEAR0_REG EEARL
573 #define EEAR1_REG EEARL
574 #define EEAR2_REG EEARL
575 #define EEAR3_REG EEARL
576 #define EEAR4_REG EEARL
577 #define EEAR5_REG EEARL
578 #define EEAR6_REG EEARL
579 #define EEAR7_REG EEARL
582 #define TOIE0_REG TIMSK0
583 #define OCIE0A_REG TIMSK0
584 #define OCIE0B_REG TIMSK0
587 #define TOIE1_REG TIMSK1
588 #define OCIE1A_REG TIMSK1
591 #define CS00_REG TCCR0B
592 #define CS01_REG TCCR0B
593 #define CS02_REG TCCR0B
594 #define WGM02_REG TCCR0B
595 #define FOC0B_REG TCCR0B
596 #define FOC0A_REG TCCR0B
599 #define BGCC0_REG BGCCR
600 #define BGCC1_REG BGCCR
601 #define BGCC2_REG BGCCR
602 #define BGCC3_REG BGCCR
603 #define BGCC4_REG BGCCR
604 #define BGCC5_REG BGCCR
605 #define BGD_REG BGCCR
608 #define VADMUX0_REG VADMUX
609 #define VADMUX1_REG VADMUX
610 #define VADMUX2_REG VADMUX
611 #define VADMUX3_REG VADMUX
614 #define TWPS0_REG TWSR
615 #define TWPS1_REG TWSR
616 #define TWS3_REG TWSR
617 #define TWS4_REG TWSR
618 #define TWS5_REG TWSR
619 #define TWS6_REG TWSR
620 #define TWS7_REG TWSR
623 #define VADC8_REG VADCH
624 #define VADC9_REG VADCH
625 #define VADC10_REG VADCH
626 #define VADC11_REG VADCH
629 #define GPIOR20_REG GPIOR2
630 #define GPIOR21_REG GPIOR2
631 #define GPIOR22_REG GPIOR2
632 #define GPIOR23_REG GPIOR2
633 #define GPIOR24_REG GPIOR2
634 #define GPIOR25_REG GPIOR2
635 #define GPIOR26_REG GPIOR2
636 #define GPIOR27_REG GPIOR2
639 #define PCINT0_REG PCMSK0
640 #define PCINT1_REG PCMSK0
641 #define PCINT2_REG PCMSK0
642 #define PCINT3_REG PCMSK0
643 #define PCINT4_REG PCMSK0
644 #define PCINT5_REG PCMSK0
645 #define PCINT6_REG PCMSK0
646 #define PCINT7_REG PCMSK0
649 #define VADC0_REG VADCL
650 #define VADC1_REG VADCL
651 #define VADC2_REG VADCL
652 #define VADC3_REG VADCL
653 #define VADC4_REG VADCL
654 #define VADC5_REG VADCL
655 #define VADC6_REG VADCL
656 #define VADC7_REG VADCL
659 #define ISC00_REG EICRA
660 #define ISC01_REG EICRA
661 #define ISC10_REG EICRA
662 #define ISC11_REG EICRA
663 #define ISC20_REG EICRA
664 #define ISC21_REG EICRA
665 #define ISC30_REG EICRA
666 #define ISC31_REG EICRA
669 #define VADCCIE_REG VADCSR
670 #define VADCCIF_REG VADCSR
671 #define VADSC_REG VADCSR
672 #define VADEN_REG VADCSR
675 #define FCAL0_REG FOSCCAL
676 #define FCAL1_REG FOSCCAL
677 #define FCAL2_REG FOSCCAL
678 #define FCAL3_REG FOSCCAL
679 #define FCAL4_REG FOSCCAL
680 #define FCAL5_REG FOSCCAL
681 #define FCAL6_REG FOSCCAL
682 #define FCAL7_REG FOSCCAL
685 #define VADC0D_REG DIDR0
686 #define VADC1D_REG DIDR0
687 #define VADC2D_REG DIDR0
688 #define VADC3D_REG DIDR0
691 #define WGM00_REG TCCR0A
692 #define WGM01_REG TCCR0A
693 #define COM0B0_REG TCCR0A
694 #define COM0B1_REG TCCR0A
695 #define COM0A0_REG TCCR0A
696 #define COM0A1_REG TCCR0A
699 #define IVCE_REG MCUCR
700 #define IVSEL_REG MCUCR
701 #define PUD_REG MCUCR
702 #define JTD_REG MCUCR
705 #define CBE1_REG CBCR
706 #define CBE2_REG CBCR
707 #define CBE3_REG CBCR
708 #define CBE4_REG CBCR
711 #define TWBCIP_REG TWBCSR
712 #define TWBDT0_REG TWBCSR
713 #define TWBDT1_REG TWBCSR
714 #define TWBCIE_REG TWBCSR
715 #define TWBCIF_REG TWBCSR
718 #define OCR1AL0_REG OCR1AL
719 #define OCR1AL1_REG OCR1AL
720 #define OCR1AL2_REG OCR1AL
721 #define OCR1AL3_REG OCR1AL
722 #define OCR1AL4_REG OCR1AL
723 #define OCR1AL5_REG OCR1AL
724 #define OCR1AL6_REG OCR1AL
725 #define OCR1AL7_REG OCR1AL
728 #define CADRCC0_REG CADRCC
729 #define CADRCC1_REG CADRCC
730 #define CADRCC2_REG CADRCC
731 #define CADRCC3_REG CADRCC
732 #define CADRCC4_REG CADRCC
733 #define CADRCC5_REG CADRCC
734 #define CADRCC6_REG CADRCC
735 #define CADRCC7_REG CADRCC
738 #define PINB0_REG PINB
739 #define PINB1_REG PINB
740 #define PINB2_REG PINB
741 #define PINB3_REG PINB
742 #define PINB4_REG PINB
743 #define PINB5_REG PINB
744 #define PINB6_REG PINB
745 #define PINB7_REG PINB
748 #define INTF0_REG EIFR
749 #define INTF1_REG EIFR
750 #define INTF2_REG EIFR
751 #define INTF3_REG EIFR
754 #define TOV0_REG TIFR0
755 #define OCF0A_REG TIFR0
756 #define OCF0B_REG TIFR0
759 #define TOV1_REG TIFR1
760 #define OCF1A_REG TIFR1
763 #define ADC0_PORT PORTA
765 #define PCINT0_PORT PORTA
768 #define ADC1_PORT PORTA
770 #define PCINT1_PORT PORTA
773 #define ADC2_PORT PORTA
775 #define PCINT2_PORT PORTA
778 #define ADC3_PORT PORTA
780 #define PCINT3_PORT PORTA
783 #define ADC4_PORT PORTA
785 #define INT0_PORT PORTA
787 #define PCINT4_PORT PORTA
790 #define INT1_PORT PORTA
792 #define PCINT5_PORT PORTA
795 #define INT2_PORT PORTA
797 #define PCINT6_PORT PORTA
800 #define INT3_PORT PORTA
802 #define PCINT7_PORT PORTA
805 #define TDO_PORT PORTB
807 #define PCINT8_PORT PORTB
810 #define TDI_PORT PORTB
812 #define PCINT9_PORT PORTB
815 #define TMS_PORT PORTB
817 #define PCINT10_PORT PORTB
818 #define PCINT10_BIT 2
820 #define TCK_PORT PORTB
822 #define PCINT11_PORT PORTB
823 #define PCINT11_BIT 3
825 #define PCINT12_PORT PORTB
826 #define PCINT12_BIT 4
828 #define PCINT13_PORT PORTB
829 #define PCINT13_BIT 5
831 #define OC0A_PORT PORTB
833 #define PCINT14_PORT PORTB
834 #define PCINT14_BIT 6
836 #define OC0B_PORT PORTB
838 #define PCINT15_PORT PORTB
839 #define PCINT15_BIT 7
842 #define T0_PORT PORTD