config/arm/meson.build

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright(c) 2017 Intel Corporation.
   3 # Copyright(c) 2017 Cavium, Inc
   4
   5 arm_force_native_march = false
   6
   7 # common flags to all aarch64 builds, with lowest priority
   8 flags_common = [
   9         # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
  10         # to determine the best threshold in code. Refer to notes in source file
  11         # (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.
  12         ['RTE_ARCH_ARM64_MEMCPY', false],
  13         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
  14         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
  15         # Leave below RTE_ARM64_MEMCPY_xxx options commented out,
  16         # unless there are strong reasons.
  17         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
  18         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
  19         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
  20
  21         ['RTE_NET_FM10K', false],
  22         ['RTE_NET_AVP', false],
  23
  24         ['RTE_SCHED_VECTOR', false],
  25         ['RTE_ARM_USE_WFE', false],
  26         ['RTE_ARCH_ARM64', true],
  27         ['RTE_CACHE_LINE_SIZE', 128]
  28 ]
  29
  30 # implementer specific aarch64 flags, with middle priority
  31 # (will overwrite common flags)
  32 flags_implementer_generic = [
  33         ['RTE_MACHINE', '"armv8a"'],
  34         ['RTE_USE_C11_MEM_MODEL', true],
  35         ['RTE_MAX_LCORE', 256]
  36 ]
  37 flags_implementer_arm = [
  38         ['RTE_MACHINE', '"armv8a"'],
  39         ['RTE_USE_C11_MEM_MODEL', true],
  40         ['RTE_CACHE_LINE_SIZE', 64],
  41         ['RTE_MAX_LCORE', 16]
  42 ]
  43 flags_implementer_cavium = [
  44         ['RTE_MAX_VFIO_GROUPS', 128],
  45         ['RTE_MAX_LCORE', 96],
  46         ['RTE_MAX_NUMA_NODES', 2]
  47 ]
  48 flags_implementer_dpaa = [
  49         ['RTE_MACHINE', '"dpaa"'],
  50         ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
  51         ['RTE_USE_C11_MEM_MODEL', true],
  52         ['RTE_CACHE_LINE_SIZE', 64],
  53         ['RTE_MAX_LCORE', 16],
  54         ['RTE_MAX_NUMA_NODES', 1]
  55 ]
  56 flags_implementer_emag = [
  57         ['RTE_MACHINE', '"emag"'],
  58         ['RTE_CACHE_LINE_SIZE', 64],
  59         ['RTE_MAX_LCORE', 32],
  60         ['RTE_MAX_NUMA_NODES', 1]
  61 ]
  62 flags_implementer_armada = [
  63         ['RTE_MACHINE', '"armv8a"'],
  64         ['RTE_CACHE_LINE_SIZE', 64],
  65         ['RTE_MAX_LCORE', 16],
  66         ['RTE_MAX_NUMA_NODES', 1]
  67 ]
  68
  69 # part number specific aarch64 flags, with highest priority
  70 # (will overwrite both common and implementer specific flags)
  71 flags_part_number_thunderx = [
  72         ['RTE_MACHINE', '"thunderx"'],
  73         ['RTE_USE_C11_MEM_MODEL', false]
  74 ]
  75 flags_part_number_thunderx2 = [
  76         ['RTE_MACHINE', '"thunderx2"'],
  77         ['RTE_ARM_FEATURE_ATOMICS', true],
  78         ['RTE_USE_C11_MEM_MODEL', true],
  79         ['RTE_CACHE_LINE_SIZE', 64],
  80         ['RTE_MAX_LCORE', 256],
  81         ['RTE_MAX_NUMA_NODES', 2]
  82 ]
  83 flags_part_number_octeontx2 = [
  84         ['RTE_MACHINE', '"octeontx2"'],
  85         ['RTE_ARM_FEATURE_ATOMICS', true],
  86         ['RTE_USE_C11_MEM_MODEL', true],
  87         ['RTE_EAL_IGB_UIO', false],
  88         ['RTE_MAX_LCORE', 36],
  89         ['RTE_MAX_NUMA_NODES', 1]
  90 ]
  91 flags_part_number_n1generic = [
  92         ['RTE_MACHINE', '"neoverse-n1"'],
  93         ['RTE_ARM_FEATURE_ATOMICS', true],
  94         ['RTE_USE_C11_MEM_MODEL', true],
  95         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
  96         ['RTE_LIBRTE_VHOST_NUMA', false],
  97         ['RTE_MAX_MEM_MB', 1048576],
  98         ['RTE_CACHE_LINE_SIZE', 64],
  99         ['RTE_MAX_LCORE', 64],
 100         ['RTE_MAX_NUMA_NODES', 1]
 101 ]
 102 flags_part_number_n2generic = [
 103         ['RTE_MACHINE', '"neoverse-n2"'],
 104         ['RTE_ARM_FEATURE_ATOMICS', true],
 105         ['RTE_USE_C11_MEM_MODEL', true],
 106         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
 107         ['RTE_LIBRTE_VHOST_NUMA', false],
 108         ['RTE_MAX_LCORE', 64],
 109         ['RTE_CACHE_LINE_SIZE', 64]
 110 ]
 111
 112 # arm config (implementer 0x41) is the default config
 113 part_number_config_arm = [
 114         ['generic', ['-march=armv8-a+crc', '-moutline-atomics']],
 115         ['native', ['-march=native']],
 116         ['0xd03', ['-mcpu=cortex-a53']],
 117         ['0xd04', ['-mcpu=cortex-a35']],
 118         ['0xd07', ['-mcpu=cortex-a57']],
 119         ['0xd08', ['-mcpu=cortex-a72']],
 120         ['0xd09', ['-mcpu=cortex-a73']],
 121         ['0xd0a', ['-mcpu=cortex-a75']],
 122         ['0xd0b', ['-mcpu=cortex-a76']],
 123         ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic],
 124         ['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_part_number_n2generic]
 125 ]
 126
 127 part_number_config_cavium = [
 128         ['generic', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
 129         ['native', ['-march=native']],
 130         ['0xa1', ['-mcpu=thunderxt88'], flags_part_number_thunderx],
 131         ['0xa2', ['-mcpu=thunderxt81'], flags_part_number_thunderx],
 132         ['0xa3', ['-mcpu=thunderxt83'], flags_part_number_thunderx],
 133         ['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_part_number_thunderx2],
 134         ['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2]
 135 ]
 136 part_number_config_emag = [
 137         ['generic', ['-march=armv8-a+crc+crypto', '-mtune=emag']],
 138         ['native', ['-march=native']]
 139 ]
 140
 141 ## Arm implementer ID (MIDR in Arm Architecture Reference Manual)
 142 implementer_generic = ['Generic armv8', flags_implementer_generic, part_number_config_arm]
 143 implementer_0x41 = ['Arm', flags_implementer_arm, part_number_config_arm]
 144 implementer_0x43 = ['Cavium', flags_implementer_cavium, part_number_config_cavium]
 145 implementer_0x50 = ['Ampere Computing', flags_implementer_emag, part_number_config_emag]
 146 implementer_0x56 = ['Marvell ARMADA', flags_implementer_armada, part_number_config_arm]
 147 implementer_dpaa = ['NXP DPAA', flags_implementer_dpaa, part_number_config_arm]
 148
 149 dpdk_conf.set('RTE_ARCH_ARM', 1)
 150 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
 151
 152 if dpdk_conf.get('RTE_ARCH_32')
 153         # armv7 build
 154         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
 155         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
 156         # the minimum architecture supported, armv7-a, needs the following,
 157         machine_args += '-mfpu=neon'
 158 else
 159         # aarch64 build
 160         implementer_id = 'generic'
 161         if machine == 'default' and not meson.is_cross_build()
 162                 # default build
 163                 implementer_config = implementer_generic
 164                 part_number = 'generic'
 165         elif not meson.is_cross_build()
 166                 # native build
 167                 # The script returns ['Implementer', 'Variant', 'Architecture',
 168                 # 'Primary Part number', 'Revision']
 169                 detect_vendor = find_program(join_paths(
 170                                 meson.current_source_dir(), 'armv8_machine.py'))
 171                 cmd = run_command(detect_vendor.path())
 172                 if cmd.returncode() == 0
 173                         cmd_output = cmd.stdout().to_lower().strip().split(' ')
 174                         implementer_id = cmd_output[0]
 175                         part_number = cmd_output[3]
 176                 endif
 177                 # Set to generic if variable is not found
 178                 implementer_config = get_variable('implementer_' + implementer_id, ['generic'])
 179                 if implementer_config[0] == 'generic'
 180                         implementer_config = implementer_generic
 181                         part_number = 'generic'
 182                 endif
 183                 if arm_force_native_march == true
 184                         part_number = 'native'
 185                 endif
 186         else
 187                 # cross build
 188                 implementer_id = meson.get_cross_property('implementer_id', 'generic')
 189                 part_number = meson.get_cross_property('part_number', 'generic')
 190                 implementer_config = get_variable('implementer_' + implementer_id)
 191         endif
 192
 193         message('Arm implementer: ' + implementer_config[0])
 194         message('Arm part number: ' + part_number)
 195
 196         # use default flags with implementer flags
 197         dpdk_flags = flags_common + implementer_config[1]
 198
 199         machine_args = [] # Clear previous machine args
 200         foreach marg: implementer_config[2]
 201                 if marg[0] == part_number
 202                         # apply supported machine args
 203                         foreach flag: marg[1]
 204                                 if cc.has_argument(flag)
 205                                         machine_args += flag
 206                                 endif
 207                         endforeach
 208                         if marg.length() > 2
 209                                 # add extra flags for the part
 210                                 dpdk_flags += marg[2]
 211                         endif
 212                 endif
 213         endforeach
 214
 215         # apply flags
 216         foreach flag: dpdk_flags
 217                 if flag.length() > 0
 218                         dpdk_conf.set(flag[0], flag[1])
 219                 endif
 220         endforeach
 221 endif
 222 message('Using machine args: @0@'.format(machine_args))
 223
 224 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 225     cc.get_define('__aarch64__', args: machine_args) != '')
 226         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 227 endif
 228
 229 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
 230         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
 231 endif
 232
 233 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
 234         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
 235         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 236 endif