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3 Copyright 2015 Mellanox
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34 The MLX5 poll mode driver library (**librte_pmd_mlx5**) provides support
35 for **Mellanox ConnectX-4**, **Mellanox ConnectX-4 Lx** and **Mellanox
36 ConnectX-5** families of 10/25/40/50/100 Gb/s adapters as well as their
37 virtual functions (VF) in SR-IOV context.
39 Information and documentation about these adapters can be found on the
40 `Mellanox website <http://www.mellanox.com>`__. Help is also provided by the
41 `Mellanox community <http://community.mellanox.com/welcome>`__.
43 There is also a `section dedicated to this poll mode driver
44 <http://www.mellanox.com/page/products_dyn?product_family=209&mtag=pmd_for_dpdk>`__.
48 Due to external dependencies, this driver is disabled by default. It must
49 be enabled manually by setting ``CONFIG_RTE_LIBRTE_MLX5_PMD=y`` and
52 Implementation details
53 ----------------------
55 Besides its dependency on libibverbs (that implies libmlx5 and associated
56 kernel support), librte_pmd_mlx5 relies heavily on system calls for control
57 operations such as querying/updating the MTU and flow control parameters.
59 For security reasons and robustness, this driver only deals with virtual
60 memory addresses. The way resources allocations are handled by the kernel
61 combined with hardware specifications that allow it to handle virtual memory
62 addresses directly ensure that DPDK applications cannot access random
63 physical memory (or memory that does not belong to the current process).
65 This capability allows the PMD to coexist with kernel network interfaces
66 which remain functional, although they stop receiving unicast packets as
67 long as they share the same MAC address.
68 This means legacy linux control tools (for example: ethtool, ifconfig and
69 more) can operate on the same network interfaces that owned by the DPDK
72 Enabling librte_pmd_mlx5 causes DPDK applications to be linked against
78 - Multi arch support: x86_64, POWER8, ARMv8.
79 - Multiple TX and RX queues.
80 - Support for scattered TX and RX frames.
81 - IPv4, IPv6, TCPv4, TCPv6, UDPv4 and UDPv6 RSS on any number of queues.
82 - Several RSS hash keys, one for each flow type.
83 - Configurable RETA table.
84 - Support for multiple MAC addresses.
88 - RX CRC stripping configuration.
90 - Multicast promiscuous mode.
91 - Hardware checksum offloads.
92 - Flow director (RTE_FDIR_MODE_PERFECT, RTE_FDIR_MODE_PERFECT_MAC_VLAN and
96 - KVM and VMware ESX SR-IOV modes are supported.
97 - RSS hash result is supported.
99 - Hardware checksum TX offload for VXLAN and GRE.
101 - Statistics query including Basic, Extended and per queue.
107 - Inner RSS for VXLAN frames is not supported yet.
108 - Hardware checksum RX offloads for VXLAN inner header are not supported yet.
109 - Forked secondary process not supported.
110 - Flow pattern without any specific vlan will match for vlan packets as well:
112 When VLAN spec is not specified in the pattern, the matching rule will be created with VLAN as a wild card.
113 Meaning, the flow rule::
115 flow create 0 ingress pattern eth / vlan vid is 3 / ipv4 / end ...
117 Will only match vlan packets with vid=3. and the flow rules::
119 flow create 0 ingress pattern eth / ipv4 / end ...
123 flow create 0 ingress pattern eth / vlan / ipv4 / end ...
125 Will match any ipv4 packet (VLAN included).
127 - A multi segment packet must have less than 6 segments in case the Tx burst function
128 is set to multi-packet send or Enhanced multi-packet send. Otherwise it must have
129 less than 50 segments.
130 - Count action for RTE flow is only supported in Mellanox OFED 4.2.
131 - Flows with a VXLAN Network Identifier equal (or ends to be equal)
132 to 0 are not supported.
133 - VXLAN TSO and checksum offloads are not supported on VM.
138 MLX5 supports various of methods to report statistics:
140 Port statistics can be queried using ``rte_eth_stats_get()``. The port statistics are through SW only and counts the number of packets received or sent successfully by the PMD.
142 Extended statistics can be queried using ``rte_eth_xstats_get()``. The extended statistics expose a wider set of counters counted by the device. The extended port statistics counts the number of packets received or sent successfully by the port. As Mellanox NICs are using the :ref:`Bifurcated Linux Driver <linux_gsg_linux_drivers>` those counters counts also packet received or sent by the Linux kernel. The counters with ``_phy`` suffix counts the total events on the physical port, therefore not valid for VF.
144 Finally per-flow statistics can by queried using ``rte_flow_query`` when attaching a count action for specific flow. The flow counter counts the number of packets received successfully by the port and match the specific flow.
152 These options can be modified in the ``.config`` file.
154 - ``CONFIG_RTE_LIBRTE_MLX5_PMD`` (default **n**)
156 Toggle compilation of librte_pmd_mlx5 itself.
158 - ``CONFIG_RTE_LIBRTE_MLX5_DEBUG`` (default **n**)
160 Toggle debugging code and stricter compilation flags. Enabling this option
161 adds additional run-time checks and debugging messages at the cost of
164 - ``CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE`` (default **8**)
166 Maximum number of cached memory pools (MPs) per TX queue. Each MP from
167 which buffers are to be transmitted must be associated to memory regions
168 (MRs). This is a slow operation that must be cached.
170 This value is always 1 for RX queues since they use a single MP.
172 Environment variables
173 ~~~~~~~~~~~~~~~~~~~~~
175 - ``MLX5_PMD_ENABLE_PADDING``
177 Enables HW packet padding in PCI bus transactions.
179 When packet size is cache aligned and CRC stripping is enabled, 4 fewer
180 bytes are written to the PCI bus. Enabling padding makes such packets
183 In cases where PCI bandwidth is the bottleneck, padding can improve
186 This is disabled by default since this can also decrease performance for
187 unaligned packet sizes.
189 - ``MLX5_SHUT_UP_BF``
191 Configures HW Tx doorbell register as IO-mapped.
193 By default, the HW Tx doorbell is configured as a write-combining register.
194 The register would be flushed to HW usually when the write-combining buffer
195 becomes full, but it depends on CPU design.
197 Except for vectorized Tx burst routines, a write memory barrier is enforced
198 after updating the register so that the update can be immediately visible to
201 When vectorized Tx burst is called, the barrier is set only if the burst size
202 is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental
203 variable will bring better latency even though the maximum throughput can
206 Run-time configuration
207 ~~~~~~~~~~~~~~~~~~~~~~
209 - librte_pmd_mlx5 brings kernel network interfaces up during initialization
210 because it is affected by their state. Forcing them down prevents packets
213 - **ethtool** operations on related kernel interfaces also affect the PMD.
215 - ``rxq_cqe_comp_en`` parameter [int]
217 A nonzero value enables the compression of CQE on RX side. This feature
218 allows to save PCI bandwidth and improve performance. Enabled by default.
222 - x86_64 with ConnectX-4, ConnectX-4 LX and ConnectX-5.
223 - POWER8 and ARMv8 with ConnectX-4 LX and ConnectX-5.
225 - ``txq_inline`` parameter [int]
227 Amount of data to be inlined during TX operations. Improves latency.
228 Can improve PPS performance when PCI back pressure is detected and may be
229 useful for scenarios involving heavy traffic on many queues.
231 Because additional software logic is necessary to handle this mode, this
232 option should be used with care, as it can lower performance when back
233 pressure is not expected.
235 - ``txqs_min_inline`` parameter [int]
237 Enable inline send only when the number of TX queues is greater or equal
240 This option should be used in combination with ``txq_inline`` above.
242 On ConnectX-4, ConnectX-4 LX and ConnectX-5 without Enhanced MPW:
244 - Disabled by default.
245 - In case ``txq_inline`` is set recommendation is 4.
247 On ConnectX-5 with Enhanced MPW:
249 - Set to 8 by default.
251 - ``txq_mpw_en`` parameter [int]
253 A nonzero value enables multi-packet send (MPS) for ConnectX-4 Lx and
254 enhanced multi-packet send (Enhanced MPS) for ConnectX-5. MPS allows the
255 TX burst function to pack up multiple packets in a single descriptor
256 session in order to save PCI bandwidth and improve performance at the
257 cost of a slightly higher CPU usage. When ``txq_inline`` is set along
258 with ``txq_mpw_en``, TX burst function tries to copy entire packet data
259 on to TX descriptor instead of including pointer of packet only if there
260 is enough room remained in the descriptor. ``txq_inline`` sets
261 per-descriptor space for either pointers or inlined packets. In addition,
262 Enhanced MPS supports hybrid mode - mixing inlined packets and pointers
263 in the same descriptor.
265 This option cannot be used with certain offloads such as ``DEV_TX_OFFLOAD_TCP_TSO,
266 DEV_TX_OFFLOAD_VXLAN_TNL_TSO, DEV_TX_OFFLOAD_GRE_TNL_TSO, DEV_TX_OFFLOAD_VLAN_INSERT``.
267 When those offloads are requested the MPS send function will not be used.
269 It is currently only supported on the ConnectX-4 Lx and ConnectX-5
270 families of adapters. Enabled by default.
272 - ``txq_mpw_hdr_dseg_en`` parameter [int]
274 A nonzero value enables including two pointers in the first block of TX
275 descriptor. This can be used to lessen CPU load for memory copy.
277 Effective only when Enhanced MPS is supported. Disabled by default.
279 - ``txq_max_inline_len`` parameter [int]
281 Maximum size of packet to be inlined. This limits the size of packet to
282 be inlined. If the size of a packet is larger than configured value, the
283 packet isn't inlined even though there's enough space remained in the
284 descriptor. Instead, the packet is included with pointer.
286 Effective only when Enhanced MPS is supported. The default value is 256.
288 - ``tx_vec_en`` parameter [int]
290 A nonzero value enables Tx vector on ConnectX-5 only NIC if the number of
291 global Tx queues on the port is lesser than MLX5_VPMD_MIN_TXQS.
293 This option cannot be used with certain offloads such as ``DEV_TX_OFFLOAD_TCP_TSO,
294 DEV_TX_OFFLOAD_VXLAN_TNL_TSO, DEV_TX_OFFLOAD_GRE_TNL_TSO, DEV_TX_OFFLOAD_VLAN_INSERT``.
295 When those offloads are requested the MPS send function will not be used.
297 Enabled by default on ConnectX-5.
299 - ``rx_vec_en`` parameter [int]
301 A nonzero value enables Rx vector if the port is not configured in
302 multi-segment otherwise this parameter is ignored.
309 This driver relies on external libraries and kernel drivers for resources
310 allocations and initialization. The following dependencies are not part of
311 DPDK and must be installed separately:
315 User space Verbs framework used by librte_pmd_mlx5. This library provides
316 a generic interface between the kernel and low-level user space drivers
319 It allows slow and privileged operations (context initialization, hardware
320 resources allocations) to be managed by the kernel and fast operations to
321 never leave user space.
325 Low-level user space driver library for Mellanox ConnectX-4/ConnectX-5
326 devices, it is automatically loaded by libibverbs.
328 This library basically implements send/receive calls to the hardware
333 They provide the kernel-side Verbs API and low level device drivers that
334 manage actual hardware initialization and resources sharing with user
337 Unlike most other PMDs, these modules must remain loaded and bound to
340 - mlx5_core: hardware driver managing Mellanox ConnectX-4/ConnectX-5
341 devices and related Ethernet kernel network devices.
342 - mlx5_ib: InifiniBand device driver.
343 - ib_uverbs: user space driver for Verbs (entry point for libibverbs).
345 - **Firmware update**
347 Mellanox OFED releases include firmware updates for ConnectX-4/ConnectX-5
350 Because each release provides new features, these updates must be applied to
351 match the kernel modules and libraries they come with.
355 Both libraries are BSD and GPL licensed. Linux kernel modules are GPL
361 Either RDMA Core library with a recent enough Linux kernel release
362 (recommended) or Mellanox OFED, which provides compatibility with older
365 RMDA Core with Linux Kernel
366 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
368 - Minimal kernel version : v4.14 or the most recent 4.14-rc (see `Linux installation documentation`_)
369 - Minimal rdma-core version: v15+ commit 0c5f5765213a ("Merge pull request #227 from yishaih/tm")
370 (see `RDMA Core installation documentation`_)
372 .. _`Linux installation documentation`: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/plain/Documentation/admin-guide/README.rst
373 .. _`RDMA Core installation documentation`: https://raw.githubusercontent.com/linux-rdma/rdma-core/master/README.md
378 - Mellanox OFED version: **4.2**.
381 - ConnectX-4: **12.21.1000** and above.
382 - ConnectX-4 Lx: **14.21.1000** and above.
383 - ConnectX-5: **16.21.1000** and above.
384 - ConnectX-5 Ex: **16.21.1000** and above.
386 While these libraries and kernel modules are available on OpenFabrics
387 Alliance's `website <https://www.openfabrics.org/>`__ and provided by package
388 managers on most distributions, this PMD requires Ethernet extensions that
389 may not be supported at the moment (this is a work in progress).
392 <http://www.mellanox.com/page/products_dyn?product_family=26&mtag=linux>`__
393 includes the necessary support and should be used in the meantime. For DPDK,
394 only libibverbs, libmlx5, mlnx-ofed-kernel packages and firmware updates are
395 required from that distribution.
399 Several versions of Mellanox OFED are available. Installing the version
400 this DPDK release was developed and tested against is strongly
401 recommended. Please check the `prerequisites`_.
406 * Mellanox(R) ConnectX(R)-4 10G MCX4111A-XCAT (1x10G)
407 * Mellanox(R) ConnectX(R)-4 10G MCX4121A-XCAT (2x10G)
408 * Mellanox(R) ConnectX(R)-4 25G MCX4111A-ACAT (1x25G)
409 * Mellanox(R) ConnectX(R)-4 25G MCX4121A-ACAT (2x25G)
410 * Mellanox(R) ConnectX(R)-4 40G MCX4131A-BCAT (1x40G)
411 * Mellanox(R) ConnectX(R)-4 40G MCX413A-BCAT (1x40G)
412 * Mellanox(R) ConnectX(R)-4 40G MCX415A-BCAT (1x40G)
413 * Mellanox(R) ConnectX(R)-4 50G MCX4131A-GCAT (1x50G)
414 * Mellanox(R) ConnectX(R)-4 50G MCX413A-GCAT (1x50G)
415 * Mellanox(R) ConnectX(R)-4 50G MCX414A-BCAT (2x50G)
416 * Mellanox(R) ConnectX(R)-4 50G MCX415A-GCAT (2x50G)
417 * Mellanox(R) ConnectX(R)-4 50G MCX416A-BCAT (2x50G)
418 * Mellanox(R) ConnectX(R)-4 50G MCX416A-GCAT (2x50G)
419 * Mellanox(R) ConnectX(R)-4 50G MCX415A-CCAT (1x100G)
420 * Mellanox(R) ConnectX(R)-4 100G MCX416A-CCAT (2x100G)
421 * Mellanox(R) ConnectX(R)-4 Lx 10G MCX4121A-XCAT (2x10G)
422 * Mellanox(R) ConnectX(R)-4 Lx 25G MCX4121A-ACAT (2x25G)
423 * Mellanox(R) ConnectX(R)-5 100G MCX556A-ECAT (2x100G)
424 * Mellanox(R) ConnectX(R)-5 Ex EN 100G MCX516A-CDAT (2x100G)
426 Quick Start Guide on OFED
427 -------------------------
429 1. Download latest Mellanox OFED. For more info check the `prerequisites`_.
432 2. Install the required libraries and kernel modules either by installing
433 only the required set, or by installing the entire Mellanox OFED:
435 .. code-block:: console
437 ./mlnxofedinstall --upstream-libs --dpdk
439 3. Verify the firmware is the correct one:
441 .. code-block:: console
445 4. Verify all ports links are set to Ethernet:
447 .. code-block:: console
449 mlxconfig -d <mst device> query | grep LINK_TYPE
453 Link types may have to be configured to Ethernet:
455 .. code-block:: console
457 mlxconfig -d <mst device> set LINK_TYPE_P1/2=1/2/3
459 * LINK_TYPE_P1=<1|2|3> , 1=Infiniband 2=Ethernet 3=VPI(auto-sense)
461 For hypervisors verify SR-IOV is enabled on the NIC:
463 .. code-block:: console
465 mlxconfig -d <mst device> query | grep SRIOV_EN
468 If needed, set enable the set the relevant fields:
470 .. code-block:: console
472 mlxconfig -d <mst device> set SRIOV_EN=1 NUM_OF_VFS=16
473 mlxfwreset -d <mst device> reset
475 5. Restart the driver:
477 .. code-block:: console
479 /etc/init.d/openibd restart
483 .. code-block:: console
485 service openibd restart
487 If link type was changed, firmware must be reset as well:
489 .. code-block:: console
491 mlxfwreset -d <mst device> reset
493 For hypervisors, after reset write the sysfs number of virtual functions
496 To dynamically instantiate a given number of virtual functions (VFs):
498 .. code-block:: console
500 echo [num_vfs] > /sys/class/infiniband/mlx5_0/device/sriov_numvfs
502 6. Compile DPDK and you are ready to go. See instructions on
503 :ref:`Development Kit Build System <Development_Kit_Build_System>`
508 1. Configure aggressive CQE Zipping for maximum performance:
510 .. code-block:: console
512 mlxconfig -d <mst device> s CQE_COMPRESSION=1
514 To set it back to the default CQE Zipping mode use:
516 .. code-block:: console
518 mlxconfig -d <mst device> s CQE_COMPRESSION=0
520 2. In case of virtualization:
522 - Make sure that hypervisor kernel is 3.16 or newer.
523 - Configure boot with ``iommu=pt``.
525 - Make sure to allocate a VM on huge pages.
526 - Make sure to set CPU pinning.
528 3. Use the CPU near local NUMA node to which the PCIe adapter is connected,
529 for better performance. For VMs, verify that the right CPU
530 and NUMA node are pinned according to the above. Run:
532 .. code-block:: console
536 to identify the NUMA node to which the PCIe adapter is connected.
538 4. If more than one adapter is used, and root complex capabilities allow
539 to put both adapters on the same NUMA node without PCI bandwidth degradation,
540 it is recommended to locate both adapters on the same NUMA node.
541 This in order to forward packets from one to the other without
542 NUMA performance penalty.
544 5. Disable pause frames:
546 .. code-block:: console
548 ethtool -A <netdev> rx off tx off
550 6. Verify IO non-posted prefetch is disabled by default. This can be checked
551 via the BIOS configuration. Please contact you server provider for more
552 information about the settings.
556 On some machines, depends on the machine integrator, it is beneficial
557 to set the PCI max read request parameter to 1K. This can be
558 done in the following way:
560 To query the read request size use:
562 .. code-block:: console
564 setpci -s <NIC PCI address> 68.w
566 If the output is different than 3XXX, set it by:
568 .. code-block:: console
570 setpci -s <NIC PCI address> 68.w=3XXX
572 The XXX can be different on different systems. Make sure to configure
573 according to the setpci output.
578 Compared to librte_pmd_mlx4 that implements a single RSS configuration per
579 port, librte_pmd_mlx5 supports per-protocol RSS configuration.
581 Since ``testpmd`` defaults to IP RSS mode and there is currently no
582 command-line parameter to enable additional protocols (UDP and TCP as well
583 as IP), the following commands must be entered from its CLI to get the same
584 behavior as librte_pmd_mlx4:
586 .. code-block:: console
589 > port config all rss all
595 This section demonstrates how to launch **testpmd** with Mellanox
596 ConnectX-4/ConnectX-5 devices managed by librte_pmd_mlx5.
598 #. Load the kernel modules:
600 .. code-block:: console
602 modprobe -a ib_uverbs mlx5_core mlx5_ib
604 Alternatively if MLNX_OFED is fully installed, the following script can
607 .. code-block:: console
609 /etc/init.d/openibd restart
613 User space I/O kernel modules (uio and igb_uio) are not used and do
614 not have to be loaded.
616 #. Make sure Ethernet interfaces are in working order and linked to kernel
617 verbs. Related sysfs entries should be present:
619 .. code-block:: console
621 ls -d /sys/class/net/*/device/infiniband_verbs/uverbs* | cut -d / -f 5
625 .. code-block:: console
632 #. Optionally, retrieve their PCI bus addresses for whitelisting:
634 .. code-block:: console
637 for intf in eth2 eth3 eth4 eth5;
639 (cd "/sys/class/net/${intf}/device/" && pwd -P);
642 sed -n 's,.*/\(.*\),-w \1,p'
646 .. code-block:: console
653 #. Request huge pages:
655 .. code-block:: console
657 echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages/nr_hugepages
659 #. Start testpmd with basic parameters:
661 .. code-block:: console
663 testpmd -l 8-15 -n 4 -w 05:00.0 -w 05:00.1 -w 06:00.0 -w 06:00.1 -- --rxq=2 --txq=2 -i
667 .. code-block:: console
670 EAL: PCI device 0000:05:00.0 on NUMA socket 0
671 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
672 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_0" (VF: false)
673 PMD: librte_pmd_mlx5: 1 port(s) detected
674 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fe
675 EAL: PCI device 0000:05:00.1 on NUMA socket 0
676 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
677 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_1" (VF: false)
678 PMD: librte_pmd_mlx5: 1 port(s) detected
679 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:ff
680 EAL: PCI device 0000:06:00.0 on NUMA socket 0
681 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
682 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_2" (VF: false)
683 PMD: librte_pmd_mlx5: 1 port(s) detected
684 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fa
685 EAL: PCI device 0000:06:00.1 on NUMA socket 0
686 EAL: probe driver: 15b3:1013 librte_pmd_mlx5
687 PMD: librte_pmd_mlx5: PCI information matches, using device "mlx5_3" (VF: false)
688 PMD: librte_pmd_mlx5: 1 port(s) detected
689 PMD: librte_pmd_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fb
690 Interactive-mode selected
691 Configuring Port 0 (socket 0)
692 PMD: librte_pmd_mlx5: 0x8cba80: TX queues number update: 0 -> 2
693 PMD: librte_pmd_mlx5: 0x8cba80: RX queues number update: 0 -> 2
694 Port 0: E4:1D:2D:E7:0C:FE
695 Configuring Port 1 (socket 0)
696 PMD: librte_pmd_mlx5: 0x8ccac8: TX queues number update: 0 -> 2
697 PMD: librte_pmd_mlx5: 0x8ccac8: RX queues number update: 0 -> 2
698 Port 1: E4:1D:2D:E7:0C:FF
699 Configuring Port 2 (socket 0)
700 PMD: librte_pmd_mlx5: 0x8cdb10: TX queues number update: 0 -> 2
701 PMD: librte_pmd_mlx5: 0x8cdb10: RX queues number update: 0 -> 2
702 Port 2: E4:1D:2D:E7:0C:FA
703 Configuring Port 3 (socket 0)
704 PMD: librte_pmd_mlx5: 0x8ceb58: TX queues number update: 0 -> 2
705 PMD: librte_pmd_mlx5: 0x8ceb58: RX queues number update: 0 -> 2
706 Port 3: E4:1D:2D:E7:0C:FB
707 Checking link statuses...
708 Port 0 Link Up - speed 40000 Mbps - full-duplex
709 Port 1 Link Up - speed 40000 Mbps - full-duplex
710 Port 2 Link Up - speed 10000 Mbps - full-duplex
711 Port 3 Link Up - speed 10000 Mbps - full-duplex