2 Copyright(c) 2017 Marvell International Ltd.
3 Copyright(c) 2017 Semihalf.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions
10 * Redistributions of source code must retain the above copyright
11 notice, this list of conditions and the following disclaimer.
12 * Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in
14 the documentation and/or other materials provided with the
16 * Neither the name of the copyright holder nor the names of its
17 contributors may be used to endorse or promote products derived
18 from this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 .. _mrvl_poll_mode_driver:
35 ======================
37 The MRVL PMD (librte_pmd_mrvl) provides poll mode driver support
38 for the Marvell PPv2 (Packet Processor v2) 1/10 Gbps adapter.
40 Detailed information about SoCs that use PPv2 can be obtained here:
42 * https://www.marvell.com/embedded-processors/armada-70xx/
43 * https://www.marvell.com/embedded-processors/armada-80xx/
47 Due to external dependencies, this driver is disabled by default. It must
48 be enabled manually by setting relevant configuration option manually.
49 Please refer to `Config File Options`_ section for further details.
55 Features of the MRVL PMD are:
65 - Multicast MAC filter
79 - Number of lcores is limited to 9 by MUSDK internal design. If more lcores
80 need to be allocated, locking will have to be considered. Number of available
81 lcores can be changed via ``MRVL_MUSDK_HIFS_RESERVED`` define in
82 ``mrvl_ethdev.c`` source file.
84 - Flushing vlans added for filtering is not possible due to MUSDK missing
85 functionality. Current workaround is to reset board so that PPv2 has a
86 chance to start in a sane state.
92 - Custom Linux Kernel sources
94 .. code-block:: console
96 git clone https://github.com/MarvellEmbeddedProcessors/linux-marvell.git -b linux-4.4.52-armada-17.10
98 - Out of tree `mvpp2x_sysfs` kernel module sources
100 .. code-block:: console
102 git clone https://github.com/MarvellEmbeddedProcessors/mvpp2x-marvell.git -b mvpp2x-armada-17.10
104 - MUSDK (Marvell User-Space SDK) sources
106 .. code-block:: console
108 git clone https://github.com/MarvellEmbeddedProcessors/musdk-marvell.git -b musdk-armada-17.10
110 MUSDK is a light-weight library that provides direct access to Marvell's
111 PPv2 (Packet Processor v2). Alternatively prebuilt MUSDK library can be
112 requested from `Marvell Extranet <https://extranet.marvell.com>`_. Once
113 approval has been granted, library can be found by typing ``musdk`` in
116 To get better understanding of the library one can consult documentation
117 available in the ``doc`` top level directory of the MUSDK sources.
119 MUSDK must be configured with the following features:
121 .. code-block:: console
123 --enable-bpool-dma=64
127 Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup
134 The following options can be modified in the ``config`` file.
136 - ``CONFIG_RTE_LIBRTE_MRVL_PMD`` (default ``n``)
138 Toggle compilation of the librte_pmd_mrvl driver.
144 QoS configuration is done through external configuration file. Path to the
145 file must be given as `cfg` in driver's vdev parameter list.
150 .. code-block:: console
152 [port <portnum> default]
153 default_tc = <default_tc>
154 mapping_priority = <mapping_priority>
155 policer_enable = <policer_enable>
156 token_unit = <token_unit>
162 rate_limit_enable = <rate_limit_enable>
163 rate_limit = <rate_limit>
164 burst_size = <burst_size>
166 [port <portnum> tc <traffic_class>]
167 rxq = <rx_queue_list>
170 default_color = <default_color>
172 [port <portnum> tc <traffic_class>]
173 rxq = <rx_queue_list>
177 [port <portnum> txq <txqnum>]
178 sched_mode = <sched_mode>
179 wrr_weight = <wrr_weight>
181 rate_limit_enable = <rate_limit_enable>
182 rate_limit = <rate_limit>
183 burst_size = <burst_size>
187 - ``<portnum>``: DPDK Port number (0..n).
189 - ``<default_tc>``: Default traffic class (e.g. 0)
191 - ``<mapping_priority>``: QoS priority for mapping (`ip`, `vlan`, `ip/vlan` or `vlan/ip`).
193 - ``<traffic_class>``: Traffic Class to be configured.
195 - ``<rx_queue_list>``: List of DPDK RX queues (e.g. 0 1 3-4)
197 - ``<pcp_list>``: List of PCP values to handle in particular TC (e.g. 0 1 3-4 7).
199 - ``<dscp_list>``: List of DSCP values to handle in particular TC (e.g. 0-12 32-48 63).
201 - ``<policer_enable>``: Enable ingress policer.
203 - ``<token_unit>``: Policer token unit (`bytes` or `packets`).
205 - ``<color_mode>``: Policer color mode (`aware` or `blind`).
207 - ``<cir>``: Committed information rate in unit of kilo bits per second (data rate) or packets per second.
209 - ``<cbs>``: Committed burst size in unit of kilo bytes or number of packets.
211 - ``<ebs>``: Excess burst size in unit of kilo bytes or number of packets.
213 - ``<default_color>``: Default color for specific tc.
215 - ``<rate_limit_enable>``: Enables per port or per txq rate limiting.
217 - ``<rate_limit>``: Committed information rate, in kilo bits per second.
219 - ``<burst_size>``: Committed burst size, in kilo bytes.
221 - ``<sched_mode>``: Egress scheduler mode (`wrr` or `sp`).
223 - ``<wrr_weight>``: Txq weight.
225 Setting PCP/DSCP values for the default TC is not required. All PCP/DSCP
226 values not assigned explicitly to particular TC will be handled by the
229 Configuration file example
230 ^^^^^^^^^^^^^^^^^^^^^^^^^^
232 .. code-block:: console
236 mapping_priority = ip
238 rate_limit_enable = 1
263 mapping_priority = vlan/ip
285 rate_limit_enable = 1
292 .. code-block:: console
294 ./testpmd --vdev=eth_mrvl,iface=eth0,iface=eth2,cfg=/home/user/mrvl.conf \
295 -c 7 -- -i -a --disable-hw-vlan-strip --rxq=3 --txq=3
301 Driver needs precompiled MUSDK library during compilation.
303 .. code-block:: console
305 export CROSS_COMPILE=<toolchain>/bin/aarch64-linux-gnu-
307 ./configure --host=aarch64-linux-gnu --enable-bpool-dma=64
310 MUSDK will be installed to `usr/local` under current directory.
311 For the detailed build instructions please consult ``doc/musdk_get_started.txt``.
313 Before the DPDK build process the environmental variable ``LIBMUSDK_PATH`` with
314 the path to the MUSDK installation directory needs to be exported.
316 .. code-block:: console
318 export LIBMUSDK_PATH=<musdk>/usr/local
319 export CROSS=aarch64-linux-gnu-
320 make config T=arm64-armv8a-linuxapp-gcc
321 sed -ri 's,(MRVL_PMD=)n,\1y,' build/.config
327 PPv2 offers packet classification capabilities via classifier engine which
328 can be configured via generic flow API offered by DPDK.
330 Supported flow actions
331 ~~~~~~~~~~~~~~~~~~~~~~
333 Following flow action items are supported by the driver:
341 Following flow items and their respective fields are supported by the driver:
359 * destination address
366 * destination address
378 Classifier match engine
379 ~~~~~~~~~~~~~~~~~~~~~~~
381 Classifier has an internal match engine which can be configured to
382 operate in either exact or maskable mode.
384 Mode is selected upon creation of the first unique flow rule as follows:
386 * maskable, if key size is up to 8 bytes.
387 * exact, otherwise, i.e for keys bigger than 8 bytes.
389 Where the key size equals the number of bytes of all fields specified
392 .. table:: Examples of key size calculation
394 +----------------------------------------------------------------------------+-------------------+-------------+
395 | Flow pattern | Key size in bytes | Used engine |
396 +============================================================================+===================+=============+
397 | ETH (destination MAC) / VLAN (VID) | 6 + 2 = 8 | Maskable |
398 +----------------------------------------------------------------------------+-------------------+-------------+
399 | VLAN (VID) / IPV4 (source address) | 2 + 4 = 6 | Maskable |
400 +----------------------------------------------------------------------------+-------------------+-------------+
401 | TCP (source port, destination port) | 2 + 2 = 4 | Maskable |
402 +----------------------------------------------------------------------------+-------------------+-------------+
403 | VLAN (priority) / IPV4 (source address) | 1 + 4 = 5 | Maskable |
404 +----------------------------------------------------------------------------+-------------------+-------------+
405 | IPV4 (destination address) / UDP (source port, destination port) | 6 + 2 + 2 = 10 | Exact |
406 +----------------------------------------------------------------------------+-------------------+-------------+
407 | VLAN (VID) / IPV6 (flow label, destination address) | 2 + 3 + 16 = 21 | Exact |
408 +----------------------------------------------------------------------------+-------------------+-------------+
409 | IPV4 (DSCP, source address, destination address) | 1 + 4 + 4 = 9 | Exact |
410 +----------------------------------------------------------------------------+-------------------+-------------+
411 | IPV6 (flow label, source address, destination address) | 3 + 16 + 16 = 35 | Exact |
412 +----------------------------------------------------------------------------+-------------------+-------------+
414 From the user perspective maskable mode means that masks specified
415 via flow rules are respected. In case of exact match mode, masks
416 which do not provide exact matching (all bits masked) are ignored.
418 If the flow matches more than one classifier rule the first
419 (with the lowest index) matched takes precedence.
421 Flow rules usage example
422 ~~~~~~~~~~~~~~~~~~~~~~~~
424 Before proceeding run testpmd user application:
426 .. code-block:: console
428 ./testpmd --vdev=net_mrvl,iface=eth0,iface=eth2 -c 3 -- -i --p 3 -a --disable-hw-vlan-strip
433 .. code-block:: console
435 testpmd> flow create 0 ingress pattern eth src is 10:11:12:13:14:15 / end actions drop / end
437 In this case key size is 6 bytes thus maskable type is selected. Testpmd
438 will set mask to ff:ff:ff:ff:ff:ff i.e traffic explicitly matching
439 above rule will be dropped.
444 .. code-block:: console
446 testpmd> flow create 0 ingress pattern ipv4 src spec 10.10.10.0 src mask 255.255.255.0 / tcp src spec 0x10 src mask 0x10 / end action drop / end
448 In this case key size is 8 bytes thus maskable type is selected.
449 Flows which have IPv4 source addresses ranging from 10.10.10.0 to 10.10.10.255
450 and tcp source port set to 16 will be dropped.
455 .. code-block:: console
457 testpmd> flow create 0 ingress pattern vlan vid spec 0x10 vid mask 0x10 / ipv4 src spec 10.10.1.1 src mask 255.255.0.0 dst spec 11.11.11.1 dst mask 255.255.255.0 / end actions drop / end
459 In this case key size is 10 bytes thus exact type is selected.
460 Even though each item has partial mask set, masks will be ignored.
461 As a result only flows with VID set to 16 and IPv4 source and destination
462 addresses set to 10.10.1.1 and 11.11.11.1 respectively will be dropped.
467 Following limitations need to be taken into account while creating flow rules:
469 * For IPv4 exact match type the key size must be up to 12 bytes.
470 * For IPv6 exact match type the key size must be up to 36 bytes.
471 * Following fields cannot be partially masked (all masks are treated as
478 * TCP/UDP: source port, destination port
480 * Only one classifier table can be created thus all rules in the table
481 have to match table format. Table format is set during creation of
482 the first unique flow rule.
483 * Up to 5 fields can be specified per flow rule.
484 * Up to 20 flow rules can be added.
486 For additional information about classifier please consult
487 ``doc/musdk_cls_user_guide.txt``.
492 MRVL PMD requires extra out of tree kernel modules to function properly.
493 `musdk_uio` and `mv_pp_uio` sources are part of the MUSDK. Please consult
494 ``doc/musdk_get_started.txt`` for the detailed build instructions.
495 For `mvpp2x_sysfs` please consult ``Documentation/pp22_sysfs.txt`` for the
496 detailed build instructions.
498 .. code-block:: console
502 insmod mvpp2x_sysfs.ko
504 Additionally interfaces used by DPDK application need to be put up:
506 .. code-block:: console
511 In order to run testpmd example application following command can be used:
513 .. code-block:: console
515 ./testpmd --vdev=eth_mrvl,iface=eth0,iface=eth2 -c 7 -- \
516 --burst=128 --txd=2048 --rxd=1024 --rxq=2 --txq=2 --nb-cores=2 \