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39 #ifndef _FSL_DPCI_CMD_H
40 #define _FSL_DPCI_CMD_H
43 #define DPCI_VER_MAJOR 3
44 #define DPCI_VER_MINOR 3
47 #define DPCI_CMDID_CLOSE 0x8001
48 #define DPCI_CMDID_OPEN 0x8071
49 #define DPCI_CMDID_CREATE 0x9072
50 #define DPCI_CMDID_DESTROY 0x9871
51 #define DPCI_CMDID_GET_API_VERSION 0xa071
53 #define DPCI_CMDID_ENABLE 0x0021
54 #define DPCI_CMDID_DISABLE 0x0031
55 #define DPCI_CMDID_GET_ATTR 0x0041
56 #define DPCI_CMDID_RESET 0x0051
57 #define DPCI_CMDID_IS_ENABLED 0x0061
59 #define DPCI_CMDID_SET_IRQ_ENABLE 0x0121
60 #define DPCI_CMDID_GET_IRQ_ENABLE 0x0131
61 #define DPCI_CMDID_SET_IRQ_MASK 0x0141
62 #define DPCI_CMDID_GET_IRQ_MASK 0x0151
63 #define DPCI_CMDID_GET_IRQ_STATUS 0x0161
64 #define DPCI_CMDID_CLEAR_IRQ_STATUS 0x0171
66 #define DPCI_CMDID_SET_RX_QUEUE 0x0e01
67 #define DPCI_CMDID_GET_LINK_STATE 0x0e11
68 #define DPCI_CMDID_GET_PEER_ATTR 0x0e21
69 #define DPCI_CMDID_GET_RX_QUEUE 0x0e31
70 #define DPCI_CMDID_GET_TX_QUEUE 0x0e41
71 #define DPCI_CMDID_SET_OPR 0x0e51
72 #define DPCI_CMDID_GET_OPR 0x0e61
74 /* cmd, param, offset, width, type, arg_name */
75 #define DPCI_CMD_OPEN(cmd, dpci_id) \
76 MC_CMD_OP(cmd, 0, 0, 32, int, dpci_id)
78 /* cmd, param, offset, width, type, arg_name */
79 #define DPCI_CMD_CREATE(cmd, cfg) \
81 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_of_priorities);\
82 MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
85 /* cmd, param, offset, width, type, arg_name */
86 #define DPCI_RSP_IS_ENABLED(cmd, en) \
87 MC_RSP_OP(cmd, 0, 0, 1, int, en)
89 /* cmd, param, offset, width, type, arg_name */
90 #define DPCI_RSP_GET_ATTRIBUTES(cmd, attr) \
92 MC_RSP_OP(cmd, 0, 0, 32, int, (attr)->id);\
93 MC_RSP_OP(cmd, 0, 48, 8, uint8_t, (attr)->num_of_priorities);\
96 /* cmd, param, offset, width, type, arg_name */
97 #define DPCI_RSP_GET_PEER_ATTR(cmd, attr) \
99 MC_RSP_OP(cmd, 0, 0, 32, int, attr->peer_id);\
100 MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_of_priorities);\
103 /* cmd, param, offset, width, type, arg_name */
104 #define DPCI_RSP_GET_LINK_STATE(cmd, up) \
105 MC_RSP_OP(cmd, 0, 0, 1, int, up)
107 /* cmd, param, offset, width, type, arg_name */
108 #define DPCI_CMD_SET_RX_QUEUE(cmd, priority, cfg) \
110 MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id);\
111 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority);\
112 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority);\
113 MC_CMD_OP(cmd, 0, 48, 4, enum dpci_dest, cfg->dest_cfg.dest_type);\
114 MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx);\
115 MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
118 /* cmd, param, offset, width, type, arg_name */
119 #define DPCI_CMD_GET_RX_QUEUE(cmd, priority) \
120 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
122 /* cmd, param, offset, width, type, arg_name */
123 #define DPCI_RSP_GET_RX_QUEUE(cmd, attr) \
125 MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
126 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
127 MC_RSP_OP(cmd, 0, 48, 4, enum dpci_dest, attr->dest_cfg.dest_type);\
128 MC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\
129 MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
132 /* cmd, param, offset, width, type, arg_name */
133 #define DPCI_CMD_GET_TX_QUEUE(cmd, priority) \
134 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, priority)
136 /* cmd, param, offset, width, type, arg_name */
137 #define DPCI_RSP_GET_TX_QUEUE(cmd, attr) \
138 MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid)
140 /* cmd, param, offset, width, type, arg_name */
141 #define DPCI_RSP_GET_API_VERSION(cmd, major, minor) \
143 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\
144 MC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\
147 #endif /* _FSL_DPCI_CMD_H */