1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 bitmap_ctzll(uint64_t slab)
14 return __builtin_ctzll(slab);
18 nix_tm_clear_shaper_profiles(struct nix *nix)
20 struct nix_tm_shaper_profile *shaper_profile;
22 shaper_profile = TAILQ_FIRST(&nix->shaper_profile_list);
23 while (shaper_profile != NULL) {
24 if (shaper_profile->ref_cnt)
25 plt_warn("Shaper profile %u has non zero references",
27 TAILQ_REMOVE(&nix->shaper_profile_list, shaper_profile, shaper);
28 nix_tm_shaper_profile_free(shaper_profile);
29 shaper_profile = TAILQ_FIRST(&nix->shaper_profile_list);
34 nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)
36 uint64_t regval_mask[MAX_REGS_PER_MBOX_MSG];
37 uint64_t regval[MAX_REGS_PER_MBOX_MSG];
38 struct nix_tm_shaper_profile *profile;
39 uint64_t reg[MAX_REGS_PER_MBOX_MSG];
40 struct mbox *mbox = (&nix->dev)->mbox;
41 struct nix_txschq_config *req;
46 memset(regval, 0, sizeof(regval));
47 memset(regval_mask, 0, sizeof(regval_mask));
49 profile = nix_tm_shaper_profile_search(nix, node->shaper_profile_id);
50 hw_lvl = node->hw_lvl;
52 /* Need this trigger to configure TL1 */
53 if (!nix_tm_have_tl1_access(nix) && hw_lvl == NIX_TXSCH_LVL_TL2) {
54 /* Prepare default conf for TL1 */
55 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
56 req->lvl = NIX_TXSCH_LVL_TL1;
58 k = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg,
61 rc = mbox_process(mbox);
66 /* Prepare topology config */
67 k = nix_tm_topology_reg_prep(nix, node, reg, regval, regval_mask);
69 /* Prepare schedule config */
70 k += nix_tm_sched_reg_prep(nix, node, ®[k], ®val[k]);
72 /* Prepare shaping config */
73 k += nix_tm_shaper_reg_prep(node, profile, ®[k], ®val[k]);
78 /* Copy and send config mbox */
79 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
83 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
84 mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k);
85 mbox_memcpy(req->regval_mask, regval_mask, sizeof(uint64_t) * k);
87 rc = mbox_process(mbox);
93 plt_err("Txschq conf failed for node %p, rc=%d", node, rc);
98 nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)
100 struct nix_tm_node_list *list;
101 struct nix_tm_node *node;
105 list = nix_tm_node_list(nix, tree);
107 for (hw_lvl = 0; hw_lvl <= nix->tm_root_lvl; hw_lvl++) {
108 TAILQ_FOREACH(node, list, node) {
109 if (node->hw_lvl != hw_lvl)
111 rc = nix_tm_node_reg_conf(nix, node);
121 nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree)
123 struct nix_tm_node *child, *parent;
124 struct nix_tm_node_list *list;
125 uint32_t rr_prio, max_prio;
128 list = nix_tm_node_list(nix, tree);
130 /* Release all the node hw resources locally
131 * if parent marked as dirty and resource exists.
133 TAILQ_FOREACH(child, list, node) {
134 /* Release resource only if parent direct hierarchy changed */
135 if (child->flags & NIX_TM_NODE_HWRES && child->parent &&
136 child->parent->child_realloc) {
137 nix_tm_free_node_resource(nix, child);
139 child->max_prio = UINT32_MAX;
142 TAILQ_FOREACH(parent, list, node) {
143 /* Count group of children of same priority i.e are RR */
144 rr_num = nix_tm_check_rr(nix, parent->id, tree, &rr_prio,
147 /* Assuming that multiple RR groups are
148 * not configured based on capability.
150 parent->rr_prio = rr_prio;
151 parent->rr_num = rr_num;
152 parent->max_prio = max_prio;
159 nix_tm_root_node_get(struct nix *nix, int tree)
161 struct nix_tm_node_list *list = nix_tm_node_list(nix, tree);
162 struct nix_tm_node *tm_node;
164 TAILQ_FOREACH(tm_node, list, node) {
165 if (tm_node->hw_lvl == nix->tm_root_lvl)
173 nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)
175 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
176 struct nix_tm_shaper_profile *profile;
177 uint32_t node_id, parent_id, lvl;
178 struct nix_tm_node *parent_node;
179 uint32_t priority, profile_id;
180 uint8_t hw_lvl, exp_next_lvl;
181 enum roc_nix_tm_tree tree;
185 priority = node->priority;
186 parent_id = node->parent_id;
187 profile_id = node->shaper_profile_id;
191 plt_tm_dbg("Add node %s lvl %u id %u, prio 0x%x weight 0x%x "
192 "parent %u profile 0x%x tree %u",
193 nix_tm_hwlvl2str(nix_tm_lvl2nix(nix, lvl)), lvl, node_id,
194 priority, node->weight, parent_id, profile_id, tree);
196 if (tree >= ROC_NIX_TM_TREE_MAX)
197 return NIX_ERR_PARAM;
199 /* Translate sw level id's to nix hw level id's */
200 hw_lvl = nix_tm_lvl2nix(nix, lvl);
201 if (hw_lvl == NIX_TXSCH_LVL_CNT && !nix_tm_is_leaf(nix, lvl))
202 return NIX_ERR_TM_INVALID_LVL;
204 /* Leaf nodes have to be same priority */
205 if (nix_tm_is_leaf(nix, lvl) && priority != 0)
206 return NIX_ERR_TM_INVALID_PRIO;
208 parent_node = nix_tm_node_search(nix, parent_id, tree);
210 if (node_id < nix->nb_tx_queues)
211 exp_next_lvl = NIX_TXSCH_LVL_SMQ;
213 exp_next_lvl = hw_lvl + 1;
215 /* Check if there is no parent node yet */
216 if (hw_lvl != nix->tm_root_lvl &&
217 (!parent_node || parent_node->hw_lvl != exp_next_lvl))
218 return NIX_ERR_TM_INVALID_PARENT;
220 /* Check if a node already exists */
221 if (nix_tm_node_search(nix, node_id, tree))
222 return NIX_ERR_TM_NODE_EXISTS;
224 /* Check if root node exists */
225 if (hw_lvl == nix->tm_root_lvl && nix_tm_root_node_get(nix, tree))
226 return NIX_ERR_TM_NODE_EXISTS;
228 profile = nix_tm_shaper_profile_search(nix, profile_id);
229 if (!nix_tm_is_leaf(nix, lvl)) {
230 /* Check if shaper profile exists for non leaf node */
231 if (!profile && profile_id != ROC_NIX_TM_SHAPER_PROFILE_NONE)
232 return NIX_ERR_TM_INVALID_SHAPER_PROFILE;
234 /* Packet mode in profile should match with that of tm node */
235 if (profile && profile->pkt_mode != node->pkt_mode)
236 return NIX_ERR_TM_PKT_MODE_MISMATCH;
239 /* Check if there is second DWRR already in siblings or holes in prio */
240 rc = nix_tm_validate_prio(nix, lvl, parent_id, priority, tree);
244 if (node->weight > roc_nix_tm_max_sched_wt_get())
245 return NIX_ERR_TM_WEIGHT_EXCEED;
247 /* Maintain minimum weight */
251 node->hw_lvl = nix_tm_lvl2nix(nix, lvl);
253 node->max_prio = UINT32_MAX;
254 node->hw_id = NIX_TM_HW_ID_INVALID;
260 node->parent = parent_node;
262 parent_node->child_realloc = true;
263 node->parent_hw_id = NIX_TM_HW_ID_INVALID;
265 TAILQ_INSERT_TAIL(&nix->trees[tree], node, node);
266 plt_tm_dbg("Added node %s lvl %u id %u (%p)",
267 nix_tm_hwlvl2str(node->hw_lvl), lvl, node_id, node);
272 nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)
274 struct mbox *mbox = (&nix->dev)->mbox;
275 struct nix_txschq_config *req;
276 struct nix_tm_node *p;
279 /* Enable nodes in path for flush to succeed */
280 if (!nix_tm_is_leaf(nix, node->lvl))
285 if (!(p->flags & NIX_TM_NODE_ENABLED) &&
286 (p->flags & NIX_TM_NODE_HWRES)) {
287 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
288 req->lvl = p->hw_lvl;
289 req->num_regs = nix_tm_sw_xoff_prep(p, false, req->reg,
291 rc = mbox_process(mbox);
295 p->flags |= NIX_TM_NODE_ENABLED;
304 nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable)
306 struct mbox *mbox = (&nix->dev)->mbox;
307 struct nix_txschq_config *req;
312 plt_tm_dbg("Setting SMQ %u XOFF/FLUSH to %s", smq,
313 enable ? "enable" : "disable");
315 rc = nix_tm_clear_path_xoff(nix, node);
319 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
320 req->lvl = NIX_TXSCH_LVL_SMQ;
323 req->reg[0] = NIX_AF_SMQX_CFG(smq);
324 req->regval[0] = enable ? (BIT_ULL(50) | BIT_ULL(49)) : 0;
325 req->regval_mask[0] =
326 enable ? ~(BIT_ULL(50) | BIT_ULL(49)) : ~BIT_ULL(50);
328 return mbox_process(mbox);
332 nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
335 struct nix_tm_node *node;
338 node = nix_tm_node_search(nix, sq, nix->tm_tree);
340 /* Check if we found a valid leaf node */
341 if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||
342 node->parent->hw_id == NIX_TM_HW_ID_INVALID) {
346 /* Get SMQ Id of leaf node's parent */
347 *smq = node->parent->hw_id;
348 *rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);
350 rc = nix_tm_smq_xoff(nix, node->parent, false);
353 node->flags |= NIX_TM_NODE_ENABLED;
358 roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq)
360 struct nix *nix = roc_nix_to_nix_priv(sq->roc_nix);
361 uint16_t sqb_cnt, head_off, tail_off;
362 uint64_t wdata, val, prev;
363 uint16_t qid = sq->qid;
365 uint64_t timeout; /* 10's of usec */
367 /* Wait for enough time based on shaper min rate */
368 timeout = (sq->nb_desc * roc_nix_max_pkt_len(sq->roc_nix) * 8 * 1E5);
369 /* Wait for worst case scenario of this SQ being last priority
370 * and so have to wait for all other SQ's drain out by their own.
372 timeout = timeout * nix->nb_tx_queues;
373 timeout = timeout / nix->tm_rate_min;
377 wdata = ((uint64_t)qid << 32);
378 regaddr = (int64_t *)(nix->base + NIX_LF_SQ_OP_STATUS);
379 val = roc_atomic64_add_nosync(wdata, regaddr);
381 /* Spin multiple iterations as "sq->fc_cache_pkts" can still
382 * have space to send pkts even though fc_mem is disabled
388 val = roc_atomic64_add_nosync(wdata, regaddr);
389 /* Continue on error */
390 if (val & BIT_ULL(63))
396 sqb_cnt = val & 0xFFFF;
397 head_off = (val >> 20) & 0x3F;
398 tail_off = (val >> 28) & 0x3F;
400 /* SQ reached quiescent state */
401 if (sqb_cnt <= 1 && head_off == tail_off &&
402 (*(volatile uint64_t *)sq->fc == sq->nb_sqb_bufs)) {
414 roc_nix_tm_dump(sq->roc_nix);
415 roc_nix_queues_ctx_dump(sq->roc_nix);
419 /* Flush and disable tx queue and its parent SMQ */
421 nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
423 struct roc_nix *roc_nix = sq->roc_nix;
424 struct nix_tm_node *node, *sibling;
425 struct nix_tm_node_list *list;
426 enum roc_nix_tm_tree tree;
432 nix = roc_nix_to_nix_priv(roc_nix);
434 /* Need not do anything if tree is in disabled state */
435 if (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
438 mbox = (&nix->dev)->mbox;
442 list = nix_tm_node_list(nix, tree);
444 /* Find the node for this SQ */
445 node = nix_tm_node_search(nix, qid, tree);
446 if (!node || !(node->flags & NIX_TM_NODE_ENABLED)) {
447 plt_err("Invalid node/state for sq %u", qid);
451 /* Enable CGX RXTX to drain pkts */
452 if (!roc_nix->io_enabled) {
453 /* Though it enables both RX MCAM Entries and CGX Link
454 * we assume all the rx queues are stopped way back.
456 mbox_alloc_msg_nix_lf_start_rx(mbox);
457 rc = mbox_process(mbox);
459 plt_err("cgx start failed, rc=%d", rc);
464 /* Disable smq xoff for case it was enabled earlier */
465 rc = nix_tm_smq_xoff(nix, node->parent, false);
467 plt_err("Failed to enable smq %u, rc=%d", node->parent->hw_id,
472 /* As per HRM, to disable an SQ, all other SQ's
473 * that feed to same SMQ must be paused before SMQ flush.
475 TAILQ_FOREACH(sibling, list, node) {
476 if (sibling->parent != node->parent)
478 if (!(sibling->flags & NIX_TM_NODE_ENABLED))
486 rc = roc_nix_tm_sq_aura_fc(sq, false);
488 plt_err("Failed to disable sqb aura fc, rc=%d", rc);
492 /* Wait for sq entries to be flushed */
493 rc = roc_nix_tm_sq_flush_spin(sq);
495 plt_err("Failed to drain sq %u, rc=%d\n", sq->qid, rc);
500 node->flags &= ~NIX_TM_NODE_ENABLED;
502 /* Disable and flush */
503 rc = nix_tm_smq_xoff(nix, node->parent, true);
505 plt_err("Failed to disable smq %u, rc=%d", node->parent->hw_id,
510 /* Restore cgx state */
511 if (!roc_nix->io_enabled) {
512 mbox_alloc_msg_nix_lf_stop_rx(mbox);
513 rc |= mbox_process(mbox);
520 nix_tm_sq_flush_post(struct roc_nix_sq *sq)
522 struct roc_nix *roc_nix = sq->roc_nix;
523 struct nix_tm_node *node, *sibling;
524 struct nix_tm_node_list *list;
525 enum roc_nix_tm_tree tree;
526 struct roc_nix_sq *s_sq;
532 nix = roc_nix_to_nix_priv(roc_nix);
534 /* Need not do anything if tree is in disabled state */
535 if (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
540 list = nix_tm_node_list(nix, tree);
542 /* Find the node for this SQ */
543 node = nix_tm_node_search(nix, qid, tree);
545 plt_err("Invalid node for sq %u", qid);
549 /* Enable all the siblings back */
550 TAILQ_FOREACH(sibling, list, node) {
551 if (sibling->parent != node->parent)
554 if (sibling->id == qid)
557 if (!(sibling->flags & NIX_TM_NODE_ENABLED))
561 s_sq = nix->sqs[s_qid];
566 /* Enable back if any SQ is still present */
567 rc = nix_tm_smq_xoff(nix, node->parent, false);
569 plt_err("Failed to enable smq %u, rc=%d",
570 node->parent->hw_id, rc);
576 rc = roc_nix_tm_sq_aura_fc(s_sq, true);
578 plt_err("Failed to enable sqb aura fc, rc=%d", rc);
587 nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
588 bool rr_quantum_only)
590 struct mbox *mbox = (&nix->dev)->mbox;
591 uint16_t qid = node->id, smq;
595 smq = node->parent->hw_id;
596 rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);
599 plt_tm_dbg("Update sq(%u) rr_quantum 0x%" PRIx64, qid,
602 plt_tm_dbg("Enabling sq(%u)->smq(%u), rr_quantum 0x%" PRIx64,
603 qid, smq, rr_quantum);
605 if (qid > nix->nb_tx_queues)
608 if (roc_model_is_cn9k()) {
609 struct nix_aq_enq_req *aq;
611 aq = mbox_alloc_msg_nix_aq_enq(mbox);
613 aq->ctype = NIX_AQ_CTYPE_SQ;
614 aq->op = NIX_AQ_INSTOP_WRITE;
616 /* smq update only when needed */
617 if (!rr_quantum_only) {
619 aq->sq_mask.smq = ~aq->sq_mask.smq;
621 aq->sq.smq_rr_quantum = rr_quantum;
622 aq->sq_mask.smq_rr_quantum = ~aq->sq_mask.smq_rr_quantum;
624 struct nix_cn10k_aq_enq_req *aq;
626 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
628 aq->ctype = NIX_AQ_CTYPE_SQ;
629 aq->op = NIX_AQ_INSTOP_WRITE;
631 /* smq update only when needed */
632 if (!rr_quantum_only) {
634 aq->sq_mask.smq = ~aq->sq_mask.smq;
636 aq->sq.smq_rr_weight = rr_quantum;
637 aq->sq_mask.smq_rr_weight = ~aq->sq_mask.smq_rr_weight;
640 rc = mbox_process(mbox);
642 plt_err("Failed to set smq, rc=%d", rc);
647 nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
650 uint16_t avail, thresh, to_free = 0, schq;
651 struct mbox *mbox = (&nix->dev)->mbox;
652 struct nix_txsch_free_req *req;
653 struct plt_bitmap *bmp;
658 bmp = contig ? nix->schq_contig_bmp[hw_lvl] : nix->schq_bmp[hw_lvl];
660 contig ? nix->contig_rsvd[hw_lvl] : nix->discontig_rsvd[hw_lvl];
661 plt_bitmap_scan_init(bmp);
663 avail = nix_tm_resource_avail(nix, hw_lvl, contig);
666 /* Release only above threshold */
668 to_free = avail - thresh;
670 /* Release everything */
674 /* Now release resources to AF */
676 if (!slab && !plt_bitmap_scan(bmp, &pos, &slab))
679 schq = bitmap_ctzll(slab);
680 slab &= ~(1ULL << schq);
684 req = mbox_alloc_msg_nix_txsch_free(mbox);
688 req->schq_lvl = hw_lvl;
690 rc = mbox_process(mbox);
692 plt_err("failed to release hwres %s(%u) rc %d",
693 nix_tm_hwlvl2str(hw_lvl), schq, rc);
697 plt_tm_dbg("Released hwres %s(%u)", nix_tm_hwlvl2str(hw_lvl),
699 plt_bitmap_clear(bmp, schq);
704 plt_err("resource inconsistency for %s(%u)",
705 nix_tm_hwlvl2str(hw_lvl), contig);
712 nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)
714 struct mbox *mbox = (&nix->dev)->mbox;
715 struct nix_txsch_free_req *req;
716 struct plt_bitmap *bmp;
717 uint16_t avail, hw_id;
721 hw_lvl = node->hw_lvl;
723 bmp = nix->schq_bmp[hw_lvl];
724 /* Free specific HW resource */
725 plt_tm_dbg("Free hwres %s(%u) lvl %u id %u (%p)",
726 nix_tm_hwlvl2str(node->hw_lvl), hw_id, node->lvl, node->id,
729 avail = nix_tm_resource_avail(nix, hw_lvl, false);
730 /* Always for now free to discontiguous queue when avail
733 if (nix->discontig_rsvd[hw_lvl] &&
734 avail < nix->discontig_rsvd[hw_lvl]) {
735 PLT_ASSERT(hw_id < NIX_TM_MAX_HW_TXSCHQ);
736 PLT_ASSERT(plt_bitmap_get(bmp, hw_id) == 0);
737 plt_bitmap_set(bmp, hw_id);
738 node->hw_id = NIX_TM_HW_ID_INVALID;
739 node->flags &= ~NIX_TM_NODE_HWRES;
744 req = mbox_alloc_msg_nix_txsch_free(mbox);
748 req->schq_lvl = node->hw_lvl;
750 rc = mbox_process(mbox);
752 plt_err("failed to release hwres %s(%u) rc %d",
753 nix_tm_hwlvl2str(node->hw_lvl), hw_id, rc);
757 /* Mark parent as dirty for reallocing it's children */
759 node->parent->child_realloc = true;
761 node->hw_id = NIX_TM_HW_ID_INVALID;
762 node->flags &= ~NIX_TM_NODE_HWRES;
763 plt_tm_dbg("Released hwres %s(%u) to af",
764 nix_tm_hwlvl2str(node->hw_lvl), hw_id);
769 nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
770 enum roc_nix_tm_tree tree, bool free)
772 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
773 struct nix_tm_shaper_profile *profile;
774 struct nix_tm_node *node, *child;
775 struct nix_tm_node_list *list;
779 plt_tm_dbg("Delete node id %u tree %u", node_id, tree);
781 node = nix_tm_node_search(nix, node_id, tree);
783 return NIX_ERR_TM_INVALID_NODE;
785 list = nix_tm_node_list(nix, tree);
786 /* Check for any existing children */
787 TAILQ_FOREACH(child, list, node) {
788 if (child->parent == node)
789 return NIX_ERR_TM_CHILD_EXISTS;
792 /* Remove shaper profile reference */
793 profile_id = node->shaper_profile_id;
794 profile = nix_tm_shaper_profile_search(nix, profile_id);
796 /* Free hw resource locally */
797 if (node->flags & NIX_TM_NODE_HWRES) {
798 rc = nix_tm_free_node_resource(nix, node);
806 TAILQ_REMOVE(list, node, node);
808 plt_tm_dbg("Deleted node %s lvl %u id %u, prio 0x%x weight 0x%x "
809 "parent %u profile 0x%x tree %u (%p)",
810 nix_tm_hwlvl2str(node->hw_lvl), node->lvl, node->id,
811 node->priority, node->weight,
812 node->parent ? node->parent->id : UINT32_MAX,
813 node->shaper_profile_id, tree, node);
814 /* Free only if requested */
816 nix_tm_node_free(node);
821 nix_tm_assign_hw_id(struct nix *nix, struct nix_tm_node *parent,
822 uint16_t *contig_id, int *contig_cnt,
823 struct nix_tm_node_list *list)
825 struct nix_tm_node *child;
826 struct plt_bitmap *bmp;
827 uint8_t child_hw_lvl;
833 child_hw_lvl = parent->hw_lvl - 1;
834 bmp = nix->schq_bmp[child_hw_lvl];
835 plt_bitmap_scan_init(bmp);
838 /* Save spare schq if it is case of RR + SP */
839 if (parent->rr_prio != 0xf && *contig_cnt > 1)
840 spare_schq = *contig_id + parent->rr_prio;
842 TAILQ_FOREACH(child, list, node) {
845 if (child->parent->id != parent->id)
848 /* Resource never expected to be present */
849 if (child->flags & NIX_TM_NODE_HWRES) {
850 plt_err("Resource exists for child (%s)%u, id %u (%p)",
851 nix_tm_hwlvl2str(child->hw_lvl), child->hw_id,
857 plt_bitmap_scan(bmp, &pos, &slab);
859 if (child->priority == parent->rr_prio && spare_schq != -1) {
860 /* Use spare schq first if present */
863 *contig_cnt = *contig_cnt - 1;
865 } else if (child->priority == parent->rr_prio) {
866 /* Assign a discontiguous queue */
868 plt_err("Schq not found for Child %u "
870 child->id, child->lvl, child);
874 schq = bitmap_ctzll(slab);
875 slab &= ~(1ULL << schq);
877 plt_bitmap_clear(bmp, schq);
879 /* Assign a contiguous queue */
880 schq = *contig_id + child->priority;
881 *contig_cnt = *contig_cnt - 1;
884 plt_tm_dbg("Resource %s(%u), for lvl %u id %u(%p)",
885 nix_tm_hwlvl2str(child->hw_lvl), schq, child->lvl,
889 child->parent_hw_id = parent->hw_id;
890 child->flags |= NIX_TM_NODE_HWRES;
897 nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree)
899 struct nix_tm_node *parent, *root = NULL;
900 struct plt_bitmap *bmp, *bmp_contig;
901 struct nix_tm_node_list *list;
902 uint8_t child_hw_lvl, hw_lvl;
903 uint16_t contig_id, j;
908 list = nix_tm_node_list(nix, tree);
909 /* Walk from TL1 to TL4 parents */
910 for (hw_lvl = NIX_TXSCH_LVL_TL1; hw_lvl > 0; hw_lvl--) {
911 TAILQ_FOREACH(parent, list, node) {
912 child_hw_lvl = parent->hw_lvl - 1;
913 if (parent->hw_lvl != hw_lvl)
916 /* Remember root for future */
917 if (parent->hw_lvl == nix->tm_root_lvl)
920 if (!parent->child_realloc) {
921 /* Skip when parent is not dirty */
922 if (nix_tm_child_res_valid(list, parent))
924 plt_err("Parent not dirty but invalid "
925 "child res parent id %u(lvl %u)",
926 parent->id, parent->lvl);
930 bmp_contig = nix->schq_contig_bmp[child_hw_lvl];
932 /* Prealloc contiguous indices for a parent */
933 contig_id = NIX_TM_MAX_HW_TXSCHQ;
934 cnt = (int)parent->max_prio + 1;
936 plt_bitmap_scan_init(bmp_contig);
937 if (!plt_bitmap_scan(bmp_contig, &pos, &slab)) {
938 plt_err("Contig schq not found");
941 contig_id = pos + bitmap_ctzll(slab);
943 /* Check if we have enough */
944 for (j = contig_id; j < contig_id + cnt; j++) {
945 if (!plt_bitmap_get(bmp_contig, j))
949 if (j != contig_id + cnt) {
950 plt_err("Contig schq not sufficient");
954 for (j = contig_id; j < contig_id + cnt; j++)
955 plt_bitmap_clear(bmp_contig, j);
958 /* Assign hw id to all children */
959 rc = nix_tm_assign_hw_id(nix, parent, &contig_id, &cnt,
962 plt_err("Unexpected err, contig res alloc, "
963 "parent %u, of %s, rc=%d, cnt=%d",
964 parent->id, nix_tm_hwlvl2str(hw_lvl),
969 /* Clear the dirty bit as children's
970 * resources are reallocated.
972 parent->child_realloc = false;
976 /* Root is always expected to be there */
980 if (root->flags & NIX_TM_NODE_HWRES)
983 /* Process root node */
984 bmp = nix->schq_bmp[nix->tm_root_lvl];
985 plt_bitmap_scan_init(bmp);
986 if (!plt_bitmap_scan(bmp, &pos, &slab)) {
987 plt_err("Resource not allocated for root");
991 root->hw_id = pos + bitmap_ctzll(slab);
992 root->flags |= NIX_TM_NODE_HWRES;
993 plt_bitmap_clear(bmp, root->hw_id);
995 /* Get TL1 id as well when root is not TL1 */
996 if (!nix_tm_have_tl1_access(nix)) {
997 bmp = nix->schq_bmp[NIX_TXSCH_LVL_TL1];
999 plt_bitmap_scan_init(bmp);
1000 if (!plt_bitmap_scan(bmp, &pos, &slab)) {
1001 plt_err("Resource not found for TL1");
1004 root->parent_hw_id = pos + bitmap_ctzll(slab);
1005 plt_bitmap_clear(bmp, root->parent_hw_id);
1008 plt_tm_dbg("Resource %s(%u) for root(id %u) (%p)",
1009 nix_tm_hwlvl2str(root->hw_lvl), root->hw_id, root->id, root);
1015 nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp)
1020 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1021 for (i = 0; i < rsp->schq[lvl]; i++)
1022 plt_bitmap_set(nix->schq_bmp[lvl],
1023 rsp->schq_list[lvl][i]);
1025 for (i = 0; i < rsp->schq_contig[lvl]; i++)
1026 plt_bitmap_set(nix->schq_contig_bmp[lvl],
1027 rsp->schq_contig_list[lvl][i]);
1032 nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)
1034 uint16_t schq_contig[NIX_TXSCH_LVL_CNT];
1035 struct mbox *mbox = (&nix->dev)->mbox;
1036 uint16_t schq[NIX_TXSCH_LVL_CNT];
1037 struct nix_txsch_alloc_req *req;
1038 struct nix_txsch_alloc_rsp *rsp;
1043 memset(schq, 0, sizeof(schq));
1044 memset(schq_contig, 0, sizeof(schq_contig));
1046 /* Estimate requirement */
1047 rc = nix_tm_resource_estimate(nix, schq_contig, schq, tree);
1051 /* Release existing contiguous resources when realloc requested
1052 * as there is no way to guarantee continuity of old with new.
1054 for (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1055 if (schq_contig[hw_lvl])
1056 nix_tm_release_resources(nix, hw_lvl, true, false);
1059 /* Alloc as needed */
1062 req = mbox_alloc_msg_nix_txsch_alloc(mbox);
1067 mbox_memcpy(req->schq, schq, sizeof(req->schq));
1068 mbox_memcpy(req->schq_contig, schq_contig,
1069 sizeof(req->schq_contig));
1071 /* Each alloc can be at max of MAX_TXSCHQ_PER_FUNC per level.
1072 * So split alloc to multiple requests.
1074 for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
1075 if (req->schq[i] > MAX_TXSCHQ_PER_FUNC)
1076 req->schq[i] = MAX_TXSCHQ_PER_FUNC;
1077 schq[i] -= req->schq[i];
1079 if (req->schq_contig[i] > MAX_TXSCHQ_PER_FUNC)
1080 req->schq_contig[i] = MAX_TXSCHQ_PER_FUNC;
1081 schq_contig[i] -= req->schq_contig[i];
1083 if (schq[i] || schq_contig[i])
1087 rc = mbox_process_msg(mbox, (void *)&rsp);
1091 nix_tm_copy_rsp_to_nix(nix, rsp);
1094 nix->tm_link_cfg_lvl = rsp->link_cfg_lvl;
1097 for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
1098 if (nix_tm_release_resources(nix, i, true, false))
1099 plt_err("Failed to release contig resources of "
1102 if (nix_tm_release_resources(nix, i, false, false))
1103 plt_err("Failed to release discontig resources of "
1111 nix_tm_prepare_default_tree(struct roc_nix *roc_nix)
1113 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1114 uint32_t nonleaf_id = nix->nb_tx_queues;
1115 struct nix_tm_node *node = NULL;
1116 uint8_t leaf_lvl, lvl, lvl_end;
1120 /* Add ROOT, SCH1, SCH2, SCH3, [SCH4] nodes */
1121 parent = ROC_NIX_TM_NODE_ID_INVALID;
1122 /* With TL1 access we have an extra level */
1123 lvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 :
1126 for (lvl = ROC_TM_LVL_ROOT; lvl <= lvl_end; lvl++) {
1128 node = nix_tm_node_alloc();
1132 node->id = nonleaf_id;
1133 node->parent_id = parent;
1135 node->weight = NIX_TM_DFLT_RR_WT;
1136 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1138 node->tree = ROC_NIX_TM_DEFAULT;
1140 rc = nix_tm_node_add(roc_nix, node);
1143 parent = nonleaf_id;
1147 parent = nonleaf_id - 1;
1148 leaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :
1151 /* Add leaf nodes */
1152 for (i = 0; i < nix->nb_tx_queues; i++) {
1154 node = nix_tm_node_alloc();
1159 node->parent_id = parent;
1161 node->weight = NIX_TM_DFLT_RR_WT;
1162 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1163 node->lvl = leaf_lvl;
1164 node->tree = ROC_NIX_TM_DEFAULT;
1166 rc = nix_tm_node_add(roc_nix, node);
1173 nix_tm_node_free(node);
1178 roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)
1180 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1181 uint32_t nonleaf_id = nix->nb_tx_queues;
1182 struct nix_tm_node *node = NULL;
1183 uint8_t leaf_lvl, lvl, lvl_end;
1187 /* Add ROOT, SCH1, SCH2 nodes */
1188 parent = ROC_NIX_TM_NODE_ID_INVALID;
1189 lvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH3 :
1192 for (lvl = ROC_TM_LVL_ROOT; lvl <= lvl_end; lvl++) {
1194 node = nix_tm_node_alloc();
1198 node->id = nonleaf_id;
1199 node->parent_id = parent;
1201 node->weight = NIX_TM_DFLT_RR_WT;
1202 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1204 node->tree = ROC_NIX_TM_RLIMIT;
1206 rc = nix_tm_node_add(roc_nix, node);
1209 parent = nonleaf_id;
1213 /* SMQ is mapped to SCH4 when we have TL1 access and SCH3 otherwise */
1214 lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 : ROC_TM_LVL_SCH3);
1216 /* Add per queue SMQ nodes i.e SCH4 / SCH3 */
1217 for (i = 0; i < nix->nb_tx_queues; i++) {
1219 node = nix_tm_node_alloc();
1223 node->id = nonleaf_id + i;
1224 node->parent_id = parent;
1226 node->weight = NIX_TM_DFLT_RR_WT;
1227 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1229 node->tree = ROC_NIX_TM_RLIMIT;
1231 rc = nix_tm_node_add(roc_nix, node);
1236 parent = nonleaf_id;
1237 leaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :
1240 /* Add leaf nodes */
1241 for (i = 0; i < nix->nb_tx_queues; i++) {
1243 node = nix_tm_node_alloc();
1248 node->parent_id = parent + i;
1250 node->weight = NIX_TM_DFLT_RR_WT;
1251 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1252 node->lvl = leaf_lvl;
1253 node->tree = ROC_NIX_TM_RLIMIT;
1255 rc = nix_tm_node_add(roc_nix, node);
1262 nix_tm_node_free(node);
1267 nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask, bool hw_only)
1269 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1270 struct nix_tm_shaper_profile *profile;
1271 struct nix_tm_node *node, *next_node;
1272 struct nix_tm_node_list *list;
1273 enum roc_nix_tm_tree tree;
1274 uint32_t profile_id;
1277 for (tree = 0; tree < ROC_NIX_TM_TREE_MAX; tree++) {
1278 if (!(tree_mask & BIT(tree)))
1281 plt_tm_dbg("Freeing resources of tree %u", tree);
1283 list = nix_tm_node_list(nix, tree);
1284 next_node = TAILQ_FIRST(list);
1287 next_node = TAILQ_NEXT(node, node);
1289 if (!nix_tm_is_leaf(nix, node->lvl) &&
1290 node->flags & NIX_TM_NODE_HWRES) {
1291 /* Clear xoff in path for flush to succeed */
1292 rc = nix_tm_clear_path_xoff(nix, node);
1295 rc = nix_tm_free_node_resource(nix, node);
1301 /* Leave software elements if needed */
1305 next_node = TAILQ_FIRST(list);
1308 next_node = TAILQ_NEXT(node, node);
1310 plt_tm_dbg("Free node lvl %u id %u (%p)", node->lvl,
1313 profile_id = node->shaper_profile_id;
1314 profile = nix_tm_shaper_profile_search(nix, profile_id);
1318 TAILQ_REMOVE(list, node, node);
1319 nix_tm_node_free(node);
1326 nix_tm_conf_init(struct roc_nix *roc_nix)
1328 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1329 uint32_t bmp_sz, hw_lvl;
1333 PLT_STATIC_ASSERT(sizeof(struct nix_tm_node) <= ROC_NIX_TM_NODE_SZ);
1334 PLT_STATIC_ASSERT(sizeof(struct nix_tm_shaper_profile) <=
1335 ROC_NIX_TM_SHAPER_PROFILE_SZ);
1338 for (i = 0; i < ROC_NIX_TM_TREE_MAX; i++)
1339 TAILQ_INIT(&nix->trees[i]);
1341 TAILQ_INIT(&nix->shaper_profile_list);
1342 nix->tm_rate_min = 1E9; /* 1Gbps */
1345 bmp_sz = plt_bitmap_get_memory_footprint(NIX_TM_MAX_HW_TXSCHQ);
1346 bmp_mem = plt_zmalloc(bmp_sz * NIX_TXSCH_LVL_CNT * 2, 0);
1349 nix->schq_bmp_mem = bmp_mem;
1351 /* Init contiguous and discontiguous bitmap per lvl */
1353 for (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1354 /* Bitmap for discontiguous resource */
1355 nix->schq_bmp[hw_lvl] =
1356 plt_bitmap_init(NIX_TM_MAX_HW_TXSCHQ, bmp_mem, bmp_sz);
1357 if (!nix->schq_bmp[hw_lvl])
1360 bmp_mem = PLT_PTR_ADD(bmp_mem, bmp_sz);
1362 /* Bitmap for contiguous resource */
1363 nix->schq_contig_bmp[hw_lvl] =
1364 plt_bitmap_init(NIX_TM_MAX_HW_TXSCHQ, bmp_mem, bmp_sz);
1365 if (!nix->schq_contig_bmp[hw_lvl])
1368 bmp_mem = PLT_PTR_ADD(bmp_mem, bmp_sz);
1371 /* Disable TL1 Static Priority when VF's are enabled
1372 * as otherwise VF's TL2 reallocation will be needed
1373 * runtime to support a specific topology of PF.
1375 if (nix->pci_dev->max_vfs)
1376 nix->tm_flags |= NIX_TM_TL1_NO_SP;
1378 /* TL1 access is only for PF's */
1379 if (roc_nix_is_pf(roc_nix)) {
1380 nix->tm_flags |= NIX_TM_TL1_ACCESS;
1381 nix->tm_root_lvl = NIX_TXSCH_LVL_TL1;
1383 nix->tm_root_lvl = NIX_TXSCH_LVL_TL2;
1388 nix_tm_conf_fini(roc_nix);
1393 nix_tm_conf_fini(struct roc_nix *roc_nix)
1395 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1398 for (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1399 plt_bitmap_free(nix->schq_bmp[hw_lvl]);
1400 plt_bitmap_free(nix->schq_contig_bmp[hw_lvl]);
1402 plt_free(nix->schq_bmp_mem);