1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
11 /* devX creation object */
12 struct mlx5_devx_obj {
13 struct mlx5dv_devx_obj *obj; /* The DV object. */
14 int id; /* The object ID. */
17 struct mlx5_devx_mkey_attr {
24 /* HCA qos attributes. */
25 struct mlx5_hca_qos_attr {
26 uint32_t sup:1; /* Whether QOS is supported. */
27 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
28 uint32_t flow_meter_reg_share:1;
29 /* Whether reg_c share is supported. */
30 uint8_t log_max_flow_meter;
31 /* Power of the maximum supported meters. */
32 uint8_t flow_meter_reg_c_ids;
33 /* Bitmap of the reg_Cs available for flow meter to use. */
37 /* HCA supports this number of time periods for LRO. */
38 #define MLX5_LRO_NUM_SUPP_PERIODS 4
41 struct mlx5_hca_attr {
42 uint32_t eswitch_manager:1;
43 uint32_t flow_counters_dump:1;
44 uint8_t flow_counter_bulk_alloc_bitmap;
45 uint32_t eth_net_offloads:1;
47 uint32_t wqe_vlan_insert:1;
48 uint32_t wqe_inline_mode:2;
49 uint32_t vport_inline_mode:3;
50 uint32_t tunnel_stateless_geneve_rx:1;
51 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
52 uint32_t tunnel_stateless_gtp:1;
54 uint32_t tunnel_lro_gre:1;
55 uint32_t tunnel_lro_vxlan:1;
56 uint32_t lro_max_msg_sz_mode:2;
57 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
58 uint32_t flex_parser_protocols;
60 uint32_t log_max_hairpin_queues:5;
61 uint32_t log_max_hairpin_wq_data_sz:5;
62 uint32_t log_max_hairpin_num_packets:5;
64 struct mlx5_hca_qos_attr qos;
67 struct mlx5_devx_wq_attr {
69 uint32_t wq_signature:1;
70 uint32_t end_padding_mode:2;
72 uint32_t hds_skip_first_sge:1;
73 uint32_t log2_hds_buf_size:3;
74 uint32_t page_offset:5;
81 uint32_t log_wq_stride:4;
82 uint32_t log_wq_pg_sz:5;
84 uint32_t dbr_umem_valid:1;
85 uint32_t wq_umem_valid:1;
86 uint32_t log_hairpin_num_packets:5;
87 uint32_t log_hairpin_data_sz:5;
88 uint32_t single_wqe_log_num_of_strides:4;
89 uint32_t two_byte_shift_en:1;
90 uint32_t single_stride_log_num_of_bytes:3;
93 uint64_t wq_umem_offset;
96 /* Create RQ attributes structure, used by create RQ operation. */
97 struct mlx5_devx_create_rq_attr {
99 uint32_t delay_drop_en:1;
100 uint32_t scatter_fcs:1;
102 uint32_t mem_rq_type:4;
104 uint32_t flush_in_error_en:1;
106 uint32_t user_index:24;
108 uint32_t counter_set_id:8;
110 struct mlx5_devx_wq_attr wq_attr;
113 /* Modify RQ attributes structure, used by modify RQ operation. */
114 struct mlx5_devx_modify_rq_attr {
116 uint32_t rq_state:4; /* Current RQ state. */
117 uint32_t state:4; /* Required RQ state. */
118 uint32_t scatter_fcs:1;
120 uint32_t counter_set_id:8;
121 uint32_t hairpin_peer_sq:24;
122 uint32_t hairpin_peer_vhca:16;
123 uint64_t modify_bitmask;
124 uint32_t lwm:16; /* Contained WQ lwm. */
127 struct mlx5_rx_hash_field_select {
128 uint32_t l3_prot_type:1;
129 uint32_t l4_prot_type:1;
130 uint32_t selected_fields:30;
133 /* TIR attributes structure, used by TIR operations. */
134 struct mlx5_devx_tir_attr {
135 uint32_t disp_type:4;
136 uint32_t lro_timeout_period_usecs:16;
137 uint32_t lro_enable_mask:4;
138 uint32_t lro_max_msg_sz:8;
139 uint32_t inline_rqn:24;
140 uint32_t rx_hash_symmetric:1;
141 uint32_t tunneled_offload_en:1;
142 uint32_t indirect_table:24;
143 uint32_t rx_hash_fn:4;
144 uint32_t self_lb_block:2;
145 uint32_t transport_domain:24;
146 uint32_t rx_hash_toeplitz_key[10];
147 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
148 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
151 /* RQT attributes structure, used by RQT operations. */
152 struct mlx5_devx_rqt_attr {
153 uint32_t rqt_max_size:16;
154 uint32_t rqt_actual_size:16;
158 /* TIS attributes structure. */
159 struct mlx5_devx_tis_attr {
160 uint32_t strict_lag_tx_port_affinity:1;
162 uint32_t lag_tx_port_affinity:4;
164 uint32_t transport_domain:24;
167 /* SQ attributes structure, used by SQ create operation. */
168 struct mlx5_devx_create_sq_attr {
170 uint32_t cd_master:1;
172 uint32_t flush_in_error_en:1;
173 uint32_t allow_multi_pkt_send_wqe:1;
174 uint32_t min_wqe_inline_mode:3;
177 uint32_t allow_swp:1;
179 uint32_t user_index:24;
181 uint32_t packet_pacing_rate_limit_index:16;
182 uint32_t tis_lst_sz:16;
184 struct mlx5_devx_wq_attr wq_attr;
187 /* SQ attributes structure, used by SQ modify operation. */
188 struct mlx5_devx_modify_sq_attr {
191 uint32_t hairpin_peer_rq:24;
192 uint32_t hairpin_peer_vhca:16;
195 /* mlx5_devx_cmds.c */
197 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
199 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
200 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
201 int clear, uint32_t n_counters,
202 uint64_t *pkts, uint64_t *bytes,
203 uint32_t mkey, void *addr,
204 struct mlx5dv_devx_cmd_comp *cmd_comp,
206 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
207 struct mlx5_hca_attr *attr);
208 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
209 struct mlx5_devx_mkey_attr *attr);
210 int mlx5_devx_get_out_command_status(void *out);
211 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
213 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
214 struct mlx5_devx_create_rq_attr *rq_attr,
216 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
217 struct mlx5_devx_modify_rq_attr *rq_attr);
218 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
219 struct mlx5_devx_tir_attr *tir_attr);
220 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
221 struct mlx5_devx_rqt_attr *rqt_attr);
222 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
223 struct mlx5_devx_create_sq_attr *sq_attr);
224 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
225 struct mlx5_devx_modify_sq_attr *sq_attr);
226 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
227 struct mlx5_devx_tis_attr *tis_attr);
228 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
229 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
231 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */