1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
13 #include <rte_atomic.h>
14 #include <rte_byteorder.h>
17 #include <rte_spinlock.h>
18 #include <rte_crypto_sym.h>
19 #include <rte_cryptodev.h>
23 #define AES_BLOCK_SIZE 16
24 #define CMAC_PAD_VALUE 0x80
25 #define CTR_NONCE_SIZE 4
27 #define CCP_SHA3_CTX_SIZE 200
29 /**Macro helpers for CCP command creation*/
30 #define CCP_AES_SIZE(p) ((p)->aes.size)
31 #define CCP_AES_ENCRYPT(p) ((p)->aes.encrypt)
32 #define CCP_AES_MODE(p) ((p)->aes.mode)
33 #define CCP_AES_TYPE(p) ((p)->aes.type)
34 #define CCP_DES_ENCRYPT(p) ((p)->des.encrypt)
35 #define CCP_DES_MODE(p) ((p)->des.mode)
36 #define CCP_DES_TYPE(p) ((p)->des.type)
37 #define CCP_SHA_TYPE(p) ((p)->sha.type)
38 #define CCP_PT_BYTESWAP(p) ((p)->pt.byteswap)
39 #define CCP_PT_BITWISE(p) ((p)->pt.bitwise)
42 #define HMAC_IPAD_VALUE 0x36
43 #define HMAC_OPAD_VALUE 0x5c
45 #ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH
46 #define MD5_DIGEST_SIZE 16
47 #define MD5_BLOCK_SIZE 64
51 #define SHA_COMMON_DIGEST_SIZE 32
52 #define SHA1_DIGEST_SIZE 20
53 #define SHA1_BLOCK_SIZE 64
55 #define SHA224_DIGEST_SIZE 28
56 #define SHA224_BLOCK_SIZE 64
57 #define SHA3_224_BLOCK_SIZE 144
59 #define SHA256_DIGEST_SIZE 32
60 #define SHA256_BLOCK_SIZE 64
61 #define SHA3_256_BLOCK_SIZE 136
63 #define SHA384_DIGEST_SIZE 48
64 #define SHA384_BLOCK_SIZE 128
65 #define SHA3_384_BLOCK_SIZE 104
67 #define SHA512_DIGEST_SIZE 64
68 #define SHA512_BLOCK_SIZE 128
69 #define SHA3_512_BLOCK_SIZE 72
71 /* SHA LSB intialiazation values */
73 #define SHA1_H0 0x67452301UL
74 #define SHA1_H1 0xefcdab89UL
75 #define SHA1_H2 0x98badcfeUL
76 #define SHA1_H3 0x10325476UL
77 #define SHA1_H4 0xc3d2e1f0UL
79 #define SHA224_H0 0xc1059ed8UL
80 #define SHA224_H1 0x367cd507UL
81 #define SHA224_H2 0x3070dd17UL
82 #define SHA224_H3 0xf70e5939UL
83 #define SHA224_H4 0xffc00b31UL
84 #define SHA224_H5 0x68581511UL
85 #define SHA224_H6 0x64f98fa7UL
86 #define SHA224_H7 0xbefa4fa4UL
88 #define SHA256_H0 0x6a09e667UL
89 #define SHA256_H1 0xbb67ae85UL
90 #define SHA256_H2 0x3c6ef372UL
91 #define SHA256_H3 0xa54ff53aUL
92 #define SHA256_H4 0x510e527fUL
93 #define SHA256_H5 0x9b05688cUL
94 #define SHA256_H6 0x1f83d9abUL
95 #define SHA256_H7 0x5be0cd19UL
97 #define SHA384_H0 0xcbbb9d5dc1059ed8ULL
98 #define SHA384_H1 0x629a292a367cd507ULL
99 #define SHA384_H2 0x9159015a3070dd17ULL
100 #define SHA384_H3 0x152fecd8f70e5939ULL
101 #define SHA384_H4 0x67332667ffc00b31ULL
102 #define SHA384_H5 0x8eb44a8768581511ULL
103 #define SHA384_H6 0xdb0c2e0d64f98fa7ULL
104 #define SHA384_H7 0x47b5481dbefa4fa4ULL
106 #define SHA512_H0 0x6a09e667f3bcc908ULL
107 #define SHA512_H1 0xbb67ae8584caa73bULL
108 #define SHA512_H2 0x3c6ef372fe94f82bULL
109 #define SHA512_H3 0xa54ff53a5f1d36f1ULL
110 #define SHA512_H4 0x510e527fade682d1ULL
111 #define SHA512_H5 0x9b05688c2b3e6c1fULL
112 #define SHA512_H6 0x1f83d9abfb41bd6bULL
113 #define SHA512_H7 0x5be0cd19137e2179ULL
116 * CCP supported AES modes
119 CCP_AES_MODE_ECB = 0,
133 enum ccp_aes_ghash_mode {
134 CCP_AES_MODE_GHASH_AAD = 0,
135 CCP_AES_MODE_GHASH_FINAL
139 * CCP supported AES types
142 CCP_AES_TYPE_128 = 0,
148 /***** 3DES engine *****/
151 * CCP supported DES/3DES modes
154 CCP_DES_MODE_ECB = 0, /* Not supported */
160 * CCP supported DES types
163 CCP_DES_TYPE_128 = 0, /* 112 + 16 parity */
164 CCP_DES_TYPE_192, /* 168 + 24 parity */
168 /***** SHA engine *****/
171 * ccp_sha_type - type of SHA operation
173 * @CCP_SHA_TYPE_1: SHA-1 operation
174 * @CCP_SHA_TYPE_224: SHA-224 operation
175 * @CCP_SHA_TYPE_256: SHA-256 operation
193 * CCP supported cipher algorithms
195 enum ccp_cipher_algo {
196 CCP_CIPHER_ALGO_AES_CBC = 0,
197 CCP_CIPHER_ALGO_AES_ECB,
198 CCP_CIPHER_ALGO_AES_CTR,
199 CCP_CIPHER_ALGO_AES_GCM,
200 CCP_CIPHER_ALGO_3DES_CBC,
204 * CCP cipher operation type
206 enum ccp_cipher_dir {
207 CCP_CIPHER_DIR_DECRYPT = 0,
208 CCP_CIPHER_DIR_ENCRYPT = 1,
212 * CCP supported hash algorithms
215 CCP_AUTH_ALGO_SHA1 = 0,
216 CCP_AUTH_ALGO_SHA1_HMAC,
217 CCP_AUTH_ALGO_SHA224,
218 CCP_AUTH_ALGO_SHA224_HMAC,
219 CCP_AUTH_ALGO_SHA3_224,
220 CCP_AUTH_ALGO_SHA3_224_HMAC,
221 CCP_AUTH_ALGO_SHA256,
222 CCP_AUTH_ALGO_SHA256_HMAC,
223 CCP_AUTH_ALGO_SHA3_256,
224 CCP_AUTH_ALGO_SHA3_256_HMAC,
225 CCP_AUTH_ALGO_SHA384,
226 CCP_AUTH_ALGO_SHA384_HMAC,
227 CCP_AUTH_ALGO_SHA3_384,
228 CCP_AUTH_ALGO_SHA3_384_HMAC,
229 CCP_AUTH_ALGO_SHA512,
230 CCP_AUTH_ALGO_SHA512_HMAC,
231 CCP_AUTH_ALGO_SHA3_512,
232 CCP_AUTH_ALGO_SHA3_512_HMAC,
233 CCP_AUTH_ALGO_AES_CMAC,
234 CCP_AUTH_ALGO_AES_GCM,
235 #ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH
236 CCP_AUTH_ALGO_MD5_HMAC,
241 * CCP hash operation type
244 CCP_AUTH_OP_GENERATE = 0,
245 CCP_AUTH_OP_VERIFY = 1,
248 /* CCP crypto private session structure */
250 enum ccp_cmd_order cmd_id;
251 /**< chain order mode */
256 /**< IV parameters */
258 enum ccp_cipher_algo algo;
259 enum ccp_engine engine;
261 enum ccp_aes_mode aes_mode;
262 enum ccp_des_mode des_mode;
265 enum ccp_aes_type aes_type;
266 enum ccp_des_type des_type;
268 enum ccp_cipher_dir dir;
270 /**< max cipher key size 256 bits */
274 phys_addr_t key_phys;
275 /**AES-ctr nonce(4) iv(8) ctr*/
277 phys_addr_t nonce_phys;
279 /**< Cipher Parameters */
282 enum ccp_hash_algo algo;
283 enum ccp_engine engine;
285 enum ccp_aes_mode aes_mode;
288 enum ccp_sha_type sha_type;
289 enum ccp_aes_type aes_type;
293 /**< max hash key size 144 bytes (struct capabilties) */
295 /**< max be key size of AES is 32*/
297 phys_addr_t key_phys;
298 uint64_t digest_length;
303 /**< Buffer to store Software generated precomute values*/
304 /**< For HMAC H(ipad ^ key) and H(opad ^ key) */
305 /**< For CMAC K1 IV and K2 IV*/
306 uint8_t pre_compute[2 * CCP_SHA3_CTX_SIZE];
307 /**< SHA3 initial ctx all zeros*/
308 uint8_t sha3_ctx[200];
311 /**< Authentication Parameters */
312 enum rte_crypto_aead_algorithm aead_algo;
313 /**< AEAD Algorithm */
316 } __rte_cache_aligned;
318 extern uint8_t ccp_cryptodev_driver_id;
323 * Set and validate CCP crypto session parameters
325 * @param sess ccp private session
326 * @param xform crypto xform for this session
327 * @return 0 on success otherwise -1
329 int ccp_set_session_parameters(struct ccp_session *sess,
330 const struct rte_crypto_sym_xform *xform);
333 * Find count of slots
335 * @param session CCP private session
336 * @return count of free slots available
338 int ccp_compute_slot_count(struct ccp_session *session);
341 * process crypto ops to be enqueued
343 * @param qp CCP crypto queue-pair
344 * @param op crypto ops table
345 * @param cmd_q CCP cmd queue
346 * @param nb_ops No. of ops to be submitted
347 * @return 0 on success otherwise -1
349 int process_ops_to_enqueue(const struct ccp_qp *qp,
350 struct rte_crypto_op **op,
351 struct ccp_queue *cmd_q,
356 * process crypto ops to be dequeued
358 * @param qp CCP crypto queue-pair
359 * @param op crypto ops table
360 * @param nb_ops requested no. of ops
361 * @return 0 on success otherwise -1
363 int process_ops_to_dequeue(struct ccp_qp *qp,
364 struct rte_crypto_op **op,
369 * Apis for SHA3 partial hash generation
370 * @param data_in buffer pointer on which phash is applied
371 * @param data_out phash result in ccp be format is written
373 int partial_hash_sha3_224(uint8_t *data_in,
376 int partial_hash_sha3_256(uint8_t *data_in,
379 int partial_hash_sha3_384(uint8_t *data_in,
382 int partial_hash_sha3_512(uint8_t *data_in,
385 #endif /* _CCP_CRYPTO_H_ */