1 /* Copyright 2013-2016 Freescale Semiconductor Inc.
2 * Copyright (c) 2016 NXP.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution.
11 * * Neither the name of the above-listed copyright holders nor the
12 * names of any contributors may be used to endorse or promote products
13 * derived from this software without specific prior written permission.
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _FSL_DPSECI_CMD_H
35 #define _FSL_DPSECI_CMD_H
38 #define DPSECI_VER_MAJOR 5
39 #define DPSECI_VER_MINOR 0
42 #define DPSECI_CMDID_CLOSE ((0x800 << 4) | (0x1))
43 #define DPSECI_CMDID_OPEN ((0x809 << 4) | (0x1))
44 #define DPSECI_CMDID_CREATE ((0x909 << 4) | (0x1))
45 #define DPSECI_CMDID_DESTROY ((0x989 << 4) | (0x1))
46 #define DPSECI_CMDID_GET_API_VERSION ((0xa09 << 4) | (0x1))
48 #define DPSECI_CMDID_ENABLE ((0x002 << 4) | (0x1))
49 #define DPSECI_CMDID_DISABLE ((0x003 << 4) | (0x1))
50 #define DPSECI_CMDID_GET_ATTR ((0x004 << 4) | (0x1))
51 #define DPSECI_CMDID_RESET ((0x005 << 4) | (0x1))
52 #define DPSECI_CMDID_IS_ENABLED ((0x006 << 4) | (0x1))
54 #define DPSECI_CMDID_SET_IRQ ((0x010 << 4) | (0x1))
55 #define DPSECI_CMDID_GET_IRQ ((0x011 << 4) | (0x1))
56 #define DPSECI_CMDID_SET_IRQ_ENABLE ((0x012 << 4) | (0x1))
57 #define DPSECI_CMDID_GET_IRQ_ENABLE ((0x013 << 4) | (0x1))
58 #define DPSECI_CMDID_SET_IRQ_MASK ((0x014 << 4) | (0x1))
59 #define DPSECI_CMDID_GET_IRQ_MASK ((0x015 << 4) | (0x1))
60 #define DPSECI_CMDID_GET_IRQ_STATUS ((0x016 << 4) | (0x1))
61 #define DPSECI_CMDID_CLEAR_IRQ_STATUS ((0x017 << 4) | (0x1))
63 #define DPSECI_CMDID_SET_RX_QUEUE ((0x194 << 4) | (0x1))
64 #define DPSECI_CMDID_GET_RX_QUEUE ((0x196 << 4) | (0x1))
65 #define DPSECI_CMDID_GET_TX_QUEUE ((0x197 << 4) | (0x1))
66 #define DPSECI_CMDID_GET_SEC_ATTR ((0x198 << 4) | (0x1))
67 #define DPSECI_CMDID_GET_SEC_COUNTERS ((0x199 << 4) | (0x1))
69 /* cmd, param, offset, width, type, arg_name */
70 #define DPSECI_CMD_OPEN(cmd, dpseci_id) \
71 MC_CMD_OP(cmd, 0, 0, 32, int, dpseci_id)
73 /* cmd, param, offset, width, type, arg_name */
74 #define DPSECI_CMD_CREATE(cmd, cfg) \
76 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->priorities[0]);\
77 MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->priorities[1]);\
78 MC_CMD_OP(cmd, 0, 16, 8, uint8_t, cfg->priorities[2]);\
79 MC_CMD_OP(cmd, 0, 24, 8, uint8_t, cfg->priorities[3]);\
80 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->priorities[4]);\
81 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->priorities[5]);\
82 MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->priorities[6]);\
83 MC_CMD_OP(cmd, 0, 56, 8, uint8_t, cfg->priorities[7]);\
84 MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->num_tx_queues);\
85 MC_CMD_OP(cmd, 1, 8, 8, uint8_t, cfg->num_rx_queues);\
88 /* cmd, param, offset, width, type, arg_name */
89 #define DPSECI_RSP_IS_ENABLED(cmd, en) \
90 MC_RSP_OP(cmd, 0, 0, 1, int, en)
92 /* cmd, param, offset, width, type, arg_name */
93 #define DPSECI_CMD_SET_IRQ(cmd, irq_index, irq_cfg) \
95 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, irq_index);\
96 MC_CMD_OP(cmd, 0, 32, 32, uint32_t, irq_cfg->val);\
97 MC_CMD_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
98 MC_CMD_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
101 /* cmd, param, offset, width, type, arg_name */
102 #define DPSECI_CMD_GET_IRQ(cmd, irq_index) \
103 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
105 /* cmd, param, offset, width, type, arg_name */
106 #define DPSECI_RSP_GET_IRQ(cmd, type, irq_cfg) \
108 MC_RSP_OP(cmd, 0, 0, 32, uint32_t, irq_cfg->val); \
109 MC_RSP_OP(cmd, 1, 0, 64, uint64_t, irq_cfg->addr);\
110 MC_RSP_OP(cmd, 2, 0, 32, int, irq_cfg->irq_num); \
111 MC_RSP_OP(cmd, 2, 32, 32, int, type); \
114 /* cmd, param, offset, width, type, arg_name */
115 #define DPSECI_CMD_SET_IRQ_ENABLE(cmd, irq_index, enable_state) \
117 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, enable_state); \
118 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
121 /* cmd, param, offset, width, type, arg_name */
122 #define DPSECI_CMD_GET_IRQ_ENABLE(cmd, irq_index) \
123 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
125 /* cmd, param, offset, width, type, arg_name */
126 #define DPSECI_RSP_GET_IRQ_ENABLE(cmd, enable_state) \
127 MC_RSP_OP(cmd, 0, 0, 8, uint8_t, enable_state)
129 /* cmd, param, offset, width, type, arg_name */
130 #define DPSECI_CMD_SET_IRQ_MASK(cmd, irq_index, mask) \
132 MC_CMD_OP(cmd, 0, 0, 32, uint32_t, mask); \
133 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
136 /* cmd, param, offset, width, type, arg_name */
137 #define DPSECI_CMD_GET_IRQ_MASK(cmd, irq_index) \
138 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index)
140 /* cmd, param, offset, width, type, arg_name */
141 #define DPSECI_RSP_GET_IRQ_MASK(cmd, mask) \
142 MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mask)
144 /* cmd, param, offset, width, type, arg_name */
145 #define DPSECI_CMD_GET_IRQ_STATUS(cmd, irq_index, status) \
147 MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status);\
148 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index);\
151 /* cmd, param, offset, width, type, arg_name */
152 #define DPSECI_RSP_GET_IRQ_STATUS(cmd, status) \
153 MC_RSP_OP(cmd, 0, 0, 32, uint32_t, status)
155 /* cmd, param, offset, width, type, arg_name */
156 #define DPSECI_CMD_CLEAR_IRQ_STATUS(cmd, irq_index, status) \
158 MC_CMD_OP(cmd, 0, 0, 32, uint32_t, status); \
159 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, irq_index); \
162 /* cmd, param, offset, width, type, arg_name */
163 #define DPSECI_RSP_GET_ATTR(cmd, attr) \
165 MC_RSP_OP(cmd, 0, 0, 32, int, attr->id); \
166 MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->num_tx_queues); \
167 MC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->num_rx_queues); \
170 /* cmd, param, offset, width, type, arg_name */
171 #define DPSECI_CMD_SET_RX_QUEUE(cmd, queue, cfg) \
173 MC_CMD_OP(cmd, 0, 0, 32, int, cfg->dest_cfg.dest_id); \
174 MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->dest_cfg.priority); \
175 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue); \
176 MC_CMD_OP(cmd, 0, 48, 4, enum dpseci_dest, cfg->dest_cfg.dest_type); \
177 MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \
178 MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\
179 MC_CMD_OP(cmd, 2, 32, 1, int, cfg->order_preservation_en);\
182 /* cmd, param, offset, width, type, arg_name */
183 #define DPSECI_CMD_GET_RX_QUEUE(cmd, queue) \
184 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)
186 /* cmd, param, offset, width, type, arg_name */
187 #define DPSECI_RSP_GET_RX_QUEUE(cmd, attr) \
189 MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id);\
190 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\
191 MC_RSP_OP(cmd, 0, 48, 4, enum dpseci_dest, attr->dest_cfg.dest_type);\
192 MC_RSP_OP(cmd, 1, 0, 8, uint64_t, attr->user_ctx);\
193 MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->fqid);\
194 MC_RSP_OP(cmd, 2, 32, 1, int, attr->order_preservation_en);\
197 /* cmd, param, offset, width, type, arg_name */
198 #define DPSECI_CMD_GET_TX_QUEUE(cmd, queue) \
199 MC_CMD_OP(cmd, 0, 40, 8, uint8_t, queue)
201 /* cmd, param, offset, width, type, arg_name */
202 #define DPSECI_RSP_GET_TX_QUEUE(cmd, attr) \
204 MC_RSP_OP(cmd, 0, 32, 32, uint32_t, attr->fqid);\
205 MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->priority);\
208 /* cmd, param, offset, width, type, arg_name */
209 #define DPSECI_RSP_GET_SEC_ATTR(cmd, attr) \
211 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, attr->ip_id);\
212 MC_RSP_OP(cmd, 0, 16, 8, uint8_t, attr->major_rev);\
213 MC_RSP_OP(cmd, 0, 24, 8, uint8_t, attr->minor_rev);\
214 MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->era);\
215 MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->deco_num);\
216 MC_RSP_OP(cmd, 1, 8, 8, uint8_t, attr->zuc_auth_acc_num);\
217 MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->zuc_enc_acc_num);\
218 MC_RSP_OP(cmd, 1, 32, 8, uint8_t, attr->snow_f8_acc_num);\
219 MC_RSP_OP(cmd, 1, 40, 8, uint8_t, attr->snow_f9_acc_num);\
220 MC_RSP_OP(cmd, 1, 48, 8, uint8_t, attr->crc_acc_num);\
221 MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->pk_acc_num);\
222 MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->kasumi_acc_num);\
223 MC_RSP_OP(cmd, 2, 16, 8, uint8_t, attr->rng_acc_num);\
224 MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->md_acc_num);\
225 MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->arc4_acc_num);\
226 MC_RSP_OP(cmd, 2, 48, 8, uint8_t, attr->des_acc_num);\
227 MC_RSP_OP(cmd, 2, 56, 8, uint8_t, attr->aes_acc_num);\
230 /* cmd, param, offset, width, type, arg_name */
231 #define DPSECI_RSP_GET_SEC_COUNTERS(cmd, counters) \
233 MC_RSP_OP(cmd, 0, 0, 64, uint64_t, counters->dequeued_requests);\
234 MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counters->ob_enc_requests);\
235 MC_RSP_OP(cmd, 2, 0, 64, uint64_t, counters->ib_dec_requests);\
236 MC_RSP_OP(cmd, 3, 0, 64, uint64_t, counters->ob_enc_bytes);\
237 MC_RSP_OP(cmd, 4, 0, 64, uint64_t, counters->ob_prot_bytes);\
238 MC_RSP_OP(cmd, 5, 0, 64, uint64_t, counters->ib_dec_bytes);\
239 MC_RSP_OP(cmd, 6, 0, 64, uint64_t, counters->ib_valid_bytes);\
242 /* cmd, param, offset, width, type, arg_name */
243 #define DPSECI_RSP_GET_API_VERSION(cmd, major, minor) \
245 MC_RSP_OP(cmd, 0, 0, 16, uint16_t, major);\
246 MC_RSP_OP(cmd, 0, 16, 16, uint16_t, minor);\
249 #endif /* _FSL_DPSECI_CMD_H */