1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2021 NVIDIA Corporation & Affiliates
10 #include <rte_cryptodev.h>
11 #include <rte_cryptodev_pmd.h>
13 #include <mlx5_common_utils.h>
14 #include <mlx5_common_devx.h>
15 #include <mlx5_common_mr.h>
17 #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)
18 #define MLX5_CRYPTO_KEY_LENGTH 80
19 #define MLX5_CRYPTO_WQE_SET_SIZE 1024
21 struct mlx5_crypto_priv {
22 TAILQ_ENTRY(mlx5_crypto_priv) next;
23 struct ibv_context *ctx; /* Device context. */
24 struct rte_pci_device *pci_dev;
25 struct rte_cryptodev *crypto_dev;
26 void *uar; /* User Access Region. */
27 uint32_t pdn; /* Protection Domain number. */
29 struct mlx5_hlist *dek_hlist; /* Dek hash list. */
30 struct rte_cryptodev_config dev_config;
31 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
32 struct mlx5_devx_obj *login_obj;
35 struct mlx5_crypto_qp {
36 struct mlx5_devx_cq cq_obj;
37 struct mlx5_devx_obj *qp_obj;
38 struct mlx5dv_devx_umem *umem_obj;
40 volatile uint32_t *db_rec;
41 struct rte_crypto_op **ops;
42 struct mlx5_mr_ctrl mr_ctrl;
45 struct mlx5_crypto_dek {
46 struct mlx5_list_entry entry; /* Pointer to DEK hash list entry. */
47 struct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */
48 uint8_t data[MLX5_CRYPTO_KEY_LENGTH]; /* DEK key data. */
49 bool size_is_48; /* Whether the key\data size is 48 bytes or not. */
50 } __rte_cache_aligned;
53 struct mlx5_crypto_devarg_params {
55 struct mlx5_devx_crypto_login_attr login_attr;
59 mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,
60 struct mlx5_crypto_dek *dek);
62 struct mlx5_crypto_dek *
63 mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,
64 struct rte_crypto_cipher_xform *cipher);
67 mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);
70 mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv);
72 #endif /* MLX5_CRYPTO_H_ */