1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
11 #include "otx2_cryptodev.h"
12 #include "otx2_cryptodev_capabilities.h"
13 #include "otx2_cryptodev_hw_access.h"
14 #include "otx2_cryptodev_mbox.h"
15 #include "otx2_cryptodev_ops.h"
16 #include "otx2_mbox.h"
17 #include "otx2_sec_idev.h"
19 #include "cpt_hw_types.h"
20 #include "cpt_pmd_logs.h"
21 #include "cpt_pmd_ops_helper.h"
22 #include "cpt_ucode.h"
23 #include "cpt_ucode_asym.h"
25 #define METABUF_POOL_CACHE_SIZE 512
27 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
29 /* Forward declarations */
32 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
35 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
37 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
41 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
42 struct otx2_cpt_qp *qp, uint8_t qp_id,
45 char mempool_name[RTE_MEMPOOL_NAMESIZE];
46 struct cpt_qp_meta_info *meta_info;
47 struct rte_mempool *pool;
53 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
55 /* Get meta len for scatter gather mode */
56 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
58 /* Extra 32B saved for future considerations */
59 sg_mlen += 4 * sizeof(uint64_t);
61 /* Get meta len for linear buffer (direct) mode */
62 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
64 /* Extra 32B saved for future considerations */
65 lb_mlen += 4 * sizeof(uint64_t);
68 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
70 /* Get meta len required for asymmetric operations */
71 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
75 * Check max requirement for meta buffer to
76 * support crypto op of any type (sym/asym).
78 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
80 /* Allocate mempool */
82 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
83 dev->data->dev_id, qp_id);
85 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
86 METABUF_POOL_CACHE_SIZE, 0,
90 CPT_LOG_ERR("Could not create mempool for metabuf");
94 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
97 CPT_LOG_ERR("Could not set mempool ops");
101 ret = rte_mempool_populate_default(pool);
103 CPT_LOG_ERR("Could not populate metabuf pool");
107 meta_info = &qp->meta_info;
109 meta_info->pool = pool;
110 meta_info->lb_mlen = lb_mlen;
111 meta_info->sg_mlen = sg_mlen;
116 rte_mempool_free(pool);
121 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
123 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
125 rte_mempool_free(meta_info->pool);
127 meta_info->pool = NULL;
128 meta_info->lb_mlen = 0;
129 meta_info->sg_mlen = 0;
133 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
135 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
136 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
139 for (i = 0; i < nb_ethport; i++) {
140 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
141 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
148 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
152 /* Publish inline Tx QP to eth dev security */
153 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
160 static struct otx2_cpt_qp *
161 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
164 struct otx2_cpt_vf *vf = dev->data->dev_private;
165 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
166 const struct rte_memzone *lf_mem;
167 uint32_t len, iq_len, size_div40;
168 char name[RTE_MEMZONE_NAMESIZE];
169 uint64_t used_len, iova;
170 struct otx2_cpt_qp *qp;
175 /* Allocate queue pair */
176 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
179 CPT_LOG_ERR("Could not allocate queue pair");
183 iq_len = OTX2_CPT_IQ_LEN;
186 * Queue size must be a multiple of 40 and effective queue size to
187 * software is (size_div40 - 1) * 40
189 size_div40 = (iq_len + 40 - 1) / 40 + 1;
191 /* For pending queue */
192 len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
194 /* Space for instruction group memory */
195 len += size_div40 * 16;
197 /* So that instruction queues start as pg size aligned */
198 len = RTE_ALIGN(len, pg_sz);
200 /* For instruction queues */
201 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
203 /* Wastage after instruction queues */
204 len = RTE_ALIGN(len, pg_sz);
206 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
209 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
210 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
211 RTE_CACHE_LINE_SIZE);
212 if (lf_mem == NULL) {
213 CPT_LOG_ERR("Could not allocate reserved memzone");
222 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
224 CPT_LOG_ERR("Could not create mempool for metabuf");
228 /* Initialize pending queue */
229 qp->pend_q.rid_queue = (struct rid *)va;
230 qp->pend_q.enq_tail = 0;
231 qp->pend_q.deq_head = 0;
232 qp->pend_q.pending_count = 0;
234 used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
235 used_len += size_div40 * 16;
236 used_len = RTE_ALIGN(used_len, pg_sz);
239 qp->iq_dma_addr = iova;
241 qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
243 lmtline = vf->otx2_dev.bar2 +
244 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
245 OTX2_LMT_LF_LMTLINE(0);
247 qp->lmtline = (void *)lmtline;
249 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
251 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
252 if (ret && (ret != -ENOENT)) {
253 CPT_LOG_ERR("Could not delete inline configuration");
254 goto mempool_destroy;
257 otx2_cpt_iq_disable(qp);
259 ret = otx2_cpt_qp_inline_cfg(dev, qp);
261 CPT_LOG_ERR("Could not configure queue for inline IPsec");
262 goto mempool_destroy;
265 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
268 CPT_LOG_ERR("Could not enable instruction queue");
269 goto mempool_destroy;
275 otx2_cpt_metabuf_mempool_destroy(qp);
277 rte_memzone_free(lf_mem);
284 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
286 const struct rte_memzone *lf_mem;
287 char name[RTE_MEMZONE_NAMESIZE];
290 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
291 if (ret && (ret != -ENOENT)) {
292 CPT_LOG_ERR("Could not delete inline configuration");
296 otx2_cpt_iq_disable(qp);
298 otx2_cpt_metabuf_mempool_destroy(qp);
300 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
303 lf_mem = rte_memzone_lookup(name);
305 ret = rte_memzone_free(lf_mem);
315 sym_xform_verify(struct rte_crypto_sym_xform *xform)
318 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
319 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
320 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
323 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
324 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
325 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
328 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
329 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
330 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
331 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
334 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
335 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
336 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
337 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
341 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
342 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
343 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
350 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
351 struct rte_cryptodev_sym_session *sess,
352 struct rte_mempool *pool)
354 struct cpt_sess_misc *misc;
358 ret = sym_xform_verify(xform);
362 if (unlikely(rte_mempool_get(pool, &priv))) {
363 CPT_LOG_ERR("Could not allocate session private data");
367 memset(priv, 0, sizeof(struct cpt_sess_misc) +
368 offsetof(struct cpt_ctx, fctx));
372 for ( ; xform != NULL; xform = xform->next) {
373 switch (xform->type) {
374 case RTE_CRYPTO_SYM_XFORM_AEAD:
375 ret = fill_sess_aead(xform, misc);
377 case RTE_CRYPTO_SYM_XFORM_CIPHER:
378 ret = fill_sess_cipher(xform, misc);
380 case RTE_CRYPTO_SYM_XFORM_AUTH:
381 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
382 ret = fill_sess_gmac(xform, misc);
384 ret = fill_sess_auth(xform, misc);
394 set_sym_session_private_data(sess, driver_id, misc);
396 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
397 sizeof(struct cpt_sess_misc);
400 * IE engines support IPsec operations
401 * SE engines support IPsec operations and Air-Crypto operations
404 misc->egrp = OTX2_CPT_EGRP_SE;
406 misc->egrp = OTX2_CPT_EGRP_SE_IE;
411 rte_mempool_put(pool, priv);
417 sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
419 void *priv = get_sym_session_private_data(sess, driver_id);
420 struct rte_mempool *pool;
425 memset(priv, 0, cpt_get_session_size());
427 pool = rte_mempool_from_obj(priv);
429 set_sym_session_private_data(sess, driver_id, NULL);
431 rte_mempool_put(pool, priv);
434 static __rte_always_inline int32_t __rte_hot
435 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
436 struct pending_queue *pend_q,
437 struct cpt_request_info *req)
439 void *lmtline = qp->lmtline;
440 union cpt_inst_s inst;
443 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
447 inst.s9x.res_addr = req->comp_baddr;
451 inst.s9x.ei0 = req->ist.ei0;
452 inst.s9x.ei1 = req->ist.ei1;
453 inst.s9x.ei2 = req->ist.ei2;
454 inst.s9x.ei3 = req->ist.ei3;
456 req->time_out = rte_get_timer_cycles() +
457 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
460 /* Copy CPT command to LMTLINE */
461 memcpy(lmtline, &inst, sizeof(inst));
464 * Make sure compiler does not reorder memcpy and ldeor.
465 * LMTST transactions are always flushed from the write
466 * buffer immediately, a DMB is not required to push out
470 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
471 } while (lmt_status == 0);
473 pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
475 /* We will use soft queue length here to limit requests */
476 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
477 pend_q->pending_count += 1;
482 static __rte_always_inline int32_t __rte_hot
483 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
484 struct rte_crypto_op *op,
485 struct pending_queue *pend_q)
487 struct cpt_qp_meta_info *minfo = &qp->meta_info;
488 struct rte_crypto_asym_op *asym_op = op->asym;
489 struct asym_op_params params = {0};
490 struct cpt_asym_sess_misc *sess;
496 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
497 CPT_LOG_ERR("Could not allocate meta buffer for request");
501 sess = get_asym_session_private_data(asym_op->session,
502 otx2_cryptodev_driver_id);
504 /* Store IO address of the mdata to meta_buf */
505 params.meta_buf = rte_mempool_virt2iova(mdata);
508 cop[0] = (uintptr_t)mdata;
509 cop[1] = (uintptr_t)op;
510 cop[2] = cop[3] = 0ULL;
512 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
513 params.req->op = cop;
515 /* Adjust meta_buf to point to end of cpt_request_info structure */
516 params.meta_buf += (4 * sizeof(uintptr_t)) +
517 sizeof(struct cpt_request_info);
518 switch (sess->xfrm_type) {
519 case RTE_CRYPTO_ASYM_XFORM_MODEX:
520 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
524 case RTE_CRYPTO_ASYM_XFORM_RSA:
525 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
529 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
530 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
534 case RTE_CRYPTO_ASYM_XFORM_ECPM:
535 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
536 sess->ec_ctx.curveid);
541 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
546 /* Set engine group of AE */
547 w3 = (vq_cmd_word3_t *)¶ms.req->ist.ei3;
548 w3->s.grp = OTX2_CPT_EGRP_AE;
550 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req);
553 CPT_LOG_DP_ERR("Could not enqueue crypto req");
560 free_op_meta(mdata, minfo->pool);
565 static __rte_always_inline int __rte_hot
566 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
567 struct pending_queue *pend_q)
569 struct rte_crypto_sym_op *sym_op = op->sym;
570 struct cpt_request_info *req;
571 struct cpt_sess_misc *sess;
577 sess = get_sym_session_private_data(sym_op->session,
578 otx2_cryptodev_driver_id);
580 cpt_op = sess->cpt_op;
582 if (cpt_op & CPT_OP_CIPHER_MASK)
583 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
586 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
590 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
591 op, (unsigned int)cpt_op, ret);
595 w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
596 w3->s.grp = sess->egrp;
598 ret = otx2_cpt_enqueue_req(qp, pend_q, req);
601 /* Free buffer allocated by fill params routines */
602 free_op_meta(mdata, qp->meta_info.pool);
608 static __rte_always_inline int __rte_hot
609 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
610 struct pending_queue *pend_q)
612 const int driver_id = otx2_cryptodev_driver_id;
613 struct rte_crypto_sym_op *sym_op = op->sym;
614 struct rte_cryptodev_sym_session *sess;
617 /* Create temporary session */
619 if (rte_mempool_get(qp->sess_mp, (void **)&sess))
622 ret = sym_session_configure(driver_id, sym_op->xform, sess,
627 sym_op->session = sess;
629 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
637 sym_session_clear(driver_id, sess);
639 rte_mempool_put(qp->sess_mp, sess);
644 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
646 uint16_t nb_allowed, count = 0;
647 struct otx2_cpt_qp *qp = qptr;
648 struct pending_queue *pend_q;
649 struct rte_crypto_op *op;
652 pend_q = &qp->pend_q;
654 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
655 if (nb_ops > nb_allowed)
658 for (count = 0; count < nb_ops; count++) {
660 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
661 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
662 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
664 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
666 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
667 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
668 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
681 static __rte_always_inline void
682 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
683 struct rte_crypto_rsa_xform *rsa_ctx)
685 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
687 switch (rsa->op_type) {
688 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
689 rsa->cipher.length = rsa_ctx->n.length;
690 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
692 case RTE_CRYPTO_ASYM_OP_DECRYPT:
693 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
694 rsa->message.length = rsa_ctx->n.length;
695 memcpy(rsa->message.data, req->rptr,
696 rsa->message.length);
698 /* Get length of decrypted output */
699 rsa->message.length = rte_cpu_to_be_16
700 (*((uint16_t *)req->rptr));
702 * Offset output data pointer by length field
703 * (2 bytes) and copy decrypted data.
705 memcpy(rsa->message.data, req->rptr + 2,
706 rsa->message.length);
709 case RTE_CRYPTO_ASYM_OP_SIGN:
710 rsa->sign.length = rsa_ctx->n.length;
711 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
713 case RTE_CRYPTO_ASYM_OP_VERIFY:
714 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
715 rsa->sign.length = rsa_ctx->n.length;
716 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
718 /* Get length of signed output */
719 rsa->sign.length = rte_cpu_to_be_16
720 (*((uint16_t *)req->rptr));
722 * Offset output data pointer by length field
723 * (2 bytes) and copy signed data.
725 memcpy(rsa->sign.data, req->rptr + 2,
728 if (memcmp(rsa->sign.data, rsa->message.data,
729 rsa->message.length)) {
730 CPT_LOG_DP_ERR("RSA verification failed");
731 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
735 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
736 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
741 static __rte_always_inline void
742 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
743 struct cpt_request_info *req,
744 struct cpt_asym_ec_ctx *ec)
746 int prime_len = ec_grp[ec->curveid].prime.length;
748 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
751 /* Separate out sign r and s components */
752 memcpy(ecdsa->r.data, req->rptr, prime_len);
753 memcpy(ecdsa->s.data, req->rptr + ROUNDUP8(prime_len), prime_len);
754 ecdsa->r.length = prime_len;
755 ecdsa->s.length = prime_len;
758 static __rte_always_inline void
759 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
760 struct cpt_request_info *req,
761 struct cpt_asym_ec_ctx *ec)
763 int prime_len = ec_grp[ec->curveid].prime.length;
765 memcpy(ecpm->r.x.data, req->rptr, prime_len);
766 memcpy(ecpm->r.y.data, req->rptr + ROUNDUP8(prime_len), prime_len);
767 ecpm->r.x.length = prime_len;
768 ecpm->r.y.length = prime_len;
772 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
773 struct cpt_request_info *req)
775 struct rte_crypto_asym_op *op = cop->asym;
776 struct cpt_asym_sess_misc *sess;
778 sess = get_asym_session_private_data(op->session,
779 otx2_cryptodev_driver_id);
781 switch (sess->xfrm_type) {
782 case RTE_CRYPTO_ASYM_XFORM_RSA:
783 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
785 case RTE_CRYPTO_ASYM_XFORM_MODEX:
786 op->modex.result.length = sess->mod_ctx.modulus.length;
787 memcpy(op->modex.result.data, req->rptr,
788 op->modex.result.length);
790 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
791 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
793 case RTE_CRYPTO_ASYM_XFORM_ECPM:
794 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
797 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
798 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
804 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
805 uintptr_t *rsp, uint8_t cc)
807 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
808 if (likely(cc == NO_ERR)) {
809 /* Verify authentication data if required */
810 if (unlikely(rsp[2]))
811 compl_auth_verify(cop, (uint8_t *)rsp[2],
814 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
816 if (cc == ERR_GC_ICV_MISCOMPARE)
817 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
819 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
822 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
823 sym_session_clear(otx2_cryptodev_driver_id,
825 rte_mempool_put(qp->sess_mp, cop->sym->session);
826 cop->sym->session = NULL;
830 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
831 if (likely(cc == NO_ERR)) {
832 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
834 * Pass cpt_req_info stored in metabuf during
837 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
838 otx2_cpt_asym_post_process(cop,
839 (struct cpt_request_info *)rsp);
841 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
845 static __rte_always_inline uint8_t
846 otx2_cpt_compcode_get(struct cpt_request_info *req)
848 volatile struct cpt_res_s_9s *res;
851 res = (volatile struct cpt_res_s_9s *)req->completion_addr;
853 if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
854 if (rte_get_timer_cycles() < req->time_out)
855 return ERR_REQ_PENDING;
857 CPT_LOG_DP_ERR("Request timed out");
858 return ERR_REQ_TIMEOUT;
861 if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
863 if (unlikely(res->uc_compcode)) {
864 ret = res->uc_compcode;
865 CPT_LOG_DP_DEBUG("Request failed with microcode error");
866 CPT_LOG_DP_DEBUG("MC completion code 0x%x",
870 CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
873 switch (res->compcode) {
874 case CPT_9X_COMP_E_INSTERR:
875 CPT_LOG_DP_ERR("Request failed with instruction error");
877 case CPT_9X_COMP_E_FAULT:
878 CPT_LOG_DP_ERR("Request failed with DMA fault");
880 case CPT_9X_COMP_E_HWERR:
881 CPT_LOG_DP_ERR("Request failed with hardware error");
884 CPT_LOG_DP_ERR("Request failed with unknown completion code");
892 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
894 int i, nb_pending, nb_completed;
895 struct otx2_cpt_qp *qp = qptr;
896 struct pending_queue *pend_q;
897 struct cpt_request_info *req;
898 struct rte_crypto_op *cop;
904 pend_q = &qp->pend_q;
906 nb_pending = pend_q->pending_count;
908 if (nb_ops > nb_pending)
911 for (i = 0; i < nb_ops; i++) {
912 rid = &pend_q->rid_queue[pend_q->deq_head];
913 req = (struct cpt_request_info *)(rid->rid);
915 cc[i] = otx2_cpt_compcode_get(req);
917 if (unlikely(cc[i] == ERR_REQ_PENDING))
922 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
923 pend_q->pending_count -= 1;
928 for (i = 0; i < nb_completed; i++) {
929 rsp = (void *)ops[i];
931 metabuf = (void *)rsp[0];
932 cop = (void *)rsp[1];
936 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
938 free_op_meta(metabuf, qp->meta_info.pool);
947 otx2_cpt_dev_config(struct rte_cryptodev *dev,
948 struct rte_cryptodev_config *conf)
950 struct otx2_cpt_vf *vf = dev->data->dev_private;
953 if (conf->nb_queue_pairs > vf->max_queues) {
954 CPT_LOG_ERR("Invalid number of queue pairs requested");
958 dev->feature_flags &= ~conf->ff_disable;
960 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
961 /* Initialize shared FPM table */
962 ret = cpt_fpm_init(otx2_fpm_iova);
967 /* Unregister error interrupts */
968 if (vf->err_intr_registered)
969 otx2_cpt_err_intr_unregister(dev);
973 ret = otx2_cpt_queues_detach(dev);
975 CPT_LOG_ERR("Could not detach CPT queues");
981 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
983 CPT_LOG_ERR("Could not attach CPT queues");
987 ret = otx2_cpt_msix_offsets_get(dev);
989 CPT_LOG_ERR("Could not get MSI-X offsets");
993 /* Register error interrupts */
994 ret = otx2_cpt_err_intr_register(dev);
996 CPT_LOG_ERR("Could not register error interrupts");
1000 ret = otx2_cpt_inline_init(dev);
1002 CPT_LOG_ERR("Could not enable inline IPsec");
1003 goto intr_unregister;
1006 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1007 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1013 otx2_cpt_err_intr_unregister(dev);
1015 otx2_cpt_queues_detach(dev);
1020 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1024 CPT_PMD_INIT_FUNC_TRACE();
1030 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1032 CPT_PMD_INIT_FUNC_TRACE();
1034 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1039 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1041 struct otx2_cpt_vf *vf = dev->data->dev_private;
1044 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1045 ret = otx2_cpt_queue_pair_release(dev, i);
1050 /* Unregister error interrupts */
1051 if (vf->err_intr_registered)
1052 otx2_cpt_err_intr_unregister(dev);
1055 if (vf->nb_queues) {
1056 ret = otx2_cpt_queues_detach(dev);
1058 CPT_LOG_ERR("Could not detach CPT queues");
1065 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1066 struct rte_cryptodev_info *info)
1068 struct otx2_cpt_vf *vf = dev->data->dev_private;
1071 info->max_nb_queue_pairs = vf->max_queues;
1072 info->feature_flags = dev->feature_flags;
1073 info->capabilities = otx2_cpt_capabilities_get(vf->hw_caps);
1074 info->sym.max_nb_sessions = 0;
1075 info->driver_id = otx2_cryptodev_driver_id;
1076 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1077 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1082 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1083 const struct rte_cryptodev_qp_conf *conf,
1084 int socket_id __rte_unused)
1086 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1087 struct rte_pci_device *pci_dev;
1088 struct otx2_cpt_qp *qp;
1090 CPT_PMD_INIT_FUNC_TRACE();
1092 if (dev->data->queue_pairs[qp_id] != NULL)
1093 otx2_cpt_queue_pair_release(dev, qp_id);
1095 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1096 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1097 conf->nb_descriptors);
1101 pci_dev = RTE_DEV_TO_PCI(dev->device);
1103 if (pci_dev->mem_resource[2].addr == NULL) {
1104 CPT_LOG_ERR("Invalid PCI mem address");
1108 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1110 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1114 qp->sess_mp = conf->mp_session;
1115 qp->sess_mp_priv = conf->mp_session_private;
1116 dev->data->queue_pairs[qp_id] = qp;
1122 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1124 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1127 CPT_PMD_INIT_FUNC_TRACE();
1132 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1134 ret = otx2_cpt_qp_destroy(dev, qp);
1136 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1140 dev->data->queue_pairs[qp_id] = NULL;
1146 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1148 return cpt_get_session_size();
1152 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1153 struct rte_crypto_sym_xform *xform,
1154 struct rte_cryptodev_sym_session *sess,
1155 struct rte_mempool *pool)
1157 CPT_PMD_INIT_FUNC_TRACE();
1159 return sym_session_configure(dev->driver_id, xform, sess, pool);
1163 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1164 struct rte_cryptodev_sym_session *sess)
1166 CPT_PMD_INIT_FUNC_TRACE();
1168 return sym_session_clear(dev->driver_id, sess);
1172 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1174 return sizeof(struct cpt_asym_sess_misc);
1178 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1179 struct rte_crypto_asym_xform *xform,
1180 struct rte_cryptodev_asym_session *sess,
1181 struct rte_mempool *pool)
1183 struct cpt_asym_sess_misc *priv;
1186 CPT_PMD_INIT_FUNC_TRACE();
1188 if (rte_mempool_get(pool, (void **)&priv)) {
1189 CPT_LOG_ERR("Could not allocate session_private_data");
1193 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1195 ret = cpt_fill_asym_session_parameters(priv, xform);
1197 CPT_LOG_ERR("Could not configure session parameters");
1199 /* Return session to mempool */
1200 rte_mempool_put(pool, priv);
1204 set_asym_session_private_data(sess, dev->driver_id, priv);
1209 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1210 struct rte_cryptodev_asym_session *sess)
1212 struct cpt_asym_sess_misc *priv;
1213 struct rte_mempool *sess_mp;
1215 CPT_PMD_INIT_FUNC_TRACE();
1217 priv = get_asym_session_private_data(sess, dev->driver_id);
1221 /* Free resources allocated in session_cfg */
1222 cpt_free_asym_session_parameters(priv);
1224 /* Reset and free object back to pool */
1225 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1226 sess_mp = rte_mempool_from_obj(priv);
1227 set_asym_session_private_data(sess, dev->driver_id, NULL);
1228 rte_mempool_put(sess_mp, priv);
1231 struct rte_cryptodev_ops otx2_cpt_ops = {
1232 /* Device control ops */
1233 .dev_configure = otx2_cpt_dev_config,
1234 .dev_start = otx2_cpt_dev_start,
1235 .dev_stop = otx2_cpt_dev_stop,
1236 .dev_close = otx2_cpt_dev_close,
1237 .dev_infos_get = otx2_cpt_dev_info_get,
1240 .stats_reset = NULL,
1241 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1242 .queue_pair_release = otx2_cpt_queue_pair_release,
1244 /* Symmetric crypto ops */
1245 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1246 .sym_session_configure = otx2_cpt_sym_session_configure,
1247 .sym_session_clear = otx2_cpt_sym_session_clear,
1249 /* Asymmetric crypto ops */
1250 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1251 .asym_session_configure = otx2_cpt_asym_session_cfg,
1252 .asym_session_clear = otx2_cpt_asym_session_clear,