4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <rte_cryptodev_pci.h>
64 #include <openssl/evp.h>
68 #include "qat_crypto.h"
69 #include "adf_transport_access_macros.h"
74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
75 struct qat_pmd_private *internals) {
77 const struct rte_cryptodev_capabilities *capability;
79 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
80 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
81 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
84 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
87 if (capability->sym.cipher.algo == algo)
94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
95 struct qat_pmd_private *internals) {
97 const struct rte_cryptodev_capabilities *capability;
99 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
100 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
101 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
104 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
107 if (capability->sym.auth.algo == algo)
113 /** Encrypt a single partial block
114 * Depends on openssl libcrypto
115 * Uses ECB+XOR to do CFB encryption, same result, more performant
118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
119 uint8_t *iv, int ivlen, int srclen,
122 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
124 uint8_t encrypted_iv[16];
127 /* ECB method: encrypt the IV, then XOR this with plaintext */
128 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
130 goto cipher_encrypt_err;
132 for (i = 0; i < srclen; i++)
133 *(dst+i) = *(src+i)^(encrypted_iv[i]);
138 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
142 /** Decrypt a single partial block
143 * Depends on openssl libcrypto
144 * Uses ECB+XOR to do CFB encryption, same result, more performant
147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
148 uint8_t *iv, int ivlen, int srclen,
151 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
153 uint8_t encrypted_iv[16];
156 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
157 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
159 goto cipher_decrypt_err;
161 for (i = 0; i < srclen; i++)
162 *(dst+i) = *(src+i)^(encrypted_iv[i]);
167 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
171 /** Creates a context in either AES or DES in ECB mode
172 * Depends on openssl libcrypto
175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
176 enum rte_crypto_cipher_operation direction __rte_unused,
179 const EVP_CIPHER *algo = NULL;
180 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
185 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
186 algo = EVP_des_ecb();
188 algo = EVP_aes_128_ecb();
190 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
191 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
198 EVP_CIPHER_CTX_free(ctx);
202 /** Frees a context previously created
203 * Depends on openssl libcrypto
206 bpi_cipher_ctx_free(void *bpi_ctx)
209 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
212 static inline uint32_t
213 adf_modulo(uint32_t data, uint32_t shift);
216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
217 struct qat_crypto_op_cookie *qat_op_cookie);
219 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
222 struct qat_session *sess = session;
223 phys_addr_t cd_paddr;
225 PMD_INIT_FUNC_TRACE();
228 bpi_cipher_ctx_free(sess->bpi_ctx);
229 sess->bpi_ctx = NULL;
231 cd_paddr = sess->cd_paddr;
232 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
233 sess->cd_paddr = cd_paddr;
235 PMD_DRV_LOG(ERR, "NULL session");
239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
242 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
243 return ICP_QAT_FW_LA_CMD_CIPHER;
245 /* Authentication Only */
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
247 return ICP_QAT_FW_LA_CMD_AUTH;
249 if (xform->next == NULL)
252 /* Cipher then Authenticate */
253 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
254 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
255 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
257 /* Authenticate then Cipher */
258 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
259 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
260 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
265 static struct rte_crypto_auth_xform *
266 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
269 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
278 static struct rte_crypto_cipher_xform *
279 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
282 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
283 return &xform->cipher;
291 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
292 struct rte_crypto_sym_xform *xform, void *session_private)
294 struct qat_session *session = session_private;
295 struct qat_pmd_private *internals = dev->data->dev_private;
296 struct rte_crypto_cipher_xform *cipher_xform = NULL;
298 /* Get cipher xform from crypto xform chain */
299 cipher_xform = qat_get_cipher_xform(xform);
301 session->cipher_iv.offset = cipher_xform->iv.offset;
302 session->cipher_iv.length = cipher_xform->iv.length;
304 switch (cipher_xform->algo) {
305 case RTE_CRYPTO_CIPHER_AES_CBC:
306 if (qat_alg_validate_aes_key(cipher_xform->key.length,
307 &session->qat_cipher_alg) != 0) {
308 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
311 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
313 case RTE_CRYPTO_CIPHER_AES_GCM:
314 if (qat_alg_validate_aes_key(cipher_xform->key.length,
315 &session->qat_cipher_alg) != 0) {
316 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
319 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
321 case RTE_CRYPTO_CIPHER_AES_CTR:
322 if (qat_alg_validate_aes_key(cipher_xform->key.length,
323 &session->qat_cipher_alg) != 0) {
324 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
327 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
329 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
330 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
331 &session->qat_cipher_alg) != 0) {
332 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
335 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
337 case RTE_CRYPTO_CIPHER_NULL:
338 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
340 case RTE_CRYPTO_CIPHER_KASUMI_F8:
341 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
342 &session->qat_cipher_alg) != 0) {
343 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
346 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
348 case RTE_CRYPTO_CIPHER_3DES_CBC:
349 if (qat_alg_validate_3des_key(cipher_xform->key.length,
350 &session->qat_cipher_alg) != 0) {
351 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
354 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
356 case RTE_CRYPTO_CIPHER_DES_CBC:
357 if (qat_alg_validate_des_key(cipher_xform->key.length,
358 &session->qat_cipher_alg) != 0) {
359 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
362 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
364 case RTE_CRYPTO_CIPHER_3DES_CTR:
365 if (qat_alg_validate_3des_key(cipher_xform->key.length,
366 &session->qat_cipher_alg) != 0) {
367 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
370 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
372 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
373 session->bpi_ctx = bpi_cipher_ctx_init(
376 cipher_xform->key.data);
377 if (session->bpi_ctx == NULL) {
378 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
381 if (qat_alg_validate_des_key(cipher_xform->key.length,
382 &session->qat_cipher_alg) != 0) {
383 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
386 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
388 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
389 session->bpi_ctx = bpi_cipher_ctx_init(
392 cipher_xform->key.data);
393 if (session->bpi_ctx == NULL) {
394 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
397 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
398 &session->qat_cipher_alg) != 0) {
399 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
402 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
404 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
405 if (!qat_is_cipher_alg_supported(
406 cipher_xform->algo, internals)) {
407 PMD_DRV_LOG(ERR, "%s not supported on this device",
408 rte_crypto_cipher_algorithm_strings
409 [cipher_xform->algo]);
412 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
413 &session->qat_cipher_alg) != 0) {
414 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
417 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
419 case RTE_CRYPTO_CIPHER_3DES_ECB:
420 case RTE_CRYPTO_CIPHER_AES_ECB:
421 case RTE_CRYPTO_CIPHER_AES_CCM:
422 case RTE_CRYPTO_CIPHER_AES_F8:
423 case RTE_CRYPTO_CIPHER_AES_XTS:
424 case RTE_CRYPTO_CIPHER_ARC4:
425 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
429 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
434 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
435 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
437 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
439 if (qat_alg_aead_session_create_content_desc_cipher(session,
440 cipher_xform->key.data,
441 cipher_xform->key.length))
447 if (session->bpi_ctx) {
448 bpi_cipher_ctx_free(session->bpi_ctx);
449 session->bpi_ctx = NULL;
456 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
457 struct rte_crypto_sym_xform *xform, void *session_private)
459 struct qat_session *session = session_private;
462 PMD_INIT_FUNC_TRACE();
464 /* Get requested QAT command id */
465 qat_cmd_id = qat_get_cmd_id(xform);
466 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
467 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
470 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
471 switch (session->qat_cmd) {
472 case ICP_QAT_FW_LA_CMD_CIPHER:
473 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
475 case ICP_QAT_FW_LA_CMD_AUTH:
476 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
478 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
479 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
480 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
482 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
483 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
484 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
486 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
487 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
488 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
489 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
490 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
491 case ICP_QAT_FW_LA_CMD_MGF1:
492 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
493 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
494 case ICP_QAT_FW_LA_CMD_DELIMITER:
495 PMD_DRV_LOG(ERR, "Unsupported Service %u",
499 PMD_DRV_LOG(ERR, "Unsupported Service %u",
511 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
512 struct rte_crypto_sym_xform *xform,
513 struct qat_session *session_private)
516 struct qat_session *session = session_private;
517 struct rte_crypto_auth_xform *auth_xform = NULL;
518 struct rte_crypto_cipher_xform *cipher_xform = NULL;
519 struct qat_pmd_private *internals = dev->data->dev_private;
520 auth_xform = qat_get_auth_xform(xform);
521 uint8_t *key_data = auth_xform->key.data;
522 uint8_t key_length = auth_xform->key.length;
524 switch (auth_xform->algo) {
525 case RTE_CRYPTO_AUTH_SHA1_HMAC:
526 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
528 case RTE_CRYPTO_AUTH_SHA224_HMAC:
529 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
531 case RTE_CRYPTO_AUTH_SHA256_HMAC:
532 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
534 case RTE_CRYPTO_AUTH_SHA384_HMAC:
535 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
537 case RTE_CRYPTO_AUTH_SHA512_HMAC:
538 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
540 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
541 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
543 case RTE_CRYPTO_AUTH_AES_GCM:
544 cipher_xform = qat_get_cipher_xform(xform);
546 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
548 key_data = cipher_xform->key.data;
549 key_length = cipher_xform->key.length;
551 case RTE_CRYPTO_AUTH_AES_GMAC:
552 if (qat_alg_validate_aes_key(auth_xform->key.length,
553 &session->qat_cipher_alg) != 0) {
554 PMD_DRV_LOG(ERR, "Invalid AES key size");
557 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
558 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
561 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
562 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
564 case RTE_CRYPTO_AUTH_MD5_HMAC:
565 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
567 case RTE_CRYPTO_AUTH_NULL:
568 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
570 case RTE_CRYPTO_AUTH_KASUMI_F9:
571 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
573 case RTE_CRYPTO_AUTH_ZUC_EIA3:
574 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
575 PMD_DRV_LOG(ERR, "%s not supported on this device",
576 rte_crypto_auth_algorithm_strings
580 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
582 case RTE_CRYPTO_AUTH_SHA1:
583 case RTE_CRYPTO_AUTH_SHA256:
584 case RTE_CRYPTO_AUTH_SHA512:
585 case RTE_CRYPTO_AUTH_SHA224:
586 case RTE_CRYPTO_AUTH_SHA384:
587 case RTE_CRYPTO_AUTH_MD5:
588 case RTE_CRYPTO_AUTH_AES_CCM:
589 case RTE_CRYPTO_AUTH_AES_CMAC:
590 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
591 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
595 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
600 session->auth_iv.offset = auth_xform->iv.offset;
601 session->auth_iv.length = auth_xform->iv.length;
603 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
604 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
605 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
606 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
608 * It needs to create cipher desc content first,
609 * then authentication
611 if (qat_alg_aead_session_create_content_desc_cipher(session,
612 auth_xform->key.data,
613 auth_xform->key.length))
616 if (qat_alg_aead_session_create_content_desc_auth(session,
620 auth_xform->digest_length,
624 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
625 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
627 * It needs to create authentication desc content first,
630 if (qat_alg_aead_session_create_content_desc_auth(session,
634 auth_xform->digest_length,
638 if (qat_alg_aead_session_create_content_desc_cipher(session,
639 auth_xform->key.data,
640 auth_xform->key.length))
643 /* Restore to authentication only only */
644 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
646 if (qat_alg_aead_session_create_content_desc_auth(session,
649 auth_xform->add_auth_data_length,
650 auth_xform->digest_length,
655 session->digest_length = auth_xform->digest_length;
662 unsigned qat_crypto_sym_get_session_private_size(
663 struct rte_cryptodev *dev __rte_unused)
665 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
668 static inline uint32_t
669 qat_bpicipher_preprocess(struct qat_session *ctx,
670 struct rte_crypto_op *op)
672 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
673 struct rte_crypto_sym_op *sym_op = op->sym;
674 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
676 if (last_block_len &&
677 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
679 /* Decrypt last block */
680 uint8_t *last_block, *dst, *iv;
681 uint32_t last_block_offset = sym_op->cipher.data.offset +
682 sym_op->cipher.data.length - last_block_len;
683 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
684 uint8_t *, last_block_offset);
686 if (unlikely(sym_op->m_dst != NULL))
687 /* out-of-place operation (OOP) */
688 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
689 uint8_t *, last_block_offset);
693 if (last_block_len < sym_op->cipher.data.length)
694 /* use previous block ciphertext as IV */
695 iv = last_block - block_len;
697 /* runt block, i.e. less than one full block */
698 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
699 ctx->cipher_iv.offset);
701 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
702 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
704 if (sym_op->m_dst != NULL)
705 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
708 bpi_cipher_decrypt(last_block, dst, iv, block_len,
709 last_block_len, ctx->bpi_ctx);
710 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
711 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
713 if (sym_op->m_dst != NULL)
714 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
719 return sym_op->cipher.data.length - last_block_len;
722 static inline uint32_t
723 qat_bpicipher_postprocess(struct qat_session *ctx,
724 struct rte_crypto_op *op)
726 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
727 struct rte_crypto_sym_op *sym_op = op->sym;
728 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
730 if (last_block_len > 0 &&
731 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
733 /* Encrypt last block */
734 uint8_t *last_block, *dst, *iv;
735 uint32_t last_block_offset;
737 last_block_offset = sym_op->cipher.data.offset +
738 sym_op->cipher.data.length - last_block_len;
739 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
740 uint8_t *, last_block_offset);
742 if (unlikely(sym_op->m_dst != NULL))
743 /* out-of-place operation (OOP) */
744 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
745 uint8_t *, last_block_offset);
749 if (last_block_len < sym_op->cipher.data.length)
750 /* use previous block ciphertext as IV */
751 iv = dst - block_len;
753 /* runt block, i.e. less than one full block */
754 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
755 ctx->cipher_iv.offset);
757 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
758 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
760 if (sym_op->m_dst != NULL)
761 rte_hexdump(stdout, "BPI: dst before post-process:",
762 dst, last_block_len);
764 bpi_cipher_encrypt(last_block, dst, iv, block_len,
765 last_block_len, ctx->bpi_ctx);
766 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
767 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
769 if (sym_op->m_dst != NULL)
770 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
774 return sym_op->cipher.data.length - last_block_len;
778 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
781 register struct qat_queue *queue;
782 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
783 register uint32_t nb_ops_sent = 0;
784 register struct rte_crypto_op **cur_op = ops;
786 uint16_t nb_ops_possible = nb_ops;
787 register uint8_t *base_addr;
788 register uint32_t tail;
791 if (unlikely(nb_ops == 0))
794 /* read params used a lot in main loop into registers */
795 queue = &(tmp_qp->tx_q);
796 base_addr = (uint8_t *)queue->base_addr;
799 /* Find how many can actually fit on the ring */
800 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
801 - queue->max_inflights;
803 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
804 nb_ops_possible = nb_ops - overflow;
805 if (nb_ops_possible == 0)
809 while (nb_ops_sent != nb_ops_possible) {
810 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
811 tmp_qp->op_cookies[tail / queue->msg_size]);
813 tmp_qp->stats.enqueue_err_count++;
815 * This message cannot be enqueued,
816 * decrease number of ops that wasn't sent
818 rte_atomic16_sub(&tmp_qp->inflights16,
819 nb_ops_possible - nb_ops_sent);
820 if (nb_ops_sent == 0)
825 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
830 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
831 queue->hw_queue_number, tail);
833 tmp_qp->stats.enqueued_count += nb_ops_sent;
838 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
841 struct qat_queue *queue;
842 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
843 uint32_t msg_counter = 0;
844 struct rte_crypto_op *rx_op;
845 struct icp_qat_fw_comn_resp *resp_msg;
847 queue = &(tmp_qp->rx_q);
848 resp_msg = (struct icp_qat_fw_comn_resp *)
849 ((uint8_t *)queue->base_addr + queue->head);
851 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
852 msg_counter != nb_ops) {
853 rx_op = (struct rte_crypto_op *)(uintptr_t)
854 (resp_msg->opaque_data);
856 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
857 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
858 sizeof(struct icp_qat_fw_comn_resp));
861 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
862 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
863 resp_msg->comn_hdr.comn_status)) {
864 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
866 struct qat_session *sess = (struct qat_session *)
867 (rx_op->sym->session->_private);
869 qat_bpicipher_postprocess(sess, rx_op);
870 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
873 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
874 queue->head = adf_modulo(queue->head +
876 ADF_RING_SIZE_MODULO(queue->queue_size));
877 resp_msg = (struct icp_qat_fw_comn_resp *)
878 ((uint8_t *)queue->base_addr +
884 if (msg_counter > 0) {
885 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
886 queue->hw_bundle_number,
887 queue->hw_queue_number, queue->head);
888 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
889 tmp_qp->stats.dequeued_count += msg_counter;
895 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
896 struct qat_alg_buf_list *list, uint32_t data_len)
900 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
901 buff_start + rte_pktmbuf_data_len(buf);
903 list->bufers[0].addr = buff_start;
904 list->bufers[0].resrvd = 0;
905 list->bufers[0].len = buf_len;
907 if (data_len <= buf_len) {
909 list->bufers[0].len = data_len;
915 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
916 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
922 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
923 list->bufers[nr].resrvd = 0;
924 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
926 buf_len += list->bufers[nr].len;
929 if (buf_len > data_len) {
930 list->bufers[nr].len -=
942 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
943 struct icp_qat_fw_la_cipher_req_params *cipher_param,
944 struct rte_crypto_op *op,
945 struct icp_qat_fw_la_bulk_req *qat_req)
947 /* copy IV into request if it fits */
948 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
949 rte_memcpy(cipher_param->u.cipher_IV_array,
950 rte_crypto_op_ctod_offset(op, uint8_t *,
954 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
955 qat_req->comn_hdr.serv_specif_flags,
956 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
957 cipher_param->u.s.cipher_IV_ptr =
958 rte_crypto_op_ctophys_offset(op,
964 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
965 struct qat_crypto_op_cookie *qat_op_cookie)
968 struct qat_session *ctx;
969 struct icp_qat_fw_la_cipher_req_params *cipher_param;
970 struct icp_qat_fw_la_auth_req_params *auth_param;
971 register struct icp_qat_fw_la_bulk_req *qat_req;
972 uint8_t do_auth = 0, do_cipher = 0;
973 uint32_t cipher_len = 0, cipher_ofs = 0;
974 uint32_t auth_len = 0, auth_ofs = 0;
975 uint32_t min_ofs = 0;
976 uint64_t src_buf_start = 0, dst_buf_start = 0;
979 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
980 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
981 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
982 "operation requests, op (%p) is not a "
983 "symmetric operation.", op);
987 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
988 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
989 " requests, op (%p) is sessionless.", op);
993 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
994 PMD_DRV_LOG(ERR, "Session was not created for this device");
998 ctx = (struct qat_session *)op->sym->session->_private;
999 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1000 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1001 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1002 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1003 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1005 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1006 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1009 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1012 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1019 if (ctx->qat_cipher_alg ==
1020 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1021 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1022 ctx->qat_cipher_alg ==
1023 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1026 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1027 || (cipher_param->cipher_offset
1028 % BYTE_LENGTH != 0))) {
1030 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1031 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1034 cipher_len = op->sym->cipher.data.length >> 3;
1035 cipher_ofs = op->sym->cipher.data.offset >> 3;
1037 } else if (ctx->bpi_ctx) {
1038 /* DOCSIS - only send complete blocks to device
1039 * Process any partial block using CFB mode.
1040 * Even if 0 complete blocks, still send this to device
1041 * to get into rx queue for post-process and dequeuing
1043 cipher_len = qat_bpicipher_preprocess(ctx, op);
1044 cipher_ofs = op->sym->cipher.data.offset;
1046 cipher_len = op->sym->cipher.data.length;
1047 cipher_ofs = op->sym->cipher.data.offset;
1050 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1051 cipher_param, op, qat_req);
1052 min_ofs = cipher_ofs;
1057 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1058 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1059 ctx->qat_hash_alg ==
1060 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1061 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1062 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1064 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1065 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1068 auth_ofs = op->sym->auth.data.offset >> 3;
1069 auth_len = op->sym->auth.data.length >> 3;
1071 if (ctx->qat_hash_alg ==
1072 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1074 auth_len = auth_len + auth_ofs + 1 -
1075 ICP_QAT_HW_KASUMI_BLK_SZ;
1076 auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1078 auth_len = auth_len + auth_ofs + 1;
1082 auth_param->u1.aad_adr =
1083 rte_crypto_op_ctophys_offset(op,
1084 ctx->auth_iv.offset);
1086 } else if (ctx->qat_hash_alg ==
1087 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1088 ctx->qat_hash_alg ==
1089 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1092 auth_ofs = op->sym->cipher.data.offset;
1093 auth_len = op->sym->cipher.data.length;
1095 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1098 set_cipher_iv(ctx->auth_iv.length,
1099 ctx->auth_iv.offset,
1100 cipher_param, op, qat_req);
1103 auth_ofs = op->sym->auth.data.offset;
1104 auth_len = op->sym->auth.data.length;
1109 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1113 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1116 /* adjust for chain case */
1117 if (do_cipher && do_auth)
1118 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1120 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1123 if (unlikely(op->sym->m_dst != NULL)) {
1124 /* Out-of-place operation (OOP)
1125 * Don't align DMA start. DMA the minimum data-set
1126 * so as not to overwrite data in dest buffer
1129 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1131 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1134 /* In-place operation
1135 * Start DMA at nearest aligned address below min_ofs
1138 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1139 & QAT_64_BTYE_ALIGN_MASK;
1141 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1142 rte_pktmbuf_headroom(op->sym->m_src))
1144 /* alignment has pushed addr ahead of start of mbuf
1145 * so revert and take the performance hit
1148 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1151 dst_buf_start = src_buf_start;
1155 cipher_param->cipher_offset =
1156 (uint32_t)rte_pktmbuf_mtophys_offset(
1157 op->sym->m_src, cipher_ofs) - src_buf_start;
1158 cipher_param->cipher_length = cipher_len;
1160 cipher_param->cipher_offset = 0;
1161 cipher_param->cipher_length = 0;
1164 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1165 op->sym->m_src, auth_ofs) - src_buf_start;
1166 auth_param->auth_len = auth_len;
1168 auth_param->auth_off = 0;
1169 auth_param->auth_len = 0;
1171 qat_req->comn_mid.dst_length =
1172 qat_req->comn_mid.src_length =
1173 (cipher_param->cipher_offset + cipher_param->cipher_length)
1174 > (auth_param->auth_off + auth_param->auth_len) ?
1175 (cipher_param->cipher_offset + cipher_param->cipher_length)
1176 : (auth_param->auth_off + auth_param->auth_len);
1180 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1181 QAT_COMN_PTR_TYPE_SGL);
1182 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1183 &qat_op_cookie->qat_sgl_list_src,
1184 qat_req->comn_mid.src_length);
1186 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1190 if (likely(op->sym->m_dst == NULL))
1191 qat_req->comn_mid.dest_data_addr =
1192 qat_req->comn_mid.src_data_addr =
1193 qat_op_cookie->qat_sgl_src_phys_addr;
1195 ret = qat_sgl_fill_array(op->sym->m_dst,
1197 &qat_op_cookie->qat_sgl_list_dst,
1198 qat_req->comn_mid.dst_length);
1201 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1206 qat_req->comn_mid.src_data_addr =
1207 qat_op_cookie->qat_sgl_src_phys_addr;
1208 qat_req->comn_mid.dest_data_addr =
1209 qat_op_cookie->qat_sgl_dst_phys_addr;
1212 qat_req->comn_mid.src_data_addr = src_buf_start;
1213 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1216 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1217 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1218 if (ctx->cipher_iv.length == 12 ||
1219 ctx->auth_iv.length == 12) {
1221 * For GCM a 12 byte IV is allowed,
1222 * but we need to inform the f/w
1224 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1225 qat_req->comn_hdr.serv_specif_flags,
1226 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1230 qat_req->comn_mid.dst_length =
1231 qat_req->comn_mid.src_length =
1232 rte_pktmbuf_data_len(op->sym->m_src);
1233 auth_param->u1.aad_adr = 0;
1234 auth_param->auth_len = op->sym->auth.data.length;
1235 auth_param->auth_off = op->sym->auth.data.offset;
1236 auth_param->u2.aad_sz = 0;
1240 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1241 rte_hexdump(stdout, "qat_req:", qat_req,
1242 sizeof(struct icp_qat_fw_la_bulk_req));
1243 rte_hexdump(stdout, "src_data:",
1244 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1245 rte_pktmbuf_data_len(op->sym->m_src));
1247 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1249 ctx->cipher_iv.offset);
1250 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1251 ctx->cipher_iv.length);
1255 if (ctx->auth_iv.length) {
1256 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1258 ctx->auth_iv.offset);
1259 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1260 ctx->auth_iv.length);
1262 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1263 ctx->digest_length);
1264 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1271 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1273 uint32_t div = data >> shift;
1274 uint32_t mult = div << shift;
1279 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1281 struct rte_cryptodev_sym_session *sess = sym_sess;
1282 struct qat_session *s = (void *)sess->_private;
1284 PMD_INIT_FUNC_TRACE();
1285 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1286 offsetof(struct qat_session, cd) +
1287 offsetof(struct rte_cryptodev_sym_session, _private);
1290 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1291 __rte_unused struct rte_cryptodev_config *config)
1293 PMD_INIT_FUNC_TRACE();
1297 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1299 PMD_INIT_FUNC_TRACE();
1303 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1305 PMD_INIT_FUNC_TRACE();
1308 int qat_dev_close(struct rte_cryptodev *dev)
1312 PMD_INIT_FUNC_TRACE();
1314 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1315 ret = qat_crypto_sym_qp_release(dev, i);
1323 void qat_dev_info_get(struct rte_cryptodev *dev,
1324 struct rte_cryptodev_info *info)
1326 struct qat_pmd_private *internals = dev->data->dev_private;
1328 PMD_INIT_FUNC_TRACE();
1330 info->max_nb_queue_pairs =
1331 ADF_NUM_SYM_QPS_PER_BUNDLE *
1332 ADF_NUM_BUNDLES_PER_DEV;
1333 info->feature_flags = dev->feature_flags;
1334 info->capabilities = internals->qat_dev_capabilities;
1335 info->sym.max_nb_sessions = internals->max_nb_sessions;
1336 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1337 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1341 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1342 struct rte_cryptodev_stats *stats)
1345 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1347 PMD_INIT_FUNC_TRACE();
1348 if (stats == NULL) {
1349 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1352 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1353 if (qp[i] == NULL) {
1354 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1358 stats->enqueued_count += qp[i]->stats.enqueued_count;
1359 stats->dequeued_count += qp[i]->stats.dequeued_count;
1360 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1361 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1365 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1368 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1370 PMD_INIT_FUNC_TRACE();
1371 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1372 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1373 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");