4 * Copyright (C) 2017 Cavium Inc. All rights reserved.
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7 * modification, are permitted provided that the following conditions
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33 #ifndef __OCTEONTX_FPAVF_H__
34 #define __OCTEONTX_FPAVF_H__
36 #include <rte_debug.h>
39 #ifdef RTE_LIBRTE_OCTEONTX_MEMPOOL_DEBUG
40 #define fpavf_log_info(fmt, args...) \
41 RTE_LOG(INFO, PMD, "%s() line %u: " fmt "\n", \
42 __func__, __LINE__, ## args)
43 #define fpavf_log_dbg(fmt, args...) \
44 RTE_LOG(DEBUG, PMD, "%s() line %u: " fmt "\n", \
45 __func__, __LINE__, ## args)
47 #define fpavf_log_info(fmt, args...)
48 #define fpavf_log_dbg(fmt, args...)
51 #define fpavf_func_trace fpavf_log_dbg
52 #define fpavf_log_err(fmt, args...) \
53 RTE_LOG(ERR, PMD, "%s() line %u: " fmt "\n", \
54 __func__, __LINE__, ## args)
56 /* fpa pool Vendor ID and Device ID */
57 #define PCI_VENDOR_ID_CAVIUM 0x177D
58 #define PCI_DEVICE_ID_OCTEONTX_FPA_VF 0xA053
61 #define FPA_GPOOL_MASK (FPA_VF_MAX-1)
63 /* FPA VF register offsets */
64 #define FPA_VF_INT(x) (0x200ULL | ((x) << 22))
65 #define FPA_VF_INT_W1S(x) (0x210ULL | ((x) << 22))
66 #define FPA_VF_INT_ENA_W1S(x) (0x220ULL | ((x) << 22))
67 #define FPA_VF_INT_ENA_W1C(x) (0x230ULL | ((x) << 22))
69 #define FPA_VF_VHPOOL_AVAILABLE(vhpool) (0x04150 | ((vhpool)&0x0))
70 #define FPA_VF_VHPOOL_THRESHOLD(vhpool) (0x04160 | ((vhpool)&0x0))
71 #define FPA_VF_VHPOOL_START_ADDR(vhpool) (0x04200 | ((vhpool)&0x0))
72 #define FPA_VF_VHPOOL_END_ADDR(vhpool) (0x04210 | ((vhpool)&0x0))
74 #define FPA_VF_VHAURA_CNT(vaura) (0x20120 | ((vaura)&0xf)<<18)
75 #define FPA_VF_VHAURA_CNT_ADD(vaura) (0x20128 | ((vaura)&0xf)<<18)
76 #define FPA_VF_VHAURA_CNT_LIMIT(vaura) (0x20130 | ((vaura)&0xf)<<18)
77 #define FPA_VF_VHAURA_CNT_THRESHOLD(vaura) (0x20140 | ((vaura)&0xf)<<18)
78 #define FPA_VF_VHAURA_OP_ALLOC(vaura) (0x30000 | ((vaura)&0xf)<<18)
79 #define FPA_VF_VHAURA_OP_FREE(vaura) (0x38000 | ((vaura)&0xf)<<18)
81 #define FPA_VF_FREE_ADDRS_S(x, y, z) \
82 ((x) | (((y) & 0x1ff) << 3) | ((((z) & 1)) << 14))
84 /* FPA VF register offsets from VF_BAR4, size 2 MByte */
85 #define FPA_VF_MSIX_VEC_ADDR 0x00000
86 #define FPA_VF_MSIX_VEC_CTL 0x00008
87 #define FPA_VF_MSIX_PBA 0xF0000
89 #define FPA_VF0_APERTURE_SHIFT 22
90 #define FPA_AURA_SET_SIZE 16
92 #define FPA_MAX_OBJ_SIZE (128 * 1024)
93 #define OCTEONTX_FPAVF_BUF_OFFSET 128
95 #define FPAVF_STATIC_ASSERTION(s) _Static_assert(s, #s)
98 * In Cavium OcteonTX SoC, all accesses to the device registers are
99 * implicitly strongly ordered. So, the relaxed version of IO operation is
100 * safe to use with out any IO memory barriers.
102 #define fpavf_read64 rte_read64_relaxed
103 #define fpavf_write64 rte_write64_relaxed
105 /* ARM64 specific functions */
106 #if defined(RTE_ARCH_ARM64)
107 #define fpavf_load_pair(val0, val1, addr) ({ \
109 "ldp %x[x0], %x[x1], [%x[p1]]" \
110 :[x0]"=r"(val0), [x1]"=r"(val1) \
114 #define fpavf_store_pair(val0, val1, addr) ({ \
116 "stp %x[x0], %x[x1], [%x[p1]]" \
117 ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
119 #else /* Un optimized functions for building on non arm64 arch */
121 #define fpavf_load_pair(val0, val1, addr) \
123 val0 = rte_read64(addr); \
124 val1 = rte_read64(((uint8_t *)addr) + 8); \
127 #define fpavf_store_pair(val0, val1, addr) \
129 rte_write64(val0, addr); \
130 rte_write64(val1, (((uint8_t *)addr) + 8)); \
135 octeontx_fpa_bufpool_create(unsigned int object_size, unsigned int object_count,
136 unsigned int buf_offset, char **va_start,
139 octeontx_fpa_bufpool_destroy(uintptr_t handle, int node);
141 octeontx_fpa_bufpool_block_size(uintptr_t handle);
143 octeontx_fpa_bufpool_free_count(uintptr_t handle);
145 static __rte_always_inline uint8_t
146 octeontx_fpa_bufpool_gpool(uintptr_t handle)
148 return (uint8_t)handle & FPA_GPOOL_MASK;
150 #endif /* __OCTEONTX_FPAVF_H__ */