1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
17 #include <rte_byteorder.h>
19 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
20 #ifndef __LITTLE_ENDIAN
21 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
24 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
26 #define __BIG_ENDIAN RTE_BIG_ENDIAN
28 #undef __LITTLE_ENDIAN
31 #include "ecore_mfw_req.h"
32 #include "ecore_fw_defs.h"
33 #include "ecore_hsi.h"
34 #include "ecore_reg.h"
37 typedef rte_iova_t ecore_dma_addr_t; /* expected to be 64 bit wide */
38 typedef volatile int ecore_atomic_t;
41 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */
43 #define ECORE_SWCID_SHIFT 17
44 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1)
46 #define ECORE_MC_HASH_SIZE 8
47 #define ECORE_MC_HASH_OFFSET(sc, i) \
48 (BAR_TSTRORM_INTMEM + \
49 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4)
51 #define ECORE_MAX_MULTICAST 64
52 #define ECORE_MAX_EMUL_MULTI 1
54 #define IRO sc->iro_array
56 typedef rte_spinlock_t ECORE_MUTEX;
57 #define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex)
58 #define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex)
59 #define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex)
61 typedef rte_spinlock_t ECORE_MUTEX_SPIN;
62 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin)
63 #define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */
64 #define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */
66 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb()
67 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb()
68 #define ECORE_SMP_MB() mb()
69 #define ECORE_SMP_RMB() rmb()
70 #define ECORE_SMP_WMB() wmb()
71 #define ECORE_MMIOWB() wmb()
73 #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit))
74 #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit))
76 #define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var)
77 #define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var)
78 #define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var)
79 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var)
81 #define atomic_load_acq_int (int)*
82 #define atomic_store_rel_int(a, v) (*a = v)
83 #define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o)
85 #define atomic_load_acq_long (long)*
86 #define atomic_store_rel_long(a, v) (*a = v)
87 #define atomic_set_acq_long(a, v) (*a |= v)
88 #define atomic_clear_acq_long(a, v) (*a &= ~v)
89 #define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o)
90 #define atomic_subtract_acq_long(a, v) (*a -= v)
91 #define atomic_add_acq_long(a, v) (*a += v)
93 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a)
94 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v)
95 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n)
97 #define ECORE_RET_PENDING(pending_bit, pending) \
98 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS)
100 #define ECORE_SET_FLAG(value, mask, flag) \
102 (value) &= ~(mask); \
103 (value) |= ((flag) << (mask##_SHIFT)); \
106 #define ECORE_GET_FLAG(value, mask) \
107 (((value) &= (mask)) >> (mask##_SHIFT))
109 #define ECORE_MIGHT_SLEEP()
111 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id)
113 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s)
114 #define ECORE_MEMCPY(_a, _b, _s) rte_memcpy(_a, _b, _s)
115 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s)
117 #define ECORE_CPU_TO_LE16(x) htole16(x)
118 #define ECORE_CPU_TO_LE32(x) htole32(x)
120 #define ECORE_WAIT(_s, _t) DELAY(1000)
121 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000)
123 #define ECORE_LIKELY(x) likely(x)
124 #define ECORE_UNLIKELY(x) unlikely(x)
126 #define ECORE_ZALLOC(_size, _flags, _sc) \
127 rte_zmalloc("", _size, RTE_CACHE_LINE_SIZE)
129 #define ECORE_CALLOC(_len, _size, _flags, _sc) \
130 rte_calloc("", _len, _size, RTE_CACHE_LINE_SIZE)
132 #define ECORE_FREE(_s, _buf, _size) \
135 #define SC_ILT(sc) ((sc)->ilt)
136 #define ILOG2(x) bnx2x_ilog2(x)
138 #define ECORE_ILT_ZALLOC(x, y, size, str) \
140 x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \
142 if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \
143 size, (struct bnx2x_dma *)x, \
144 str, RTE_CACHE_LINE_SIZE) != 0) { \
149 *y = ((struct bnx2x_dma *)x)->paddr; \
154 #define ECORE_ILT_FREE(x, y, size) \
163 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
165 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
166 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
167 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE
169 #define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation
171 #define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index
173 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a))
175 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN
177 #define ECORE_PATH_ID SC_PATH
178 #define ECORE_PORT_ID SC_PORT
179 #define ECORE_FUNC_ID SC_FUNC
180 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC
182 #define CRCPOLY_LE 0xedb88320
183 uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p,
184 uint32_t len, uint32_t magic);
186 uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc);
189 static inline uint32_t
190 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len)
192 return ecore_calc_crc32(seed, mac, len, CRCPOLY_LE);
195 #define ecore_sp_post(_sc, _a, _b, _c, _d) \
196 bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d)
198 #define ECORE_DBG_BREAK_IF(exp) \
200 if (unlikely(exp)) { \
201 rte_panic("ECORE"); \
205 #define ECORE_BUG() \
207 rte_panic("BUG (%s:%d)", __FILE__, __LINE__); \
210 #define ECORE_BUG_ON(exp) \
213 rte_panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \
218 #define ECORE_MSG(sc, m, ...) \
219 PMD_DRV_LOG(DEBUG, sc, m, ##__VA_ARGS__)
221 typedef struct _ecore_list_entry_t
223 struct _ecore_list_entry_t *next, *prev;
224 } ecore_list_entry_t;
226 typedef struct ecore_list_t
228 ecore_list_entry_t *head, *tail;
232 /* initialize the list */
233 #define ECORE_LIST_INIT(_list) \
235 (_list)->head = NULL; \
236 (_list)->tail = NULL; \
240 /* return TRUE if the element is the last on the list */
241 #define ECORE_LIST_IS_LAST(_elem, _list) \
242 (_elem == (_list)->tail)
244 /* return TRUE if the list is empty */
245 #define ECORE_LIST_IS_EMPTY(_list) \
248 /* return the first element */
249 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \
250 (cast *)((_list)->head)
252 /* return the next element */
253 #define ECORE_LIST_NEXT(_elem, _link, cast) \
254 (cast *)((&((_elem)->_link))->next)
256 /* push an element on the head of the list */
257 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \
259 (_elem)->prev = (ecore_list_entry_t *)0; \
260 (_elem)->next = (_list)->head; \
261 if ((_list)->tail == (ecore_list_entry_t *)0) { \
262 (_list)->tail = (_elem); \
264 (_list)->head->prev = (_elem); \
266 (_list)->head = (_elem); \
270 /* push an element on the tail of the list */
271 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \
273 (_elem)->next = (ecore_list_entry_t *)0; \
274 (_elem)->prev = (_list)->tail; \
275 if ((_list)->tail) { \
276 (_list)->tail->next = (_elem); \
278 (_list)->head = (_elem); \
280 (_list)->tail = (_elem); \
284 /* push list1 on the head of list2 and return with list1 as empty */
285 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \
287 (_list1)->tail->next = (_list2)->head; \
288 if ((_list2)->head) { \
289 (_list2)->head->prev = (_list1)->tail; \
291 (_list2)->tail = (_list1)->tail; \
293 (_list2)->head = (_list1)->head; \
294 (_list2)->cnt += (_list1)->cnt; \
295 (_list1)->head = NULL; \
296 (_list1)->tail = NULL; \
300 /* remove an element from the list */
301 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \
303 if ((_list)->head == (_elem)) { \
304 if ((_list)->head) { \
305 (_list)->head = (_list)->head->next; \
306 if ((_list)->head) { \
307 (_list)->head->prev = (ecore_list_entry_t *)0; \
309 (_list)->tail = (ecore_list_entry_t *)0; \
313 } else if ((_list)->tail == (_elem)) { \
314 if ((_list)->tail) { \
315 (_list)->tail = (_list)->tail->prev; \
316 if ((_list)->tail) { \
317 (_list)->tail->next = (ecore_list_entry_t *)0; \
319 (_list)->head = (ecore_list_entry_t *)0; \
324 (_elem)->prev->next = (_elem)->next; \
325 (_elem)->next->prev = (_elem)->prev; \
331 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \
332 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \
334 pos = ECORE_LIST_NEXT(pos, _link, cast))
336 /* walk the list (safely) */
337 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \
338 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \
339 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \
342 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL)
345 /* Manipulate a bit vector defined as an array of uint64_t */
347 /* Number of bits in one sge_mask array element */
348 #define BIT_VEC64_ELEM_SZ 64
349 #define BIT_VEC64_ELEM_SHIFT 6
350 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1)
352 #define __BIT_VEC64_SET_BIT(el, bit) \
354 el = ((el) | ((uint64_t)0x1 << (bit))); \
357 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
359 el = ((el) & (~((uint64_t)0x1 << (bit)))); \
362 #define BIT_VEC64_SET_BIT(vec64, idx) \
363 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
364 (idx) & BIT_VEC64_ELEM_MASK)
366 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
367 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
368 (idx) & BIT_VEC64_ELEM_MASK)
370 #define BIT_VEC64_TEST_BIT(vec64, idx) \
371 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
372 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
375 * Creates a bitmask of all ones in less significant bits.
376 * idx - index of the most significant bit in the created mask
378 #define BIT_VEC64_ONES_MASK(idx) \
379 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
380 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0))
382 /* fill in a MAC address the way the FW likes it */
384 ecore_set_fw_mac_addr(uint16_t *fw_hi,
389 ((uint8_t *)fw_hi)[0] = mac[1];
390 ((uint8_t *)fw_hi)[1] = mac[0];
391 ((uint8_t *)fw_mid)[0] = mac[3];
392 ((uint8_t *)fw_mid)[1] = mac[2];
393 ((uint8_t *)fw_lo)[0] = mac[5];
394 ((uint8_t *)fw_lo)[1] = mac[4];
398 enum ecore_status_t {
406 /* PENDING is not an error and should be positive */
421 /* Bits representing general command's configuration */
425 /* Wait until all pending commands complete */
427 /* Don't send a ramrod, only update a registry */
429 /* Configure HW according to the current object state */
431 /* Execute the next command now */
433 /* Don't add a new command and continue execution of posponed
434 * commands. If not set a new command will be added to the
435 * pending commands list.
438 /* If there is another pending ramrod, wait until it finishes and
439 * re-try to submit this one. This flag can be set only in sleepable
440 * context, and should not be set from the context that completes the
441 * ramrods as deadlock will occur.
449 ECORE_OBJ_TYPE_RX_TX,
452 /* Public slow path states */
454 ECORE_FILTER_MAC_PENDING,
455 ECORE_FILTER_VLAN_PENDING,
456 ECORE_FILTER_VLAN_MAC_PENDING,
457 ECORE_FILTER_RX_MODE_PENDING,
458 ECORE_FILTER_RX_MODE_SCHED,
459 ECORE_FILTER_ISCSI_ETH_START_SCHED,
460 ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
461 ECORE_FILTER_FCOE_ETH_START_SCHED,
462 ECORE_FILTER_FCOE_ETH_STOP_SCHED,
463 ECORE_FILTER_MCAST_PENDING,
464 ECORE_FILTER_MCAST_SCHED,
465 ECORE_FILTER_RSS_CONF_PENDING,
466 ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
467 ECORE_AFEX_PENDING_VIFSET_MCP_ACK
470 struct ecore_raw_obj {
477 /* Ramrod data buffer params */
479 ecore_dma_addr_t rdata_mapping;
481 /* Ramrod state params */
482 int state; /* "ramrod is pending" state bit */
483 unsigned long *pstate; /* pointer to state buffer */
485 ecore_obj_type obj_type;
487 int (*wait_comp)(struct bnx2x_softc *sc,
488 struct ecore_raw_obj *o);
490 int (*check_pending)(struct ecore_raw_obj *o);
491 void (*clear_pending)(struct ecore_raw_obj *o);
492 void (*set_pending)(struct ecore_raw_obj *o);
495 /************************* VLAN-MAC commands related parameters ***************/
496 struct ecore_mac_ramrod_data {
497 uint8_t mac[ETH_ALEN];
498 uint8_t is_inner_mac;
501 struct ecore_vlan_ramrod_data {
505 struct ecore_vlan_mac_ramrod_data {
506 uint8_t mac[ETH_ALEN];
507 uint8_t is_inner_mac;
511 union ecore_classification_ramrod_data {
512 struct ecore_mac_ramrod_data mac;
513 struct ecore_vlan_ramrod_data vlan;
514 struct ecore_vlan_mac_ramrod_data vlan_mac;
517 /* VLAN_MAC commands */
518 enum ecore_vlan_mac_cmd {
524 struct ecore_vlan_mac_data {
525 /* Requested command: ECORE_VLAN_MAC_XX */
526 enum ecore_vlan_mac_cmd cmd;
527 /* used to contain the data related vlan_mac_flags bits from
530 unsigned long vlan_mac_flags;
532 /* Needed for MOVE command */
533 struct ecore_vlan_mac_obj *target_obj;
535 union ecore_classification_ramrod_data u;
538 /*************************** Exe Queue obj ************************************/
539 union ecore_exe_queue_cmd_data {
540 struct ecore_vlan_mac_data vlan_mac;
546 struct ecore_exeq_elem {
547 ecore_list_entry_t link;
549 /* Length of this element in the exe_chunk. */
552 union ecore_exe_queue_cmd_data cmd_data;
555 union ecore_qable_obj;
557 union ecore_exeq_comp_elem {
558 union event_ring_elem *elem;
561 struct ecore_exe_queue_obj;
563 typedef int (*exe_q_validate)(struct bnx2x_softc *sc,
564 union ecore_qable_obj *o,
565 struct ecore_exeq_elem *elem);
567 typedef int (*exe_q_remove)(struct bnx2x_softc *sc,
568 union ecore_qable_obj *o,
569 struct ecore_exeq_elem *elem);
571 /* Return positive if entry was optimized, 0 - if not, negative
572 * in case of an error.
574 typedef int (*exe_q_optimize)(struct bnx2x_softc *sc,
575 union ecore_qable_obj *o,
576 struct ecore_exeq_elem *elem);
577 typedef int (*exe_q_execute)(struct bnx2x_softc *sc,
578 union ecore_qable_obj *o,
579 ecore_list_t *exe_chunk,
580 unsigned long *ramrod_flags);
581 typedef struct ecore_exeq_elem *
582 (*exe_q_get)(struct ecore_exe_queue_obj *o,
583 struct ecore_exeq_elem *elem);
585 struct ecore_exe_queue_obj {
586 /* Commands pending for an execution. */
587 ecore_list_t exe_queue;
589 /* Commands pending for an completion. */
590 ecore_list_t pending_comp;
592 ECORE_MUTEX_SPIN lock;
594 /* Maximum length of commands' list for one execution */
597 union ecore_qable_obj *owner;
599 /****** Virtual functions ******/
601 * Called before commands execution for commands that are really
602 * going to be executed (after 'optimize').
604 * Must run under exe_queue->lock
606 exe_q_validate validate;
609 * Called before removing pending commands, cleaning allocated
610 * resources (e.g., credits from validate)
615 * This will try to cancel the current pending commands list
616 * considering the new command.
618 * Returns the number of optimized commands or a negative error code
620 * Must run under exe_queue->lock
622 exe_q_optimize optimize;
625 * Run the next commands chunk (owner specific).
627 exe_q_execute execute;
630 * Return the exe_queue element containing the specific command
631 * if any. Otherwise return NULL.
635 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
637 * Element in the VLAN_MAC registry list having all current configured
640 struct ecore_vlan_mac_registry_elem {
641 ecore_list_entry_t link;
643 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
644 * Relevant for 57711 only. VLANs and MACs share the
645 * same CAM for these chips.
649 /* Needed for DEL and RESTORE flows */
650 unsigned long vlan_mac_flags;
652 union ecore_classification_ramrod_data u;
655 /* Bits representing VLAN_MAC commands specific flags */
661 ECORE_DONT_CONSUME_CAM_CREDIT,
662 ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
665 struct ecore_vlan_mac_ramrod_params {
666 /* Object to run the command from */
667 struct ecore_vlan_mac_obj *vlan_mac_obj;
669 /* General command flags: COMP_WAIT, etc. */
670 unsigned long ramrod_flags;
672 /* Command specific configuration request */
673 struct ecore_vlan_mac_data user_req;
676 struct ecore_vlan_mac_obj {
677 struct ecore_raw_obj raw;
679 /* Bookkeeping list: will prevent the addition of already existing
683 /* Implement a simple reader/writer lock on the head list.
684 * all these fields should only be accessed under the exe_queue lock
686 uint8_t head_reader; /* Num. of readers accessing head list */
687 int head_exe_request; /* Pending execution request. */
688 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
690 /* Execution queue interface instance */
691 struct ecore_exe_queue_obj exe_queue;
693 /* MACs credit pool */
694 struct ecore_credit_pool_obj *macs_pool;
696 /* VLANs credit pool */
697 struct ecore_credit_pool_obj *vlans_pool;
699 /* RAMROD command to be used */
702 /* copy first n elements onto preallocated buffer
704 * @param n number of elements to get
705 * @param buf buffer preallocated by caller into which elements
706 * will be copied. Note elements are 4-byte aligned
707 * so buffer size must be able to accommodate the
710 * @return number of copied bytes
713 int (*get_n_elements)(struct bnx2x_softc *sc,
714 struct ecore_vlan_mac_obj *o, int n, uint8_t *base,
715 uint8_t stride, uint8_t size);
718 * Checks if ADD-ramrod with the given params may be performed.
720 * @return zero if the element may be added
723 int (*check_add)(struct bnx2x_softc *sc,
724 struct ecore_vlan_mac_obj *o,
725 union ecore_classification_ramrod_data *data);
728 * Checks if DEL-ramrod with the given params may be performed.
730 * @return TRUE if the element may be deleted
732 struct ecore_vlan_mac_registry_elem *
733 (*check_del)(struct bnx2x_softc *sc,
734 struct ecore_vlan_mac_obj *o,
735 union ecore_classification_ramrod_data *data);
738 * Checks if DEL-ramrod with the given params may be performed.
740 * @return TRUE if the element may be deleted
742 int (*check_move)(struct bnx2x_softc *sc,
743 struct ecore_vlan_mac_obj *src_o,
744 struct ecore_vlan_mac_obj *dst_o,
745 union ecore_classification_ramrod_data *data);
748 * Update the relevant credit object(s) (consume/return
751 int (*get_credit)(struct ecore_vlan_mac_obj *o);
752 int (*put_credit)(struct ecore_vlan_mac_obj *o);
753 int (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
754 int (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
757 * Configures one rule in the ramrod data buffer.
759 void (*set_one_rule)(struct bnx2x_softc *sc,
760 struct ecore_vlan_mac_obj *o,
761 struct ecore_exeq_elem *elem, int rule_idx,
765 * Delete all configured elements having the given
766 * vlan_mac_flags specification. Assumes no pending for
767 * execution commands. Will schedule all all currently
768 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
769 * specification for deletion and will use the given
770 * ramrod_flags for the last DEL operation.
774 * @param ramrod_flags RAMROD_XX flags
776 * @return 0 if the last operation has completed successfully
777 * and there are no more elements left, positive value
778 * if there are pending for completion commands,
779 * negative value in case of failure.
781 int (*delete_all)(struct bnx2x_softc *sc,
782 struct ecore_vlan_mac_obj *o,
783 unsigned long *vlan_mac_flags,
784 unsigned long *ramrod_flags);
787 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
788 * configured elements list.
791 * @param p Command parameters (RAMROD_COMP_WAIT bit in
792 * ramrod_flags is only taken into an account)
793 * @param ppos a pointer to the cookie that should be given back in the
794 * next call to make function handle the next element. If
795 * *ppos is set to NULL it will restart the iterator.
796 * If returned *ppos == NULL this means that the last
797 * element has been handled.
801 int (*restore)(struct bnx2x_softc *sc,
802 struct ecore_vlan_mac_ramrod_params *p,
803 struct ecore_vlan_mac_registry_elem **ppos);
806 * Should be called on a completion arrival.
810 * @param cqe Completion element we are handling
811 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
812 * pending commands will be executed.
813 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
814 * may also be set if needed.
816 * @return 0 if there are neither pending nor waiting for
817 * completion commands. Positive value if there are
818 * pending for execution or for completion commands.
819 * Negative value in case of an error (including an
822 int (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o,
823 union event_ring_elem *cqe,
824 unsigned long *ramrod_flags);
827 * Wait for completion of all commands. Don't schedule new ones,
828 * just wait. It assumes that the completion code will schedule
831 int (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o);
835 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0,
836 ECORE_LLH_CAM_ETH_LINE,
837 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
840 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
842 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
843 * a ecore_rx_mode_ramrod_params.
846 ECORE_RX_MODE_FCOE_ETH,
847 ECORE_RX_MODE_ISCSI_ETH,
851 ECORE_ACCEPT_UNICAST,
852 ECORE_ACCEPT_MULTICAST,
853 ECORE_ACCEPT_ALL_UNICAST,
854 ECORE_ACCEPT_ALL_MULTICAST,
855 ECORE_ACCEPT_BROADCAST,
856 ECORE_ACCEPT_UNMATCHED,
857 ECORE_ACCEPT_ANY_VLAN
860 struct ecore_rx_mode_ramrod_params {
861 struct ecore_rx_mode_obj *rx_mode_obj;
862 unsigned long *pstate;
867 unsigned long ramrod_flags;
868 unsigned long rx_mode_flags;
870 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
871 * a tstorm_eth_mac_filter_config (e1x).
874 ecore_dma_addr_t rdata_mapping;
876 /* Rx mode settings */
877 unsigned long rx_accept_flags;
879 /* internal switching settings */
880 unsigned long tx_accept_flags;
883 struct ecore_rx_mode_obj {
884 int (*config_rx_mode)(struct bnx2x_softc *sc,
885 struct ecore_rx_mode_ramrod_params *p);
887 int (*wait_comp)(struct bnx2x_softc *sc,
888 struct ecore_rx_mode_ramrod_params *p);
891 /********************** Set multicast group ***********************************/
893 struct ecore_mcast_list_elem {
894 ecore_list_entry_t link;
898 union ecore_mcast_config_data {
900 uint8_t bin; /* used in a RESTORE flow */
903 struct ecore_mcast_ramrod_params {
904 struct ecore_mcast_obj *mcast_obj;
906 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
907 unsigned long ramrod_flags;
909 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
913 enum ecore_mcast_cmd {
915 ECORE_MCAST_CMD_CONT,
917 ECORE_MCAST_CMD_RESTORE,
920 struct ecore_mcast_obj {
921 struct ecore_raw_obj raw;
925 #define ECORE_MCAST_BINS_NUM 256
926 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64)
927 uint64_t vec[ECORE_MCAST_VEC_SZ];
929 /** Number of BINs to clear. Should be updated
930 * immediately when a command arrives in order to
931 * properly create DEL commands.
942 /* Pending commands */
943 ecore_list_t pending_cmds_head;
945 /* A state that is set in raw.pstate, when there are pending commands */
948 /* Maximal number of mcast MACs configured in one command */
951 /* Total number of currently pending MACs to configure: both
952 * in the pending commands list and in the current command.
954 int total_pending_num;
959 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above)
961 int (*config_mcast)(struct bnx2x_softc *sc,
962 struct ecore_mcast_ramrod_params *p,
963 enum ecore_mcast_cmd cmd);
966 * Fills the ramrod data during the RESTORE flow.
970 * @param start_idx Registry index to start from
971 * @param rdata_idx Index in the ramrod data to start from
973 * @return -1 if we handled the whole registry or index of the last
974 * handled registry element.
976 int (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,
977 int start_bin, int *rdata_idx);
979 int (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,
980 struct ecore_mcast_ramrod_params *p,
981 enum ecore_mcast_cmd cmd);
983 void (*set_one_rule)(struct bnx2x_softc *sc,
984 struct ecore_mcast_obj *o, int idx,
985 union ecore_mcast_config_data *cfg_data,
986 enum ecore_mcast_cmd cmd);
988 /** Checks if there are more mcast MACs to be set or a previous
989 * command is still pending.
991 int (*check_pending)(struct ecore_mcast_obj *o);
994 * Set/Clear/Check SCHEDULED state of the object
996 void (*set_sched)(struct ecore_mcast_obj *o);
997 void (*clear_sched)(struct ecore_mcast_obj *o);
998 int (*check_sched)(struct ecore_mcast_obj *o);
1000 /* Wait until all pending commands complete */
1001 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);
1004 * Handle the internal object counters needed for proper
1005 * commands handling. Checks that the provided parameters are
1008 int (*validate)(struct bnx2x_softc *sc,
1009 struct ecore_mcast_ramrod_params *p,
1010 enum ecore_mcast_cmd cmd);
1013 * Restore the values of internal counters in case of a failure.
1015 void (*revert)(struct bnx2x_softc *sc,
1016 struct ecore_mcast_ramrod_params *p,
1019 int (*get_registry_size)(struct ecore_mcast_obj *o);
1020 void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
1023 /*************************** Credit handling **********************************/
1024 struct ecore_credit_pool_obj {
1026 /* Current amount of credit in the pool */
1027 ecore_atomic_t credit;
1029 /* Maximum allowed credit. put() will check against it. */
1032 /* Allocate a pool table statically.
1034 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
1036 * The set bit in the table will mean that the entry is available.
1038 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
1039 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE];
1041 /* Base pool offset (initialized differently */
1042 int base_pool_offset;
1045 * Get the next free pool entry.
1047 * @return TRUE if there was a free entry in the pool
1049 int (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
1052 * Return the entry back to the pool.
1054 * @return TRUE if entry is legal and has been successfully
1055 * returned to the pool.
1057 int (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
1060 * Get the requested amount of credit from the pool.
1062 * @param cnt Amount of requested credit
1063 * @return TRUE if the operation is successful
1065 int (*get)(struct ecore_credit_pool_obj *o, int cnt);
1068 * Returns the credit to the pool.
1070 * @param cnt Amount of credit to return
1071 * @return TRUE if the operation is successful
1073 int (*put)(struct ecore_credit_pool_obj *o, int cnt);
1076 * Reads the current amount of credit.
1078 int (*check)(struct ecore_credit_pool_obj *o);
1081 /*************************** RSS configuration ********************************/
1083 /* RSS_MODE bits are mutually exclusive */
1084 ECORE_RSS_MODE_DISABLED,
1085 ECORE_RSS_MODE_REGULAR,
1087 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
1096 ECORE_RSS_TUNNELING,
1099 struct ecore_config_rss_params {
1100 struct ecore_rss_config_obj *rss_obj;
1102 /* may have RAMROD_COMP_WAIT set only */
1103 unsigned long ramrod_flags;
1105 /* ECORE_RSS_X bits */
1106 unsigned long rss_flags;
1108 /* Number hash bits to take into an account */
1109 uint8_t rss_result_mask;
1111 /* Indirection table */
1112 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1114 /* RSS hash values */
1115 uint32_t rss_key[10];
1117 /* valid only if ECORE_RSS_UPDATE_TOE is set */
1118 uint16_t toe_rss_bitmap;
1120 /* valid if ECORE_RSS_TUNNELING is set */
1121 uint16_t tunnel_value;
1122 uint16_t tunnel_mask;
1125 struct ecore_rss_config_obj {
1126 struct ecore_raw_obj raw;
1128 /* RSS engine to use */
1131 /* Last configured indirection table */
1132 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1134 /* flags for enabling 4-tupple hash on UDP */
1138 int (*config_rss)(struct bnx2x_softc *sc,
1139 struct ecore_config_rss_params *p);
1142 /*********************** Queue state update ***********************************/
1144 /* UPDATE command options */
1146 ECORE_Q_UPDATE_IN_VLAN_REM,
1147 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG,
1148 ECORE_Q_UPDATE_OUT_VLAN_REM,
1149 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,
1150 ECORE_Q_UPDATE_ANTI_SPOOF,
1151 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG,
1152 ECORE_Q_UPDATE_ACTIVATE,
1153 ECORE_Q_UPDATE_ACTIVATE_CHNG,
1154 ECORE_Q_UPDATE_DEF_VLAN_EN,
1155 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,
1156 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,
1157 ECORE_Q_UPDATE_SILENT_VLAN_REM,
1158 ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
1159 ECORE_Q_UPDATE_TX_SWITCHING,
1162 /* Allowed Queue states */
1163 enum ecore_q_state {
1164 ECORE_Q_STATE_RESET,
1165 ECORE_Q_STATE_INITIALIZED,
1166 ECORE_Q_STATE_ACTIVE,
1167 ECORE_Q_STATE_MULTI_COS,
1168 ECORE_Q_STATE_MCOS_TERMINATED,
1169 ECORE_Q_STATE_INACTIVE,
1170 ECORE_Q_STATE_STOPPED,
1171 ECORE_Q_STATE_TERMINATED,
1172 ECORE_Q_STATE_FLRED,
1176 /* Allowed Queue states */
1177 enum ecore_q_logical_state {
1178 ECORE_Q_LOGICAL_STATE_ACTIVE,
1179 ECORE_Q_LOGICAL_STATE_STOPPED,
1182 /* Allowed commands */
1183 enum ecore_queue_cmd {
1186 ECORE_Q_CMD_SETUP_TX_ONLY,
1187 ECORE_Q_CMD_DEACTIVATE,
1188 ECORE_Q_CMD_ACTIVATE,
1190 ECORE_Q_CMD_UPDATE_TPA,
1192 ECORE_Q_CMD_CFC_DEL,
1193 ECORE_Q_CMD_TERMINATE,
1198 /* queue SETUP + INIT flags */
1201 ECORE_Q_FLG_TPA_IPV6,
1202 ECORE_Q_FLG_TPA_GRO,
1204 ECORE_Q_FLG_ZERO_STATS,
1214 ECORE_Q_FLG_LEADING_RSS,
1216 ECORE_Q_FLG_DEF_VLAN,
1217 ECORE_Q_FLG_TX_SWITCH,
1219 ECORE_Q_FLG_ANTI_SPOOF,
1220 ECORE_Q_FLG_SILENT_VLAN_REM,
1221 ECORE_Q_FLG_FORCE_DEFAULT_PRI,
1222 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
1223 ECORE_Q_FLG_PCSUM_ON_PKT,
1224 ECORE_Q_FLG_TUN_INC_INNER_IP_ID
1227 /* Queue type options: queue type may be a combination of below. */
1230 ECORE_Q_TYPE_HAS_RX,
1231 ECORE_Q_TYPE_HAS_TX,
1234 #define ECORE_PRIMARY_CID_INDEX 0
1235 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */
1236 #define ECORE_MULTI_TX_COS_E2_E3A0 2
1237 #define ECORE_MULTI_TX_COS_E3B0 3
1238 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */
1239 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
1241 struct ecore_queue_init_params {
1243 unsigned long flags;
1246 uint8_t sb_cq_index;
1250 unsigned long flags;
1253 uint8_t sb_cq_index;
1256 /* CID context in the host memory */
1257 struct eth_context *cxts[ECORE_MULTI_TX_COS];
1259 /* maximum number of cos supported by hardware */
1263 struct ecore_queue_terminate_params {
1264 /* index within the tx_only cids of this queue object */
1268 struct ecore_queue_cfc_del_params {
1269 /* index within the tx_only cids of this queue object */
1273 struct ecore_queue_update_params {
1274 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */
1276 uint16_t silent_removal_value;
1277 uint16_t silent_removal_mask;
1278 /* index within the tx_only cids of this queue object */
1282 struct rxq_pause_params {
1287 uint16_t sge_th_lo; /* valid if ECORE_Q_FLG_TPA */
1288 uint16_t sge_th_hi; /* valid if ECORE_Q_FLG_TPA */
1293 struct ecore_general_setup_params {
1294 /* valid if ECORE_Q_FLG_STATS */
1302 struct ecore_rxq_setup_params {
1304 ecore_dma_addr_t dscr_map;
1305 ecore_dma_addr_t rcq_map;
1306 ecore_dma_addr_t rcq_np_map;
1308 uint16_t drop_flags;
1311 uint8_t cl_qzone_id;
1313 /* valid if ECORE_Q_FLG_TPA */
1314 uint16_t tpa_agg_sz;
1315 uint8_t max_tpa_queues;
1316 uint8_t rss_engine_id;
1318 /* valid if ECORE_Q_FLG_MCAST */
1319 uint8_t mcast_engine_id;
1321 uint8_t cache_line_log;
1323 uint8_t sb_cq_index;
1325 /* valid if BXN2X_Q_FLG_SILENT_VLAN_REM */
1326 uint16_t silent_removal_value;
1327 uint16_t silent_removal_mask;
1330 struct ecore_txq_setup_params {
1332 ecore_dma_addr_t dscr_map;
1335 uint8_t sb_cq_index;
1336 uint8_t cos; /* valid if ECORE_Q_FLG_COS */
1337 uint16_t traffic_type;
1338 /* equals to the leading rss client id, used for TX classification*/
1339 uint8_t tss_leading_cl_id;
1341 /* valid if ECORE_Q_FLG_DEF_VLAN */
1342 uint16_t default_vlan;
1345 struct ecore_queue_setup_params {
1346 struct ecore_general_setup_params gen_params;
1347 struct ecore_txq_setup_params txq_params;
1348 struct ecore_rxq_setup_params rxq_params;
1349 struct rxq_pause_params pause_params;
1350 unsigned long flags;
1353 struct ecore_queue_setup_tx_only_params {
1354 struct ecore_general_setup_params gen_params;
1355 struct ecore_txq_setup_params txq_params;
1356 unsigned long flags;
1357 /* index within the tx_only cids of this queue object */
1361 struct ecore_queue_state_params {
1362 struct ecore_queue_sp_obj *q_obj;
1364 /* Current command */
1365 enum ecore_queue_cmd cmd;
1367 /* may have RAMROD_COMP_WAIT set only */
1368 unsigned long ramrod_flags;
1370 /* Params according to the current command */
1372 struct ecore_queue_update_params update;
1373 struct ecore_queue_setup_params setup;
1374 struct ecore_queue_init_params init;
1375 struct ecore_queue_setup_tx_only_params tx_only;
1376 struct ecore_queue_terminate_params terminate;
1377 struct ecore_queue_cfc_del_params cfc_del;
1381 struct ecore_viflist_params {
1383 uint8_t func_bit_map_res;
1386 struct ecore_queue_sp_obj {
1387 uint32_t cids[ECORE_MULTI_TX_COS];
1391 /* number of traffic classes supported by queue.
1392 * The primary connection of the queue supports the first traffic
1393 * class. Any further traffic class is supported by a tx-only
1396 * Therefore max_cos is also a number of valid entries in the cids
1400 uint8_t num_tx_only, next_tx_only;
1402 enum ecore_q_state state, next_state;
1404 /* bits from enum ecore_q_type */
1407 /* ECORE_Q_CMD_XX bits. This object implements "one
1408 * pending" paradigm but for debug and tracing purposes it's
1409 * more convenient to have different bits for different
1412 unsigned long pending;
1414 /* Buffer to use as a ramrod data and its mapping */
1416 ecore_dma_addr_t rdata_mapping;
1419 * Performs one state change according to the given parameters.
1421 * @return 0 in case of success and negative value otherwise.
1423 int (*send_cmd)(struct bnx2x_softc *sc,
1424 struct ecore_queue_state_params *params);
1427 * Sets the pending bit according to the requested transition.
1429 int (*set_pending)(struct ecore_queue_sp_obj *o,
1430 struct ecore_queue_state_params *params);
1433 * Checks that the requested state transition is legal.
1435 int (*check_transition)(struct bnx2x_softc *sc,
1436 struct ecore_queue_sp_obj *o,
1437 struct ecore_queue_state_params *params);
1440 * Completes the pending command.
1442 int (*complete_cmd)(struct bnx2x_softc *sc,
1443 struct ecore_queue_sp_obj *o,
1444 enum ecore_queue_cmd);
1446 int (*wait_comp)(struct bnx2x_softc *sc,
1447 struct ecore_queue_sp_obj *o,
1448 enum ecore_queue_cmd cmd);
1451 /********************** Function state update *********************************/
1452 /* Allowed Function states */
1453 enum ecore_func_state {
1454 ECORE_F_STATE_RESET,
1455 ECORE_F_STATE_INITIALIZED,
1456 ECORE_F_STATE_STARTED,
1457 ECORE_F_STATE_TX_STOPPED,
1461 /* Allowed Function commands */
1462 enum ecore_func_cmd {
1463 ECORE_F_CMD_HW_INIT,
1466 ECORE_F_CMD_HW_RESET,
1467 ECORE_F_CMD_AFEX_UPDATE,
1468 ECORE_F_CMD_AFEX_VIFLISTS,
1469 ECORE_F_CMD_TX_STOP,
1470 ECORE_F_CMD_TX_START,
1471 ECORE_F_CMD_SWITCH_UPDATE,
1475 struct ecore_func_hw_init_params {
1476 /* A load phase returned by MCP.
1479 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1480 * FW_MSG_CODE_DRV_LOAD_COMMON
1481 * FW_MSG_CODE_DRV_LOAD_PORT
1482 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1484 uint32_t load_phase;
1487 struct ecore_func_hw_reset_params {
1488 /* A load phase returned by MCP.
1491 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1492 * FW_MSG_CODE_DRV_LOAD_COMMON
1493 * FW_MSG_CODE_DRV_LOAD_PORT
1494 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1496 uint32_t reset_phase;
1499 struct ecore_func_start_params {
1500 /* Multi Function mode:
1502 * - Switch Dependent
1503 * - Switch Independent
1507 /* Switch Dependent mode outer VLAN tag */
1508 uint16_t sd_vlan_tag;
1510 /* Function cos mode */
1511 uint8_t network_cos_mode;
1513 /* NVGRE classification enablement */
1514 uint8_t nvgre_clss_en;
1516 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
1517 uint8_t gre_tunnel_mode;
1519 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
1520 uint8_t gre_tunnel_rss;
1524 struct ecore_func_switch_update_params {
1528 struct ecore_func_afex_update_params {
1530 uint16_t afex_default_vlan;
1531 uint8_t allowed_priorities;
1534 struct ecore_func_afex_viflists_params {
1535 uint16_t vif_list_index;
1536 uint8_t func_bit_map;
1537 uint8_t afex_vif_list_command;
1538 uint8_t func_to_clear;
1540 struct ecore_func_tx_start_params {
1541 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1542 uint8_t dcb_enabled;
1543 uint8_t dcb_version;
1544 uint8_t dont_add_pri_0;
1547 struct ecore_func_state_params {
1548 struct ecore_func_sp_obj *f_obj;
1550 /* Current command */
1551 enum ecore_func_cmd cmd;
1553 /* may have RAMROD_COMP_WAIT set only */
1554 unsigned long ramrod_flags;
1556 /* Params according to the current command */
1558 struct ecore_func_hw_init_params hw_init;
1559 struct ecore_func_hw_reset_params hw_reset;
1560 struct ecore_func_start_params start;
1561 struct ecore_func_switch_update_params switch_update;
1562 struct ecore_func_afex_update_params afex_update;
1563 struct ecore_func_afex_viflists_params afex_viflists;
1564 struct ecore_func_tx_start_params tx_start;
1568 struct ecore_func_sp_drv_ops {
1569 /* Init tool + runtime initialization:
1571 * - Common (per Path)
1575 int (*init_hw_cmn_chip)(struct bnx2x_softc *sc);
1576 int (*init_hw_cmn)(struct bnx2x_softc *sc);
1577 int (*init_hw_port)(struct bnx2x_softc *sc);
1578 int (*init_hw_func)(struct bnx2x_softc *sc);
1580 /* Reset Function HW: Common, Port, Function phases. */
1581 void (*reset_hw_cmn)(struct bnx2x_softc *sc);
1582 void (*reset_hw_port)(struct bnx2x_softc *sc);
1583 void (*reset_hw_func)(struct bnx2x_softc *sc);
1585 /* Prepare/Release FW resources */
1586 int (*init_fw)(struct bnx2x_softc *sc);
1587 void (*release_fw)(struct bnx2x_softc *sc);
1590 struct ecore_func_sp_obj {
1591 enum ecore_func_state state, next_state;
1593 /* ECORE_FUNC_CMD_XX bits. This object implements "one
1594 * pending" paradigm but for debug and tracing purposes it's
1595 * more convenient to have different bits for different
1598 unsigned long pending;
1600 /* Buffer to use as a ramrod data and its mapping */
1602 ecore_dma_addr_t rdata_mapping;
1604 /* Buffer to use as a afex ramrod data and its mapping.
1605 * This can't be same rdata as above because afex ramrod requests
1606 * can arrive to the object in parallel to other ramrod requests.
1609 ecore_dma_addr_t afex_rdata_mapping;
1611 /* this mutex validates that when pending flag is taken, the next
1612 * ramrod to be sent will be the one set the pending bit
1614 ECORE_MUTEX one_pending_mutex;
1616 /* Driver interface */
1617 struct ecore_func_sp_drv_ops *drv;
1620 * Performs one state change according to the given parameters.
1622 * @return 0 in case of success and negative value otherwise.
1624 int (*send_cmd)(struct bnx2x_softc *sc,
1625 struct ecore_func_state_params *params);
1628 * Checks that the requested state transition is legal.
1630 int (*check_transition)(struct bnx2x_softc *sc,
1631 struct ecore_func_sp_obj *o,
1632 struct ecore_func_state_params *params);
1635 * Completes the pending command.
1637 int (*complete_cmd)(struct bnx2x_softc *sc,
1638 struct ecore_func_sp_obj *o,
1639 enum ecore_func_cmd cmd);
1641 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o,
1642 enum ecore_func_cmd cmd);
1645 /********************** Interfaces ********************************************/
1646 /* Queueable objects set */
1647 union ecore_qable_obj {
1648 struct ecore_vlan_mac_obj vlan_mac;
1650 /************** Function state update *********/
1651 void ecore_init_func_obj(struct bnx2x_softc *sc,
1652 struct ecore_func_sp_obj *obj,
1653 void *rdata, ecore_dma_addr_t rdata_mapping,
1654 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,
1655 struct ecore_func_sp_drv_ops *drv_iface);
1657 int ecore_func_state_change(struct bnx2x_softc *sc,
1658 struct ecore_func_state_params *params);
1660 enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc,
1661 struct ecore_func_sp_obj *o);
1662 /******************* Queue State **************/
1663 void ecore_init_queue_obj(struct bnx2x_softc *sc,
1664 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids,
1665 uint8_t cid_cnt, uint8_t func_id, void *rdata,
1666 ecore_dma_addr_t rdata_mapping, unsigned long type);
1668 int ecore_queue_state_change(struct bnx2x_softc *sc,
1669 struct ecore_queue_state_params *params);
1671 /********************* VLAN-MAC ****************/
1672 void ecore_init_mac_obj(struct bnx2x_softc *sc,
1673 struct ecore_vlan_mac_obj *mac_obj,
1674 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1675 ecore_dma_addr_t rdata_mapping, int state,
1676 unsigned long *pstate, ecore_obj_type type,
1677 struct ecore_credit_pool_obj *macs_pool);
1679 void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,
1680 struct ecore_vlan_mac_obj *o);
1681 int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,
1682 struct ecore_vlan_mac_obj *o);
1683 void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,
1684 struct ecore_vlan_mac_obj *o);
1685 int ecore_config_vlan_mac(struct bnx2x_softc *sc,
1686 struct ecore_vlan_mac_ramrod_params *p);
1688 int ecore_vlan_mac_move(struct bnx2x_softc *sc,
1689 struct ecore_vlan_mac_ramrod_params *p,
1690 struct ecore_vlan_mac_obj *dest_o);
1692 /********************* RX MODE ****************/
1694 void ecore_init_rx_mode_obj(struct bnx2x_softc *sc,
1695 struct ecore_rx_mode_obj *o);
1698 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1700 * @p: Command parameters
1702 * Return: 0 - if operation was successful and there is no pending completions,
1703 * positive number - if there are pending completions,
1704 * negative - if there were errors
1706 int ecore_config_rx_mode(struct bnx2x_softc *sc,
1707 struct ecore_rx_mode_ramrod_params *p);
1709 /****************** MULTICASTS ****************/
1711 void ecore_init_mcast_obj(struct bnx2x_softc *sc,
1712 struct ecore_mcast_obj *mcast_obj,
1713 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,
1714 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,
1715 int state, unsigned long *pstate,
1716 ecore_obj_type type);
1719 * ecore_config_mcast - Configure multicast MACs list.
1721 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1723 * May configure a new list
1724 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
1725 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current
1726 * configuration, continue to execute the pending commands
1727 * (ECORE_MCAST_CMD_CONT).
1729 * If previous command is still pending or if number of MACs to
1730 * configure is more that maximum number of MACs in one command,
1731 * the current command will be enqueued to the tail of the
1732 * pending commands list.
1734 * Return: 0 is operation was successful and there are no pending completions,
1735 * negative if there were errors, positive if there are pending
1738 int ecore_config_mcast(struct bnx2x_softc *sc,
1739 struct ecore_mcast_ramrod_params *p,
1740 enum ecore_mcast_cmd cmd);
1742 /****************** CREDIT POOL ****************/
1743 void ecore_init_mac_credit_pool(struct bnx2x_softc *sc,
1744 struct ecore_credit_pool_obj *p, uint8_t func_id,
1746 void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,
1747 struct ecore_credit_pool_obj *p, uint8_t func_id,
1750 /****************** RSS CONFIGURATION ****************/
1751 void ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,
1752 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
1753 void *rdata, ecore_dma_addr_t rdata_mapping,
1754 int state, unsigned long *pstate,
1755 ecore_obj_type type);
1758 * ecore_config_rss - Updates RSS configuration according to provided parameters
1760 * Return: 0 in case of success
1762 int ecore_config_rss(struct bnx2x_softc *sc,
1763 struct ecore_config_rss_params *p);
1766 #endif /* ECORE_SP_H */