1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
23 #define BNXT_MAX_MTU 9500
24 #define VLAN_TAG_SIZE 4
25 #define BNXT_MAX_LED 4
27 struct bnxt_led_info {
32 uint16_t led_state_caps;
33 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
34 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
36 uint16_t led_color_caps;
44 uint16_t led_blink_on;
45 uint16_t led_blink_off;
50 #define BNXT_LED_DFLT_ENA \
51 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
52 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
53 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
54 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
55 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
57 #define BNXT_LED_DFLT_ENA_SHIFT 6
59 #define BNXT_LED_DFLT_ENABLES(x) \
60 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
62 enum bnxt_hw_context {
64 HW_CONTEXT_IS_RSS = 1,
65 HW_CONTEXT_IS_COS = 2,
69 struct bnxt_vlan_table_entry {
72 } __attribute__((packed));
74 struct bnxt_vlan_antispoof_table_entry {
78 } __attribute__((packed));
80 struct bnxt_child_vf_info {
82 struct bnxt_vlan_table_entry *vlan_table;
83 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
84 STAILQ_HEAD(, bnxt_filter_info) filter;
85 uint32_t func_cfg_flags;
92 uint8_t vlan_spoof_en;
98 #define BNXT_FIRST_PF_FID 1
99 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
100 #define BNXT_FIRST_VF_FID 128
101 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
102 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
104 uint16_t first_vf_id;
107 uint32_t func_cfg_flags;
109 rte_iova_t vf_req_buf_dma_addr;
110 uint32_t vf_req_fwd[8];
111 uint16_t total_vnics;
112 struct bnxt_child_vf_info *vf_info;
113 #define BNXT_EVB_MODE_NONE 0
114 #define BNXT_EVB_MODE_VEB 1
115 #define BNXT_EVB_MODE_VEPA 2
119 /* Max wait time is 10 * 100ms = 1s */
120 #define BNXT_LINK_WAIT_CNT 10
121 #define BNXT_LINK_WAIT_INTERVAL 100
122 struct bnxt_link_info {
125 uint8_t phy_link_status;
133 #define PHY_VER_LEN 3
134 uint8_t phy_ver[PHY_VER_LEN];
136 uint16_t support_speeds;
137 uint16_t auto_link_speed;
138 uint16_t force_link_speed;
139 uint16_t auto_link_speed_mask;
140 uint32_t preemphasis;
145 #define BNXT_COS_QUEUE_COUNT 8
146 struct bnxt_cos_queue_info {
152 STAILQ_ENTRY(rte_flow) next;
153 struct bnxt_filter_info *filter;
154 struct bnxt_vnic_info *vnic;
157 struct bnxt_ptp_cfg {
158 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
159 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
160 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
161 struct rte_timecounter tc;
162 struct rte_timecounter tx_tstamp_tc;
163 struct rte_timecounter rx_tstamp_tc;
165 #define BNXT_MAX_TX_TS 1
167 #define BNXT_PTP_MSG_SYNC (1 << 0)
168 #define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
169 #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
170 #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
171 #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
172 #define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
173 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
174 #define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
175 #define BNXT_PTP_MSG_SIGNALING (1 << 12)
176 #define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
177 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
178 BNXT_PTP_MSG_DELAY_REQ | \
179 BNXT_PTP_MSG_PDELAY_REQ | \
180 BNXT_PTP_MSG_PDELAY_RESP)
181 uint8_t tx_tstamp_en:1;
184 #define BNXT_PTP_RX_TS_L 0
185 #define BNXT_PTP_RX_TS_H 1
186 #define BNXT_PTP_RX_SEQ 2
187 #define BNXT_PTP_RX_FIFO 3
188 #define BNXT_PTP_RX_FIFO_PENDING 0x1
189 #define BNXT_PTP_RX_FIFO_ADV 4
190 #define BNXT_PTP_RX_REGS 5
192 #define BNXT_PTP_TX_TS_L 0
193 #define BNXT_PTP_TX_TS_H 1
194 #define BNXT_PTP_TX_SEQ 2
195 #define BNXT_PTP_TX_FIFO 3
196 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
197 #define BNXT_PTP_TX_REGS 4
198 uint32_t rx_regs[BNXT_PTP_RX_REGS];
199 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
200 uint32_t tx_regs[BNXT_PTP_TX_REGS];
201 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
204 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
208 struct rte_eth_dev *eth_dev;
209 struct rte_eth_rss_conf rss_conf;
210 struct rte_pci_device *pdev;
213 #define BNXT_FLAG_REGISTERED (1 << 0)
214 #define BNXT_FLAG_VF (1 << 1)
215 #define BNXT_FLAG_PORT_STATS (1 << 2)
216 #define BNXT_FLAG_JUMBO (1 << 3)
217 #define BNXT_FLAG_SHORT_CMD (1 << 4)
218 #define BNXT_FLAG_UPDATE_HASH (1 << 5)
219 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
220 #define BNXT_FLAG_MULTI_HOST (1 << 7)
221 #define BNXT_FLAG_INIT_DONE (1 << 31)
222 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
223 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
224 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
225 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
226 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
228 unsigned int rx_nr_rings;
229 unsigned int rx_cp_nr_rings;
230 struct bnxt_rx_queue **rx_queues;
231 const void *rx_mem_zone;
232 struct rx_port_stats *hw_rx_port_stats;
233 rte_iova_t hw_rx_port_stats_map;
235 unsigned int tx_nr_rings;
236 unsigned int tx_cp_nr_rings;
237 struct bnxt_tx_queue **tx_queues;
238 const void *tx_mem_zone;
239 struct tx_port_stats *hw_tx_port_stats;
240 rte_iova_t hw_tx_port_stats_map;
242 /* Default completion ring */
243 struct bnxt_cp_ring_info *def_cp_ring;
244 uint32_t max_ring_grps;
245 struct bnxt_ring_grp_info *grp_info;
247 unsigned int nr_vnics;
249 struct bnxt_vnic_info *vnic_info;
250 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
252 struct bnxt_filter_info *filter_info;
253 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
255 /* VNIC pointer for flow filter (VMDq) pools */
256 #define MAX_FF_POOLS 256
257 STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS];
259 struct bnxt_irq *irq_tbl;
261 #define MAX_NUM_MAC_ADDR 32
262 uint8_t mac_addr[ETHER_ADDR_LEN];
264 uint16_t hwrm_cmd_seq;
265 void *hwrm_cmd_resp_addr;
266 rte_iova_t hwrm_cmd_resp_dma_addr;
267 void *hwrm_short_cmd_req_addr;
268 rte_iova_t hwrm_short_cmd_req_dma_addr;
269 rte_spinlock_t hwrm_lock;
270 uint16_t max_req_len;
271 uint16_t max_resp_len;
273 struct bnxt_link_info link_info;
274 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
277 uint8_t dflt_mac_addr[ETHER_ADDR_LEN];
278 uint16_t max_rsscos_ctx;
279 uint16_t max_cp_rings;
280 uint16_t max_tx_rings;
281 uint16_t max_rx_rings;
284 uint16_t max_stat_ctx;
286 struct bnxt_pf_info pf;
287 uint8_t port_partition_type;
289 uint8_t vxlan_port_cnt;
290 uint8_t geneve_port_cnt;
292 uint16_t geneve_port;
293 uint16_t vxlan_fw_dst_port_id;
294 uint16_t geneve_fw_dst_port_id;
296 rte_atomic64_t rx_mbuf_alloc_fail;
298 struct bnxt_led_info leds[BNXT_MAX_LED];
300 struct bnxt_ptp_cfg *ptp_cfg;
303 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
304 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
306 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG 0x6
308 bool is_bnxt_supported(struct rte_eth_dev *dev);
309 extern const struct rte_flow_ops bnxt_flow_ops;
311 extern int bnxt_logtype_driver;
312 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
313 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
316 #define PMD_DRV_LOG(level, fmt, args...) \
317 PMD_DRV_LOG_RAW(level, fmt, ## args)