4 * Copyright(c) Broadcom Limited.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev_driver.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56 #include "bnxt_nvm_defs.h"
58 #define DRV_MODULE_NAME "bnxt"
59 static const char bnxt_version[] =
60 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
62 #define PCI_VENDOR_ID_BROADCOM 0x14E4
64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
66 #define BROADCOM_DEV_ID_57414_VF 0x16c1
67 #define BROADCOM_DEV_ID_57301 0x16c8
68 #define BROADCOM_DEV_ID_57302 0x16c9
69 #define BROADCOM_DEV_ID_57304_PF 0x16ca
70 #define BROADCOM_DEV_ID_57304_VF 0x16cb
71 #define BROADCOM_DEV_ID_57417_MF 0x16cc
72 #define BROADCOM_DEV_ID_NS2 0x16cd
73 #define BROADCOM_DEV_ID_57311 0x16ce
74 #define BROADCOM_DEV_ID_57312 0x16cf
75 #define BROADCOM_DEV_ID_57402 0x16d0
76 #define BROADCOM_DEV_ID_57404 0x16d1
77 #define BROADCOM_DEV_ID_57406_PF 0x16d2
78 #define BROADCOM_DEV_ID_57406_VF 0x16d3
79 #define BROADCOM_DEV_ID_57402_MF 0x16d4
80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
81 #define BROADCOM_DEV_ID_57412 0x16d6
82 #define BROADCOM_DEV_ID_57414 0x16d7
83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
86 #define BROADCOM_DEV_ID_57412_MF 0x16de
87 #define BROADCOM_DEV_ID_57314 0x16df
88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
93 #define BROADCOM_DEV_ID_57404_MF 0x16e7
94 #define BROADCOM_DEV_ID_57406_MF 0x16e8
95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
96 #define BROADCOM_DEV_ID_57407_MF 0x16ea
97 #define BROADCOM_DEV_ID_57414_MF 0x16ec
98 #define BROADCOM_DEV_ID_57416_MF 0x16ee
100 static const struct rte_pci_id bnxt_pci_id_map[] = {
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
102 BROADCOM_DEV_ID_STRATUS_NIC_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
133 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
136 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
137 { .vendor_id = 0, /* sentinel */ },
140 #define BNXT_ETH_RSS_SUPPORT ( \
142 ETH_RSS_NONFRAG_IPV4_TCP | \
143 ETH_RSS_NONFRAG_IPV4_UDP | \
145 ETH_RSS_NONFRAG_IPV6_TCP | \
146 ETH_RSS_NONFRAG_IPV6_UDP)
148 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
149 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
151 /***********************/
154 * High level utility functions
157 static void bnxt_free_mem(struct bnxt *bp)
159 bnxt_free_filter_mem(bp);
160 bnxt_free_vnic_attributes(bp);
161 bnxt_free_vnic_mem(bp);
164 bnxt_free_tx_rings(bp);
165 bnxt_free_rx_rings(bp);
166 bnxt_free_def_cp_ring(bp);
169 static int bnxt_alloc_mem(struct bnxt *bp)
173 /* Default completion ring */
174 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
178 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
179 bp->def_cp_ring, "def_cp");
183 rc = bnxt_alloc_vnic_mem(bp);
187 rc = bnxt_alloc_vnic_attributes(bp);
191 rc = bnxt_alloc_filter_mem(bp);
202 static int bnxt_init_chip(struct bnxt *bp)
204 unsigned int i, rss_idx, fw_idx;
205 struct rte_eth_link new;
206 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
207 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
208 uint32_t intr_vector = 0;
209 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
210 uint32_t vec = BNXT_MISC_VEC_ID;
213 /* disable uio/vfio intr/eventfd mapping */
214 rte_intr_disable(intr_handle);
216 if (bp->eth_dev->data->mtu > ETHER_MTU) {
217 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
218 bp->flags |= BNXT_FLAG_JUMBO;
220 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
221 bp->flags &= ~BNXT_FLAG_JUMBO;
224 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
226 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
230 rc = bnxt_alloc_hwrm_rings(bp);
232 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
236 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
238 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
242 rc = bnxt_mq_rx_configure(bp);
244 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
248 /* VNIC configuration */
249 for (i = 0; i < bp->nr_vnics; i++) {
250 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
252 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
254 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
259 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
262 "HWRM vnic %d ctx alloc failure rc: %x\n",
267 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
269 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
274 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
277 "HWRM vnic %d filter failure rc: %x\n",
281 if (vnic->rss_table && vnic->hash_type) {
283 * Fill the RSS hash & redirection table with
284 * ring group ids for all VNICs
286 for (rss_idx = 0, fw_idx = 0;
287 rss_idx < HW_HASH_INDEX_SIZE;
288 rss_idx++, fw_idx++) {
289 if (vnic->fw_grp_ids[fw_idx] ==
292 vnic->rss_table[rss_idx] =
293 vnic->fw_grp_ids[fw_idx];
295 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
298 "HWRM vnic %d set RSS failure rc: %x\n",
304 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
306 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
307 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
309 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
311 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
314 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
318 /* check and configure queue intr-vector mapping */
319 if ((rte_intr_cap_multiple(intr_handle) ||
320 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
321 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
322 intr_vector = bp->eth_dev->data->nb_rx_queues;
323 RTE_LOG(INFO, PMD, "%s(): intr_vector = %d\n", __func__,
325 if (intr_vector > bp->rx_cp_nr_rings) {
326 RTE_LOG(ERR, PMD, "At most %d intr queues supported",
330 if (rte_intr_efd_enable(intr_handle, intr_vector))
334 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
335 intr_handle->intr_vec =
336 rte_zmalloc("intr_vec",
337 bp->eth_dev->data->nb_rx_queues *
339 if (intr_handle->intr_vec == NULL) {
340 RTE_LOG(ERR, PMD, "Failed to allocate %d rx_queues"
341 " intr_vec", bp->eth_dev->data->nb_rx_queues);
344 RTE_LOG(DEBUG, PMD, "%s(): intr_handle->intr_vec = %p "
345 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
346 __func__, intr_handle->intr_vec, intr_handle->nb_efd,
347 intr_handle->max_intr);
350 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
352 intr_handle->intr_vec[queue_id] = vec;
353 if (vec < base + intr_handle->nb_efd - 1)
357 /* enable uio/vfio intr/eventfd mapping */
358 rte_intr_enable(intr_handle);
360 rc = bnxt_get_hwrm_link_config(bp, &new);
362 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
366 if (!bp->link_info.link_up) {
367 rc = bnxt_set_hwrm_link_config(bp, true);
370 "HWRM link config failure rc: %x\n", rc);
374 bnxt_print_link_info(bp->eth_dev);
379 bnxt_free_all_hwrm_resources(bp);
381 /* Some of the error status returned by FW may not be from errno.h */
388 static int bnxt_shutdown_nic(struct bnxt *bp)
390 bnxt_free_all_hwrm_resources(bp);
391 bnxt_free_all_filters(bp);
392 bnxt_free_all_vnics(bp);
396 static int bnxt_init_nic(struct bnxt *bp)
400 rc = bnxt_init_ring_grps(bp);
405 bnxt_init_filters(bp);
407 rc = bnxt_init_chip(bp);
415 * Device configuration and status function
418 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
419 struct rte_eth_dev_info *dev_info)
421 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
422 uint16_t max_vnics, i, j, vpool, vrxq;
423 unsigned int max_rx_rings;
425 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
428 dev_info->max_mac_addrs = bp->max_l2_ctx;
429 dev_info->max_hash_mac_addrs = 0;
431 /* PF/VF specifics */
433 dev_info->max_vfs = bp->pdev->max_vfs;
434 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
435 RTE_MIN(bp->max_rsscos_ctx,
437 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
438 dev_info->max_rx_queues = max_rx_rings;
439 dev_info->max_tx_queues = max_rx_rings;
440 dev_info->reta_size = bp->max_rsscos_ctx;
441 dev_info->hash_key_size = 40;
442 max_vnics = bp->max_vnics;
444 /* Fast path specifics */
445 dev_info->min_rx_bufsize = 1;
446 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
448 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
449 DEV_RX_OFFLOAD_IPV4_CKSUM |
450 DEV_RX_OFFLOAD_UDP_CKSUM |
451 DEV_RX_OFFLOAD_TCP_CKSUM |
452 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
453 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
454 DEV_TX_OFFLOAD_IPV4_CKSUM |
455 DEV_TX_OFFLOAD_TCP_CKSUM |
456 DEV_TX_OFFLOAD_UDP_CKSUM |
457 DEV_TX_OFFLOAD_TCP_TSO |
458 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
459 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
460 DEV_TX_OFFLOAD_GRE_TNL_TSO |
461 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
462 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
465 dev_info->default_rxconf = (struct rte_eth_rxconf) {
471 .rx_free_thresh = 32,
475 dev_info->default_txconf = (struct rte_eth_txconf) {
481 .tx_free_thresh = 32,
483 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
484 ETH_TXQ_FLAGS_NOOFFLOADS,
486 eth_dev->data->dev_conf.intr_conf.lsc = 1;
488 eth_dev->data->dev_conf.intr_conf.rxq = 1;
493 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
494 * need further investigation.
498 vpool = 64; /* ETH_64_POOLS */
499 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
500 for (i = 0; i < 4; vpool >>= 1, i++) {
501 if (max_vnics > vpool) {
502 for (j = 0; j < 5; vrxq >>= 1, j++) {
503 if (dev_info->max_rx_queues > vrxq) {
509 /* Not enough resources to support VMDq */
513 /* Not enough resources to support VMDq */
517 dev_info->max_vmdq_pools = vpool;
518 dev_info->vmdq_queue_num = vrxq;
520 dev_info->vmdq_pool_base = 0;
521 dev_info->vmdq_queue_base = 0;
524 /* Configure the device based on the configuration provided */
525 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
527 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
529 bp->rx_queues = (void *)eth_dev->data->rx_queues;
530 bp->tx_queues = (void *)eth_dev->data->tx_queues;
532 /* Inherit new configurations */
533 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
534 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
535 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
537 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
539 (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
541 "Insufficient resources to support requested config\n");
543 "Num Queues Requested: Tx %d, Rx %d\n",
544 eth_dev->data->nb_tx_queues,
545 eth_dev->data->nb_rx_queues);
547 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
548 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
549 bp->max_stat_ctx, bp->max_ring_grps);
553 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
554 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
555 bp->rx_cp_nr_rings = bp->rx_nr_rings;
556 bp->tx_cp_nr_rings = bp->tx_nr_rings;
558 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
560 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
561 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
565 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
567 struct rte_eth_link *link = ð_dev->data->dev_link;
569 if (link->link_status)
570 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
571 eth_dev->data->port_id,
572 (uint32_t)link->link_speed,
573 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
574 ("full-duplex") : ("half-duplex\n"));
576 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
577 eth_dev->data->port_id);
580 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
582 bnxt_print_link_info(eth_dev);
586 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
588 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
592 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
594 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
595 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
599 rc = bnxt_init_nic(bp);
603 bnxt_link_update_op(eth_dev, 1);
605 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
606 vlan_mask |= ETH_VLAN_FILTER_MASK;
607 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
608 vlan_mask |= ETH_VLAN_STRIP_MASK;
609 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
613 bp->flags |= BNXT_FLAG_INIT_DONE;
617 bnxt_shutdown_nic(bp);
618 bnxt_free_tx_mbufs(bp);
619 bnxt_free_rx_mbufs(bp);
623 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
625 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
628 if (!bp->link_info.link_up)
629 rc = bnxt_set_hwrm_link_config(bp, true);
631 eth_dev->data->dev_link.link_status = 1;
633 bnxt_print_link_info(eth_dev);
637 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
639 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
641 eth_dev->data->dev_link.link_status = 0;
642 bnxt_set_hwrm_link_config(bp, false);
643 bp->link_info.link_up = 0;
648 /* Unload the driver, release resources */
649 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
651 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
653 if (bp->eth_dev->data->dev_started) {
654 /* TBD: STOP HW queues DMA */
655 eth_dev->data->dev_link.link_status = 0;
657 bnxt_set_hwrm_link_config(bp, false);
658 bnxt_hwrm_port_clr_stats(bp);
659 bp->flags &= ~BNXT_FLAG_INIT_DONE;
660 bnxt_shutdown_nic(bp);
664 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
666 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
668 if (bp->dev_stopped == 0)
669 bnxt_dev_stop_op(eth_dev);
671 bnxt_free_tx_mbufs(bp);
672 bnxt_free_rx_mbufs(bp);
674 if (eth_dev->data->mac_addrs != NULL) {
675 rte_free(eth_dev->data->mac_addrs);
676 eth_dev->data->mac_addrs = NULL;
678 if (bp->grp_info != NULL) {
679 rte_free(bp->grp_info);
684 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
687 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
688 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
689 struct bnxt_vnic_info *vnic;
690 struct bnxt_filter_info *filter, *temp_filter;
691 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
695 * Loop through all VNICs from the specified filter flow pools to
696 * remove the corresponding MAC addr filter
698 for (i = 0; i < pool; i++) {
699 if (!(pool_mask & (1ULL << i)))
702 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
703 filter = STAILQ_FIRST(&vnic->filter);
705 temp_filter = STAILQ_NEXT(filter, next);
706 if (filter->mac_index == index) {
707 STAILQ_REMOVE(&vnic->filter, filter,
708 bnxt_filter_info, next);
709 bnxt_hwrm_clear_l2_filter(bp, filter);
710 filter->mac_index = INVALID_MAC_INDEX;
711 memset(&filter->l2_addr, 0,
714 &bp->free_filter_list,
717 filter = temp_filter;
723 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
724 struct ether_addr *mac_addr,
725 uint32_t index, uint32_t pool)
727 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
728 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
729 struct bnxt_filter_info *filter;
732 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
737 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
740 /* Attach requested MAC address to the new l2_filter */
741 STAILQ_FOREACH(filter, &vnic->filter, next) {
742 if (filter->mac_index == index) {
744 "MAC addr already existed for pool %d\n", pool);
748 filter = bnxt_alloc_filter(bp);
750 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
753 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
754 filter->mac_index = index;
755 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
756 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
759 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
762 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
763 struct rte_eth_link new;
764 unsigned int cnt = BNXT_LINK_WAIT_CNT;
766 memset(&new, 0, sizeof(new));
768 /* Retrieve link info from hardware */
769 rc = bnxt_get_hwrm_link_config(bp, &new);
771 new.link_speed = ETH_LINK_SPEED_100M;
772 new.link_duplex = ETH_LINK_FULL_DUPLEX;
774 "Failed to retrieve link rc = 0x%x!\n", rc);
777 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
779 if (!wait_to_complete)
781 } while (!new.link_status && cnt--);
784 /* Timed out or success */
785 if (new.link_status != eth_dev->data->dev_link.link_status ||
786 new.link_speed != eth_dev->data->dev_link.link_speed) {
787 memcpy(ð_dev->data->dev_link, &new,
788 sizeof(struct rte_eth_link));
789 bnxt_print_link_info(eth_dev);
795 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
797 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
798 struct bnxt_vnic_info *vnic;
800 if (bp->vnic_info == NULL)
803 vnic = &bp->vnic_info[0];
805 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
806 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
809 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
811 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
812 struct bnxt_vnic_info *vnic;
814 if (bp->vnic_info == NULL)
817 vnic = &bp->vnic_info[0];
819 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
820 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
823 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
825 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
826 struct bnxt_vnic_info *vnic;
828 if (bp->vnic_info == NULL)
831 vnic = &bp->vnic_info[0];
833 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
834 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
837 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
839 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
840 struct bnxt_vnic_info *vnic;
842 if (bp->vnic_info == NULL)
845 vnic = &bp->vnic_info[0];
847 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
848 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
851 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
852 struct rte_eth_rss_reta_entry64 *reta_conf,
855 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
856 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
857 struct bnxt_vnic_info *vnic;
860 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
863 if (reta_size != HW_HASH_INDEX_SIZE) {
864 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
865 "(%d) must equal the size supported by the hardware "
866 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
869 /* Update the RSS VNIC(s) */
870 for (i = 0; i < MAX_FF_POOLS; i++) {
871 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
872 memcpy(vnic->rss_table, reta_conf, reta_size);
874 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
880 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
881 struct rte_eth_rss_reta_entry64 *reta_conf,
884 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
885 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
886 struct rte_intr_handle *intr_handle
887 = &bp->pdev->intr_handle;
889 /* Retrieve from the default VNIC */
892 if (!vnic->rss_table)
895 if (reta_size != HW_HASH_INDEX_SIZE) {
896 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
897 "(%d) must equal the size supported by the hardware "
898 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
901 /* EW - need to revisit here copying from uint64_t to uint16_t */
902 memcpy(reta_conf, vnic->rss_table, reta_size);
904 if (rte_intr_allow_others(intr_handle)) {
905 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
906 bnxt_dev_lsc_intr_setup(eth_dev);
912 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
913 struct rte_eth_rss_conf *rss_conf)
915 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
916 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
917 struct bnxt_vnic_info *vnic;
918 uint16_t hash_type = 0;
922 * If RSS enablement were different than dev_configure,
923 * then return -EINVAL
925 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
926 if (!rss_conf->rss_hf)
927 RTE_LOG(ERR, PMD, "Hash type NONE\n");
929 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
933 bp->flags |= BNXT_FLAG_UPDATE_HASH;
934 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
936 if (rss_conf->rss_hf & ETH_RSS_IPV4)
937 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
938 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
939 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
940 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
941 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
942 if (rss_conf->rss_hf & ETH_RSS_IPV6)
943 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
944 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
945 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
946 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
947 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
949 /* Update the RSS VNIC(s) */
950 for (i = 0; i < MAX_FF_POOLS; i++) {
951 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
952 vnic->hash_type = hash_type;
955 * Use the supplied key if the key length is
956 * acceptable and the rss_key is not NULL
958 if (rss_conf->rss_key &&
959 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
960 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
961 rss_conf->rss_key_len);
963 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
969 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
970 struct rte_eth_rss_conf *rss_conf)
972 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
973 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
977 /* RSS configuration is the same for all VNICs */
978 if (vnic && vnic->rss_hash_key) {
979 if (rss_conf->rss_key) {
980 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
981 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
982 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
985 hash_types = vnic->hash_type;
986 rss_conf->rss_hf = 0;
987 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
988 rss_conf->rss_hf |= ETH_RSS_IPV4;
989 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
991 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
992 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
994 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
996 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
997 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
999 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1001 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1002 rss_conf->rss_hf |= ETH_RSS_IPV6;
1003 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1005 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1006 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1008 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1010 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1011 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1013 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1017 "Unknwon RSS config from firmware (%08x), RSS disabled",
1022 rss_conf->rss_hf = 0;
1027 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1028 struct rte_eth_fc_conf *fc_conf)
1030 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1031 struct rte_eth_link link_info;
1034 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1038 memset(fc_conf, 0, sizeof(*fc_conf));
1039 if (bp->link_info.auto_pause)
1040 fc_conf->autoneg = 1;
1041 switch (bp->link_info.pause) {
1043 fc_conf->mode = RTE_FC_NONE;
1045 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1046 fc_conf->mode = RTE_FC_TX_PAUSE;
1048 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1049 fc_conf->mode = RTE_FC_RX_PAUSE;
1051 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1052 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1053 fc_conf->mode = RTE_FC_FULL;
1059 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1060 struct rte_eth_fc_conf *fc_conf)
1062 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1064 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1065 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
1069 switch (fc_conf->mode) {
1071 bp->link_info.auto_pause = 0;
1072 bp->link_info.force_pause = 0;
1074 case RTE_FC_RX_PAUSE:
1075 if (fc_conf->autoneg) {
1076 bp->link_info.auto_pause =
1077 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1078 bp->link_info.force_pause = 0;
1080 bp->link_info.auto_pause = 0;
1081 bp->link_info.force_pause =
1082 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1085 case RTE_FC_TX_PAUSE:
1086 if (fc_conf->autoneg) {
1087 bp->link_info.auto_pause =
1088 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1089 bp->link_info.force_pause = 0;
1091 bp->link_info.auto_pause = 0;
1092 bp->link_info.force_pause =
1093 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1097 if (fc_conf->autoneg) {
1098 bp->link_info.auto_pause =
1099 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1100 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1101 bp->link_info.force_pause = 0;
1103 bp->link_info.auto_pause = 0;
1104 bp->link_info.force_pause =
1105 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1106 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1110 return bnxt_set_hwrm_link_config(bp, true);
1113 /* Add UDP tunneling port */
1115 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1116 struct rte_eth_udp_tunnel *udp_tunnel)
1118 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1119 uint16_t tunnel_type = 0;
1122 switch (udp_tunnel->prot_type) {
1123 case RTE_TUNNEL_TYPE_VXLAN:
1124 if (bp->vxlan_port_cnt) {
1125 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1126 udp_tunnel->udp_port);
1127 if (bp->vxlan_port != udp_tunnel->udp_port) {
1128 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1131 bp->vxlan_port_cnt++;
1135 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1136 bp->vxlan_port_cnt++;
1138 case RTE_TUNNEL_TYPE_GENEVE:
1139 if (bp->geneve_port_cnt) {
1140 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1141 udp_tunnel->udp_port);
1142 if (bp->geneve_port != udp_tunnel->udp_port) {
1143 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1146 bp->geneve_port_cnt++;
1150 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1151 bp->geneve_port_cnt++;
1154 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1157 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1163 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1164 struct rte_eth_udp_tunnel *udp_tunnel)
1166 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1167 uint16_t tunnel_type = 0;
1171 switch (udp_tunnel->prot_type) {
1172 case RTE_TUNNEL_TYPE_VXLAN:
1173 if (!bp->vxlan_port_cnt) {
1174 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1177 if (bp->vxlan_port != udp_tunnel->udp_port) {
1178 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1179 udp_tunnel->udp_port, bp->vxlan_port);
1182 if (--bp->vxlan_port_cnt)
1186 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1187 port = bp->vxlan_fw_dst_port_id;
1189 case RTE_TUNNEL_TYPE_GENEVE:
1190 if (!bp->geneve_port_cnt) {
1191 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1194 if (bp->geneve_port != udp_tunnel->udp_port) {
1195 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1196 udp_tunnel->udp_port, bp->geneve_port);
1199 if (--bp->geneve_port_cnt)
1203 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1204 port = bp->geneve_fw_dst_port_id;
1207 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1211 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1214 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1217 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1218 bp->geneve_port = 0;
1223 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1225 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1226 struct bnxt_vnic_info *vnic;
1229 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1231 /* Cycle through all VNICs */
1232 for (i = 0; i < bp->nr_vnics; i++) {
1234 * For each VNIC and each associated filter(s)
1235 * if VLAN exists && VLAN matches vlan_id
1236 * remove the MAC+VLAN filter
1237 * add a new MAC only filter
1239 * VLAN filter doesn't exist, just skip and continue
1241 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1242 filter = STAILQ_FIRST(&vnic->filter);
1244 temp_filter = STAILQ_NEXT(filter, next);
1246 if (filter->enables & chk &&
1247 filter->l2_ovlan == vlan_id) {
1248 /* Must delete the filter */
1249 STAILQ_REMOVE(&vnic->filter, filter,
1250 bnxt_filter_info, next);
1251 bnxt_hwrm_clear_l2_filter(bp, filter);
1253 &bp->free_filter_list,
1257 * Need to examine to see if the MAC
1258 * filter already existed or not before
1259 * allocating a new one
1262 new_filter = bnxt_alloc_filter(bp);
1265 "MAC/VLAN filter alloc failed\n");
1269 STAILQ_INSERT_TAIL(&vnic->filter,
1271 /* Inherit MAC from previous filter */
1272 new_filter->mac_index =
1274 memcpy(new_filter->l2_addr,
1275 filter->l2_addr, ETHER_ADDR_LEN);
1276 /* MAC only filter */
1277 rc = bnxt_hwrm_set_l2_filter(bp,
1283 "Del Vlan filter for %d\n",
1286 filter = temp_filter;
1294 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1296 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1297 struct bnxt_vnic_info *vnic;
1300 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1301 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1302 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1304 /* Cycle through all VNICs */
1305 for (i = 0; i < bp->nr_vnics; i++) {
1307 * For each VNIC and each associated filter(s)
1309 * if VLAN matches vlan_id
1310 * VLAN filter already exists, just skip and continue
1312 * add a new MAC+VLAN filter
1314 * Remove the old MAC only filter
1315 * Add a new MAC+VLAN filter
1317 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1318 filter = STAILQ_FIRST(&vnic->filter);
1320 temp_filter = STAILQ_NEXT(filter, next);
1322 if (filter->enables & chk) {
1323 if (filter->l2_ovlan == vlan_id)
1326 /* Must delete the MAC filter */
1327 STAILQ_REMOVE(&vnic->filter, filter,
1328 bnxt_filter_info, next);
1329 bnxt_hwrm_clear_l2_filter(bp, filter);
1330 filter->l2_ovlan = 0;
1332 &bp->free_filter_list,
1335 new_filter = bnxt_alloc_filter(bp);
1338 "MAC/VLAN filter alloc failed\n");
1342 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1344 /* Inherit MAC from the previous filter */
1345 new_filter->mac_index = filter->mac_index;
1346 memcpy(new_filter->l2_addr, filter->l2_addr,
1348 /* MAC + VLAN ID filter */
1349 new_filter->l2_ovlan = vlan_id;
1350 new_filter->l2_ovlan_mask = 0xF000;
1351 new_filter->enables |= en;
1352 rc = bnxt_hwrm_set_l2_filter(bp,
1358 "Added Vlan filter for %d\n", vlan_id);
1360 filter = temp_filter;
1368 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1369 uint16_t vlan_id, int on)
1371 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1373 /* These operations apply to ALL existing MAC/VLAN filters */
1375 return bnxt_add_vlan_filter(bp, vlan_id);
1377 return bnxt_del_vlan_filter(bp, vlan_id);
1381 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1383 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1386 if (mask & ETH_VLAN_FILTER_MASK) {
1387 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1388 /* Remove any VLAN filters programmed */
1389 for (i = 0; i < 4095; i++)
1390 bnxt_del_vlan_filter(bp, i);
1392 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1393 dev->data->dev_conf.rxmode.hw_vlan_filter);
1396 if (mask & ETH_VLAN_STRIP_MASK) {
1397 /* Enable or disable VLAN stripping */
1398 for (i = 0; i < bp->nr_vnics; i++) {
1399 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1400 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401 vnic->vlan_strip = true;
1403 vnic->vlan_strip = false;
1404 bnxt_hwrm_vnic_cfg(bp, vnic);
1406 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1407 dev->data->dev_conf.rxmode.hw_vlan_strip);
1410 if (mask & ETH_VLAN_EXTEND_MASK)
1411 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1417 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1419 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1420 /* Default Filter is tied to VNIC 0 */
1421 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1422 struct bnxt_filter_info *filter;
1428 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1430 STAILQ_FOREACH(filter, &vnic->filter, next) {
1431 /* Default Filter is at Index 0 */
1432 if (filter->mac_index != 0)
1434 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1437 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1438 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1439 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1441 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1442 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1443 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1446 filter->mac_index = 0;
1447 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1452 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1453 struct ether_addr *mc_addr_set,
1454 uint32_t nb_mc_addr)
1456 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1457 char *mc_addr_list = (char *)mc_addr_set;
1458 struct bnxt_vnic_info *vnic;
1459 uint32_t off = 0, i = 0;
1461 vnic = &bp->vnic_info[0];
1463 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1464 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1468 /* TODO Check for Duplicate mcast addresses */
1469 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1470 for (i = 0; i < nb_mc_addr; i++) {
1471 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1472 off += ETHER_ADDR_LEN;
1475 vnic->mc_addr_cnt = i;
1478 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1482 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1484 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1485 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1486 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1487 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1490 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1491 fw_major, fw_minor, fw_updt);
1493 ret += 1; /* add the size of '\0' */
1494 if (fw_size < (uint32_t)ret)
1501 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1502 struct rte_eth_rxq_info *qinfo)
1504 struct bnxt_rx_queue *rxq;
1506 rxq = dev->data->rx_queues[queue_id];
1508 qinfo->mp = rxq->mb_pool;
1509 qinfo->scattered_rx = dev->data->scattered_rx;
1510 qinfo->nb_desc = rxq->nb_rx_desc;
1512 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1513 qinfo->conf.rx_drop_en = 0;
1514 qinfo->conf.rx_deferred_start = 0;
1518 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1519 struct rte_eth_txq_info *qinfo)
1521 struct bnxt_tx_queue *txq;
1523 txq = dev->data->tx_queues[queue_id];
1525 qinfo->nb_desc = txq->nb_tx_desc;
1527 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1528 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1529 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1531 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1532 qinfo->conf.tx_rs_thresh = 0;
1533 qinfo->conf.txq_flags = txq->txq_flags;
1534 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1537 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1539 struct bnxt *bp = eth_dev->data->dev_private;
1540 struct rte_eth_dev_info dev_info;
1541 uint32_t max_dev_mtu;
1545 bnxt_dev_info_get_op(eth_dev, &dev_info);
1546 max_dev_mtu = dev_info.max_rx_pktlen -
1547 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1549 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1550 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1551 ETHER_MIN_MTU, max_dev_mtu);
1556 if (new_mtu > ETHER_MTU) {
1557 bp->flags |= BNXT_FLAG_JUMBO;
1558 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1560 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1561 bp->flags &= ~BNXT_FLAG_JUMBO;
1564 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1565 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1567 eth_dev->data->mtu = new_mtu;
1568 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1570 for (i = 0; i < bp->nr_vnics; i++) {
1571 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1573 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1574 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1575 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1579 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1588 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1590 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1591 uint16_t vlan = bp->vlan;
1594 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1596 "PVID cannot be modified for this function\n");
1599 bp->vlan = on ? pvid : 0;
1601 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1608 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1610 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1612 return bnxt_hwrm_port_led_cfg(bp, true);
1616 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1618 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1620 return bnxt_hwrm_port_led_cfg(bp, false);
1624 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1626 uint32_t desc = 0, raw_cons = 0, cons;
1627 struct bnxt_cp_ring_info *cpr;
1628 struct bnxt_rx_queue *rxq;
1629 struct rx_pkt_cmpl *rxcmp;
1634 rxq = dev->data->rx_queues[rx_queue_id];
1638 while (raw_cons < rxq->nb_rx_desc) {
1639 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1640 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1642 if (!CMPL_VALID(rxcmp, valid))
1644 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1645 cmp_type = CMP_TYPE(rxcmp);
1646 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1647 cmp = (rte_le_to_cpu_32(
1648 ((struct rx_tpa_end_cmpl *)
1649 (rxcmp))->agg_bufs_v1) &
1650 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1651 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1653 } else if (cmp_type == 0x11) {
1655 cmp = (rxcmp->agg_bufs_v1 &
1656 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1657 RX_PKT_CMPL_AGG_BUFS_SFT;
1662 raw_cons += cmp ? cmp : 2;
1669 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1671 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1672 struct bnxt_rx_ring_info *rxr;
1673 struct bnxt_cp_ring_info *cpr;
1674 struct bnxt_sw_rx_bd *rx_buf;
1675 struct rx_pkt_cmpl *rxcmp;
1676 uint32_t cons, cp_cons;
1684 if (offset >= rxq->nb_rx_desc)
1687 cons = RING_CMP(cpr->cp_ring_struct, offset);
1688 cp_cons = cpr->cp_raw_cons;
1689 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1691 if (cons > cp_cons) {
1692 if (CMPL_VALID(rxcmp, cpr->valid))
1693 return RTE_ETH_RX_DESC_DONE;
1695 if (CMPL_VALID(rxcmp, !cpr->valid))
1696 return RTE_ETH_RX_DESC_DONE;
1698 rx_buf = &rxr->rx_buf_ring[cons];
1699 if (rx_buf->mbuf == NULL)
1700 return RTE_ETH_RX_DESC_UNAVAIL;
1703 return RTE_ETH_RX_DESC_AVAIL;
1707 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1709 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1710 struct bnxt_tx_ring_info *txr;
1711 struct bnxt_cp_ring_info *cpr;
1712 struct bnxt_sw_tx_bd *tx_buf;
1713 struct tx_pkt_cmpl *txcmp;
1714 uint32_t cons, cp_cons;
1722 if (offset >= txq->nb_tx_desc)
1725 cons = RING_CMP(cpr->cp_ring_struct, offset);
1726 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1727 cp_cons = cpr->cp_raw_cons;
1729 if (cons > cp_cons) {
1730 if (CMPL_VALID(txcmp, cpr->valid))
1731 return RTE_ETH_TX_DESC_UNAVAIL;
1733 if (CMPL_VALID(txcmp, !cpr->valid))
1734 return RTE_ETH_TX_DESC_UNAVAIL;
1736 tx_buf = &txr->tx_buf_ring[cons];
1737 if (tx_buf->mbuf == NULL)
1738 return RTE_ETH_TX_DESC_DONE;
1740 return RTE_ETH_TX_DESC_FULL;
1743 static struct bnxt_filter_info *
1744 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1745 struct rte_eth_ethertype_filter *efilter,
1746 struct bnxt_vnic_info *vnic0,
1747 struct bnxt_vnic_info *vnic,
1750 struct bnxt_filter_info *mfilter = NULL;
1754 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1755 efilter->ether_type == ETHER_TYPE_IPv6) {
1756 RTE_LOG(ERR, PMD, "invalid ether_type(0x%04x) in"
1757 " ethertype filter.", efilter->ether_type);
1761 if (efilter->queue >= bp->rx_nr_rings) {
1762 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1767 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1768 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1770 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1775 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1776 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1777 if ((!memcmp(efilter->mac_addr.addr_bytes,
1778 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1780 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1781 mfilter->ethertype == efilter->ether_type)) {
1787 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1788 if ((!memcmp(efilter->mac_addr.addr_bytes,
1789 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1790 mfilter->ethertype == efilter->ether_type &&
1792 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1806 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1807 enum rte_filter_op filter_op,
1810 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1811 struct rte_eth_ethertype_filter *efilter =
1812 (struct rte_eth_ethertype_filter *)arg;
1813 struct bnxt_filter_info *bfilter, *filter1;
1814 struct bnxt_vnic_info *vnic, *vnic0;
1817 if (filter_op == RTE_ETH_FILTER_NOP)
1821 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
1826 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1827 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1829 switch (filter_op) {
1830 case RTE_ETH_FILTER_ADD:
1831 bnxt_match_and_validate_ether_filter(bp, efilter,
1836 bfilter = bnxt_get_unused_filter(bp);
1837 if (bfilter == NULL) {
1839 "Not enough resources for a new filter.\n");
1842 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1843 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1845 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1847 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1848 bfilter->ethertype = efilter->ether_type;
1849 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1851 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1852 if (filter1 == NULL) {
1857 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1858 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1860 bfilter->dst_id = vnic->fw_vnic_id;
1862 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1864 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1867 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1870 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1872 case RTE_ETH_FILTER_DELETE:
1873 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1875 if (ret == -EEXIST) {
1876 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1878 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1880 bnxt_free_filter(bp, filter1);
1881 } else if (ret == 0) {
1882 RTE_LOG(ERR, PMD, "No matching filter found\n");
1886 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
1892 bnxt_free_filter(bp, bfilter);
1898 parse_ntuple_filter(struct bnxt *bp,
1899 struct rte_eth_ntuple_filter *nfilter,
1900 struct bnxt_filter_info *bfilter)
1904 if (nfilter->queue >= bp->rx_nr_rings) {
1905 RTE_LOG(ERR, PMD, "Invalid queue %d\n", nfilter->queue);
1909 switch (nfilter->dst_port_mask) {
1911 bfilter->dst_port_mask = -1;
1912 bfilter->dst_port = nfilter->dst_port;
1913 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1914 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1917 RTE_LOG(ERR, PMD, "invalid dst_port mask.");
1921 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1922 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1924 switch (nfilter->proto_mask) {
1926 if (nfilter->proto == 17) /* IPPROTO_UDP */
1927 bfilter->ip_protocol = 17;
1928 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1929 bfilter->ip_protocol = 6;
1932 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1935 RTE_LOG(ERR, PMD, "invalid protocol mask.");
1939 switch (nfilter->dst_ip_mask) {
1941 bfilter->dst_ipaddr_mask[0] = -1;
1942 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1943 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1944 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1947 RTE_LOG(ERR, PMD, "invalid dst_ip mask.");
1951 switch (nfilter->src_ip_mask) {
1953 bfilter->src_ipaddr_mask[0] = -1;
1954 bfilter->src_ipaddr[0] = nfilter->src_ip;
1955 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1956 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1959 RTE_LOG(ERR, PMD, "invalid src_ip mask.");
1963 switch (nfilter->src_port_mask) {
1965 bfilter->src_port_mask = -1;
1966 bfilter->src_port = nfilter->src_port;
1967 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1968 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1971 RTE_LOG(ERR, PMD, "invalid src_port mask.");
1976 //nfilter->priority = (uint8_t)filter->priority;
1978 bfilter->enables = en;
1982 static struct bnxt_filter_info*
1983 bnxt_match_ntuple_filter(struct bnxt *bp,
1984 struct bnxt_filter_info *bfilter,
1985 struct bnxt_vnic_info **mvnic)
1987 struct bnxt_filter_info *mfilter = NULL;
1990 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1991 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1992 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1993 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1994 bfilter->src_ipaddr_mask[0] ==
1995 mfilter->src_ipaddr_mask[0] &&
1996 bfilter->src_port == mfilter->src_port &&
1997 bfilter->src_port_mask == mfilter->src_port_mask &&
1998 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1999 bfilter->dst_ipaddr_mask[0] ==
2000 mfilter->dst_ipaddr_mask[0] &&
2001 bfilter->dst_port == mfilter->dst_port &&
2002 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2003 bfilter->flags == mfilter->flags &&
2004 bfilter->enables == mfilter->enables) {
2015 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2016 struct rte_eth_ntuple_filter *nfilter,
2017 enum rte_filter_op filter_op)
2019 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2020 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2023 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2024 RTE_LOG(ERR, PMD, "only 5tuple is supported.");
2028 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2029 RTE_LOG(ERR, PMD, "Ntuple filter: TCP flags not supported\n");
2033 bfilter = bnxt_get_unused_filter(bp);
2034 if (bfilter == NULL) {
2036 "Not enough resources for a new filter.\n");
2039 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2043 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2044 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2045 filter1 = STAILQ_FIRST(&vnic0->filter);
2046 if (filter1 == NULL) {
2051 bfilter->dst_id = vnic->fw_vnic_id;
2052 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2054 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2055 bfilter->ethertype = 0x800;
2056 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2058 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2060 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2061 bfilter->dst_id == mfilter->dst_id) {
2062 RTE_LOG(ERR, PMD, "filter exists.\n");
2065 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2066 bfilter->dst_id != mfilter->dst_id) {
2067 mfilter->dst_id = vnic->fw_vnic_id;
2068 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2069 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2070 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2071 RTE_LOG(ERR, PMD, "filter with matching pattern exists.\n");
2072 RTE_LOG(ERR, PMD, " Updated it to the new destination queue\n");
2075 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2076 RTE_LOG(ERR, PMD, "filter doesn't exist.");
2081 if (filter_op == RTE_ETH_FILTER_ADD) {
2082 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2083 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2086 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2088 if (mfilter == NULL) {
2089 /* This should not happen. But for Coverity! */
2093 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2095 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2096 bnxt_free_filter(bp, mfilter);
2097 mfilter->fw_l2_filter_id = -1;
2098 bnxt_free_filter(bp, bfilter);
2099 bfilter->fw_l2_filter_id = -1;
2104 bfilter->fw_l2_filter_id = -1;
2105 bnxt_free_filter(bp, bfilter);
2110 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2111 enum rte_filter_op filter_op,
2114 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2117 if (filter_op == RTE_ETH_FILTER_NOP)
2121 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
2126 switch (filter_op) {
2127 case RTE_ETH_FILTER_ADD:
2128 ret = bnxt_cfg_ntuple_filter(bp,
2129 (struct rte_eth_ntuple_filter *)arg,
2132 case RTE_ETH_FILTER_DELETE:
2133 ret = bnxt_cfg_ntuple_filter(bp,
2134 (struct rte_eth_ntuple_filter *)arg,
2138 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
2146 bnxt_parse_fdir_filter(struct bnxt *bp,
2147 struct rte_eth_fdir_filter *fdir,
2148 struct bnxt_filter_info *filter)
2150 enum rte_fdir_mode fdir_mode =
2151 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2152 struct bnxt_vnic_info *vnic0, *vnic;
2153 struct bnxt_filter_info *filter1;
2157 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2160 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2161 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2163 switch (fdir->input.flow_type) {
2164 case RTE_ETH_FLOW_IPV4:
2165 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2167 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2168 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2169 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2171 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2172 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2173 filter->ip_addr_type =
2174 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2175 filter->src_ipaddr_mask[0] = 0xffffffff;
2176 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2177 filter->dst_ipaddr_mask[0] = 0xffffffff;
2178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2179 filter->ethertype = 0x800;
2180 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2182 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2183 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2184 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2185 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2187 filter->dst_port_mask = 0xffff;
2188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2189 filter->src_port_mask = 0xffff;
2190 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2191 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2192 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2193 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2194 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2195 filter->ip_protocol = 6;
2196 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2197 filter->ip_addr_type =
2198 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2199 filter->src_ipaddr_mask[0] = 0xffffffff;
2200 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2201 filter->dst_ipaddr_mask[0] = 0xffffffff;
2202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2203 filter->ethertype = 0x800;
2204 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2206 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2207 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2209 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2211 filter->dst_port_mask = 0xffff;
2212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2213 filter->src_port_mask = 0xffff;
2214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2215 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2216 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2217 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2219 filter->ip_protocol = 17;
2220 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2221 filter->ip_addr_type =
2222 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2223 filter->src_ipaddr_mask[0] = 0xffffffff;
2224 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2225 filter->dst_ipaddr_mask[0] = 0xffffffff;
2226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2227 filter->ethertype = 0x800;
2228 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2230 case RTE_ETH_FLOW_IPV6:
2231 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2233 filter->ip_addr_type =
2234 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2235 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2236 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2237 rte_memcpy(filter->src_ipaddr,
2238 fdir->input.flow.ipv6_flow.src_ip, 16);
2239 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2240 rte_memcpy(filter->dst_ipaddr,
2241 fdir->input.flow.ipv6_flow.dst_ip, 16);
2242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2243 memset(filter->dst_ipaddr_mask, 0xff, 16);
2244 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2245 memset(filter->src_ipaddr_mask, 0xff, 16);
2246 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2247 filter->ethertype = 0x86dd;
2248 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2250 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2251 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2253 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2255 filter->dst_port_mask = 0xffff;
2256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2257 filter->src_port_mask = 0xffff;
2258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2259 filter->ip_addr_type =
2260 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2261 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2262 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2263 rte_memcpy(filter->src_ipaddr,
2264 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2266 rte_memcpy(filter->dst_ipaddr,
2267 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2268 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2269 memset(filter->dst_ipaddr_mask, 0xff, 16);
2270 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2271 memset(filter->src_ipaddr_mask, 0xff, 16);
2272 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2273 filter->ethertype = 0x86dd;
2274 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2276 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2277 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2278 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2279 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2280 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2281 filter->dst_port_mask = 0xffff;
2282 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2283 filter->src_port_mask = 0xffff;
2284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2285 filter->ip_addr_type =
2286 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2287 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2288 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2289 rte_memcpy(filter->src_ipaddr,
2290 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2292 rte_memcpy(filter->dst_ipaddr,
2293 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2294 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2295 memset(filter->dst_ipaddr_mask, 0xff, 16);
2296 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2297 memset(filter->src_ipaddr_mask, 0xff, 16);
2298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2299 filter->ethertype = 0x86dd;
2300 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2302 case RTE_ETH_FLOW_L2_PAYLOAD:
2303 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2304 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2306 case RTE_ETH_FLOW_VXLAN:
2307 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2309 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2310 filter->tunnel_type =
2311 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2312 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2314 case RTE_ETH_FLOW_NVGRE:
2315 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2317 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2318 filter->tunnel_type =
2319 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2320 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2322 case RTE_ETH_FLOW_UNKNOWN:
2323 case RTE_ETH_FLOW_RAW:
2324 case RTE_ETH_FLOW_FRAG_IPV4:
2325 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2326 case RTE_ETH_FLOW_FRAG_IPV6:
2327 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2328 case RTE_ETH_FLOW_IPV6_EX:
2329 case RTE_ETH_FLOW_IPV6_TCP_EX:
2330 case RTE_ETH_FLOW_IPV6_UDP_EX:
2331 case RTE_ETH_FLOW_GENEVE:
2337 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2338 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2340 RTE_LOG(ERR, PMD, "Invalid queue %d\n", fdir->action.rx_queue);
2345 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2346 rte_memcpy(filter->dst_macaddr,
2347 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2348 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2351 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2352 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2353 filter1 = STAILQ_FIRST(&vnic0->filter);
2354 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2356 filter->dst_id = vnic->fw_vnic_id;
2357 for (i = 0; i < ETHER_ADDR_LEN; i++)
2358 if (filter->dst_macaddr[i] == 0x00)
2359 filter1 = STAILQ_FIRST(&vnic0->filter);
2361 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2364 if (filter1 == NULL)
2367 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2368 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2370 filter->enables = en;
2375 static struct bnxt_filter_info *
2376 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf)
2378 struct bnxt_filter_info *mf = NULL;
2381 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2382 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2384 STAILQ_FOREACH(mf, &vnic->filter, next) {
2385 if (mf->filter_type == nf->filter_type &&
2386 mf->flags == nf->flags &&
2387 mf->src_port == nf->src_port &&
2388 mf->src_port_mask == nf->src_port_mask &&
2389 mf->dst_port == nf->dst_port &&
2390 mf->dst_port_mask == nf->dst_port_mask &&
2391 mf->ip_protocol == nf->ip_protocol &&
2392 mf->ip_addr_type == nf->ip_addr_type &&
2393 mf->ethertype == nf->ethertype &&
2394 mf->vni == nf->vni &&
2395 mf->tunnel_type == nf->tunnel_type &&
2396 mf->l2_ovlan == nf->l2_ovlan &&
2397 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2398 mf->l2_ivlan == nf->l2_ivlan &&
2399 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2400 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2401 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2403 !memcmp(mf->src_macaddr, nf->src_macaddr,
2405 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2407 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2408 sizeof(nf->src_ipaddr)) &&
2409 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2410 sizeof(nf->src_ipaddr_mask)) &&
2411 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2412 sizeof(nf->dst_ipaddr)) &&
2413 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2414 sizeof(nf->dst_ipaddr_mask)))
2422 bnxt_fdir_filter(struct rte_eth_dev *dev,
2423 enum rte_filter_op filter_op,
2426 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2427 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2428 struct bnxt_filter_info *filter, *match;
2429 struct bnxt_vnic_info *vnic;
2432 if (filter_op == RTE_ETH_FILTER_NOP)
2435 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2438 switch (filter_op) {
2439 case RTE_ETH_FILTER_ADD:
2440 case RTE_ETH_FILTER_DELETE:
2442 filter = bnxt_get_unused_filter(bp);
2443 if (filter == NULL) {
2445 "Not enough resources for a new flow.\n");
2449 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2452 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2454 match = bnxt_match_fdir(bp, filter);
2455 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2456 RTE_LOG(ERR, PMD, "Flow already exists.\n");
2460 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2461 RTE_LOG(ERR, PMD, "Flow does not exist.\n");
2466 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2467 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2470 STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2472 if (filter_op == RTE_ETH_FILTER_ADD) {
2473 ret = bnxt_hwrm_set_ntuple_filter(bp,
2478 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2480 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2481 STAILQ_REMOVE(&vnic->filter, match,
2482 bnxt_filter_info, next);
2483 bnxt_free_filter(bp, match);
2484 filter->fw_l2_filter_id = -1;
2485 bnxt_free_filter(bp, filter);
2488 case RTE_ETH_FILTER_FLUSH:
2489 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2490 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2492 STAILQ_FOREACH(filter, &vnic->filter, next) {
2493 if (filter->filter_type ==
2494 HWRM_CFA_NTUPLE_FILTER) {
2496 bnxt_hwrm_clear_ntuple_filter(bp,
2498 STAILQ_REMOVE(&vnic->filter, filter,
2499 bnxt_filter_info, next);
2504 case RTE_ETH_FILTER_UPDATE:
2505 case RTE_ETH_FILTER_STATS:
2506 case RTE_ETH_FILTER_INFO:
2508 RTE_LOG(ERR, PMD, "operation %u not implemented", filter_op);
2511 RTE_LOG(ERR, PMD, "unknown operation %u", filter_op);
2518 filter->fw_l2_filter_id = -1;
2519 bnxt_free_filter(bp, filter);
2524 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2525 enum rte_filter_type filter_type,
2526 enum rte_filter_op filter_op, void *arg)
2530 switch (filter_type) {
2531 case RTE_ETH_FILTER_TUNNEL:
2533 "filter type: %d: To be implemented\n", filter_type);
2535 case RTE_ETH_FILTER_FDIR:
2536 ret = bnxt_fdir_filter(dev, filter_op, arg);
2538 case RTE_ETH_FILTER_NTUPLE:
2539 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2541 case RTE_ETH_FILTER_ETHERTYPE:
2542 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2544 case RTE_ETH_FILTER_GENERIC:
2545 if (filter_op != RTE_ETH_FILTER_GET)
2547 *(const void **)arg = &bnxt_flow_ops;
2551 "Filter type (%d) not supported", filter_type);
2558 static const uint32_t *
2559 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2561 static const uint32_t ptypes[] = {
2562 RTE_PTYPE_L2_ETHER_VLAN,
2563 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2564 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2568 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2569 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2570 RTE_PTYPE_INNER_L4_ICMP,
2571 RTE_PTYPE_INNER_L4_TCP,
2572 RTE_PTYPE_INNER_L4_UDP,
2576 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2581 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2584 uint32_t reg_base = *reg_arr & 0xfffff000;
2588 for (i = 0; i < count; i++) {
2589 if ((reg_arr[i] & 0xfffff000) != reg_base)
2592 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2593 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2597 static int bnxt_map_ptp_regs(struct bnxt *bp)
2599 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2603 reg_arr = ptp->rx_regs;
2604 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2608 reg_arr = ptp->tx_regs;
2609 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2613 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2614 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2616 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2617 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2622 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2624 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2625 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2626 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2627 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2630 static uint64_t bnxt_cc_read(struct bnxt *bp)
2634 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2635 BNXT_GRCPF_REG_SYNC_TIME));
2636 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2637 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2641 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2643 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2646 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2647 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2648 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2651 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2652 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2653 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2654 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2655 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2656 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2661 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2663 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2664 struct bnxt_pf_info *pf = &bp->pf;
2671 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2672 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2673 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2676 port_id = pf->port_id;
2677 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2678 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2680 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2681 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2682 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2683 /* bnxt_clr_rx_ts(bp); TBD */
2687 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2688 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2689 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2690 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2696 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2699 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2700 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2705 ns = rte_timespec_to_ns(ts);
2706 /* Set the timecounters to a new value. */
2713 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2715 uint64_t ns, systime_cycles;
2716 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2717 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2722 systime_cycles = bnxt_cc_read(bp);
2723 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2724 *ts = rte_ns_to_timespec(ns);
2729 bnxt_timesync_enable(struct rte_eth_dev *dev)
2731 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2732 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2739 ptp->tx_tstamp_en = 1;
2740 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2742 if (!bnxt_hwrm_ptp_cfg(bp))
2743 bnxt_map_ptp_regs(bp);
2745 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2746 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2747 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2749 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2750 ptp->tc.cc_shift = shift;
2751 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2753 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2754 ptp->rx_tstamp_tc.cc_shift = shift;
2755 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2757 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2758 ptp->tx_tstamp_tc.cc_shift = shift;
2759 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2765 bnxt_timesync_disable(struct rte_eth_dev *dev)
2767 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2768 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2774 ptp->tx_tstamp_en = 0;
2777 bnxt_hwrm_ptp_cfg(bp);
2779 bnxt_unmap_ptp_regs(bp);
2785 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2786 struct timespec *timestamp,
2787 uint32_t flags __rte_unused)
2789 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2790 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2791 uint64_t rx_tstamp_cycles = 0;
2797 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2798 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2799 *timestamp = rte_ns_to_timespec(ns);
2804 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2805 struct timespec *timestamp)
2807 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2808 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2809 uint64_t tx_tstamp_cycles = 0;
2815 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2816 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2817 *timestamp = rte_ns_to_timespec(ns);
2823 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2825 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2826 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2831 ptp->tc.nsec += delta;
2837 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2839 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2841 uint32_t dir_entries;
2842 uint32_t entry_length;
2844 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n",
2845 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus,
2846 bp->pdev->addr.devid, bp->pdev->addr.function);
2848 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2852 return dir_entries * entry_length;
2856 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2857 struct rte_dev_eeprom_info *in_eeprom)
2859 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2863 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2864 "len = %d\n", __func__, bp->pdev->addr.domain,
2865 bp->pdev->addr.bus, bp->pdev->addr.devid,
2866 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2868 if (in_eeprom->offset == 0) /* special offset value to get directory */
2869 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2872 index = in_eeprom->offset >> 24;
2873 offset = in_eeprom->offset & 0xffffff;
2876 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2877 in_eeprom->length, in_eeprom->data);
2882 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2885 case BNX_DIR_TYPE_CHIMP_PATCH:
2886 case BNX_DIR_TYPE_BOOTCODE:
2887 case BNX_DIR_TYPE_BOOTCODE_2:
2888 case BNX_DIR_TYPE_APE_FW:
2889 case BNX_DIR_TYPE_APE_PATCH:
2890 case BNX_DIR_TYPE_KONG_FW:
2891 case BNX_DIR_TYPE_KONG_PATCH:
2892 case BNX_DIR_TYPE_BONO_FW:
2893 case BNX_DIR_TYPE_BONO_PATCH:
2900 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2903 case BNX_DIR_TYPE_AVS:
2904 case BNX_DIR_TYPE_EXP_ROM_MBA:
2905 case BNX_DIR_TYPE_PCIE:
2906 case BNX_DIR_TYPE_TSCF_UCODE:
2907 case BNX_DIR_TYPE_EXT_PHY:
2908 case BNX_DIR_TYPE_CCM:
2909 case BNX_DIR_TYPE_ISCSI_BOOT:
2910 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2911 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2918 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2920 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2921 bnxt_dir_type_is_other_exec_format(dir_type);
2925 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2926 struct rte_dev_eeprom_info *in_eeprom)
2928 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2929 uint8_t index, dir_op;
2930 uint16_t type, ext, ordinal, attr;
2932 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2933 "len = %d\n", __func__, bp->pdev->addr.domain,
2934 bp->pdev->addr.bus, bp->pdev->addr.devid,
2935 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2938 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n");
2942 type = in_eeprom->magic >> 16;
2944 if (type == 0xffff) { /* special value for directory operations */
2945 index = in_eeprom->magic & 0xff;
2946 dir_op = in_eeprom->magic >> 8;
2950 case 0x0e: /* erase */
2951 if (in_eeprom->offset != ~in_eeprom->magic)
2953 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2959 /* Create or re-write an NVM item: */
2960 if (bnxt_dir_type_is_executable(type) == true)
2962 ext = in_eeprom->magic & 0xffff;
2963 ordinal = in_eeprom->offset >> 16;
2964 attr = in_eeprom->offset & 0xffff;
2966 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2967 in_eeprom->data, in_eeprom->length);
2975 static const struct eth_dev_ops bnxt_dev_ops = {
2976 .dev_infos_get = bnxt_dev_info_get_op,
2977 .dev_close = bnxt_dev_close_op,
2978 .dev_configure = bnxt_dev_configure_op,
2979 .dev_start = bnxt_dev_start_op,
2980 .dev_stop = bnxt_dev_stop_op,
2981 .dev_set_link_up = bnxt_dev_set_link_up_op,
2982 .dev_set_link_down = bnxt_dev_set_link_down_op,
2983 .stats_get = bnxt_stats_get_op,
2984 .stats_reset = bnxt_stats_reset_op,
2985 .rx_queue_setup = bnxt_rx_queue_setup_op,
2986 .rx_queue_release = bnxt_rx_queue_release_op,
2987 .tx_queue_setup = bnxt_tx_queue_setup_op,
2988 .tx_queue_release = bnxt_tx_queue_release_op,
2989 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
2990 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
2991 .reta_update = bnxt_reta_update_op,
2992 .reta_query = bnxt_reta_query_op,
2993 .rss_hash_update = bnxt_rss_hash_update_op,
2994 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
2995 .link_update = bnxt_link_update_op,
2996 .promiscuous_enable = bnxt_promiscuous_enable_op,
2997 .promiscuous_disable = bnxt_promiscuous_disable_op,
2998 .allmulticast_enable = bnxt_allmulticast_enable_op,
2999 .allmulticast_disable = bnxt_allmulticast_disable_op,
3000 .mac_addr_add = bnxt_mac_addr_add_op,
3001 .mac_addr_remove = bnxt_mac_addr_remove_op,
3002 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3003 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3004 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3005 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3006 .vlan_filter_set = bnxt_vlan_filter_set_op,
3007 .vlan_offload_set = bnxt_vlan_offload_set_op,
3008 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3009 .mtu_set = bnxt_mtu_set_op,
3010 .mac_addr_set = bnxt_set_default_mac_addr_op,
3011 .xstats_get = bnxt_dev_xstats_get_op,
3012 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3013 .xstats_reset = bnxt_dev_xstats_reset_op,
3014 .fw_version_get = bnxt_fw_version_get,
3015 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3016 .rxq_info_get = bnxt_rxq_info_get_op,
3017 .txq_info_get = bnxt_txq_info_get_op,
3018 .dev_led_on = bnxt_dev_led_on_op,
3019 .dev_led_off = bnxt_dev_led_off_op,
3020 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3021 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3022 .rx_queue_count = bnxt_rx_queue_count_op,
3023 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3024 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3025 .filter_ctrl = bnxt_filter_ctrl_op,
3026 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3027 .get_eeprom_length = bnxt_get_eeprom_length_op,
3028 .get_eeprom = bnxt_get_eeprom_op,
3029 .set_eeprom = bnxt_set_eeprom_op,
3030 .timesync_enable = bnxt_timesync_enable,
3031 .timesync_disable = bnxt_timesync_disable,
3032 .timesync_read_time = bnxt_timesync_read_time,
3033 .timesync_write_time = bnxt_timesync_write_time,
3034 .timesync_adjust_time = bnxt_timesync_adjust_time,
3035 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3036 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3039 static bool bnxt_vf_pciid(uint16_t id)
3041 if (id == BROADCOM_DEV_ID_57304_VF ||
3042 id == BROADCOM_DEV_ID_57406_VF ||
3043 id == BROADCOM_DEV_ID_5731X_VF ||
3044 id == BROADCOM_DEV_ID_5741X_VF ||
3045 id == BROADCOM_DEV_ID_57414_VF ||
3046 id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
3051 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3053 struct bnxt *bp = eth_dev->data->dev_private;
3054 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3057 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3058 if (!pci_dev->mem_resource[0].addr) {
3060 "Cannot find PCI device base address, aborting\n");
3062 goto init_err_disable;
3065 bp->eth_dev = eth_dev;
3068 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3070 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
3072 goto init_err_release;
3085 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3087 #define ALLOW_FUNC(x) \
3089 typeof(x) arg = (x); \
3090 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3091 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3094 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3096 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3097 char mz_name[RTE_MEMZONE_NAMESIZE];
3098 const struct rte_memzone *mz = NULL;
3099 static int version_printed;
3100 uint32_t total_alloc_len;
3101 rte_iova_t mz_phys_addr;
3105 if (version_printed++ == 0)
3106 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
3108 rte_eth_copy_pci_info(eth_dev, pci_dev);
3110 bp = eth_dev->data->dev_private;
3112 rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
3113 bp->dev_stopped = 1;
3115 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3118 if (bnxt_vf_pciid(pci_dev->id.device_id))
3119 bp->flags |= BNXT_FLAG_VF;
3121 rc = bnxt_init_board(eth_dev);
3124 "Board initialization failed rc: %x\n", rc);
3128 eth_dev->dev_ops = &bnxt_dev_ops;
3129 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3131 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3132 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3134 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3135 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3136 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3137 pci_dev->addr.bus, pci_dev->addr.devid,
3138 pci_dev->addr.function, "rx_port_stats");
3139 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3140 mz = rte_memzone_lookup(mz_name);
3141 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3142 sizeof(struct rx_port_stats) + 512);
3144 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3147 RTE_MEMZONE_SIZE_HINT_ONLY);
3151 memset(mz->addr, 0, mz->len);
3152 mz_phys_addr = mz->iova;
3153 if ((unsigned long)mz->addr == mz_phys_addr) {
3154 RTE_LOG(WARNING, PMD,
3155 "Memzone physical address same as virtual.\n");
3156 RTE_LOG(WARNING, PMD,
3157 "Using rte_mem_virt2iova()\n");
3158 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3159 if (mz_phys_addr == 0) {
3161 "unable to map address to physical memory\n");
3166 bp->rx_mem_zone = (const void *)mz;
3167 bp->hw_rx_port_stats = mz->addr;
3168 bp->hw_rx_port_stats_map = mz_phys_addr;
3170 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3171 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3172 pci_dev->addr.bus, pci_dev->addr.devid,
3173 pci_dev->addr.function, "tx_port_stats");
3174 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3175 mz = rte_memzone_lookup(mz_name);
3176 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3177 sizeof(struct tx_port_stats) + 512);
3179 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3182 RTE_MEMZONE_SIZE_HINT_ONLY);
3186 memset(mz->addr, 0, mz->len);
3187 mz_phys_addr = mz->iova;
3188 if ((unsigned long)mz->addr == mz_phys_addr) {
3189 RTE_LOG(WARNING, PMD,
3190 "Memzone physical address same as virtual.\n");
3191 RTE_LOG(WARNING, PMD,
3192 "Using rte_mem_virt2iova()\n");
3193 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3194 if (mz_phys_addr == 0) {
3196 "unable to map address to physical memory\n");
3201 bp->tx_mem_zone = (const void *)mz;
3202 bp->hw_tx_port_stats = mz->addr;
3203 bp->hw_tx_port_stats_map = mz_phys_addr;
3205 bp->flags |= BNXT_FLAG_PORT_STATS;
3208 rc = bnxt_alloc_hwrm_resources(bp);
3211 "hwrm resource allocation failure rc: %x\n", rc);
3214 rc = bnxt_hwrm_ver_get(bp);
3217 rc = bnxt_hwrm_queue_qportcfg(bp);
3219 RTE_LOG(ERR, PMD, "hwrm queue qportcfg failed\n");
3223 rc = bnxt_hwrm_func_qcfg(bp);
3225 RTE_LOG(ERR, PMD, "hwrm func qcfg failed\n");
3229 /* Get the MAX capabilities for this function */
3230 rc = bnxt_hwrm_func_qcaps(bp);
3232 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
3235 if (bp->max_tx_rings == 0) {
3236 RTE_LOG(ERR, PMD, "No TX rings available!\n");
3240 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3241 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3242 if (eth_dev->data->mac_addrs == NULL) {
3244 "Failed to alloc %u bytes needed to store MAC addr tbl",
3245 ETHER_ADDR_LEN * bp->max_l2_ctx);
3249 /* Copy the permanent MAC from the qcap response address now. */
3250 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3251 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3253 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3254 /* 1 ring is for default completion ring */
3255 RTE_LOG(ERR, PMD, "Insufficient resource: Ring Group\n");
3260 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3261 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3262 if (!bp->grp_info) {
3264 "Failed to alloc %zu bytes to store group info table\n",
3265 sizeof(*bp->grp_info) * bp->max_ring_grps);
3270 /* Forward all requests if firmware is new enough */
3271 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3272 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3273 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3274 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3276 RTE_LOG(WARNING, PMD,
3277 "Firmware too old for VF mailbox functionality\n");
3278 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3282 * The following are used for driver cleanup. If we disallow these,
3283 * VF drivers can't clean up cleanly.
3285 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3286 ALLOW_FUNC(HWRM_VNIC_FREE);
3287 ALLOW_FUNC(HWRM_RING_FREE);
3288 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3289 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3290 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3291 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3292 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3293 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3294 rc = bnxt_hwrm_func_driver_register(bp);
3297 "Failed to register driver");
3303 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3304 pci_dev->mem_resource[0].phys_addr,
3305 pci_dev->mem_resource[0].addr);
3307 rc = bnxt_hwrm_func_reset(bp);
3309 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
3315 //if (bp->pf.active_vfs) {
3316 // TODO: Deallocate VF resources?
3318 if (bp->pdev->max_vfs) {
3319 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3321 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
3325 rc = bnxt_hwrm_allocate_pf_only(bp);
3328 "Failed to allocate PF resources\n");
3334 bnxt_hwrm_port_led_qcaps(bp);
3336 rc = bnxt_setup_int(bp);
3340 rc = bnxt_alloc_mem(bp);
3342 goto error_free_int;
3344 rc = bnxt_request_int(bp);
3346 goto error_free_int;
3348 rc = bnxt_alloc_def_cp_ring(bp);
3350 goto error_free_int;
3352 bnxt_enable_int(bp);
3357 bnxt_disable_int(bp);
3358 bnxt_free_def_cp_ring(bp);
3359 bnxt_hwrm_func_buf_unrgtr(bp);
3363 bnxt_dev_uninit(eth_dev);
3369 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3370 struct bnxt *bp = eth_dev->data->dev_private;
3373 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3376 bnxt_disable_int(bp);
3379 if (eth_dev->data->mac_addrs != NULL) {
3380 rte_free(eth_dev->data->mac_addrs);
3381 eth_dev->data->mac_addrs = NULL;
3383 if (bp->grp_info != NULL) {
3384 rte_free(bp->grp_info);
3385 bp->grp_info = NULL;
3387 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3388 bnxt_free_hwrm_resources(bp);
3389 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3390 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3391 if (bp->dev_stopped == 0)
3392 bnxt_dev_close_op(eth_dev);
3394 rte_free(bp->pf.vf_info);
3395 eth_dev->dev_ops = NULL;
3396 eth_dev->rx_pkt_burst = NULL;
3397 eth_dev->tx_pkt_burst = NULL;
3402 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3403 struct rte_pci_device *pci_dev)
3405 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3409 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3411 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3414 static struct rte_pci_driver bnxt_rte_pmd = {
3415 .id_table = bnxt_pci_id_map,
3416 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3417 RTE_PCI_DRV_INTR_LSC,
3418 .probe = bnxt_pci_probe,
3419 .remove = bnxt_pci_remove,
3423 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3425 if (strcmp(dev->device->driver->name, drv->driver.name))
3431 bool is_bnxt_supported(struct rte_eth_dev *dev)
3433 return is_device_supported(dev, &bnxt_rte_pmd);
3436 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3437 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3438 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");