4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
57 #define DRV_MODULE_NAME "bnxt"
58 static const char bnxt_version[] =
59 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
63 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
64 #define BROADCOM_DEV_ID_57414_VF 0x16c1
65 #define BROADCOM_DEV_ID_57301 0x16c8
66 #define BROADCOM_DEV_ID_57302 0x16c9
67 #define BROADCOM_DEV_ID_57304_PF 0x16ca
68 #define BROADCOM_DEV_ID_57304_VF 0x16cb
69 #define BROADCOM_DEV_ID_57417_MF 0x16cc
70 #define BROADCOM_DEV_ID_NS2 0x16cd
71 #define BROADCOM_DEV_ID_57311 0x16ce
72 #define BROADCOM_DEV_ID_57312 0x16cf
73 #define BROADCOM_DEV_ID_57402 0x16d0
74 #define BROADCOM_DEV_ID_57404 0x16d1
75 #define BROADCOM_DEV_ID_57406_PF 0x16d2
76 #define BROADCOM_DEV_ID_57406_VF 0x16d3
77 #define BROADCOM_DEV_ID_57402_MF 0x16d4
78 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
79 #define BROADCOM_DEV_ID_57412 0x16d6
80 #define BROADCOM_DEV_ID_57414 0x16d7
81 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
82 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
83 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
84 #define BROADCOM_DEV_ID_57412_MF 0x16de
85 #define BROADCOM_DEV_ID_57314 0x16df
86 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
87 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
88 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
89 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
90 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
91 #define BROADCOM_DEV_ID_57404_MF 0x16e7
92 #define BROADCOM_DEV_ID_57406_MF 0x16e8
93 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
94 #define BROADCOM_DEV_ID_57407_MF 0x16ea
95 #define BROADCOM_DEV_ID_57414_MF 0x16ec
96 #define BROADCOM_DEV_ID_57416_MF 0x16ee
98 static const struct rte_pci_id bnxt_pci_id_map[] = {
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
145 /***********************/
148 * High level utility functions
151 static void bnxt_free_mem(struct bnxt *bp)
153 bnxt_free_filter_mem(bp);
154 bnxt_free_vnic_attributes(bp);
155 bnxt_free_vnic_mem(bp);
158 bnxt_free_tx_rings(bp);
159 bnxt_free_rx_rings(bp);
160 bnxt_free_def_cp_ring(bp);
163 static int bnxt_alloc_mem(struct bnxt *bp)
167 /* Default completion ring */
168 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
172 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
173 bp->def_cp_ring, "def_cp");
177 rc = bnxt_alloc_vnic_mem(bp);
181 rc = bnxt_alloc_vnic_attributes(bp);
185 rc = bnxt_alloc_filter_mem(bp);
196 static int bnxt_init_chip(struct bnxt *bp)
198 unsigned int i, rss_idx, fw_idx;
199 struct rte_eth_link new;
202 if (bp->eth_dev->data->mtu > ETHER_MTU) {
203 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
204 bp->flags |= BNXT_FLAG_JUMBO;
206 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
207 bp->flags &= ~BNXT_FLAG_JUMBO;
210 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
212 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
216 rc = bnxt_alloc_hwrm_rings(bp);
218 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
222 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
224 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
228 rc = bnxt_mq_rx_configure(bp);
230 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
234 /* VNIC configuration */
235 for (i = 0; i < bp->nr_vnics; i++) {
236 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
238 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
240 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
245 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
248 "HWRM vnic %d ctx alloc failure rc: %x\n",
253 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
255 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
260 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
263 "HWRM vnic %d filter failure rc: %x\n",
267 if (vnic->rss_table && vnic->hash_type) {
269 * Fill the RSS hash & redirection table with
270 * ring group ids for all VNICs
272 for (rss_idx = 0, fw_idx = 0;
273 rss_idx < HW_HASH_INDEX_SIZE;
274 rss_idx++, fw_idx++) {
275 if (vnic->fw_grp_ids[fw_idx] ==
278 vnic->rss_table[rss_idx] =
279 vnic->fw_grp_ids[fw_idx];
281 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
284 "HWRM vnic %d set RSS failure rc: %x\n",
290 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
292 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
293 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
295 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
297 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
300 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
304 rc = bnxt_get_hwrm_link_config(bp, &new);
306 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
310 if (!bp->link_info.link_up) {
311 rc = bnxt_set_hwrm_link_config(bp, true);
314 "HWRM link config failure rc: %x\n", rc);
322 bnxt_free_all_hwrm_resources(bp);
327 static int bnxt_shutdown_nic(struct bnxt *bp)
329 bnxt_free_all_hwrm_resources(bp);
330 bnxt_free_all_filters(bp);
331 bnxt_free_all_vnics(bp);
335 static int bnxt_init_nic(struct bnxt *bp)
339 bnxt_init_ring_grps(bp);
341 bnxt_init_filters(bp);
343 rc = bnxt_init_chip(bp);
351 * Device configuration and status function
354 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
355 struct rte_eth_dev_info *dev_info)
357 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
358 uint16_t max_vnics, i, j, vpool, vrxq;
360 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
363 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
364 dev_info->max_hash_mac_addrs = 0;
366 /* PF/VF specifics */
368 dev_info->max_vfs = bp->pdev->max_vfs;
369 dev_info->max_rx_queues = bp->max_rx_rings;
370 dev_info->max_tx_queues = bp->max_tx_rings;
371 dev_info->reta_size = bp->max_rsscos_ctx;
372 max_vnics = bp->max_vnics;
374 /* Fast path specifics */
375 dev_info->min_rx_bufsize = 1;
376 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
378 dev_info->rx_offload_capa = 0;
379 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
380 DEV_TX_OFFLOAD_TCP_CKSUM |
381 DEV_TX_OFFLOAD_UDP_CKSUM |
382 DEV_TX_OFFLOAD_TCP_TSO |
383 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
384 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
385 DEV_TX_OFFLOAD_GRE_TNL_TSO |
386 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
387 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
390 dev_info->default_rxconf = (struct rte_eth_rxconf) {
396 .rx_free_thresh = 32,
400 dev_info->default_txconf = (struct rte_eth_txconf) {
406 .tx_free_thresh = 32,
408 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
409 ETH_TXQ_FLAGS_NOOFFLOADS,
411 eth_dev->data->dev_conf.intr_conf.lsc = 1;
416 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
417 * need further investigation.
421 vpool = 64; /* ETH_64_POOLS */
422 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
423 for (i = 0; i < 4; vpool >>= 1, i++) {
424 if (max_vnics > vpool) {
425 for (j = 0; j < 5; vrxq >>= 1, j++) {
426 if (dev_info->max_rx_queues > vrxq) {
432 /* Not enough resources to support VMDq */
436 /* Not enough resources to support VMDq */
440 dev_info->max_vmdq_pools = vpool;
441 dev_info->vmdq_queue_num = vrxq;
443 dev_info->vmdq_pool_base = 0;
444 dev_info->vmdq_queue_base = 0;
447 /* Configure the device based on the configuration provided */
448 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
450 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
452 bp->rx_queues = (void *)eth_dev->data->rx_queues;
453 bp->tx_queues = (void *)eth_dev->data->tx_queues;
455 /* Inherit new configurations */
456 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
457 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
458 bp->rx_cp_nr_rings = bp->rx_nr_rings;
459 bp->tx_cp_nr_rings = bp->tx_nr_rings;
461 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
463 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
464 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
469 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
470 struct rte_eth_link *link)
472 struct rte_eth_link *dst = ð_dev->data->dev_link;
473 struct rte_eth_link *src = link;
475 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
476 *(uint64_t *)src) == 0)
482 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
484 struct rte_eth_link *link = ð_dev->data->dev_link;
486 if (link->link_status)
487 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
488 (uint8_t)(eth_dev->data->port_id),
489 (uint32_t)link->link_speed,
490 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
491 ("full-duplex") : ("half-duplex\n"));
493 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
494 (uint8_t)(eth_dev->data->port_id));
497 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
499 bnxt_print_link_info(eth_dev);
503 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
505 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
511 rc = bnxt_init_nic(bp);
515 bnxt_link_update_op(eth_dev, 0);
517 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
518 vlan_mask |= ETH_VLAN_FILTER_MASK;
519 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
520 vlan_mask |= ETH_VLAN_STRIP_MASK;
521 bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
526 bnxt_shutdown_nic(bp);
527 bnxt_free_tx_mbufs(bp);
528 bnxt_free_rx_mbufs(bp);
532 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
534 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
536 eth_dev->data->dev_link.link_status = 1;
537 bnxt_set_hwrm_link_config(bp, true);
541 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
543 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
545 eth_dev->data->dev_link.link_status = 0;
546 bnxt_set_hwrm_link_config(bp, false);
550 /* Unload the driver, release resources */
551 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
553 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
555 if (bp->eth_dev->data->dev_started) {
556 /* TBD: STOP HW queues DMA */
557 eth_dev->data->dev_link.link_status = 0;
559 bnxt_set_hwrm_link_config(bp, false);
560 bnxt_hwrm_port_clr_stats(bp);
561 bnxt_shutdown_nic(bp);
565 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
567 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
569 if (bp->dev_stopped == 0)
570 bnxt_dev_stop_op(eth_dev);
572 bnxt_free_tx_mbufs(bp);
573 bnxt_free_rx_mbufs(bp);
575 if (eth_dev->data->mac_addrs != NULL) {
576 rte_free(eth_dev->data->mac_addrs);
577 eth_dev->data->mac_addrs = NULL;
579 if (bp->grp_info != NULL) {
580 rte_free(bp->grp_info);
585 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
588 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
589 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
590 struct bnxt_vnic_info *vnic;
591 struct bnxt_filter_info *filter, *temp_filter;
595 * Loop through all VNICs from the specified filter flow pools to
596 * remove the corresponding MAC addr filter
598 for (i = 0; i < MAX_FF_POOLS; i++) {
599 if (!(pool_mask & (1ULL << i)))
602 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
603 filter = STAILQ_FIRST(&vnic->filter);
605 temp_filter = STAILQ_NEXT(filter, next);
606 if (filter->mac_index == index) {
607 STAILQ_REMOVE(&vnic->filter, filter,
608 bnxt_filter_info, next);
609 bnxt_hwrm_clear_filter(bp, filter);
610 filter->mac_index = INVALID_MAC_INDEX;
611 memset(&filter->l2_addr, 0,
614 &bp->free_filter_list,
617 filter = temp_filter;
623 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
624 struct ether_addr *mac_addr,
625 uint32_t index, uint32_t pool)
627 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
628 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
629 struct bnxt_filter_info *filter;
632 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
637 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
640 /* Attach requested MAC address to the new l2_filter */
641 STAILQ_FOREACH(filter, &vnic->filter, next) {
642 if (filter->mac_index == index) {
644 "MAC addr already existed for pool %d\n", pool);
648 filter = bnxt_alloc_filter(bp);
650 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
653 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
654 filter->mac_index = index;
655 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
656 return bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
659 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
662 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
663 struct rte_eth_link new;
664 unsigned int cnt = BNXT_LINK_WAIT_CNT;
666 memset(&new, 0, sizeof(new));
668 /* Retrieve link info from hardware */
669 rc = bnxt_get_hwrm_link_config(bp, &new);
671 new.link_speed = ETH_LINK_SPEED_100M;
672 new.link_duplex = ETH_LINK_FULL_DUPLEX;
674 "Failed to retrieve link rc = 0x%x!\n", rc);
677 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
679 if (!wait_to_complete)
681 } while (!new.link_status && cnt--);
684 /* Timed out or success */
685 if (new.link_status != eth_dev->data->dev_link.link_status ||
686 new.link_speed != eth_dev->data->dev_link.link_speed) {
687 rte_bnxt_atomic_write_link_status(eth_dev, &new);
688 bnxt_print_link_info(eth_dev);
694 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
696 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
697 struct bnxt_vnic_info *vnic;
699 if (bp->vnic_info == NULL)
702 vnic = &bp->vnic_info[0];
704 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
705 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
708 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
710 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
711 struct bnxt_vnic_info *vnic;
713 if (bp->vnic_info == NULL)
716 vnic = &bp->vnic_info[0];
718 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
719 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
722 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
724 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
725 struct bnxt_vnic_info *vnic;
727 if (bp->vnic_info == NULL)
730 vnic = &bp->vnic_info[0];
732 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
733 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
736 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
738 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
739 struct bnxt_vnic_info *vnic;
741 if (bp->vnic_info == NULL)
744 vnic = &bp->vnic_info[0];
746 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
747 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
750 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
751 struct rte_eth_rss_reta_entry64 *reta_conf,
754 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
755 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
756 struct bnxt_vnic_info *vnic;
759 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
762 if (reta_size != HW_HASH_INDEX_SIZE) {
763 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
764 "(%d) must equal the size supported by the hardware "
765 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
768 /* Update the RSS VNIC(s) */
769 for (i = 0; i < MAX_FF_POOLS; i++) {
770 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
771 memcpy(vnic->rss_table, reta_conf, reta_size);
773 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
779 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
780 struct rte_eth_rss_reta_entry64 *reta_conf,
783 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
784 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
785 struct rte_intr_handle *intr_handle
786 = &bp->pdev->intr_handle;
788 /* Retrieve from the default VNIC */
791 if (!vnic->rss_table)
794 if (reta_size != HW_HASH_INDEX_SIZE) {
795 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
796 "(%d) must equal the size supported by the hardware "
797 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
800 /* EW - need to revisit here copying from u64 to u16 */
801 memcpy(reta_conf, vnic->rss_table, reta_size);
803 if (rte_intr_allow_others(intr_handle)) {
804 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
805 bnxt_dev_lsc_intr_setup(eth_dev);
811 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
812 struct rte_eth_rss_conf *rss_conf)
814 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
815 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
816 struct bnxt_vnic_info *vnic;
817 uint16_t hash_type = 0;
821 * If RSS enablement were different than dev_configure,
822 * then return -EINVAL
824 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
825 if (!rss_conf->rss_hf)
828 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
831 if (rss_conf->rss_hf & ETH_RSS_IPV4)
832 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
833 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
834 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
835 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
836 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
837 if (rss_conf->rss_hf & ETH_RSS_IPV6)
838 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
839 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
840 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
841 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
842 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
844 /* Update the RSS VNIC(s) */
845 for (i = 0; i < MAX_FF_POOLS; i++) {
846 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
847 vnic->hash_type = hash_type;
850 * Use the supplied key if the key length is
851 * acceptable and the rss_key is not NULL
853 if (rss_conf->rss_key &&
854 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
855 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
856 rss_conf->rss_key_len);
858 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
864 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
865 struct rte_eth_rss_conf *rss_conf)
867 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
868 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
872 /* RSS configuration is the same for all VNICs */
873 if (vnic && vnic->rss_hash_key) {
874 if (rss_conf->rss_key) {
875 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
876 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
877 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
880 hash_types = vnic->hash_type;
881 rss_conf->rss_hf = 0;
882 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
883 rss_conf->rss_hf |= ETH_RSS_IPV4;
884 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
886 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
887 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
889 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
891 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
892 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
894 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
896 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
897 rss_conf->rss_hf |= ETH_RSS_IPV6;
898 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
900 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
901 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
903 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
905 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
906 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
908 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
912 "Unknwon RSS config from firmware (%08x), RSS disabled",
917 rss_conf->rss_hf = 0;
922 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
923 struct rte_eth_fc_conf *fc_conf)
925 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
926 struct rte_eth_link link_info;
929 rc = bnxt_get_hwrm_link_config(bp, &link_info);
933 memset(fc_conf, 0, sizeof(*fc_conf));
934 if (bp->link_info.auto_pause)
935 fc_conf->autoneg = 1;
936 switch (bp->link_info.pause) {
938 fc_conf->mode = RTE_FC_NONE;
940 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
941 fc_conf->mode = RTE_FC_TX_PAUSE;
943 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
944 fc_conf->mode = RTE_FC_RX_PAUSE;
946 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
947 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
948 fc_conf->mode = RTE_FC_FULL;
954 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
955 struct rte_eth_fc_conf *fc_conf)
957 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
959 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
960 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
964 switch (fc_conf->mode) {
966 bp->link_info.auto_pause = 0;
967 bp->link_info.force_pause = 0;
969 case RTE_FC_RX_PAUSE:
970 if (fc_conf->autoneg) {
971 bp->link_info.auto_pause =
972 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
973 bp->link_info.force_pause = 0;
975 bp->link_info.auto_pause = 0;
976 bp->link_info.force_pause =
977 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
980 case RTE_FC_TX_PAUSE:
981 if (fc_conf->autoneg) {
982 bp->link_info.auto_pause =
983 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
984 bp->link_info.force_pause = 0;
986 bp->link_info.auto_pause = 0;
987 bp->link_info.force_pause =
988 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
992 if (fc_conf->autoneg) {
993 bp->link_info.auto_pause =
994 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
995 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
996 bp->link_info.force_pause = 0;
998 bp->link_info.auto_pause = 0;
999 bp->link_info.force_pause =
1000 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1001 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1005 return bnxt_set_hwrm_link_config(bp, true);
1008 /* Add UDP tunneling port */
1010 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1011 struct rte_eth_udp_tunnel *udp_tunnel)
1013 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1014 uint16_t tunnel_type = 0;
1017 switch (udp_tunnel->prot_type) {
1018 case RTE_TUNNEL_TYPE_VXLAN:
1019 if (bp->vxlan_port_cnt) {
1020 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1021 udp_tunnel->udp_port);
1022 if (bp->vxlan_port != udp_tunnel->udp_port) {
1023 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1026 bp->vxlan_port_cnt++;
1030 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1031 bp->vxlan_port_cnt++;
1033 case RTE_TUNNEL_TYPE_GENEVE:
1034 if (bp->geneve_port_cnt) {
1035 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1036 udp_tunnel->udp_port);
1037 if (bp->geneve_port != udp_tunnel->udp_port) {
1038 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1041 bp->geneve_port_cnt++;
1045 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1046 bp->geneve_port_cnt++;
1049 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1052 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1058 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1059 struct rte_eth_udp_tunnel *udp_tunnel)
1061 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1062 uint16_t tunnel_type = 0;
1066 switch (udp_tunnel->prot_type) {
1067 case RTE_TUNNEL_TYPE_VXLAN:
1068 if (!bp->vxlan_port_cnt) {
1069 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1072 if (bp->vxlan_port != udp_tunnel->udp_port) {
1073 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1074 udp_tunnel->udp_port, bp->vxlan_port);
1077 if (--bp->vxlan_port_cnt)
1081 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1082 port = bp->vxlan_fw_dst_port_id;
1084 case RTE_TUNNEL_TYPE_GENEVE:
1085 if (!bp->geneve_port_cnt) {
1086 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1089 if (bp->geneve_port != udp_tunnel->udp_port) {
1090 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1091 udp_tunnel->udp_port, bp->geneve_port);
1094 if (--bp->geneve_port_cnt)
1098 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1099 port = bp->geneve_fw_dst_port_id;
1102 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1106 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1109 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1112 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1113 bp->geneve_port = 0;
1118 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1120 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1121 struct bnxt_vnic_info *vnic;
1124 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1126 /* Cycle through all VNICs */
1127 for (i = 0; i < bp->nr_vnics; i++) {
1129 * For each VNIC and each associated filter(s)
1130 * if VLAN exists && VLAN matches vlan_id
1131 * remove the MAC+VLAN filter
1132 * add a new MAC only filter
1134 * VLAN filter doesn't exist, just skip and continue
1136 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1137 filter = STAILQ_FIRST(&vnic->filter);
1139 temp_filter = STAILQ_NEXT(filter, next);
1141 if (filter->enables & chk &&
1142 filter->l2_ovlan == vlan_id) {
1143 /* Must delete the filter */
1144 STAILQ_REMOVE(&vnic->filter, filter,
1145 bnxt_filter_info, next);
1146 bnxt_hwrm_clear_filter(bp, filter);
1148 &bp->free_filter_list,
1152 * Need to examine to see if the MAC
1153 * filter already existed or not before
1154 * allocating a new one
1157 new_filter = bnxt_alloc_filter(bp);
1160 "MAC/VLAN filter alloc failed\n");
1164 STAILQ_INSERT_TAIL(&vnic->filter,
1166 /* Inherit MAC from previous filter */
1167 new_filter->mac_index =
1169 memcpy(new_filter->l2_addr,
1170 filter->l2_addr, ETHER_ADDR_LEN);
1171 /* MAC only filter */
1172 rc = bnxt_hwrm_set_filter(bp,
1178 "Del Vlan filter for %d\n",
1181 filter = temp_filter;
1189 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1191 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1192 struct bnxt_vnic_info *vnic;
1195 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1196 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1197 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1199 /* Cycle through all VNICs */
1200 for (i = 0; i < bp->nr_vnics; i++) {
1202 * For each VNIC and each associated filter(s)
1204 * if VLAN matches vlan_id
1205 * VLAN filter already exists, just skip and continue
1207 * add a new MAC+VLAN filter
1209 * Remove the old MAC only filter
1210 * Add a new MAC+VLAN filter
1212 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1213 filter = STAILQ_FIRST(&vnic->filter);
1215 temp_filter = STAILQ_NEXT(filter, next);
1217 if (filter->enables & chk) {
1218 if (filter->l2_ovlan == vlan_id)
1221 /* Must delete the MAC filter */
1222 STAILQ_REMOVE(&vnic->filter, filter,
1223 bnxt_filter_info, next);
1224 bnxt_hwrm_clear_filter(bp, filter);
1225 filter->l2_ovlan = 0;
1227 &bp->free_filter_list,
1230 new_filter = bnxt_alloc_filter(bp);
1233 "MAC/VLAN filter alloc failed\n");
1237 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1239 /* Inherit MAC from the previous filter */
1240 new_filter->mac_index = filter->mac_index;
1241 memcpy(new_filter->l2_addr, filter->l2_addr,
1243 /* MAC + VLAN ID filter */
1244 new_filter->l2_ovlan = vlan_id;
1245 new_filter->l2_ovlan_mask = 0xF000;
1246 new_filter->enables |= en;
1247 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id,
1252 "Added Vlan filter for %d\n", vlan_id);
1254 filter = temp_filter;
1262 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1263 uint16_t vlan_id, int on)
1265 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1267 /* These operations apply to ALL existing MAC/VLAN filters */
1269 return bnxt_add_vlan_filter(bp, vlan_id);
1271 return bnxt_del_vlan_filter(bp, vlan_id);
1275 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1277 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1280 if (mask & ETH_VLAN_FILTER_MASK) {
1281 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1282 /* Remove any VLAN filters programmed */
1283 for (i = 0; i < 4095; i++)
1284 bnxt_del_vlan_filter(bp, i);
1286 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1287 dev->data->dev_conf.rxmode.hw_vlan_filter);
1290 if (mask & ETH_VLAN_STRIP_MASK) {
1291 /* Enable or disable VLAN stripping */
1292 for (i = 0; i < bp->nr_vnics; i++) {
1293 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1294 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1295 vnic->vlan_strip = true;
1297 vnic->vlan_strip = false;
1298 bnxt_hwrm_vnic_cfg(bp, vnic);
1300 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1301 dev->data->dev_conf.rxmode.hw_vlan_strip);
1304 if (mask & ETH_VLAN_EXTEND_MASK)
1305 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1309 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1311 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1312 /* Default Filter is tied to VNIC 0 */
1313 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1314 struct bnxt_filter_info *filter;
1320 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1321 memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1323 STAILQ_FOREACH(filter, &vnic->filter, next) {
1324 /* Default Filter is at Index 0 */
1325 if (filter->mac_index != 0)
1327 rc = bnxt_hwrm_clear_filter(bp, filter);
1330 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1331 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1332 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1334 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1335 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1336 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1339 filter->mac_index = 0;
1340 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1345 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1346 struct ether_addr *mc_addr_set,
1347 uint32_t nb_mc_addr)
1349 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1350 char *mc_addr_list = (char *)mc_addr_set;
1351 struct bnxt_vnic_info *vnic;
1352 uint32_t off = 0, i = 0;
1354 vnic = &bp->vnic_info[0];
1356 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1357 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1361 /* TODO Check for Duplicate mcast addresses */
1362 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1363 for (i = 0; i < nb_mc_addr; i++) {
1364 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1365 off += ETHER_ADDR_LEN;
1368 vnic->mc_addr_cnt = i;
1371 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
1375 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1377 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1378 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1379 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1380 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1383 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1384 fw_major, fw_minor, fw_updt);
1386 ret += 1; /* add the size of '\0' */
1387 if (fw_size < (uint32_t)ret)
1394 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1395 struct rte_eth_rxq_info *qinfo)
1397 struct bnxt_rx_queue *rxq;
1399 rxq = dev->data->rx_queues[queue_id];
1401 qinfo->mp = rxq->mb_pool;
1402 qinfo->scattered_rx = dev->data->scattered_rx;
1403 qinfo->nb_desc = rxq->nb_rx_desc;
1405 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1406 qinfo->conf.rx_drop_en = 0;
1407 qinfo->conf.rx_deferred_start = 0;
1411 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1412 struct rte_eth_txq_info *qinfo)
1414 struct bnxt_tx_queue *txq;
1416 txq = dev->data->tx_queues[queue_id];
1418 qinfo->nb_desc = txq->nb_tx_desc;
1420 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1421 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1422 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1424 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1425 qinfo->conf.tx_rs_thresh = 0;
1426 qinfo->conf.txq_flags = txq->txq_flags;
1427 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1430 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1432 struct bnxt *bp = eth_dev->data->dev_private;
1433 struct rte_eth_dev_info dev_info;
1434 uint32_t max_dev_mtu;
1438 bnxt_dev_info_get_op(eth_dev, &dev_info);
1439 max_dev_mtu = dev_info.max_rx_pktlen -
1440 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1442 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1443 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1444 ETHER_MIN_MTU, max_dev_mtu);
1449 if (new_mtu > ETHER_MTU) {
1450 bp->flags |= BNXT_FLAG_JUMBO;
1451 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1453 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1454 bp->flags &= ~BNXT_FLAG_JUMBO;
1457 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1458 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1460 eth_dev->data->mtu = new_mtu;
1461 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1463 for (i = 0; i < bp->nr_vnics; i++) {
1464 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1466 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1467 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1468 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1472 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1481 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1483 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1484 uint16_t vlan = bp->vlan;
1487 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1489 "PVID cannot be modified for this function\n");
1492 bp->vlan = on ? pvid : 0;
1494 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1504 static const struct eth_dev_ops bnxt_dev_ops = {
1505 .dev_infos_get = bnxt_dev_info_get_op,
1506 .dev_close = bnxt_dev_close_op,
1507 .dev_configure = bnxt_dev_configure_op,
1508 .dev_start = bnxt_dev_start_op,
1509 .dev_stop = bnxt_dev_stop_op,
1510 .dev_set_link_up = bnxt_dev_set_link_up_op,
1511 .dev_set_link_down = bnxt_dev_set_link_down_op,
1512 .stats_get = bnxt_stats_get_op,
1513 .stats_reset = bnxt_stats_reset_op,
1514 .rx_queue_setup = bnxt_rx_queue_setup_op,
1515 .rx_queue_release = bnxt_rx_queue_release_op,
1516 .tx_queue_setup = bnxt_tx_queue_setup_op,
1517 .tx_queue_release = bnxt_tx_queue_release_op,
1518 .reta_update = bnxt_reta_update_op,
1519 .reta_query = bnxt_reta_query_op,
1520 .rss_hash_update = bnxt_rss_hash_update_op,
1521 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1522 .link_update = bnxt_link_update_op,
1523 .promiscuous_enable = bnxt_promiscuous_enable_op,
1524 .promiscuous_disable = bnxt_promiscuous_disable_op,
1525 .allmulticast_enable = bnxt_allmulticast_enable_op,
1526 .allmulticast_disable = bnxt_allmulticast_disable_op,
1527 .mac_addr_add = bnxt_mac_addr_add_op,
1528 .mac_addr_remove = bnxt_mac_addr_remove_op,
1529 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1530 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1531 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
1532 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
1533 .vlan_filter_set = bnxt_vlan_filter_set_op,
1534 .vlan_offload_set = bnxt_vlan_offload_set_op,
1535 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
1536 .mtu_set = bnxt_mtu_set_op,
1537 .mac_addr_set = bnxt_set_default_mac_addr_op,
1538 .xstats_get = bnxt_dev_xstats_get_op,
1539 .xstats_get_names = bnxt_dev_xstats_get_names_op,
1540 .xstats_reset = bnxt_dev_xstats_reset_op,
1541 .fw_version_get = bnxt_fw_version_get,
1542 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
1543 .rxq_info_get = bnxt_rxq_info_get_op,
1544 .txq_info_get = bnxt_txq_info_get_op,
1547 static bool bnxt_vf_pciid(uint16_t id)
1549 if (id == BROADCOM_DEV_ID_57304_VF ||
1550 id == BROADCOM_DEV_ID_57406_VF ||
1551 id == BROADCOM_DEV_ID_5731X_VF ||
1552 id == BROADCOM_DEV_ID_5741X_VF ||
1553 id == BROADCOM_DEV_ID_57414_VF)
1558 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1560 struct bnxt *bp = eth_dev->data->dev_private;
1561 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1564 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1565 if (!pci_dev->mem_resource[0].addr) {
1567 "Cannot find PCI device base address, aborting\n");
1569 goto init_err_disable;
1572 bp->eth_dev = eth_dev;
1575 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1577 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1579 goto init_err_release;
1592 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1594 #define ALLOW_FUNC(x) \
1596 typeof(x) arg = (x); \
1597 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
1598 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
1601 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1603 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1604 char mz_name[RTE_MEMZONE_NAMESIZE];
1605 const struct rte_memzone *mz = NULL;
1606 static int version_printed;
1607 uint32_t total_alloc_len;
1608 phys_addr_t mz_phys_addr;
1612 if (version_printed++ == 0)
1613 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
1615 rte_eth_copy_pci_info(eth_dev, pci_dev);
1616 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1618 bp = eth_dev->data->dev_private;
1619 bp->dev_stopped = 1;
1621 if (bnxt_vf_pciid(pci_dev->id.device_id))
1622 bp->flags |= BNXT_FLAG_VF;
1624 rc = bnxt_init_board(eth_dev);
1627 "Board initialization failed rc: %x\n", rc);
1630 eth_dev->dev_ops = &bnxt_dev_ops;
1631 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1632 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1634 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
1635 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1636 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1637 pci_dev->addr.bus, pci_dev->addr.devid,
1638 pci_dev->addr.function, "rx_port_stats");
1639 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1640 mz = rte_memzone_lookup(mz_name);
1641 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1642 sizeof(struct rx_port_stats) + 512);
1644 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1647 RTE_MEMZONE_SIZE_HINT_ONLY);
1651 memset(mz->addr, 0, mz->len);
1652 mz_phys_addr = mz->phys_addr;
1653 if ((unsigned long)mz->addr == mz_phys_addr) {
1654 RTE_LOG(WARNING, PMD,
1655 "Memzone physical address same as virtual.\n");
1656 RTE_LOG(WARNING, PMD,
1657 "Using rte_mem_virt2phy()\n");
1658 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1659 if (mz_phys_addr == 0) {
1661 "unable to map address to physical memory\n");
1666 bp->rx_mem_zone = (const void *)mz;
1667 bp->hw_rx_port_stats = mz->addr;
1668 bp->hw_rx_port_stats_map = mz_phys_addr;
1670 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1671 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1672 pci_dev->addr.bus, pci_dev->addr.devid,
1673 pci_dev->addr.function, "tx_port_stats");
1674 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1675 mz = rte_memzone_lookup(mz_name);
1676 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1677 sizeof(struct tx_port_stats) + 512);
1679 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1682 RTE_MEMZONE_SIZE_HINT_ONLY);
1686 memset(mz->addr, 0, mz->len);
1687 mz_phys_addr = mz->phys_addr;
1688 if ((unsigned long)mz->addr == mz_phys_addr) {
1689 RTE_LOG(WARNING, PMD,
1690 "Memzone physical address same as virtual.\n");
1691 RTE_LOG(WARNING, PMD,
1692 "Using rte_mem_virt2phy()\n");
1693 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1694 if (mz_phys_addr == 0) {
1696 "unable to map address to physical memory\n");
1701 bp->tx_mem_zone = (const void *)mz;
1702 bp->hw_tx_port_stats = mz->addr;
1703 bp->hw_tx_port_stats_map = mz_phys_addr;
1705 bp->flags |= BNXT_FLAG_PORT_STATS;
1708 rc = bnxt_alloc_hwrm_resources(bp);
1711 "hwrm resource allocation failure rc: %x\n", rc);
1714 rc = bnxt_hwrm_ver_get(bp);
1717 bnxt_hwrm_queue_qportcfg(bp);
1719 bnxt_hwrm_func_qcfg(bp);
1721 /* Get the MAX capabilities for this function */
1722 rc = bnxt_hwrm_func_qcaps(bp);
1724 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1727 if (bp->max_tx_rings == 0) {
1728 RTE_LOG(ERR, PMD, "No TX rings available!\n");
1732 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1733 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1734 if (eth_dev->data->mac_addrs == NULL) {
1736 "Failed to alloc %u bytes needed to store MAC addr tbl",
1737 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1741 /* Copy the permanent MAC from the qcap response address now. */
1742 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
1743 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1744 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1745 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1746 if (!bp->grp_info) {
1748 "Failed to alloc %zu bytes needed to store group info table\n",
1749 sizeof(*bp->grp_info) * bp->max_ring_grps);
1754 /* Forward all requests if firmware is new enough */
1755 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
1756 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
1757 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
1758 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
1760 RTE_LOG(WARNING, PMD,
1761 "Firmware too old for VF mailbox functionality\n");
1762 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
1766 * The following are used for driver cleanup. If we disallow these,
1767 * VF drivers can't clean up cleanly.
1769 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
1770 ALLOW_FUNC(HWRM_VNIC_FREE);
1771 ALLOW_FUNC(HWRM_RING_FREE);
1772 ALLOW_FUNC(HWRM_RING_GRP_FREE);
1773 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
1774 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
1775 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
1776 rc = bnxt_hwrm_func_driver_register(bp);
1779 "Failed to register driver");
1785 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1786 pci_dev->mem_resource[0].phys_addr,
1787 pci_dev->mem_resource[0].addr);
1789 rc = bnxt_hwrm_func_reset(bp);
1791 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
1797 //if (bp->pf.active_vfs) {
1798 // TODO: Deallocate VF resources?
1800 if (bp->pdev->max_vfs) {
1801 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
1803 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
1807 rc = bnxt_hwrm_allocate_pf_only(bp);
1810 "Failed to allocate PF resources\n");
1816 rc = bnxt_setup_int(bp);
1820 rc = bnxt_alloc_mem(bp);
1822 goto error_free_int;
1824 rc = bnxt_request_int(bp);
1826 goto error_free_int;
1828 rc = bnxt_alloc_def_cp_ring(bp);
1830 goto error_free_int;
1832 bnxt_enable_int(bp);
1837 bnxt_disable_int(bp);
1838 bnxt_free_def_cp_ring(bp);
1839 bnxt_hwrm_func_buf_unrgtr(bp);
1843 bnxt_dev_uninit(eth_dev);
1849 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1850 struct bnxt *bp = eth_dev->data->dev_private;
1853 bnxt_disable_int(bp);
1856 if (eth_dev->data->mac_addrs != NULL) {
1857 rte_free(eth_dev->data->mac_addrs);
1858 eth_dev->data->mac_addrs = NULL;
1860 if (bp->grp_info != NULL) {
1861 rte_free(bp->grp_info);
1862 bp->grp_info = NULL;
1864 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1865 bnxt_free_hwrm_resources(bp);
1866 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1867 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1868 if (bp->dev_stopped == 0)
1869 bnxt_dev_close_op(eth_dev);
1871 rte_free(bp->pf.vf_info);
1872 eth_dev->dev_ops = NULL;
1873 eth_dev->rx_pkt_burst = NULL;
1874 eth_dev->tx_pkt_burst = NULL;
1879 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg)
1881 struct rte_pmd_bnxt_mb_event_param cb_param;
1883 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_PROCEED;
1884 cb_param.vf_id = vf_id;
1887 _rte_eth_dev_callback_process(bp->eth_dev, RTE_ETH_EVENT_VF_MBOX,
1890 /* Default to approve */
1891 if (cb_param.retval == RTE_PMD_BNXT_MB_EVENT_PROCEED)
1892 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_NOOP_ACK;
1894 return cb_param.retval == RTE_PMD_BNXT_MB_EVENT_NOOP_ACK ? true : false;
1897 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1898 struct rte_pci_device *pci_dev)
1900 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1904 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1906 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1909 static struct rte_pci_driver bnxt_rte_pmd = {
1910 .id_table = bnxt_pci_id_map,
1911 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1912 RTE_PCI_DRV_INTR_LSC,
1913 .probe = bnxt_pci_probe,
1914 .remove = bnxt_pci_remove,
1917 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1918 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1919 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");