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38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
43 #include "bnxt_hwrm.h"
45 #include "bnxt_stats.h"
48 #define DRV_MODULE_NAME "bnxt"
49 static const char bnxt_version[] =
50 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
52 static struct rte_pci_id bnxt_pci_id_map[] = {
53 #define RTE_PCI_DEV_ID_DECL_BNXT(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
54 #include "rte_pci_dev_ids.h"
58 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
60 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
62 rte_free(eth_dev->data->mac_addrs);
63 bnxt_free_hwrm_resources(bp);
67 * Device configuration and status function
70 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
71 struct rte_eth_dev_info *dev_info)
73 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
74 uint16_t max_vnics, i, j, vpool, vrxq;
77 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
78 dev_info->max_hash_mac_addrs = 0;
82 dev_info->max_rx_queues = bp->pf.max_rx_rings;
83 dev_info->max_tx_queues = bp->pf.max_tx_rings;
84 dev_info->max_vfs = bp->pf.active_vfs;
85 dev_info->reta_size = bp->pf.max_rsscos_ctx;
86 max_vnics = bp->pf.max_vnics;
88 dev_info->max_rx_queues = bp->vf.max_rx_rings;
89 dev_info->max_tx_queues = bp->vf.max_tx_rings;
90 dev_info->reta_size = bp->vf.max_rsscos_ctx;
91 max_vnics = bp->vf.max_vnics;
94 /* Fast path specifics */
95 dev_info->min_rx_bufsize = 1;
96 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
98 dev_info->rx_offload_capa = 0;
99 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
100 DEV_TX_OFFLOAD_TCP_CKSUM |
101 DEV_TX_OFFLOAD_UDP_CKSUM |
102 DEV_TX_OFFLOAD_TCP_TSO;
105 dev_info->default_rxconf = (struct rte_eth_rxconf) {
111 .rx_free_thresh = 32,
115 dev_info->default_txconf = (struct rte_eth_txconf) {
121 .tx_free_thresh = 32,
123 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
124 ETH_TXQ_FLAGS_NOOFFLOADS,
129 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
130 * need further investigation.
134 vpool = 64; /* ETH_64_POOLS */
135 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
136 for (i = 0; i < 4; vpool >>= 1, i++) {
137 if (max_vnics > vpool) {
138 for (j = 0; j < 5; vrxq >>= 1, j++) {
139 if (dev_info->max_rx_queues > vrxq) {
145 /* Not enough resources to support VMDq */
149 /* Not enough resources to support VMDq */
153 dev_info->max_vmdq_pools = vpool;
154 dev_info->vmdq_queue_num = vrxq;
156 dev_info->vmdq_pool_base = 0;
157 dev_info->vmdq_queue_base = 0;
160 /* Configure the device based on the configuration provided */
161 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
163 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
166 bp->rx_queues = (void *)eth_dev->data->rx_queues;
167 bp->tx_queues = (void *)eth_dev->data->tx_queues;
169 /* Inherit new configurations */
170 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
171 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
172 bp->rx_cp_nr_rings = bp->rx_nr_rings;
173 bp->tx_cp_nr_rings = bp->tx_nr_rings;
175 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
177 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
178 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
179 rc = bnxt_set_hwrm_link_config(bp, true);
187 static struct eth_dev_ops bnxt_dev_ops = {
188 .dev_infos_get = bnxt_dev_info_get_op,
189 .dev_close = bnxt_dev_close_op,
190 .dev_configure = bnxt_dev_configure_op,
191 .stats_get = bnxt_stats_get_op,
192 .stats_reset = bnxt_stats_reset_op,
193 .rx_queue_setup = bnxt_rx_queue_setup_op,
194 .rx_queue_release = bnxt_rx_queue_release_op,
195 .tx_queue_setup = bnxt_tx_queue_setup_op,
196 .tx_queue_release = bnxt_tx_queue_release_op,
199 static bool bnxt_vf_pciid(uint16_t id)
201 if (id == BROADCOM_DEV_ID_57304_VF ||
202 id == BROADCOM_DEV_ID_57406_VF)
207 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
210 struct bnxt *bp = eth_dev->data->dev_private;
212 /* enable device (incl. PCI PM wakeup), and bus-mastering */
213 if (!eth_dev->pci_dev->mem_resource[0].addr) {
215 "Cannot find PCI device base address, aborting\n");
217 goto init_err_disable;
220 bp->eth_dev = eth_dev;
221 bp->pdev = eth_dev->pci_dev;
223 bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
225 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
227 goto init_err_release;
241 bnxt_dev_init(struct rte_eth_dev *eth_dev)
243 static int version_printed;
247 if (version_printed++ == 0)
248 RTE_LOG(INFO, PMD, "%s", bnxt_version);
250 if (eth_dev->pci_dev->addr.function >= 2 &&
251 eth_dev->pci_dev->addr.function < 4) {
252 RTE_LOG(ERR, PMD, "Function not enabled %x:\n",
253 eth_dev->pci_dev->addr.function);
258 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
259 bp = eth_dev->data->dev_private;
261 if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
262 bp->flags |= BNXT_FLAG_VF;
264 rc = bnxt_init_board(eth_dev);
267 "Board initialization failed rc: %x\n", rc);
270 eth_dev->dev_ops = &bnxt_dev_ops;
271 /* eth_dev->rx_pkt_burst = &bnxt_recv_pkts; */
272 /* eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; */
274 rc = bnxt_alloc_hwrm_resources(bp);
277 "hwrm resource allocation failure rc: %x\n", rc);
280 rc = bnxt_hwrm_ver_get(bp);
283 bnxt_hwrm_queue_qportcfg(bp);
285 /* Get the MAX capabilities for this function */
286 rc = bnxt_hwrm_func_qcaps(bp);
288 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
291 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
292 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
293 if (eth_dev->data->mac_addrs == NULL) {
295 "Failed to alloc %u bytes needed to store MAC addr tbl",
296 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
300 /* Copy the permanent MAC from the qcap response address now. */
302 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
304 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
305 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
307 rc = bnxt_hwrm_func_driver_register(bp, 0,
311 "Failed to register driver");
317 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
318 eth_dev->pci_dev->mem_resource[0].phys_addr,
319 eth_dev->pci_dev->mem_resource[0].addr);
324 eth_dev->driver->eth_dev_uninit(eth_dev);
330 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
331 struct bnxt *bp = eth_dev->data->dev_private;
334 if (eth_dev->data->mac_addrs)
335 rte_free(eth_dev->data->mac_addrs);
336 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
337 bnxt_free_hwrm_resources(bp);
341 static struct eth_driver bnxt_rte_pmd = {
343 .name = "rte_" DRV_MODULE_NAME "_pmd",
344 .id_table = bnxt_pci_id_map,
345 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
347 .eth_dev_init = bnxt_dev_init,
348 .eth_dev_uninit = bnxt_dev_uninit,
349 .dev_private_size = sizeof(struct bnxt),
352 static int bnxt_rte_pmd_init(const char *name, const char *params __rte_unused)
354 RTE_LOG(INFO, PMD, "bnxt_rte_pmd_init() called for %s\n", name);
355 rte_eth_driver_register(&bnxt_rte_pmd);
359 static struct rte_driver bnxt_pmd_drv = {
362 .init = bnxt_rte_pmd_init,
365 PMD_REGISTER_DRIVER(bnxt_pmd_drv);