1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
33 #define DRV_MODULE_NAME "bnxt"
34 static const char bnxt_version[] =
35 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
38 * The set of PCI devices this driver supports
40 static const struct rte_pci_id bnxt_pci_id_map[] = {
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
44 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
94 { .vendor_id = 0, /* sentinel */ },
97 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
98 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
99 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 static const char *const bnxt_dev_args[] = {
103 BNXT_DEVARG_FLOW_XSTAT,
104 BNXT_DEVARG_MAX_NUM_KFLOWS,
109 * truflow == false to disable the feature
110 * truflow == true to enable the feature
112 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
115 * flow_xstat == false to disable the feature
116 * flow_xstat == true to enable the feature
118 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
121 * max_num_kflows must be >= 32
122 * and must be a power-of-2 supported value
123 * return: 1 -> invalid
126 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
128 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
133 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
134 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
135 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
136 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
137 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
138 static int bnxt_restore_vlan_filters(struct bnxt *bp);
139 static void bnxt_dev_recover(void *arg);
140 static void bnxt_free_error_recovery_info(struct bnxt *bp);
141 static void bnxt_free_rep_info(struct bnxt *bp);
143 int is_bnxt_in_error(struct bnxt *bp)
145 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
147 if (bp->flags & BNXT_FLAG_FW_RESET)
153 /***********************/
156 * High level utility functions
159 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
161 if (!BNXT_CHIP_THOR(bp))
164 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
165 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
166 BNXT_RSS_ENTRIES_PER_CTX_THOR;
169 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
171 if (!BNXT_CHIP_THOR(bp))
172 return HW_HASH_INDEX_SIZE;
174 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
177 static void bnxt_free_parent_info(struct bnxt *bp)
179 rte_free(bp->parent);
182 static void bnxt_free_pf_info(struct bnxt *bp)
187 static void bnxt_free_link_info(struct bnxt *bp)
189 rte_free(bp->link_info);
192 static void bnxt_free_leds_info(struct bnxt *bp)
198 static void bnxt_free_flow_stats_info(struct bnxt *bp)
200 rte_free(bp->flow_stat);
201 bp->flow_stat = NULL;
204 static void bnxt_free_cos_queues(struct bnxt *bp)
206 rte_free(bp->rx_cos_queue);
207 rte_free(bp->tx_cos_queue);
210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
212 bnxt_free_filter_mem(bp);
213 bnxt_free_vnic_attributes(bp);
214 bnxt_free_vnic_mem(bp);
216 /* tx/rx rings are configured as part of *_queue_setup callbacks.
217 * If the number of rings change across fw update,
218 * we don't have much choice except to warn the user.
222 bnxt_free_tx_rings(bp);
223 bnxt_free_rx_rings(bp);
225 bnxt_free_async_cp_ring(bp);
226 bnxt_free_rxtx_nq_ring(bp);
228 rte_free(bp->grp_info);
232 static int bnxt_alloc_parent_info(struct bnxt *bp)
234 bp->parent = rte_zmalloc("bnxt_parent_info",
235 sizeof(struct bnxt_parent_info), 0);
236 if (bp->parent == NULL)
242 static int bnxt_alloc_pf_info(struct bnxt *bp)
244 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
251 static int bnxt_alloc_link_info(struct bnxt *bp)
254 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
255 if (bp->link_info == NULL)
261 static int bnxt_alloc_leds_info(struct bnxt *bp)
263 bp->leds = rte_zmalloc("bnxt_leds",
264 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
266 if (bp->leds == NULL)
272 static int bnxt_alloc_cos_queues(struct bnxt *bp)
275 rte_zmalloc("bnxt_rx_cosq",
276 BNXT_COS_QUEUE_COUNT *
277 sizeof(struct bnxt_cos_queue_info),
279 if (bp->rx_cos_queue == NULL)
283 rte_zmalloc("bnxt_tx_cosq",
284 BNXT_COS_QUEUE_COUNT *
285 sizeof(struct bnxt_cos_queue_info),
287 if (bp->tx_cos_queue == NULL)
293 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
295 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
296 sizeof(struct bnxt_flow_stat_info), 0);
297 if (bp->flow_stat == NULL)
303 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
307 rc = bnxt_alloc_ring_grps(bp);
311 rc = bnxt_alloc_async_ring_struct(bp);
315 rc = bnxt_alloc_vnic_mem(bp);
319 rc = bnxt_alloc_vnic_attributes(bp);
323 rc = bnxt_alloc_filter_mem(bp);
327 rc = bnxt_alloc_async_cp_ring(bp);
331 rc = bnxt_alloc_rxtx_nq_ring(bp);
335 if (BNXT_FLOW_XSTATS_EN(bp)) {
336 rc = bnxt_alloc_flow_stats_info(bp);
344 bnxt_free_mem(bp, reconfig);
348 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
350 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
351 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
352 uint64_t rx_offloads = dev_conf->rxmode.offloads;
353 struct bnxt_rx_queue *rxq;
357 rc = bnxt_vnic_grp_alloc(bp, vnic);
361 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
362 vnic_id, vnic, vnic->fw_grp_ids);
364 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
368 /* Alloc RSS context only if RSS mode is enabled */
369 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
370 int j, nr_ctxs = bnxt_rss_ctxts(bp);
373 for (j = 0; j < nr_ctxs; j++) {
374 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
380 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
384 vnic->num_lb_ctxts = nr_ctxs;
388 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
389 * setting is not available at this time, it will not be
390 * configured correctly in the CFA.
392 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
393 vnic->vlan_strip = true;
395 vnic->vlan_strip = false;
397 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
401 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
405 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
406 rxq = bp->eth_dev->data->rx_queues[j];
409 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
410 j, rxq->vnic, rxq->vnic->fw_grp_ids);
412 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
413 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
415 vnic->rx_queue_cnt++;
418 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
420 rc = bnxt_vnic_rss_configure(bp, vnic);
424 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
426 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
427 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
429 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
433 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
438 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
442 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
443 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
448 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
449 " rx_fc_in_tbl.ctx_id = %d\n",
450 bp->flow_stat->rx_fc_in_tbl.va,
451 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
452 bp->flow_stat->rx_fc_in_tbl.ctx_id);
454 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
455 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
460 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
461 " rx_fc_out_tbl.ctx_id = %d\n",
462 bp->flow_stat->rx_fc_out_tbl.va,
463 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
464 bp->flow_stat->rx_fc_out_tbl.ctx_id);
466 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
467 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
472 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
473 " tx_fc_in_tbl.ctx_id = %d\n",
474 bp->flow_stat->tx_fc_in_tbl.va,
475 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
476 bp->flow_stat->tx_fc_in_tbl.ctx_id);
478 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
479 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
484 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
485 " tx_fc_out_tbl.ctx_id = %d\n",
486 bp->flow_stat->tx_fc_out_tbl.va,
487 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
488 bp->flow_stat->tx_fc_out_tbl.ctx_id);
490 memset(bp->flow_stat->rx_fc_out_tbl.va,
492 bp->flow_stat->rx_fc_out_tbl.size);
493 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
494 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
495 bp->flow_stat->rx_fc_out_tbl.ctx_id,
496 bp->flow_stat->max_fc,
501 memset(bp->flow_stat->tx_fc_out_tbl.va,
503 bp->flow_stat->tx_fc_out_tbl.size);
504 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
505 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
506 bp->flow_stat->tx_fc_out_tbl.ctx_id,
507 bp->flow_stat->max_fc,
513 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
514 struct bnxt_ctx_mem_buf_info *ctx)
519 ctx->va = rte_zmalloc(type, size, 0);
522 rte_mem_lock_page(ctx->va);
524 ctx->dma = rte_mem_virt2iova(ctx->va);
525 if (ctx->dma == RTE_BAD_IOVA)
531 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
533 struct rte_pci_device *pdev = bp->pdev;
534 char type[RTE_MEMZONE_NAMESIZE];
538 max_fc = bp->flow_stat->max_fc;
540 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
541 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
542 /* 4 bytes for each counter-id */
543 rc = bnxt_alloc_ctx_mem_buf(type,
545 &bp->flow_stat->rx_fc_in_tbl);
549 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
552 rc = bnxt_alloc_ctx_mem_buf(type,
554 &bp->flow_stat->rx_fc_out_tbl);
558 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
560 /* 4 bytes for each counter-id */
561 rc = bnxt_alloc_ctx_mem_buf(type,
563 &bp->flow_stat->tx_fc_in_tbl);
567 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
569 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
570 rc = bnxt_alloc_ctx_mem_buf(type,
572 &bp->flow_stat->tx_fc_out_tbl);
576 rc = bnxt_register_fc_ctx_mem(bp);
581 static int bnxt_init_ctx_mem(struct bnxt *bp)
585 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
586 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
587 !BNXT_FLOW_XSTATS_EN(bp))
590 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
594 rc = bnxt_init_fc_ctx_mem(bp);
599 static int bnxt_init_chip(struct bnxt *bp)
601 struct rte_eth_link new;
602 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
603 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
604 uint32_t intr_vector = 0;
605 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
606 uint32_t vec = BNXT_MISC_VEC_ID;
610 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
611 bp->eth_dev->data->dev_conf.rxmode.offloads |=
612 DEV_RX_OFFLOAD_JUMBO_FRAME;
613 bp->flags |= BNXT_FLAG_JUMBO;
615 bp->eth_dev->data->dev_conf.rxmode.offloads &=
616 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
617 bp->flags &= ~BNXT_FLAG_JUMBO;
620 /* THOR does not support ring groups.
621 * But we will use the array to save RSS context IDs.
623 if (BNXT_CHIP_THOR(bp))
624 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
626 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
628 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
632 rc = bnxt_alloc_hwrm_rings(bp);
634 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
638 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
640 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
644 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
647 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
648 if (bp->rx_cos_queue[i].id != 0xff) {
649 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
653 "Num pools more than FW profile\n");
657 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
663 rc = bnxt_mq_rx_configure(bp);
665 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
669 /* VNIC configuration */
670 for (i = 0; i < bp->nr_vnics; i++) {
671 rc = bnxt_setup_one_vnic(bp, i);
676 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
679 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
683 /* check and configure queue intr-vector mapping */
684 if ((rte_intr_cap_multiple(intr_handle) ||
685 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
686 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
687 intr_vector = bp->eth_dev->data->nb_rx_queues;
688 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
689 if (intr_vector > bp->rx_cp_nr_rings) {
690 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
694 rc = rte_intr_efd_enable(intr_handle, intr_vector);
699 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
700 intr_handle->intr_vec =
701 rte_zmalloc("intr_vec",
702 bp->eth_dev->data->nb_rx_queues *
704 if (intr_handle->intr_vec == NULL) {
705 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
706 " intr_vec", bp->eth_dev->data->nb_rx_queues);
710 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
711 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
712 intr_handle->intr_vec, intr_handle->nb_efd,
713 intr_handle->max_intr);
714 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
716 intr_handle->intr_vec[queue_id] =
717 vec + BNXT_RX_VEC_START;
718 if (vec < base + intr_handle->nb_efd - 1)
723 /* enable uio/vfio intr/eventfd mapping */
724 rc = rte_intr_enable(intr_handle);
725 #ifndef RTE_EXEC_ENV_FREEBSD
726 /* In FreeBSD OS, nic_uio driver does not support interrupts */
731 rc = bnxt_get_hwrm_link_config(bp, &new);
733 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
737 if (!bp->link_info->link_up) {
738 rc = bnxt_set_hwrm_link_config(bp, true);
741 "HWRM link config failure rc: %x\n", rc);
745 bnxt_print_link_info(bp->eth_dev);
747 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
749 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
754 rte_free(intr_handle->intr_vec);
756 rte_intr_efd_disable(intr_handle);
758 /* Some of the error status returned by FW may not be from errno.h */
765 static int bnxt_shutdown_nic(struct bnxt *bp)
767 bnxt_free_all_hwrm_resources(bp);
768 bnxt_free_all_filters(bp);
769 bnxt_free_all_vnics(bp);
774 * Device configuration and status function
777 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
779 uint32_t link_speed = bp->link_info->support_speeds;
780 uint32_t speed_capa = 0;
782 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
783 speed_capa |= ETH_LINK_SPEED_100M;
784 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
785 speed_capa |= ETH_LINK_SPEED_100M_HD;
786 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
787 speed_capa |= ETH_LINK_SPEED_1G;
788 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
789 speed_capa |= ETH_LINK_SPEED_2_5G;
790 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
791 speed_capa |= ETH_LINK_SPEED_10G;
792 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
793 speed_capa |= ETH_LINK_SPEED_20G;
794 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
795 speed_capa |= ETH_LINK_SPEED_25G;
796 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
797 speed_capa |= ETH_LINK_SPEED_40G;
798 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
799 speed_capa |= ETH_LINK_SPEED_50G;
800 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
801 speed_capa |= ETH_LINK_SPEED_100G;
802 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
803 speed_capa |= ETH_LINK_SPEED_200G;
805 if (bp->link_info->auto_mode ==
806 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
807 speed_capa |= ETH_LINK_SPEED_FIXED;
809 speed_capa |= ETH_LINK_SPEED_AUTONEG;
814 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
815 struct rte_eth_dev_info *dev_info)
817 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
818 struct bnxt *bp = eth_dev->data->dev_private;
819 uint16_t max_vnics, i, j, vpool, vrxq;
820 unsigned int max_rx_rings;
823 rc = is_bnxt_in_error(bp);
828 dev_info->max_mac_addrs = bp->max_l2_ctx;
829 dev_info->max_hash_mac_addrs = 0;
831 /* PF/VF specifics */
833 dev_info->max_vfs = pdev->max_vfs;
835 max_rx_rings = BNXT_MAX_RINGS(bp);
836 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
837 dev_info->max_rx_queues = max_rx_rings;
838 dev_info->max_tx_queues = max_rx_rings;
839 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
840 dev_info->hash_key_size = 40;
841 max_vnics = bp->max_vnics;
844 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
845 dev_info->max_mtu = BNXT_MAX_MTU;
847 /* Fast path specifics */
848 dev_info->min_rx_bufsize = 1;
849 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
851 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
852 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
853 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
854 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
855 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
857 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
860 dev_info->default_rxconf = (struct rte_eth_rxconf) {
866 .rx_free_thresh = 32,
867 /* If no descriptors available, pkts are dropped by default */
871 dev_info->default_txconf = (struct rte_eth_txconf) {
877 .tx_free_thresh = 32,
880 eth_dev->data->dev_conf.intr_conf.lsc = 1;
882 eth_dev->data->dev_conf.intr_conf.rxq = 1;
883 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
884 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
885 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
886 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
891 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
892 * need further investigation.
896 vpool = 64; /* ETH_64_POOLS */
897 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
898 for (i = 0; i < 4; vpool >>= 1, i++) {
899 if (max_vnics > vpool) {
900 for (j = 0; j < 5; vrxq >>= 1, j++) {
901 if (dev_info->max_rx_queues > vrxq) {
907 /* Not enough resources to support VMDq */
911 /* Not enough resources to support VMDq */
915 dev_info->max_vmdq_pools = vpool;
916 dev_info->vmdq_queue_num = vrxq;
918 dev_info->vmdq_pool_base = 0;
919 dev_info->vmdq_queue_base = 0;
924 /* Configure the device based on the configuration provided */
925 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
927 struct bnxt *bp = eth_dev->data->dev_private;
928 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
931 bp->rx_queues = (void *)eth_dev->data->rx_queues;
932 bp->tx_queues = (void *)eth_dev->data->tx_queues;
933 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
934 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
936 rc = is_bnxt_in_error(bp);
940 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
941 rc = bnxt_hwrm_check_vf_rings(bp);
943 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
947 /* If a resource has already been allocated - in this case
948 * it is the async completion ring, free it. Reallocate it after
949 * resource reservation. This will ensure the resource counts
950 * are calculated correctly.
953 pthread_mutex_lock(&bp->def_cp_lock);
955 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
956 bnxt_disable_int(bp);
957 bnxt_free_cp_ring(bp, bp->async_cp_ring);
960 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
962 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
963 pthread_mutex_unlock(&bp->def_cp_lock);
967 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
968 rc = bnxt_alloc_async_cp_ring(bp);
970 pthread_mutex_unlock(&bp->def_cp_lock);
976 pthread_mutex_unlock(&bp->def_cp_lock);
978 /* legacy driver needs to get updated values */
979 rc = bnxt_hwrm_func_qcaps(bp);
981 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
986 /* Inherit new configurations */
987 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
988 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
989 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
990 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
991 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
995 if (BNXT_HAS_RING_GRPS(bp) &&
996 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
999 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1000 bp->max_vnics < eth_dev->data->nb_rx_queues)
1001 goto resource_error;
1003 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1004 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1006 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1007 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1008 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1010 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1011 eth_dev->data->mtu =
1012 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1013 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1015 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1021 "Insufficient resources to support requested config\n");
1023 "Num Queues Requested: Tx %d, Rx %d\n",
1024 eth_dev->data->nb_tx_queues,
1025 eth_dev->data->nb_rx_queues);
1027 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1028 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1029 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1033 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1035 struct rte_eth_link *link = ð_dev->data->dev_link;
1037 if (link->link_status)
1038 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1039 eth_dev->data->port_id,
1040 (uint32_t)link->link_speed,
1041 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1042 ("full-duplex") : ("half-duplex\n"));
1044 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1045 eth_dev->data->port_id);
1049 * Determine whether the current configuration requires support for scattered
1050 * receive; return 1 if scattered receive is required and 0 if not.
1052 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1057 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1060 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1061 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1063 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1064 RTE_PKTMBUF_HEADROOM);
1065 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1071 static eth_rx_burst_t
1072 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1074 struct bnxt *bp = eth_dev->data->dev_private;
1077 #ifndef RTE_LIBRTE_IEEE1588
1079 * Vector mode receive can be enabled only if scatter rx is not
1080 * in use and rx offloads are limited to VLAN stripping and
1083 if (!eth_dev->data->scattered_rx &&
1084 !(eth_dev->data->dev_conf.rxmode.offloads &
1085 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1086 DEV_RX_OFFLOAD_KEEP_CRC |
1087 DEV_RX_OFFLOAD_JUMBO_FRAME |
1088 DEV_RX_OFFLOAD_IPV4_CKSUM |
1089 DEV_RX_OFFLOAD_UDP_CKSUM |
1090 DEV_RX_OFFLOAD_TCP_CKSUM |
1091 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1092 DEV_RX_OFFLOAD_RSS_HASH |
1093 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1094 !BNXT_TRUFLOW_EN(bp)) {
1095 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1096 eth_dev->data->port_id);
1097 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1098 return bnxt_recv_pkts_vec;
1100 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1101 eth_dev->data->port_id);
1103 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1104 eth_dev->data->port_id,
1105 eth_dev->data->scattered_rx,
1106 eth_dev->data->dev_conf.rxmode.offloads);
1109 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1110 return bnxt_recv_pkts;
1113 static eth_tx_burst_t
1114 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1117 #ifndef RTE_LIBRTE_IEEE1588
1119 * Vector mode transmit can be enabled only if not using scatter rx
1122 if (!eth_dev->data->scattered_rx &&
1123 !eth_dev->data->dev_conf.txmode.offloads) {
1124 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1125 eth_dev->data->port_id);
1126 return bnxt_xmit_pkts_vec;
1128 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1129 eth_dev->data->port_id);
1131 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1132 eth_dev->data->port_id,
1133 eth_dev->data->scattered_rx,
1134 eth_dev->data->dev_conf.txmode.offloads);
1137 return bnxt_xmit_pkts;
1140 static int bnxt_handle_if_change_status(struct bnxt *bp)
1144 /* Since fw has undergone a reset and lost all contexts,
1145 * set fatal flag to not issue hwrm during cleanup
1147 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1148 bnxt_uninit_resources(bp, true);
1150 /* clear fatal flag so that re-init happens */
1151 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1152 rc = bnxt_init_resources(bp, true);
1154 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1159 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1161 struct bnxt *bp = eth_dev->data->dev_private;
1162 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1164 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1166 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1167 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1171 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1173 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1174 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1178 rc = bnxt_hwrm_if_change(bp, true);
1179 if (rc == 0 || rc != -EAGAIN)
1182 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1183 } while (retry_cnt--);
1188 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1189 rc = bnxt_handle_if_change_status(bp);
1194 bnxt_enable_int(bp);
1196 rc = bnxt_init_chip(bp);
1200 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1201 eth_dev->data->dev_started = 1;
1203 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1205 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1206 vlan_mask |= ETH_VLAN_FILTER_MASK;
1207 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1208 vlan_mask |= ETH_VLAN_STRIP_MASK;
1209 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1213 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1214 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1216 pthread_mutex_lock(&bp->def_cp_lock);
1217 bnxt_schedule_fw_health_check(bp);
1218 pthread_mutex_unlock(&bp->def_cp_lock);
1220 if (BNXT_TRUFLOW_EN(bp))
1226 bnxt_shutdown_nic(bp);
1227 bnxt_free_tx_mbufs(bp);
1228 bnxt_free_rx_mbufs(bp);
1229 bnxt_hwrm_if_change(bp, false);
1230 eth_dev->data->dev_started = 0;
1234 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1236 struct bnxt *bp = eth_dev->data->dev_private;
1239 if (!bp->link_info->link_up)
1240 rc = bnxt_set_hwrm_link_config(bp, true);
1242 eth_dev->data->dev_link.link_status = 1;
1244 bnxt_print_link_info(eth_dev);
1248 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1250 struct bnxt *bp = eth_dev->data->dev_private;
1252 eth_dev->data->dev_link.link_status = 0;
1253 bnxt_set_hwrm_link_config(bp, false);
1254 bp->link_info->link_up = 0;
1259 static void bnxt_free_switch_domain(struct bnxt *bp)
1261 if (bp->switch_domain_id)
1262 rte_eth_switch_domain_free(bp->switch_domain_id);
1265 /* Unload the driver, release resources */
1266 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1268 struct bnxt *bp = eth_dev->data->dev_private;
1269 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1270 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1272 if (BNXT_TRUFLOW_EN(bp))
1273 bnxt_ulp_deinit(bp);
1275 eth_dev->data->dev_started = 0;
1276 /* Prevent crashes when queues are still in use */
1277 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1278 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1280 bnxt_disable_int(bp);
1282 /* disable uio/vfio intr/eventfd mapping */
1283 rte_intr_disable(intr_handle);
1285 bnxt_cancel_fw_health_check(bp);
1287 bnxt_dev_set_link_down_op(eth_dev);
1289 /* Wait for link to be reset and the async notification to process.
1290 * During reset recovery, there is no need to wait and
1291 * VF/NPAR functions do not have privilege to change PHY config.
1293 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1294 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1296 /* Clean queue intr-vector mapping */
1297 rte_intr_efd_disable(intr_handle);
1298 if (intr_handle->intr_vec != NULL) {
1299 rte_free(intr_handle->intr_vec);
1300 intr_handle->intr_vec = NULL;
1303 bnxt_hwrm_port_clr_stats(bp);
1304 bnxt_free_tx_mbufs(bp);
1305 bnxt_free_rx_mbufs(bp);
1306 /* Process any remaining notifications in default completion queue */
1307 bnxt_int_handler(eth_dev);
1308 bnxt_shutdown_nic(bp);
1309 bnxt_hwrm_if_change(bp, false);
1311 rte_free(bp->mark_table);
1312 bp->mark_table = NULL;
1314 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1315 bp->rx_cosq_cnt = 0;
1316 /* All filters are deleted on a port stop. */
1317 if (BNXT_FLOW_XSTATS_EN(bp))
1318 bp->flow_stat->flow_count = 0;
1321 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1323 struct bnxt *bp = eth_dev->data->dev_private;
1325 /* cancel the recovery handler before remove dev */
1326 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1327 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1328 bnxt_cancel_fc_thread(bp);
1330 if (eth_dev->data->dev_started)
1331 bnxt_dev_stop_op(eth_dev);
1333 bnxt_free_switch_domain(bp);
1335 bnxt_uninit_resources(bp, false);
1337 bnxt_free_leds_info(bp);
1338 bnxt_free_cos_queues(bp);
1339 bnxt_free_link_info(bp);
1340 bnxt_free_pf_info(bp);
1341 bnxt_free_parent_info(bp);
1343 eth_dev->dev_ops = NULL;
1344 eth_dev->rx_pkt_burst = NULL;
1345 eth_dev->tx_pkt_burst = NULL;
1347 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1348 bp->tx_mem_zone = NULL;
1349 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1350 bp->rx_mem_zone = NULL;
1352 rte_free(bp->pf->vf_info);
1353 bp->pf->vf_info = NULL;
1355 rte_free(bp->grp_info);
1356 bp->grp_info = NULL;
1359 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1362 struct bnxt *bp = eth_dev->data->dev_private;
1363 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1364 struct bnxt_vnic_info *vnic;
1365 struct bnxt_filter_info *filter, *temp_filter;
1368 if (is_bnxt_in_error(bp))
1372 * Loop through all VNICs from the specified filter flow pools to
1373 * remove the corresponding MAC addr filter
1375 for (i = 0; i < bp->nr_vnics; i++) {
1376 if (!(pool_mask & (1ULL << i)))
1379 vnic = &bp->vnic_info[i];
1380 filter = STAILQ_FIRST(&vnic->filter);
1382 temp_filter = STAILQ_NEXT(filter, next);
1383 if (filter->mac_index == index) {
1384 STAILQ_REMOVE(&vnic->filter, filter,
1385 bnxt_filter_info, next);
1386 bnxt_hwrm_clear_l2_filter(bp, filter);
1387 bnxt_free_filter(bp, filter);
1389 filter = temp_filter;
1394 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1395 struct rte_ether_addr *mac_addr, uint32_t index,
1398 struct bnxt_filter_info *filter;
1401 /* Attach requested MAC address to the new l2_filter */
1402 STAILQ_FOREACH(filter, &vnic->filter, next) {
1403 if (filter->mac_index == index) {
1405 "MAC addr already existed for pool %d\n",
1411 filter = bnxt_alloc_filter(bp);
1413 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1417 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1418 * if the MAC that's been programmed now is a different one, then,
1419 * copy that addr to filter->l2_addr
1422 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1423 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1425 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1427 filter->mac_index = index;
1428 if (filter->mac_index == 0)
1429 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1431 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1433 bnxt_free_filter(bp, filter);
1439 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1440 struct rte_ether_addr *mac_addr,
1441 uint32_t index, uint32_t pool)
1443 struct bnxt *bp = eth_dev->data->dev_private;
1444 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1447 rc = is_bnxt_in_error(bp);
1451 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1452 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1457 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1461 /* Filter settings will get applied when port is started */
1462 if (!eth_dev->data->dev_started)
1465 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1470 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1471 bool exp_link_status)
1474 struct bnxt *bp = eth_dev->data->dev_private;
1475 struct rte_eth_link new;
1476 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1477 BNXT_LINK_DOWN_WAIT_CNT;
1479 rc = is_bnxt_in_error(bp);
1483 memset(&new, 0, sizeof(new));
1485 /* Retrieve link info from hardware */
1486 rc = bnxt_get_hwrm_link_config(bp, &new);
1488 new.link_speed = ETH_LINK_SPEED_100M;
1489 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1491 "Failed to retrieve link rc = 0x%x!\n", rc);
1495 if (!wait_to_complete || new.link_status == exp_link_status)
1498 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1502 /* Timed out or success */
1503 if (new.link_status != eth_dev->data->dev_link.link_status ||
1504 new.link_speed != eth_dev->data->dev_link.link_speed) {
1505 rte_eth_linkstatus_set(eth_dev, &new);
1507 _rte_eth_dev_callback_process(eth_dev,
1508 RTE_ETH_EVENT_INTR_LSC,
1511 bnxt_print_link_info(eth_dev);
1517 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1518 int wait_to_complete)
1520 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1523 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1525 struct bnxt *bp = eth_dev->data->dev_private;
1526 struct bnxt_vnic_info *vnic;
1530 rc = is_bnxt_in_error(bp);
1534 /* Filter settings will get applied when port is started */
1535 if (!eth_dev->data->dev_started)
1538 if (bp->vnic_info == NULL)
1541 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1543 old_flags = vnic->flags;
1544 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1545 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1547 vnic->flags = old_flags;
1552 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1554 struct bnxt *bp = eth_dev->data->dev_private;
1555 struct bnxt_vnic_info *vnic;
1559 rc = is_bnxt_in_error(bp);
1563 /* Filter settings will get applied when port is started */
1564 if (!eth_dev->data->dev_started)
1567 if (bp->vnic_info == NULL)
1570 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1572 old_flags = vnic->flags;
1573 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1574 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1576 vnic->flags = old_flags;
1581 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1583 struct bnxt *bp = eth_dev->data->dev_private;
1584 struct bnxt_vnic_info *vnic;
1588 rc = is_bnxt_in_error(bp);
1592 /* Filter settings will get applied when port is started */
1593 if (!eth_dev->data->dev_started)
1596 if (bp->vnic_info == NULL)
1599 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1601 old_flags = vnic->flags;
1602 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1603 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1605 vnic->flags = old_flags;
1610 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1612 struct bnxt *bp = eth_dev->data->dev_private;
1613 struct bnxt_vnic_info *vnic;
1617 rc = is_bnxt_in_error(bp);
1621 /* Filter settings will get applied when port is started */
1622 if (!eth_dev->data->dev_started)
1625 if (bp->vnic_info == NULL)
1628 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1630 old_flags = vnic->flags;
1631 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1632 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1634 vnic->flags = old_flags;
1639 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1640 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1642 if (qid >= bp->rx_nr_rings)
1645 return bp->eth_dev->data->rx_queues[qid];
1648 /* Return rxq corresponding to a given rss table ring/group ID. */
1649 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1651 struct bnxt_rx_queue *rxq;
1654 if (!BNXT_HAS_RING_GRPS(bp)) {
1655 for (i = 0; i < bp->rx_nr_rings; i++) {
1656 rxq = bp->eth_dev->data->rx_queues[i];
1657 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1661 for (i = 0; i < bp->rx_nr_rings; i++) {
1662 if (bp->grp_info[i].fw_grp_id == fwr)
1667 return INVALID_HW_RING_ID;
1670 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1671 struct rte_eth_rss_reta_entry64 *reta_conf,
1674 struct bnxt *bp = eth_dev->data->dev_private;
1675 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1676 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1677 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1681 rc = is_bnxt_in_error(bp);
1685 if (!vnic->rss_table)
1688 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1691 if (reta_size != tbl_size) {
1692 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1693 "(%d) must equal the size supported by the hardware "
1694 "(%d)\n", reta_size, tbl_size);
1698 for (i = 0; i < reta_size; i++) {
1699 struct bnxt_rx_queue *rxq;
1701 idx = i / RTE_RETA_GROUP_SIZE;
1702 sft = i % RTE_RETA_GROUP_SIZE;
1704 if (!(reta_conf[idx].mask & (1ULL << sft)))
1707 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1709 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1713 if (BNXT_CHIP_THOR(bp)) {
1714 vnic->rss_table[i * 2] =
1715 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1716 vnic->rss_table[i * 2 + 1] =
1717 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1719 vnic->rss_table[i] =
1720 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1724 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1728 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1729 struct rte_eth_rss_reta_entry64 *reta_conf,
1732 struct bnxt *bp = eth_dev->data->dev_private;
1733 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1734 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1735 uint16_t idx, sft, i;
1738 rc = is_bnxt_in_error(bp);
1742 /* Retrieve from the default VNIC */
1745 if (!vnic->rss_table)
1748 if (reta_size != tbl_size) {
1749 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1750 "(%d) must equal the size supported by the hardware "
1751 "(%d)\n", reta_size, tbl_size);
1755 for (idx = 0, i = 0; i < reta_size; i++) {
1756 idx = i / RTE_RETA_GROUP_SIZE;
1757 sft = i % RTE_RETA_GROUP_SIZE;
1759 if (reta_conf[idx].mask & (1ULL << sft)) {
1762 if (BNXT_CHIP_THOR(bp))
1763 qid = bnxt_rss_to_qid(bp,
1764 vnic->rss_table[i * 2]);
1766 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1768 if (qid == INVALID_HW_RING_ID) {
1769 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1772 reta_conf[idx].reta[sft] = qid;
1779 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1780 struct rte_eth_rss_conf *rss_conf)
1782 struct bnxt *bp = eth_dev->data->dev_private;
1783 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1784 struct bnxt_vnic_info *vnic;
1787 rc = is_bnxt_in_error(bp);
1792 * If RSS enablement were different than dev_configure,
1793 * then return -EINVAL
1795 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1796 if (!rss_conf->rss_hf)
1797 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1799 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1803 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1804 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1808 /* Update the default RSS VNIC(s) */
1809 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1810 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1813 * If hashkey is not specified, use the previously configured
1816 if (!rss_conf->rss_key)
1819 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1821 "Invalid hashkey length, should be 16 bytes\n");
1824 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1827 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1831 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1832 struct rte_eth_rss_conf *rss_conf)
1834 struct bnxt *bp = eth_dev->data->dev_private;
1835 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1837 uint32_t hash_types;
1839 rc = is_bnxt_in_error(bp);
1843 /* RSS configuration is the same for all VNICs */
1844 if (vnic && vnic->rss_hash_key) {
1845 if (rss_conf->rss_key) {
1846 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1847 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1848 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1851 hash_types = vnic->hash_type;
1852 rss_conf->rss_hf = 0;
1853 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1854 rss_conf->rss_hf |= ETH_RSS_IPV4;
1855 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1857 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1858 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1860 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1862 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1863 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1865 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1867 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1868 rss_conf->rss_hf |= ETH_RSS_IPV6;
1869 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1871 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1872 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1874 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1876 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1877 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1879 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1883 "Unknown RSS config from firmware (%08x), RSS disabled",
1888 rss_conf->rss_hf = 0;
1893 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1894 struct rte_eth_fc_conf *fc_conf)
1896 struct bnxt *bp = dev->data->dev_private;
1897 struct rte_eth_link link_info;
1900 rc = is_bnxt_in_error(bp);
1904 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1908 memset(fc_conf, 0, sizeof(*fc_conf));
1909 if (bp->link_info->auto_pause)
1910 fc_conf->autoneg = 1;
1911 switch (bp->link_info->pause) {
1913 fc_conf->mode = RTE_FC_NONE;
1915 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1916 fc_conf->mode = RTE_FC_TX_PAUSE;
1918 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1919 fc_conf->mode = RTE_FC_RX_PAUSE;
1921 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1922 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1923 fc_conf->mode = RTE_FC_FULL;
1929 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1930 struct rte_eth_fc_conf *fc_conf)
1932 struct bnxt *bp = dev->data->dev_private;
1935 rc = is_bnxt_in_error(bp);
1939 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1940 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1944 switch (fc_conf->mode) {
1946 bp->link_info->auto_pause = 0;
1947 bp->link_info->force_pause = 0;
1949 case RTE_FC_RX_PAUSE:
1950 if (fc_conf->autoneg) {
1951 bp->link_info->auto_pause =
1952 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1953 bp->link_info->force_pause = 0;
1955 bp->link_info->auto_pause = 0;
1956 bp->link_info->force_pause =
1957 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1960 case RTE_FC_TX_PAUSE:
1961 if (fc_conf->autoneg) {
1962 bp->link_info->auto_pause =
1963 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1964 bp->link_info->force_pause = 0;
1966 bp->link_info->auto_pause = 0;
1967 bp->link_info->force_pause =
1968 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1972 if (fc_conf->autoneg) {
1973 bp->link_info->auto_pause =
1974 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1975 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1976 bp->link_info->force_pause = 0;
1978 bp->link_info->auto_pause = 0;
1979 bp->link_info->force_pause =
1980 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1981 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1985 return bnxt_set_hwrm_link_config(bp, true);
1988 /* Add UDP tunneling port */
1990 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1991 struct rte_eth_udp_tunnel *udp_tunnel)
1993 struct bnxt *bp = eth_dev->data->dev_private;
1994 uint16_t tunnel_type = 0;
1997 rc = is_bnxt_in_error(bp);
2001 switch (udp_tunnel->prot_type) {
2002 case RTE_TUNNEL_TYPE_VXLAN:
2003 if (bp->vxlan_port_cnt) {
2004 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2005 udp_tunnel->udp_port);
2006 if (bp->vxlan_port != udp_tunnel->udp_port) {
2007 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2010 bp->vxlan_port_cnt++;
2014 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2015 bp->vxlan_port_cnt++;
2017 case RTE_TUNNEL_TYPE_GENEVE:
2018 if (bp->geneve_port_cnt) {
2019 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2020 udp_tunnel->udp_port);
2021 if (bp->geneve_port != udp_tunnel->udp_port) {
2022 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2025 bp->geneve_port_cnt++;
2029 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2030 bp->geneve_port_cnt++;
2033 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2036 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2042 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2043 struct rte_eth_udp_tunnel *udp_tunnel)
2045 struct bnxt *bp = eth_dev->data->dev_private;
2046 uint16_t tunnel_type = 0;
2050 rc = is_bnxt_in_error(bp);
2054 switch (udp_tunnel->prot_type) {
2055 case RTE_TUNNEL_TYPE_VXLAN:
2056 if (!bp->vxlan_port_cnt) {
2057 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2060 if (bp->vxlan_port != udp_tunnel->udp_port) {
2061 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2062 udp_tunnel->udp_port, bp->vxlan_port);
2065 if (--bp->vxlan_port_cnt)
2069 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2070 port = bp->vxlan_fw_dst_port_id;
2072 case RTE_TUNNEL_TYPE_GENEVE:
2073 if (!bp->geneve_port_cnt) {
2074 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2077 if (bp->geneve_port != udp_tunnel->udp_port) {
2078 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2079 udp_tunnel->udp_port, bp->geneve_port);
2082 if (--bp->geneve_port_cnt)
2086 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2087 port = bp->geneve_fw_dst_port_id;
2090 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2094 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2097 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2100 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2101 bp->geneve_port = 0;
2106 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2108 struct bnxt_filter_info *filter;
2109 struct bnxt_vnic_info *vnic;
2111 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2113 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2114 filter = STAILQ_FIRST(&vnic->filter);
2116 /* Search for this matching MAC+VLAN filter */
2117 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2118 /* Delete the filter */
2119 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2122 STAILQ_REMOVE(&vnic->filter, filter,
2123 bnxt_filter_info, next);
2124 bnxt_free_filter(bp, filter);
2126 "Deleted vlan filter for %d\n",
2130 filter = STAILQ_NEXT(filter, next);
2135 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2137 struct bnxt_filter_info *filter;
2138 struct bnxt_vnic_info *vnic;
2140 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2141 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2142 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2144 /* Implementation notes on the use of VNIC in this command:
2146 * By default, these filters belong to default vnic for the function.
2147 * Once these filters are set up, only destination VNIC can be modified.
2148 * If the destination VNIC is not specified in this command,
2149 * then the HWRM shall only create an l2 context id.
2152 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2153 filter = STAILQ_FIRST(&vnic->filter);
2154 /* Check if the VLAN has already been added */
2156 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2159 filter = STAILQ_NEXT(filter, next);
2162 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2163 * command to create MAC+VLAN filter with the right flags, enables set.
2165 filter = bnxt_alloc_filter(bp);
2168 "MAC/VLAN filter alloc failed\n");
2171 /* MAC + VLAN ID filter */
2172 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2173 * untagged packets are received
2175 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2176 * packets and only the programmed vlan's packets are received
2178 filter->l2_ivlan = vlan_id;
2179 filter->l2_ivlan_mask = 0x0FFF;
2180 filter->enables |= en;
2181 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2183 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2185 /* Free the newly allocated filter as we were
2186 * not able to create the filter in hardware.
2188 bnxt_free_filter(bp, filter);
2192 filter->mac_index = 0;
2193 /* Add this new filter to the list */
2195 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2197 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2200 "Added Vlan filter for %d\n", vlan_id);
2204 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2205 uint16_t vlan_id, int on)
2207 struct bnxt *bp = eth_dev->data->dev_private;
2210 rc = is_bnxt_in_error(bp);
2214 if (!eth_dev->data->dev_started) {
2215 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2219 /* These operations apply to ALL existing MAC/VLAN filters */
2221 return bnxt_add_vlan_filter(bp, vlan_id);
2223 return bnxt_del_vlan_filter(bp, vlan_id);
2226 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2227 struct bnxt_vnic_info *vnic)
2229 struct bnxt_filter_info *filter;
2232 filter = STAILQ_FIRST(&vnic->filter);
2234 if (filter->mac_index == 0 &&
2235 !memcmp(filter->l2_addr, bp->mac_addr,
2236 RTE_ETHER_ADDR_LEN)) {
2237 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2239 STAILQ_REMOVE(&vnic->filter, filter,
2240 bnxt_filter_info, next);
2241 bnxt_free_filter(bp, filter);
2245 filter = STAILQ_NEXT(filter, next);
2251 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2253 struct bnxt_vnic_info *vnic;
2257 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2258 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2259 /* Remove any VLAN filters programmed */
2260 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2261 bnxt_del_vlan_filter(bp, i);
2263 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2267 /* Default filter will allow packets that match the
2268 * dest mac. So, it has to be deleted, otherwise, we
2269 * will endup receiving vlan packets for which the
2270 * filter is not programmed, when hw-vlan-filter
2271 * configuration is ON
2273 bnxt_del_dflt_mac_filter(bp, vnic);
2274 /* This filter will allow only untagged packets */
2275 bnxt_add_vlan_filter(bp, 0);
2277 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2278 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2283 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2285 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2289 /* Destroy vnic filters and vnic */
2290 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2291 DEV_RX_OFFLOAD_VLAN_FILTER) {
2292 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2293 bnxt_del_vlan_filter(bp, i);
2295 bnxt_del_dflt_mac_filter(bp, vnic);
2297 rc = bnxt_hwrm_vnic_free(bp, vnic);
2301 rte_free(vnic->fw_grp_ids);
2302 vnic->fw_grp_ids = NULL;
2304 vnic->rx_queue_cnt = 0;
2310 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2312 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2315 /* Destroy, recreate and reconfigure the default vnic */
2316 rc = bnxt_free_one_vnic(bp, 0);
2320 /* default vnic 0 */
2321 rc = bnxt_setup_one_vnic(bp, 0);
2325 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2326 DEV_RX_OFFLOAD_VLAN_FILTER) {
2327 rc = bnxt_add_vlan_filter(bp, 0);
2330 rc = bnxt_restore_vlan_filters(bp);
2334 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2339 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2343 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2344 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2350 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2352 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2353 struct bnxt *bp = dev->data->dev_private;
2356 rc = is_bnxt_in_error(bp);
2360 /* Filter settings will get applied when port is started */
2361 if (!dev->data->dev_started)
2364 if (mask & ETH_VLAN_FILTER_MASK) {
2365 /* Enable or disable VLAN filtering */
2366 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2371 if (mask & ETH_VLAN_STRIP_MASK) {
2372 /* Enable or disable VLAN stripping */
2373 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2378 if (mask & ETH_VLAN_EXTEND_MASK) {
2379 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2380 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2382 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2389 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2392 struct bnxt *bp = dev->data->dev_private;
2393 int qinq = dev->data->dev_conf.rxmode.offloads &
2394 DEV_RX_OFFLOAD_VLAN_EXTEND;
2396 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2397 vlan_type != ETH_VLAN_TYPE_OUTER) {
2399 "Unsupported vlan type.");
2404 "QinQ not enabled. Needs to be ON as we can "
2405 "accelerate only outer vlan\n");
2409 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2411 case RTE_ETHER_TYPE_QINQ:
2413 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2415 case RTE_ETHER_TYPE_VLAN:
2417 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2421 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2425 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2429 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2432 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2435 bp->outer_tpid_bd |= tpid;
2436 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2437 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2439 "Can accelerate only outer vlan in QinQ\n");
2447 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2448 struct rte_ether_addr *addr)
2450 struct bnxt *bp = dev->data->dev_private;
2451 /* Default Filter is tied to VNIC 0 */
2452 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2455 rc = is_bnxt_in_error(bp);
2459 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2462 if (rte_is_zero_ether_addr(addr))
2465 /* Filter settings will get applied when port is started */
2466 if (!dev->data->dev_started)
2469 /* Check if the requested MAC is already added */
2470 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2473 /* Destroy filter and re-create it */
2474 bnxt_del_dflt_mac_filter(bp, vnic);
2476 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2477 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2478 /* This filter will allow only untagged packets */
2479 rc = bnxt_add_vlan_filter(bp, 0);
2481 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2484 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2489 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2490 struct rte_ether_addr *mc_addr_set,
2491 uint32_t nb_mc_addr)
2493 struct bnxt *bp = eth_dev->data->dev_private;
2494 char *mc_addr_list = (char *)mc_addr_set;
2495 struct bnxt_vnic_info *vnic;
2496 uint32_t off = 0, i = 0;
2499 rc = is_bnxt_in_error(bp);
2503 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2505 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2506 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2510 /* TODO Check for Duplicate mcast addresses */
2511 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2512 for (i = 0; i < nb_mc_addr; i++) {
2513 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2514 RTE_ETHER_ADDR_LEN);
2515 off += RTE_ETHER_ADDR_LEN;
2518 vnic->mc_addr_cnt = i;
2519 if (vnic->mc_addr_cnt)
2520 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2522 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2525 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2529 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2531 struct bnxt *bp = dev->data->dev_private;
2532 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2533 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2534 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2535 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2538 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2539 fw_major, fw_minor, fw_updt, fw_rsvd);
2541 ret += 1; /* add the size of '\0' */
2542 if (fw_size < (uint32_t)ret)
2549 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2550 struct rte_eth_rxq_info *qinfo)
2552 struct bnxt *bp = dev->data->dev_private;
2553 struct bnxt_rx_queue *rxq;
2555 if (is_bnxt_in_error(bp))
2558 rxq = dev->data->rx_queues[queue_id];
2560 qinfo->mp = rxq->mb_pool;
2561 qinfo->scattered_rx = dev->data->scattered_rx;
2562 qinfo->nb_desc = rxq->nb_rx_desc;
2564 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2565 qinfo->conf.rx_drop_en = 0;
2566 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2570 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2571 struct rte_eth_txq_info *qinfo)
2573 struct bnxt *bp = dev->data->dev_private;
2574 struct bnxt_tx_queue *txq;
2576 if (is_bnxt_in_error(bp))
2579 txq = dev->data->tx_queues[queue_id];
2581 qinfo->nb_desc = txq->nb_tx_desc;
2583 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2584 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2585 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2587 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2588 qinfo->conf.tx_rs_thresh = 0;
2589 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2592 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2594 struct bnxt *bp = eth_dev->data->dev_private;
2595 uint32_t new_pkt_size;
2599 rc = is_bnxt_in_error(bp);
2603 /* Exit if receive queues are not configured yet */
2604 if (!eth_dev->data->nb_rx_queues)
2607 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2608 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2612 * If vector-mode tx/rx is active, disallow any MTU change that would
2613 * require scattered receive support.
2615 if (eth_dev->data->dev_started &&
2616 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2617 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2619 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2621 "MTU change would require scattered rx support. ");
2622 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2627 if (new_mtu > RTE_ETHER_MTU) {
2628 bp->flags |= BNXT_FLAG_JUMBO;
2629 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2630 DEV_RX_OFFLOAD_JUMBO_FRAME;
2632 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2633 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2634 bp->flags &= ~BNXT_FLAG_JUMBO;
2637 /* Is there a change in mtu setting? */
2638 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2641 for (i = 0; i < bp->nr_vnics; i++) {
2642 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2645 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2646 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2650 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2651 size -= RTE_PKTMBUF_HEADROOM;
2653 if (size < new_mtu) {
2654 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2661 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2663 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2669 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2671 struct bnxt *bp = dev->data->dev_private;
2672 uint16_t vlan = bp->vlan;
2675 rc = is_bnxt_in_error(bp);
2679 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2681 "PVID cannot be modified for this function\n");
2684 bp->vlan = on ? pvid : 0;
2686 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2693 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2695 struct bnxt *bp = dev->data->dev_private;
2698 rc = is_bnxt_in_error(bp);
2702 return bnxt_hwrm_port_led_cfg(bp, true);
2706 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2708 struct bnxt *bp = dev->data->dev_private;
2711 rc = is_bnxt_in_error(bp);
2715 return bnxt_hwrm_port_led_cfg(bp, false);
2719 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2721 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2722 uint32_t desc = 0, raw_cons = 0, cons;
2723 struct bnxt_cp_ring_info *cpr;
2724 struct bnxt_rx_queue *rxq;
2725 struct rx_pkt_cmpl *rxcmp;
2728 rc = is_bnxt_in_error(bp);
2732 rxq = dev->data->rx_queues[rx_queue_id];
2734 raw_cons = cpr->cp_raw_cons;
2737 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2738 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2739 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2741 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2753 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2755 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2756 struct bnxt_rx_ring_info *rxr;
2757 struct bnxt_cp_ring_info *cpr;
2758 struct bnxt_sw_rx_bd *rx_buf;
2759 struct rx_pkt_cmpl *rxcmp;
2760 uint32_t cons, cp_cons;
2766 rc = is_bnxt_in_error(rxq->bp);
2773 if (offset >= rxq->nb_rx_desc)
2776 cons = RING_CMP(cpr->cp_ring_struct, offset);
2777 cp_cons = cpr->cp_raw_cons;
2778 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2780 if (cons > cp_cons) {
2781 if (CMPL_VALID(rxcmp, cpr->valid))
2782 return RTE_ETH_RX_DESC_DONE;
2784 if (CMPL_VALID(rxcmp, !cpr->valid))
2785 return RTE_ETH_RX_DESC_DONE;
2787 rx_buf = &rxr->rx_buf_ring[cons];
2788 if (rx_buf->mbuf == NULL)
2789 return RTE_ETH_RX_DESC_UNAVAIL;
2792 return RTE_ETH_RX_DESC_AVAIL;
2796 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2798 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2799 struct bnxt_tx_ring_info *txr;
2800 struct bnxt_cp_ring_info *cpr;
2801 struct bnxt_sw_tx_bd *tx_buf;
2802 struct tx_pkt_cmpl *txcmp;
2803 uint32_t cons, cp_cons;
2809 rc = is_bnxt_in_error(txq->bp);
2816 if (offset >= txq->nb_tx_desc)
2819 cons = RING_CMP(cpr->cp_ring_struct, offset);
2820 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2821 cp_cons = cpr->cp_raw_cons;
2823 if (cons > cp_cons) {
2824 if (CMPL_VALID(txcmp, cpr->valid))
2825 return RTE_ETH_TX_DESC_UNAVAIL;
2827 if (CMPL_VALID(txcmp, !cpr->valid))
2828 return RTE_ETH_TX_DESC_UNAVAIL;
2830 tx_buf = &txr->tx_buf_ring[cons];
2831 if (tx_buf->mbuf == NULL)
2832 return RTE_ETH_TX_DESC_DONE;
2834 return RTE_ETH_TX_DESC_FULL;
2837 static struct bnxt_filter_info *
2838 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2839 struct rte_eth_ethertype_filter *efilter,
2840 struct bnxt_vnic_info *vnic0,
2841 struct bnxt_vnic_info *vnic,
2844 struct bnxt_filter_info *mfilter = NULL;
2848 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2849 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2850 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2851 " ethertype filter.", efilter->ether_type);
2855 if (efilter->queue >= bp->rx_nr_rings) {
2856 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2861 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2862 vnic = &bp->vnic_info[efilter->queue];
2864 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2869 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2870 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2871 if ((!memcmp(efilter->mac_addr.addr_bytes,
2872 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2874 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2875 mfilter->ethertype == efilter->ether_type)) {
2881 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2882 if ((!memcmp(efilter->mac_addr.addr_bytes,
2883 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2884 mfilter->ethertype == efilter->ether_type &&
2886 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2900 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2901 enum rte_filter_op filter_op,
2904 struct bnxt *bp = dev->data->dev_private;
2905 struct rte_eth_ethertype_filter *efilter =
2906 (struct rte_eth_ethertype_filter *)arg;
2907 struct bnxt_filter_info *bfilter, *filter1;
2908 struct bnxt_vnic_info *vnic, *vnic0;
2911 if (filter_op == RTE_ETH_FILTER_NOP)
2915 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2920 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2921 vnic = &bp->vnic_info[efilter->queue];
2923 switch (filter_op) {
2924 case RTE_ETH_FILTER_ADD:
2925 bnxt_match_and_validate_ether_filter(bp, efilter,
2930 bfilter = bnxt_get_unused_filter(bp);
2931 if (bfilter == NULL) {
2933 "Not enough resources for a new filter.\n");
2936 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2937 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2938 RTE_ETHER_ADDR_LEN);
2939 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2940 RTE_ETHER_ADDR_LEN);
2941 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2942 bfilter->ethertype = efilter->ether_type;
2943 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2945 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2946 if (filter1 == NULL) {
2951 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2952 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2954 bfilter->dst_id = vnic->fw_vnic_id;
2956 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2958 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2961 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2964 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2966 case RTE_ETH_FILTER_DELETE:
2967 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2969 if (ret == -EEXIST) {
2970 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2972 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2974 bnxt_free_filter(bp, filter1);
2975 } else if (ret == 0) {
2976 PMD_DRV_LOG(ERR, "No matching filter found\n");
2980 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2986 bnxt_free_filter(bp, bfilter);
2992 parse_ntuple_filter(struct bnxt *bp,
2993 struct rte_eth_ntuple_filter *nfilter,
2994 struct bnxt_filter_info *bfilter)
2998 if (nfilter->queue >= bp->rx_nr_rings) {
2999 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3003 switch (nfilter->dst_port_mask) {
3005 bfilter->dst_port_mask = -1;
3006 bfilter->dst_port = nfilter->dst_port;
3007 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3008 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3011 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3015 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3016 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3018 switch (nfilter->proto_mask) {
3020 if (nfilter->proto == 17) /* IPPROTO_UDP */
3021 bfilter->ip_protocol = 17;
3022 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3023 bfilter->ip_protocol = 6;
3026 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3029 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3033 switch (nfilter->dst_ip_mask) {
3035 bfilter->dst_ipaddr_mask[0] = -1;
3036 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3037 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3038 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3041 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3045 switch (nfilter->src_ip_mask) {
3047 bfilter->src_ipaddr_mask[0] = -1;
3048 bfilter->src_ipaddr[0] = nfilter->src_ip;
3049 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3050 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3053 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3057 switch (nfilter->src_port_mask) {
3059 bfilter->src_port_mask = -1;
3060 bfilter->src_port = nfilter->src_port;
3061 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3062 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3065 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3069 bfilter->enables = en;
3073 static struct bnxt_filter_info*
3074 bnxt_match_ntuple_filter(struct bnxt *bp,
3075 struct bnxt_filter_info *bfilter,
3076 struct bnxt_vnic_info **mvnic)
3078 struct bnxt_filter_info *mfilter = NULL;
3081 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3082 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3083 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3084 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3085 bfilter->src_ipaddr_mask[0] ==
3086 mfilter->src_ipaddr_mask[0] &&
3087 bfilter->src_port == mfilter->src_port &&
3088 bfilter->src_port_mask == mfilter->src_port_mask &&
3089 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3090 bfilter->dst_ipaddr_mask[0] ==
3091 mfilter->dst_ipaddr_mask[0] &&
3092 bfilter->dst_port == mfilter->dst_port &&
3093 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3094 bfilter->flags == mfilter->flags &&
3095 bfilter->enables == mfilter->enables) {
3106 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3107 struct rte_eth_ntuple_filter *nfilter,
3108 enum rte_filter_op filter_op)
3110 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3111 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3114 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3115 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3119 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3120 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3124 bfilter = bnxt_get_unused_filter(bp);
3125 if (bfilter == NULL) {
3127 "Not enough resources for a new filter.\n");
3130 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3134 vnic = &bp->vnic_info[nfilter->queue];
3135 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3136 filter1 = STAILQ_FIRST(&vnic0->filter);
3137 if (filter1 == NULL) {
3142 bfilter->dst_id = vnic->fw_vnic_id;
3143 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3145 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3146 bfilter->ethertype = 0x800;
3147 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3149 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3151 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3152 bfilter->dst_id == mfilter->dst_id) {
3153 PMD_DRV_LOG(ERR, "filter exists.\n");
3156 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3157 bfilter->dst_id != mfilter->dst_id) {
3158 mfilter->dst_id = vnic->fw_vnic_id;
3159 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3160 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3161 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3162 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3163 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3166 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3167 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3172 if (filter_op == RTE_ETH_FILTER_ADD) {
3173 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3174 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3177 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3179 if (mfilter == NULL) {
3180 /* This should not happen. But for Coverity! */
3184 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3186 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3187 bnxt_free_filter(bp, mfilter);
3188 bnxt_free_filter(bp, bfilter);
3193 bnxt_free_filter(bp, bfilter);
3198 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3199 enum rte_filter_op filter_op,
3202 struct bnxt *bp = dev->data->dev_private;
3205 if (filter_op == RTE_ETH_FILTER_NOP)
3209 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3214 switch (filter_op) {
3215 case RTE_ETH_FILTER_ADD:
3216 ret = bnxt_cfg_ntuple_filter(bp,
3217 (struct rte_eth_ntuple_filter *)arg,
3220 case RTE_ETH_FILTER_DELETE:
3221 ret = bnxt_cfg_ntuple_filter(bp,
3222 (struct rte_eth_ntuple_filter *)arg,
3226 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3234 bnxt_parse_fdir_filter(struct bnxt *bp,
3235 struct rte_eth_fdir_filter *fdir,
3236 struct bnxt_filter_info *filter)
3238 enum rte_fdir_mode fdir_mode =
3239 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3240 struct bnxt_vnic_info *vnic0, *vnic;
3241 struct bnxt_filter_info *filter1;
3245 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3248 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3249 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3251 switch (fdir->input.flow_type) {
3252 case RTE_ETH_FLOW_IPV4:
3253 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3255 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3257 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3259 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3260 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3261 filter->ip_addr_type =
3262 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3263 filter->src_ipaddr_mask[0] = 0xffffffff;
3264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3265 filter->dst_ipaddr_mask[0] = 0xffffffff;
3266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3267 filter->ethertype = 0x800;
3268 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3270 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3271 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3272 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3273 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3274 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3275 filter->dst_port_mask = 0xffff;
3276 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3277 filter->src_port_mask = 0xffff;
3278 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3279 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3280 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3281 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3282 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3283 filter->ip_protocol = 6;
3284 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3285 filter->ip_addr_type =
3286 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3287 filter->src_ipaddr_mask[0] = 0xffffffff;
3288 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3289 filter->dst_ipaddr_mask[0] = 0xffffffff;
3290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3291 filter->ethertype = 0x800;
3292 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3294 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3295 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3296 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3297 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3299 filter->dst_port_mask = 0xffff;
3300 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3301 filter->src_port_mask = 0xffff;
3302 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3303 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3304 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3305 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3306 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3307 filter->ip_protocol = 17;
3308 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3309 filter->ip_addr_type =
3310 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3311 filter->src_ipaddr_mask[0] = 0xffffffff;
3312 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3313 filter->dst_ipaddr_mask[0] = 0xffffffff;
3314 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3315 filter->ethertype = 0x800;
3316 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3318 case RTE_ETH_FLOW_IPV6:
3319 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3321 filter->ip_addr_type =
3322 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3323 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3324 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3325 rte_memcpy(filter->src_ipaddr,
3326 fdir->input.flow.ipv6_flow.src_ip, 16);
3327 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3328 rte_memcpy(filter->dst_ipaddr,
3329 fdir->input.flow.ipv6_flow.dst_ip, 16);
3330 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3331 memset(filter->dst_ipaddr_mask, 0xff, 16);
3332 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3333 memset(filter->src_ipaddr_mask, 0xff, 16);
3334 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3335 filter->ethertype = 0x86dd;
3336 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3338 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3339 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3340 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3341 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3342 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3343 filter->dst_port_mask = 0xffff;
3344 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3345 filter->src_port_mask = 0xffff;
3346 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3347 filter->ip_addr_type =
3348 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3349 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3350 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3351 rte_memcpy(filter->src_ipaddr,
3352 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3353 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3354 rte_memcpy(filter->dst_ipaddr,
3355 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3356 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3357 memset(filter->dst_ipaddr_mask, 0xff, 16);
3358 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3359 memset(filter->src_ipaddr_mask, 0xff, 16);
3360 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3361 filter->ethertype = 0x86dd;
3362 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3364 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3365 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3366 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3367 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3368 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3369 filter->dst_port_mask = 0xffff;
3370 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3371 filter->src_port_mask = 0xffff;
3372 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3373 filter->ip_addr_type =
3374 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3375 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3376 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3377 rte_memcpy(filter->src_ipaddr,
3378 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3379 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3380 rte_memcpy(filter->dst_ipaddr,
3381 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3382 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3383 memset(filter->dst_ipaddr_mask, 0xff, 16);
3384 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3385 memset(filter->src_ipaddr_mask, 0xff, 16);
3386 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3387 filter->ethertype = 0x86dd;
3388 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3390 case RTE_ETH_FLOW_L2_PAYLOAD:
3391 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3392 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3394 case RTE_ETH_FLOW_VXLAN:
3395 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3397 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3398 filter->tunnel_type =
3399 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3400 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3402 case RTE_ETH_FLOW_NVGRE:
3403 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3405 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3406 filter->tunnel_type =
3407 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3408 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3410 case RTE_ETH_FLOW_UNKNOWN:
3411 case RTE_ETH_FLOW_RAW:
3412 case RTE_ETH_FLOW_FRAG_IPV4:
3413 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3414 case RTE_ETH_FLOW_FRAG_IPV6:
3415 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3416 case RTE_ETH_FLOW_IPV6_EX:
3417 case RTE_ETH_FLOW_IPV6_TCP_EX:
3418 case RTE_ETH_FLOW_IPV6_UDP_EX:
3419 case RTE_ETH_FLOW_GENEVE:
3425 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3426 vnic = &bp->vnic_info[fdir->action.rx_queue];
3428 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3432 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3433 rte_memcpy(filter->dst_macaddr,
3434 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3438 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3439 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3440 filter1 = STAILQ_FIRST(&vnic0->filter);
3441 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3443 filter->dst_id = vnic->fw_vnic_id;
3444 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3445 if (filter->dst_macaddr[i] == 0x00)
3446 filter1 = STAILQ_FIRST(&vnic0->filter);
3448 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3451 if (filter1 == NULL)
3454 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3455 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3457 filter->enables = en;
3462 static struct bnxt_filter_info *
3463 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3464 struct bnxt_vnic_info **mvnic)
3466 struct bnxt_filter_info *mf = NULL;
3469 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3470 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3472 STAILQ_FOREACH(mf, &vnic->filter, next) {
3473 if (mf->filter_type == nf->filter_type &&
3474 mf->flags == nf->flags &&
3475 mf->src_port == nf->src_port &&
3476 mf->src_port_mask == nf->src_port_mask &&
3477 mf->dst_port == nf->dst_port &&
3478 mf->dst_port_mask == nf->dst_port_mask &&
3479 mf->ip_protocol == nf->ip_protocol &&
3480 mf->ip_addr_type == nf->ip_addr_type &&
3481 mf->ethertype == nf->ethertype &&
3482 mf->vni == nf->vni &&
3483 mf->tunnel_type == nf->tunnel_type &&
3484 mf->l2_ovlan == nf->l2_ovlan &&
3485 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3486 mf->l2_ivlan == nf->l2_ivlan &&
3487 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3488 !memcmp(mf->l2_addr, nf->l2_addr,
3489 RTE_ETHER_ADDR_LEN) &&
3490 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3491 RTE_ETHER_ADDR_LEN) &&
3492 !memcmp(mf->src_macaddr, nf->src_macaddr,
3493 RTE_ETHER_ADDR_LEN) &&
3494 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3495 RTE_ETHER_ADDR_LEN) &&
3496 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3497 sizeof(nf->src_ipaddr)) &&
3498 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3499 sizeof(nf->src_ipaddr_mask)) &&
3500 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3501 sizeof(nf->dst_ipaddr)) &&
3502 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3503 sizeof(nf->dst_ipaddr_mask))) {
3514 bnxt_fdir_filter(struct rte_eth_dev *dev,
3515 enum rte_filter_op filter_op,
3518 struct bnxt *bp = dev->data->dev_private;
3519 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3520 struct bnxt_filter_info *filter, *match;
3521 struct bnxt_vnic_info *vnic, *mvnic;
3524 if (filter_op == RTE_ETH_FILTER_NOP)
3527 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3530 switch (filter_op) {
3531 case RTE_ETH_FILTER_ADD:
3532 case RTE_ETH_FILTER_DELETE:
3534 filter = bnxt_get_unused_filter(bp);
3535 if (filter == NULL) {
3537 "Not enough resources for a new flow.\n");
3541 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3544 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3546 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3547 vnic = &bp->vnic_info[0];
3549 vnic = &bp->vnic_info[fdir->action.rx_queue];
3551 match = bnxt_match_fdir(bp, filter, &mvnic);
3552 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3553 if (match->dst_id == vnic->fw_vnic_id) {
3554 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3558 match->dst_id = vnic->fw_vnic_id;
3559 ret = bnxt_hwrm_set_ntuple_filter(bp,
3562 STAILQ_REMOVE(&mvnic->filter, match,
3563 bnxt_filter_info, next);
3564 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3566 "Filter with matching pattern exist\n");
3568 "Updated it to new destination q\n");
3572 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3573 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3578 if (filter_op == RTE_ETH_FILTER_ADD) {
3579 ret = bnxt_hwrm_set_ntuple_filter(bp,
3584 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3586 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3587 STAILQ_REMOVE(&vnic->filter, match,
3588 bnxt_filter_info, next);
3589 bnxt_free_filter(bp, match);
3590 bnxt_free_filter(bp, filter);
3593 case RTE_ETH_FILTER_FLUSH:
3594 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3595 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3597 STAILQ_FOREACH(filter, &vnic->filter, next) {
3598 if (filter->filter_type ==
3599 HWRM_CFA_NTUPLE_FILTER) {
3601 bnxt_hwrm_clear_ntuple_filter(bp,
3603 STAILQ_REMOVE(&vnic->filter, filter,
3604 bnxt_filter_info, next);
3609 case RTE_ETH_FILTER_UPDATE:
3610 case RTE_ETH_FILTER_STATS:
3611 case RTE_ETH_FILTER_INFO:
3612 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3615 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3622 bnxt_free_filter(bp, filter);
3627 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3628 enum rte_filter_type filter_type,
3629 enum rte_filter_op filter_op, void *arg)
3631 struct bnxt *bp = dev->data->dev_private;
3634 ret = is_bnxt_in_error(dev->data->dev_private);
3638 switch (filter_type) {
3639 case RTE_ETH_FILTER_TUNNEL:
3641 "filter type: %d: To be implemented\n", filter_type);
3643 case RTE_ETH_FILTER_FDIR:
3644 ret = bnxt_fdir_filter(dev, filter_op, arg);
3646 case RTE_ETH_FILTER_NTUPLE:
3647 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3649 case RTE_ETH_FILTER_ETHERTYPE:
3650 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3652 case RTE_ETH_FILTER_GENERIC:
3653 if (filter_op != RTE_ETH_FILTER_GET)
3655 if (BNXT_TRUFLOW_EN(bp))
3656 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3658 *(const void **)arg = &bnxt_flow_ops;
3662 "Filter type (%d) not supported", filter_type);
3669 static const uint32_t *
3670 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3672 static const uint32_t ptypes[] = {
3673 RTE_PTYPE_L2_ETHER_VLAN,
3674 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3675 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3679 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3680 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3681 RTE_PTYPE_INNER_L4_ICMP,
3682 RTE_PTYPE_INNER_L4_TCP,
3683 RTE_PTYPE_INNER_L4_UDP,
3687 if (!dev->rx_pkt_burst)
3693 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3696 uint32_t reg_base = *reg_arr & 0xfffff000;
3700 for (i = 0; i < count; i++) {
3701 if ((reg_arr[i] & 0xfffff000) != reg_base)
3704 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3705 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3709 static int bnxt_map_ptp_regs(struct bnxt *bp)
3711 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3715 reg_arr = ptp->rx_regs;
3716 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3720 reg_arr = ptp->tx_regs;
3721 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3725 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3726 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3728 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3729 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3734 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3736 rte_write32(0, (uint8_t *)bp->bar0 +
3737 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3738 rte_write32(0, (uint8_t *)bp->bar0 +
3739 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3742 static uint64_t bnxt_cc_read(struct bnxt *bp)
3746 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3747 BNXT_GRCPF_REG_SYNC_TIME));
3748 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3749 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3753 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3755 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3758 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3759 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3760 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3763 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3764 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3765 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3766 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3767 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3768 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3773 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3775 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3776 struct bnxt_pf_info *pf = bp->pf;
3783 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3784 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3785 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3788 port_id = pf->port_id;
3789 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3790 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3792 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3793 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3794 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3795 /* bnxt_clr_rx_ts(bp); TBD */
3799 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3800 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3801 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3802 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3808 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3811 struct bnxt *bp = dev->data->dev_private;
3812 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3817 ns = rte_timespec_to_ns(ts);
3818 /* Set the timecounters to a new value. */
3825 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3827 struct bnxt *bp = dev->data->dev_private;
3828 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3829 uint64_t ns, systime_cycles = 0;
3835 if (BNXT_CHIP_THOR(bp))
3836 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3839 systime_cycles = bnxt_cc_read(bp);
3841 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3842 *ts = rte_ns_to_timespec(ns);
3847 bnxt_timesync_enable(struct rte_eth_dev *dev)
3849 struct bnxt *bp = dev->data->dev_private;
3850 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3858 ptp->tx_tstamp_en = 1;
3859 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3861 rc = bnxt_hwrm_ptp_cfg(bp);
3865 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3866 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3867 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3869 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3870 ptp->tc.cc_shift = shift;
3871 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3873 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3874 ptp->rx_tstamp_tc.cc_shift = shift;
3875 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3877 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3878 ptp->tx_tstamp_tc.cc_shift = shift;
3879 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3881 if (!BNXT_CHIP_THOR(bp))
3882 bnxt_map_ptp_regs(bp);
3888 bnxt_timesync_disable(struct rte_eth_dev *dev)
3890 struct bnxt *bp = dev->data->dev_private;
3891 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3897 ptp->tx_tstamp_en = 0;
3900 bnxt_hwrm_ptp_cfg(bp);
3902 if (!BNXT_CHIP_THOR(bp))
3903 bnxt_unmap_ptp_regs(bp);
3909 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3910 struct timespec *timestamp,
3911 uint32_t flags __rte_unused)
3913 struct bnxt *bp = dev->data->dev_private;
3914 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3915 uint64_t rx_tstamp_cycles = 0;
3921 if (BNXT_CHIP_THOR(bp))
3922 rx_tstamp_cycles = ptp->rx_timestamp;
3924 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3926 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3927 *timestamp = rte_ns_to_timespec(ns);
3932 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3933 struct timespec *timestamp)
3935 struct bnxt *bp = dev->data->dev_private;
3936 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3937 uint64_t tx_tstamp_cycles = 0;
3944 if (BNXT_CHIP_THOR(bp))
3945 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3948 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3950 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3951 *timestamp = rte_ns_to_timespec(ns);
3957 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3959 struct bnxt *bp = dev->data->dev_private;
3960 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3965 ptp->tc.nsec += delta;
3971 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3973 struct bnxt *bp = dev->data->dev_private;
3975 uint32_t dir_entries;
3976 uint32_t entry_length;
3978 rc = is_bnxt_in_error(bp);
3982 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3983 bp->pdev->addr.domain, bp->pdev->addr.bus,
3984 bp->pdev->addr.devid, bp->pdev->addr.function);
3986 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3990 return dir_entries * entry_length;
3994 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3995 struct rte_dev_eeprom_info *in_eeprom)
3997 struct bnxt *bp = dev->data->dev_private;
4002 rc = is_bnxt_in_error(bp);
4006 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4007 bp->pdev->addr.domain, bp->pdev->addr.bus,
4008 bp->pdev->addr.devid, bp->pdev->addr.function,
4009 in_eeprom->offset, in_eeprom->length);
4011 if (in_eeprom->offset == 0) /* special offset value to get directory */
4012 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4015 index = in_eeprom->offset >> 24;
4016 offset = in_eeprom->offset & 0xffffff;
4019 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4020 in_eeprom->length, in_eeprom->data);
4025 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4028 case BNX_DIR_TYPE_CHIMP_PATCH:
4029 case BNX_DIR_TYPE_BOOTCODE:
4030 case BNX_DIR_TYPE_BOOTCODE_2:
4031 case BNX_DIR_TYPE_APE_FW:
4032 case BNX_DIR_TYPE_APE_PATCH:
4033 case BNX_DIR_TYPE_KONG_FW:
4034 case BNX_DIR_TYPE_KONG_PATCH:
4035 case BNX_DIR_TYPE_BONO_FW:
4036 case BNX_DIR_TYPE_BONO_PATCH:
4044 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4047 case BNX_DIR_TYPE_AVS:
4048 case BNX_DIR_TYPE_EXP_ROM_MBA:
4049 case BNX_DIR_TYPE_PCIE:
4050 case BNX_DIR_TYPE_TSCF_UCODE:
4051 case BNX_DIR_TYPE_EXT_PHY:
4052 case BNX_DIR_TYPE_CCM:
4053 case BNX_DIR_TYPE_ISCSI_BOOT:
4054 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4055 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4063 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4065 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4066 bnxt_dir_type_is_other_exec_format(dir_type);
4070 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4071 struct rte_dev_eeprom_info *in_eeprom)
4073 struct bnxt *bp = dev->data->dev_private;
4074 uint8_t index, dir_op;
4075 uint16_t type, ext, ordinal, attr;
4078 rc = is_bnxt_in_error(bp);
4082 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4083 bp->pdev->addr.domain, bp->pdev->addr.bus,
4084 bp->pdev->addr.devid, bp->pdev->addr.function,
4085 in_eeprom->offset, in_eeprom->length);
4088 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4092 type = in_eeprom->magic >> 16;
4094 if (type == 0xffff) { /* special value for directory operations */
4095 index = in_eeprom->magic & 0xff;
4096 dir_op = in_eeprom->magic >> 8;
4100 case 0x0e: /* erase */
4101 if (in_eeprom->offset != ~in_eeprom->magic)
4103 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4109 /* Create or re-write an NVM item: */
4110 if (bnxt_dir_type_is_executable(type) == true)
4112 ext = in_eeprom->magic & 0xffff;
4113 ordinal = in_eeprom->offset >> 16;
4114 attr = in_eeprom->offset & 0xffff;
4116 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4117 in_eeprom->data, in_eeprom->length);
4124 static const struct eth_dev_ops bnxt_dev_ops = {
4125 .dev_infos_get = bnxt_dev_info_get_op,
4126 .dev_close = bnxt_dev_close_op,
4127 .dev_configure = bnxt_dev_configure_op,
4128 .dev_start = bnxt_dev_start_op,
4129 .dev_stop = bnxt_dev_stop_op,
4130 .dev_set_link_up = bnxt_dev_set_link_up_op,
4131 .dev_set_link_down = bnxt_dev_set_link_down_op,
4132 .stats_get = bnxt_stats_get_op,
4133 .stats_reset = bnxt_stats_reset_op,
4134 .rx_queue_setup = bnxt_rx_queue_setup_op,
4135 .rx_queue_release = bnxt_rx_queue_release_op,
4136 .tx_queue_setup = bnxt_tx_queue_setup_op,
4137 .tx_queue_release = bnxt_tx_queue_release_op,
4138 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4139 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4140 .reta_update = bnxt_reta_update_op,
4141 .reta_query = bnxt_reta_query_op,
4142 .rss_hash_update = bnxt_rss_hash_update_op,
4143 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4144 .link_update = bnxt_link_update_op,
4145 .promiscuous_enable = bnxt_promiscuous_enable_op,
4146 .promiscuous_disable = bnxt_promiscuous_disable_op,
4147 .allmulticast_enable = bnxt_allmulticast_enable_op,
4148 .allmulticast_disable = bnxt_allmulticast_disable_op,
4149 .mac_addr_add = bnxt_mac_addr_add_op,
4150 .mac_addr_remove = bnxt_mac_addr_remove_op,
4151 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4152 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4153 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4154 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4155 .vlan_filter_set = bnxt_vlan_filter_set_op,
4156 .vlan_offload_set = bnxt_vlan_offload_set_op,
4157 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4158 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4159 .mtu_set = bnxt_mtu_set_op,
4160 .mac_addr_set = bnxt_set_default_mac_addr_op,
4161 .xstats_get = bnxt_dev_xstats_get_op,
4162 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4163 .xstats_reset = bnxt_dev_xstats_reset_op,
4164 .fw_version_get = bnxt_fw_version_get,
4165 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4166 .rxq_info_get = bnxt_rxq_info_get_op,
4167 .txq_info_get = bnxt_txq_info_get_op,
4168 .dev_led_on = bnxt_dev_led_on_op,
4169 .dev_led_off = bnxt_dev_led_off_op,
4170 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4171 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4172 .rx_queue_count = bnxt_rx_queue_count_op,
4173 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4174 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4175 .rx_queue_start = bnxt_rx_queue_start,
4176 .rx_queue_stop = bnxt_rx_queue_stop,
4177 .tx_queue_start = bnxt_tx_queue_start,
4178 .tx_queue_stop = bnxt_tx_queue_stop,
4179 .filter_ctrl = bnxt_filter_ctrl_op,
4180 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4181 .get_eeprom_length = bnxt_get_eeprom_length_op,
4182 .get_eeprom = bnxt_get_eeprom_op,
4183 .set_eeprom = bnxt_set_eeprom_op,
4184 .timesync_enable = bnxt_timesync_enable,
4185 .timesync_disable = bnxt_timesync_disable,
4186 .timesync_read_time = bnxt_timesync_read_time,
4187 .timesync_write_time = bnxt_timesync_write_time,
4188 .timesync_adjust_time = bnxt_timesync_adjust_time,
4189 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4190 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4193 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4197 /* Only pre-map the reset GRC registers using window 3 */
4198 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4199 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4201 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4206 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4208 struct bnxt_error_recovery_info *info = bp->recovery_info;
4209 uint32_t reg_base = 0xffffffff;
4212 /* Only pre-map the monitoring GRC registers using window 2 */
4213 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4214 uint32_t reg = info->status_regs[i];
4216 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4219 if (reg_base == 0xffffffff)
4220 reg_base = reg & 0xfffff000;
4221 if ((reg & 0xfffff000) != reg_base)
4224 /* Use mask 0xffc as the Lower 2 bits indicates
4225 * address space location
4227 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4231 if (reg_base == 0xffffffff)
4234 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4235 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4240 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4242 struct bnxt_error_recovery_info *info = bp->recovery_info;
4243 uint32_t delay = info->delay_after_reset[index];
4244 uint32_t val = info->reset_reg_val[index];
4245 uint32_t reg = info->reset_reg[index];
4246 uint32_t type, offset;
4248 type = BNXT_FW_STATUS_REG_TYPE(reg);
4249 offset = BNXT_FW_STATUS_REG_OFF(reg);
4252 case BNXT_FW_STATUS_REG_TYPE_CFG:
4253 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4255 case BNXT_FW_STATUS_REG_TYPE_GRC:
4256 offset = bnxt_map_reset_regs(bp, offset);
4257 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4259 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4260 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4263 /* wait on a specific interval of time until core reset is complete */
4265 rte_delay_ms(delay);
4268 static void bnxt_dev_cleanup(struct bnxt *bp)
4270 bnxt_set_hwrm_link_config(bp, false);
4271 bp->link_info->link_up = 0;
4272 if (bp->eth_dev->data->dev_started)
4273 bnxt_dev_stop_op(bp->eth_dev);
4275 bnxt_uninit_resources(bp, true);
4278 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4280 struct rte_eth_dev *dev = bp->eth_dev;
4281 struct rte_vlan_filter_conf *vfc;
4285 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4286 vfc = &dev->data->vlan_filter_conf;
4287 vidx = vlan_id / 64;
4288 vbit = vlan_id % 64;
4290 /* Each bit corresponds to a VLAN id */
4291 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4292 rc = bnxt_add_vlan_filter(bp, vlan_id);
4301 static int bnxt_restore_mac_filters(struct bnxt *bp)
4303 struct rte_eth_dev *dev = bp->eth_dev;
4304 struct rte_eth_dev_info dev_info;
4305 struct rte_ether_addr *addr;
4311 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4314 rc = bnxt_dev_info_get_op(dev, &dev_info);
4318 /* replay MAC address configuration */
4319 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4320 addr = &dev->data->mac_addrs[i];
4322 /* skip zero address */
4323 if (rte_is_zero_ether_addr(addr))
4327 pool_mask = dev->data->mac_pool_sel[i];
4330 if (pool_mask & 1ULL) {
4331 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4337 } while (pool_mask);
4343 static int bnxt_restore_filters(struct bnxt *bp)
4345 struct rte_eth_dev *dev = bp->eth_dev;
4348 if (dev->data->all_multicast) {
4349 ret = bnxt_allmulticast_enable_op(dev);
4353 if (dev->data->promiscuous) {
4354 ret = bnxt_promiscuous_enable_op(dev);
4359 ret = bnxt_restore_mac_filters(bp);
4363 ret = bnxt_restore_vlan_filters(bp);
4364 /* TODO restore other filters as well */
4368 static void bnxt_dev_recover(void *arg)
4370 struct bnxt *bp = arg;
4371 int timeout = bp->fw_reset_max_msecs;
4374 /* Clear Error flag so that device re-init should happen */
4375 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4378 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4381 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4382 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4383 } while (rc && timeout);
4386 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4390 rc = bnxt_init_resources(bp, true);
4393 "Failed to initialize resources after reset\n");
4396 /* clear reset flag as the device is initialized now */
4397 bp->flags &= ~BNXT_FLAG_FW_RESET;
4399 rc = bnxt_dev_start_op(bp->eth_dev);
4401 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4405 rc = bnxt_restore_filters(bp);
4409 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4412 bnxt_dev_stop_op(bp->eth_dev);
4414 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4415 bnxt_uninit_resources(bp, false);
4416 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4419 void bnxt_dev_reset_and_resume(void *arg)
4421 struct bnxt *bp = arg;
4424 bnxt_dev_cleanup(bp);
4426 bnxt_wait_for_device_shutdown(bp);
4428 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4429 bnxt_dev_recover, (void *)bp);
4431 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4434 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4436 struct bnxt_error_recovery_info *info = bp->recovery_info;
4437 uint32_t reg = info->status_regs[index];
4438 uint32_t type, offset, val = 0;
4440 type = BNXT_FW_STATUS_REG_TYPE(reg);
4441 offset = BNXT_FW_STATUS_REG_OFF(reg);
4444 case BNXT_FW_STATUS_REG_TYPE_CFG:
4445 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4447 case BNXT_FW_STATUS_REG_TYPE_GRC:
4448 offset = info->mapped_status_regs[index];
4450 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4451 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4459 static int bnxt_fw_reset_all(struct bnxt *bp)
4461 struct bnxt_error_recovery_info *info = bp->recovery_info;
4465 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4466 /* Reset through master function driver */
4467 for (i = 0; i < info->reg_array_cnt; i++)
4468 bnxt_write_fw_reset_reg(bp, i);
4469 /* Wait for time specified by FW after triggering reset */
4470 rte_delay_ms(info->master_func_wait_period_after_reset);
4471 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4472 /* Reset with the help of Kong processor */
4473 rc = bnxt_hwrm_fw_reset(bp);
4475 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4481 static void bnxt_fw_reset_cb(void *arg)
4483 struct bnxt *bp = arg;
4484 struct bnxt_error_recovery_info *info = bp->recovery_info;
4487 /* Only Master function can do FW reset */
4488 if (bnxt_is_master_func(bp) &&
4489 bnxt_is_recovery_enabled(bp)) {
4490 rc = bnxt_fw_reset_all(bp);
4492 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4497 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4498 * EXCEPTION_FATAL_ASYNC event to all the functions
4499 * (including MASTER FUNC). After receiving this Async, all the active
4500 * drivers should treat this case as FW initiated recovery
4502 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4503 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4504 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4506 /* To recover from error */
4507 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4512 /* Driver should poll FW heartbeat, reset_counter with the frequency
4513 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4514 * When the driver detects heartbeat stop or change in reset_counter,
4515 * it has to trigger a reset to recover from the error condition.
4516 * A “master PF” is the function who will have the privilege to
4517 * initiate the chimp reset. The master PF will be elected by the
4518 * firmware and will be notified through async message.
4520 static void bnxt_check_fw_health(void *arg)
4522 struct bnxt *bp = arg;
4523 struct bnxt_error_recovery_info *info = bp->recovery_info;
4524 uint32_t val = 0, wait_msec;
4526 if (!info || !bnxt_is_recovery_enabled(bp) ||
4527 is_bnxt_in_error(bp))
4530 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4531 if (val == info->last_heart_beat)
4534 info->last_heart_beat = val;
4536 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4537 if (val != info->last_reset_counter)
4540 info->last_reset_counter = val;
4542 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4543 bnxt_check_fw_health, (void *)bp);
4547 /* Stop DMA to/from device */
4548 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4549 bp->flags |= BNXT_FLAG_FW_RESET;
4551 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4553 if (bnxt_is_master_func(bp))
4554 wait_msec = info->master_func_wait_period;
4556 wait_msec = info->normal_func_wait_period;
4558 rte_eal_alarm_set(US_PER_MS * wait_msec,
4559 bnxt_fw_reset_cb, (void *)bp);
4562 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4564 uint32_t polling_freq;
4566 if (!bnxt_is_recovery_enabled(bp))
4569 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4572 polling_freq = bp->recovery_info->driver_polling_freq;
4574 rte_eal_alarm_set(US_PER_MS * polling_freq,
4575 bnxt_check_fw_health, (void *)bp);
4576 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4579 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4581 if (!bnxt_is_recovery_enabled(bp))
4584 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4585 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4588 static bool bnxt_vf_pciid(uint16_t device_id)
4590 switch (device_id) {
4591 case BROADCOM_DEV_ID_57304_VF:
4592 case BROADCOM_DEV_ID_57406_VF:
4593 case BROADCOM_DEV_ID_5731X_VF:
4594 case BROADCOM_DEV_ID_5741X_VF:
4595 case BROADCOM_DEV_ID_57414_VF:
4596 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4597 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4598 case BROADCOM_DEV_ID_58802_VF:
4599 case BROADCOM_DEV_ID_57500_VF1:
4600 case BROADCOM_DEV_ID_57500_VF2:
4608 static bool bnxt_thor_device(uint16_t device_id)
4610 switch (device_id) {
4611 case BROADCOM_DEV_ID_57508:
4612 case BROADCOM_DEV_ID_57504:
4613 case BROADCOM_DEV_ID_57502:
4614 case BROADCOM_DEV_ID_57508_MF1:
4615 case BROADCOM_DEV_ID_57504_MF1:
4616 case BROADCOM_DEV_ID_57502_MF1:
4617 case BROADCOM_DEV_ID_57508_MF2:
4618 case BROADCOM_DEV_ID_57504_MF2:
4619 case BROADCOM_DEV_ID_57502_MF2:
4620 case BROADCOM_DEV_ID_57500_VF1:
4621 case BROADCOM_DEV_ID_57500_VF2:
4629 bool bnxt_stratus_device(struct bnxt *bp)
4631 uint16_t device_id = bp->pdev->id.device_id;
4633 switch (device_id) {
4634 case BROADCOM_DEV_ID_STRATUS_NIC:
4635 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4636 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4644 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4646 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4647 struct bnxt *bp = eth_dev->data->dev_private;
4649 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4650 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4651 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4652 if (!bp->bar0 || !bp->doorbell_base) {
4653 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4657 bp->eth_dev = eth_dev;
4663 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4664 struct bnxt_ctx_pg_info *ctx_pg,
4669 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4670 const struct rte_memzone *mz = NULL;
4671 char mz_name[RTE_MEMZONE_NAMESIZE];
4672 rte_iova_t mz_phys_addr;
4673 uint64_t valid_bits = 0;
4680 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4682 rmem->page_size = BNXT_PAGE_SIZE;
4683 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4684 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4685 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4687 valid_bits = PTU_PTE_VALID;
4689 if (rmem->nr_pages > 1) {
4690 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4691 "bnxt_ctx_pg_tbl%s_%x_%d",
4692 suffix, idx, bp->eth_dev->data->port_id);
4693 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4694 mz = rte_memzone_lookup(mz_name);
4696 mz = rte_memzone_reserve_aligned(mz_name,
4700 RTE_MEMZONE_SIZE_HINT_ONLY |
4701 RTE_MEMZONE_IOVA_CONTIG,
4707 memset(mz->addr, 0, mz->len);
4708 mz_phys_addr = mz->iova;
4710 rmem->pg_tbl = mz->addr;
4711 rmem->pg_tbl_map = mz_phys_addr;
4712 rmem->pg_tbl_mz = mz;
4715 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4716 suffix, idx, bp->eth_dev->data->port_id);
4717 mz = rte_memzone_lookup(mz_name);
4719 mz = rte_memzone_reserve_aligned(mz_name,
4723 RTE_MEMZONE_SIZE_HINT_ONLY |
4724 RTE_MEMZONE_IOVA_CONTIG,
4730 memset(mz->addr, 0, mz->len);
4731 mz_phys_addr = mz->iova;
4733 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4734 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4735 rmem->dma_arr[i] = mz_phys_addr + sz;
4737 if (rmem->nr_pages > 1) {
4738 if (i == rmem->nr_pages - 2 &&
4739 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4740 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4741 else if (i == rmem->nr_pages - 1 &&
4742 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4743 valid_bits |= PTU_PTE_LAST;
4745 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4751 if (rmem->vmem_size)
4752 rmem->vmem = (void **)mz->addr;
4753 rmem->dma_arr[0] = mz_phys_addr;
4757 static void bnxt_free_ctx_mem(struct bnxt *bp)
4761 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4764 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4765 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4766 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4767 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4768 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4769 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4770 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4771 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4772 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4773 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4774 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4776 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4777 if (bp->ctx->tqm_mem[i])
4778 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4785 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4787 #define min_t(type, x, y) ({ \
4788 type __min1 = (x); \
4789 type __min2 = (y); \
4790 __min1 < __min2 ? __min1 : __min2; })
4792 #define max_t(type, x, y) ({ \
4793 type __max1 = (x); \
4794 type __max2 = (y); \
4795 __max1 > __max2 ? __max1 : __max2; })
4797 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4799 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4801 struct bnxt_ctx_pg_info *ctx_pg;
4802 struct bnxt_ctx_mem_info *ctx;
4803 uint32_t mem_size, ena, entries;
4804 uint32_t entries_sp, min;
4807 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4809 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4813 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4816 ctx_pg = &ctx->qp_mem;
4817 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4818 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4819 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4823 ctx_pg = &ctx->srq_mem;
4824 ctx_pg->entries = ctx->srq_max_l2_entries;
4825 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4826 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4830 ctx_pg = &ctx->cq_mem;
4831 ctx_pg->entries = ctx->cq_max_l2_entries;
4832 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4833 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4837 ctx_pg = &ctx->vnic_mem;
4838 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4839 ctx->vnic_max_ring_table_entries;
4840 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4841 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4845 ctx_pg = &ctx->stat_mem;
4846 ctx_pg->entries = ctx->stat_max_entries;
4847 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4848 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4852 min = ctx->tqm_min_entries_per_ring;
4854 entries_sp = ctx->qp_max_l2_entries +
4855 ctx->vnic_max_vnic_entries +
4856 2 * ctx->qp_min_qp1_entries + min;
4857 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4859 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4860 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4861 entries = clamp_t(uint32_t, entries, min,
4862 ctx->tqm_max_entries_per_ring);
4863 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4864 ctx_pg = ctx->tqm_mem[i];
4865 ctx_pg->entries = i ? entries : entries_sp;
4866 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4867 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4870 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4873 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4874 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4877 "Failed to configure context mem: rc = %d\n", rc);
4879 ctx->flags |= BNXT_CTX_FLAG_INITED;
4884 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4886 struct rte_pci_device *pci_dev = bp->pdev;
4887 char mz_name[RTE_MEMZONE_NAMESIZE];
4888 const struct rte_memzone *mz = NULL;
4889 uint32_t total_alloc_len;
4890 rte_iova_t mz_phys_addr;
4892 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4895 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4896 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4897 pci_dev->addr.bus, pci_dev->addr.devid,
4898 pci_dev->addr.function, "rx_port_stats");
4899 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4900 mz = rte_memzone_lookup(mz_name);
4902 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4903 sizeof(struct rx_port_stats_ext) + 512);
4905 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4908 RTE_MEMZONE_SIZE_HINT_ONLY |
4909 RTE_MEMZONE_IOVA_CONTIG);
4913 memset(mz->addr, 0, mz->len);
4914 mz_phys_addr = mz->iova;
4916 bp->rx_mem_zone = (const void *)mz;
4917 bp->hw_rx_port_stats = mz->addr;
4918 bp->hw_rx_port_stats_map = mz_phys_addr;
4920 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4921 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4922 pci_dev->addr.bus, pci_dev->addr.devid,
4923 pci_dev->addr.function, "tx_port_stats");
4924 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4925 mz = rte_memzone_lookup(mz_name);
4927 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4928 sizeof(struct tx_port_stats_ext) + 512);
4930 mz = rte_memzone_reserve(mz_name,
4934 RTE_MEMZONE_SIZE_HINT_ONLY |
4935 RTE_MEMZONE_IOVA_CONTIG);
4939 memset(mz->addr, 0, mz->len);
4940 mz_phys_addr = mz->iova;
4942 bp->tx_mem_zone = (const void *)mz;
4943 bp->hw_tx_port_stats = mz->addr;
4944 bp->hw_tx_port_stats_map = mz_phys_addr;
4945 bp->flags |= BNXT_FLAG_PORT_STATS;
4947 /* Display extended statistics if FW supports it */
4948 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4949 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4950 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4953 bp->hw_rx_port_stats_ext = (void *)
4954 ((uint8_t *)bp->hw_rx_port_stats +
4955 sizeof(struct rx_port_stats));
4956 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4957 sizeof(struct rx_port_stats);
4958 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4960 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4961 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4962 bp->hw_tx_port_stats_ext = (void *)
4963 ((uint8_t *)bp->hw_tx_port_stats +
4964 sizeof(struct tx_port_stats));
4965 bp->hw_tx_port_stats_ext_map =
4966 bp->hw_tx_port_stats_map +
4967 sizeof(struct tx_port_stats);
4968 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4974 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4976 struct bnxt *bp = eth_dev->data->dev_private;
4979 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4980 RTE_ETHER_ADDR_LEN *
4983 if (eth_dev->data->mac_addrs == NULL) {
4984 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4988 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4992 /* Generate a random MAC address, if none was assigned by PF */
4993 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4994 bnxt_eth_hw_addr_random(bp->mac_addr);
4996 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4997 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4998 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5000 rc = bnxt_hwrm_set_mac(bp);
5005 /* Copy the permanent MAC from the FUNC_QCAPS response */
5006 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5011 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5015 /* MAC is already configured in FW */
5016 if (BNXT_HAS_DFLT_MAC_SET(bp))
5019 /* Restore the old MAC configured */
5020 rc = bnxt_hwrm_set_mac(bp);
5022 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5027 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5032 #define ALLOW_FUNC(x) \
5034 uint32_t arg = (x); \
5035 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5036 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5039 /* Forward all requests if firmware is new enough */
5040 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5041 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5042 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5043 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5045 PMD_DRV_LOG(WARNING,
5046 "Firmware too old for VF mailbox functionality\n");
5047 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5051 * The following are used for driver cleanup. If we disallow these,
5052 * VF drivers can't clean up cleanly.
5054 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5055 ALLOW_FUNC(HWRM_VNIC_FREE);
5056 ALLOW_FUNC(HWRM_RING_FREE);
5057 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5058 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5059 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5060 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5061 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5062 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5066 bnxt_get_svif(uint16_t port_id, bool func_svif)
5068 struct rte_eth_dev *eth_dev;
5071 eth_dev = &rte_eth_devices[port_id];
5072 bp = eth_dev->data->dev_private;
5074 return func_svif ? bp->func_svif : bp->port_svif;
5078 bnxt_get_vnic_id(uint16_t port)
5080 struct rte_eth_dev *eth_dev;
5081 struct bnxt_vnic_info *vnic;
5084 eth_dev = &rte_eth_devices[port];
5085 bp = eth_dev->data->dev_private;
5087 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5089 return vnic->fw_vnic_id;
5093 bnxt_get_fw_func_id(uint16_t port)
5095 struct rte_eth_dev *eth_dev;
5098 eth_dev = &rte_eth_devices[port];
5099 bp = eth_dev->data->dev_private;
5104 enum bnxt_ulp_intf_type
5105 bnxt_get_interface_type(uint16_t port)
5107 struct rte_eth_dev *eth_dev;
5110 eth_dev = &rte_eth_devices[port];
5111 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5112 return BNXT_ULP_INTF_TYPE_VF_REP;
5114 bp = eth_dev->data->dev_private;
5115 return BNXT_PF(bp) ? BNXT_ULP_INTF_TYPE_PF
5116 : BNXT_ULP_INTF_TYPE_VF;
5120 bnxt_get_phy_port_id(uint16_t port_id)
5122 struct bnxt_vf_representor *vfr;
5123 struct rte_eth_dev *eth_dev;
5126 eth_dev = &rte_eth_devices[port_id];
5127 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5128 vfr = eth_dev->data->dev_private;
5129 eth_dev = vfr->parent_dev;
5132 bp = eth_dev->data->dev_private;
5134 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5138 bnxt_get_parif(uint16_t port_id)
5140 struct bnxt_vf_representor *vfr;
5141 struct rte_eth_dev *eth_dev;
5144 eth_dev = &rte_eth_devices[port_id];
5145 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5146 vfr = eth_dev->data->dev_private;
5147 eth_dev = vfr->parent_dev;
5150 bp = eth_dev->data->dev_private;
5152 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5156 bnxt_get_vport(uint16_t port_id)
5158 return (1 << bnxt_get_phy_port_id(port_id));
5161 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5163 struct bnxt_error_recovery_info *info = bp->recovery_info;
5166 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5167 memset(info, 0, sizeof(*info));
5171 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5174 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5177 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5179 bp->recovery_info = info;
5182 static void bnxt_check_fw_status(struct bnxt *bp)
5186 if (!(bp->recovery_info &&
5187 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5190 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5191 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5192 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5196 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5198 struct bnxt_error_recovery_info *info = bp->recovery_info;
5199 uint32_t status_loc;
5202 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5203 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5204 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5205 BNXT_GRCP_WINDOW_2_BASE +
5206 offsetof(struct hcomm_status,
5208 /* If the signature is absent, then FW does not support this feature */
5209 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5210 HCOMM_STATUS_SIGNATURE_VAL)
5214 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5218 bp->recovery_info = info;
5220 memset(info, 0, sizeof(*info));
5223 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5224 BNXT_GRCP_WINDOW_2_BASE +
5225 offsetof(struct hcomm_status,
5228 /* Only pre-map the FW health status GRC register */
5229 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5232 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5233 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5234 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5236 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5237 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5239 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5244 static int bnxt_init_fw(struct bnxt *bp)
5251 rc = bnxt_map_hcomm_fw_status_reg(bp);
5255 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5257 bnxt_check_fw_status(bp);
5261 rc = bnxt_hwrm_func_reset(bp);
5265 rc = bnxt_hwrm_vnic_qcaps(bp);
5269 rc = bnxt_hwrm_queue_qportcfg(bp);
5273 /* Get the MAX capabilities for this function.
5274 * This function also allocates context memory for TQM rings and
5275 * informs the firmware about this allocated backing store memory.
5277 rc = bnxt_hwrm_func_qcaps(bp);
5281 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5285 bnxt_hwrm_port_mac_qcfg(bp);
5287 bnxt_hwrm_parent_pf_qcfg(bp);
5289 bnxt_hwrm_port_phy_qcaps(bp);
5291 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5295 bnxt_alloc_error_recovery_info(bp);
5296 /* Get the adapter error recovery support info */
5297 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5299 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5301 bnxt_hwrm_port_led_qcaps(bp);
5307 bnxt_init_locks(struct bnxt *bp)
5311 err = pthread_mutex_init(&bp->flow_lock, NULL);
5313 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5317 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5319 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5323 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5327 rc = bnxt_init_fw(bp);
5331 if (!reconfig_dev) {
5332 rc = bnxt_setup_mac_addr(bp->eth_dev);
5336 rc = bnxt_restore_dflt_mac(bp);
5341 bnxt_config_vf_req_fwd(bp);
5343 rc = bnxt_hwrm_func_driver_register(bp);
5345 PMD_DRV_LOG(ERR, "Failed to register driver");
5350 if (bp->pdev->max_vfs) {
5351 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5353 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5357 rc = bnxt_hwrm_allocate_pf_only(bp);
5360 "Failed to allocate PF resources");
5366 rc = bnxt_alloc_mem(bp, reconfig_dev);
5370 rc = bnxt_setup_int(bp);
5374 rc = bnxt_request_int(bp);
5378 rc = bnxt_init_ctx_mem(bp);
5380 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5384 rc = bnxt_init_locks(bp);
5392 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5393 const char *value, void *opaque_arg)
5395 struct bnxt *bp = opaque_arg;
5396 unsigned long truflow;
5399 if (!value || !opaque_arg) {
5401 "Invalid parameter passed to truflow devargs.\n");
5405 truflow = strtoul(value, &end, 10);
5406 if (end == NULL || *end != '\0' ||
5407 (truflow == ULONG_MAX && errno == ERANGE)) {
5409 "Invalid parameter passed to truflow devargs.\n");
5413 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5415 "Invalid value passed to truflow devargs.\n");
5419 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5420 if (BNXT_TRUFLOW_EN(bp))
5421 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5427 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5428 const char *value, void *opaque_arg)
5430 struct bnxt *bp = opaque_arg;
5431 unsigned long flow_xstat;
5434 if (!value || !opaque_arg) {
5436 "Invalid parameter passed to flow_xstat devarg.\n");
5440 flow_xstat = strtoul(value, &end, 10);
5441 if (end == NULL || *end != '\0' ||
5442 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5444 "Invalid parameter passed to flow_xstat devarg.\n");
5448 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5450 "Invalid value passed to flow_xstat devarg.\n");
5454 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5455 if (BNXT_FLOW_XSTATS_EN(bp))
5456 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5462 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5463 const char *value, void *opaque_arg)
5465 struct bnxt *bp = opaque_arg;
5466 unsigned long max_num_kflows;
5469 if (!value || !opaque_arg) {
5471 "Invalid parameter passed to max_num_kflows devarg.\n");
5475 max_num_kflows = strtoul(value, &end, 10);
5476 if (end == NULL || *end != '\0' ||
5477 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5479 "Invalid parameter passed to max_num_kflows devarg.\n");
5483 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5485 "Invalid value passed to max_num_kflows devarg.\n");
5489 bp->max_num_kflows = max_num_kflows;
5490 if (bp->max_num_kflows)
5491 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5498 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5500 struct rte_kvargs *kvlist;
5502 if (devargs == NULL)
5505 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5510 * Handler for "truflow" devarg.
5511 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5513 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5514 bnxt_parse_devarg_truflow, bp);
5517 * Handler for "flow_xstat" devarg.
5518 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5520 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5521 bnxt_parse_devarg_flow_xstat, bp);
5524 * Handler for "max_num_kflows" devarg.
5525 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5527 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5528 bnxt_parse_devarg_max_num_kflows, bp);
5530 rte_kvargs_free(kvlist);
5533 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5537 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5538 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5541 "Failed to alloc switch domain: %d\n", rc);
5544 "Switch domain allocated %d\n",
5545 bp->switch_domain_id);
5552 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5554 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5555 static int version_printed;
5559 if (version_printed++ == 0)
5560 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5562 eth_dev->dev_ops = &bnxt_dev_ops;
5563 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5564 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5567 * For secondary processes, we don't initialise any further
5568 * as primary has already done this work.
5570 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5573 rte_eth_copy_pci_info(eth_dev, pci_dev);
5575 bp = eth_dev->data->dev_private;
5577 /* Parse dev arguments passed on when starting the DPDK application. */
5578 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5580 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5582 if (bnxt_vf_pciid(pci_dev->id.device_id))
5583 bp->flags |= BNXT_FLAG_VF;
5585 if (bnxt_thor_device(pci_dev->id.device_id))
5586 bp->flags |= BNXT_FLAG_THOR_CHIP;
5588 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5589 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5590 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5591 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5592 bp->flags |= BNXT_FLAG_STINGRAY;
5594 rc = bnxt_init_board(eth_dev);
5597 "Failed to initialize board rc: %x\n", rc);
5601 rc = bnxt_alloc_pf_info(bp);
5605 rc = bnxt_alloc_link_info(bp);
5609 rc = bnxt_alloc_parent_info(bp);
5613 rc = bnxt_alloc_hwrm_resources(bp);
5616 "Failed to allocate hwrm resource rc: %x\n", rc);
5619 rc = bnxt_alloc_leds_info(bp);
5623 rc = bnxt_alloc_cos_queues(bp);
5627 rc = bnxt_init_resources(bp, false);
5631 rc = bnxt_alloc_stats_mem(bp);
5635 bnxt_alloc_switch_domain(bp);
5637 /* Pass the information to the rte_eth_dev_close() that it should also
5638 * release the private port resources.
5640 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5643 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5644 pci_dev->mem_resource[0].phys_addr,
5645 pci_dev->mem_resource[0].addr);
5650 bnxt_dev_uninit(eth_dev);
5655 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5664 ctx->dma = RTE_BAD_IOVA;
5665 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5668 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5670 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5671 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5672 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5673 bp->flow_stat->max_fc,
5676 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5677 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5678 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5679 bp->flow_stat->max_fc,
5682 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5683 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5684 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5686 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5687 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5688 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5690 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5691 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5692 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5694 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5695 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5696 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5699 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5701 bnxt_unregister_fc_ctx_mem(bp);
5703 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5704 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5705 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5706 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5709 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5711 if (BNXT_FLOW_XSTATS_EN(bp))
5712 bnxt_uninit_fc_ctx_mem(bp);
5716 bnxt_free_error_recovery_info(struct bnxt *bp)
5718 rte_free(bp->recovery_info);
5719 bp->recovery_info = NULL;
5720 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5724 bnxt_uninit_locks(struct bnxt *bp)
5726 pthread_mutex_destroy(&bp->flow_lock);
5727 pthread_mutex_destroy(&bp->def_cp_lock);
5729 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5733 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5738 bnxt_free_mem(bp, reconfig_dev);
5739 bnxt_hwrm_func_buf_unrgtr(bp);
5740 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5741 bp->flags &= ~BNXT_FLAG_REGISTERED;
5742 bnxt_free_ctx_mem(bp);
5743 if (!reconfig_dev) {
5744 bnxt_free_hwrm_resources(bp);
5745 bnxt_free_error_recovery_info(bp);
5748 bnxt_uninit_ctx_mem(bp);
5750 bnxt_uninit_locks(bp);
5751 bnxt_free_flow_stats_info(bp);
5752 bnxt_free_rep_info(bp);
5753 rte_free(bp->ptp_cfg);
5759 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5761 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5764 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5766 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5767 bnxt_dev_close_op(eth_dev);
5772 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5774 struct bnxt *bp = eth_dev->data->dev_private;
5775 struct rte_eth_dev *vf_rep_eth_dev;
5781 for (i = 0; i < bp->num_reps; i++) {
5782 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5783 if (!vf_rep_eth_dev)
5785 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5787 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5792 static void bnxt_free_rep_info(struct bnxt *bp)
5794 rte_free(bp->rep_info);
5795 bp->rep_info = NULL;
5796 rte_free(bp->cfa_code_map);
5797 bp->cfa_code_map = NULL;
5800 static int bnxt_init_rep_info(struct bnxt *bp)
5807 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5808 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5810 if (!bp->rep_info) {
5811 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5814 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5815 sizeof(*bp->cfa_code_map) *
5816 BNXT_MAX_CFA_CODE, 0);
5817 if (!bp->cfa_code_map) {
5818 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5819 bnxt_free_rep_info(bp);
5823 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5824 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5826 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5828 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5829 bnxt_free_rep_info(bp);
5835 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5836 struct rte_eth_devargs eth_da,
5837 struct rte_eth_dev *backing_eth_dev)
5839 struct rte_eth_dev *vf_rep_eth_dev;
5840 char name[RTE_ETH_NAME_MAX_LEN];
5841 struct bnxt *backing_bp;
5845 num_rep = eth_da.nb_representor_ports;
5846 if (num_rep > BNXT_MAX_VF_REPS) {
5847 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5848 num_rep, BNXT_MAX_VF_REPS);
5852 if (num_rep > RTE_MAX_ETHPORTS) {
5854 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5855 num_rep, RTE_MAX_ETHPORTS);
5859 backing_bp = backing_eth_dev->data->dev_private;
5861 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5863 "Not a PF or trusted VF. No Representor support\n");
5864 /* Returning an error is not an option.
5865 * Applications are not handling this correctly
5870 if (bnxt_init_rep_info(backing_bp))
5873 for (i = 0; i < num_rep; i++) {
5874 struct bnxt_vf_representor representor = {
5875 .vf_id = eth_da.representor_ports[i],
5876 .switch_domain_id = backing_bp->switch_domain_id,
5877 .parent_dev = backing_eth_dev
5880 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5881 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5882 representor.vf_id, BNXT_MAX_VF_REPS);
5886 /* representor port net_bdf_port */
5887 snprintf(name, sizeof(name), "net_%s_representor_%d",
5888 pci_dev->device.name, eth_da.representor_ports[i]);
5890 ret = rte_eth_dev_create(&pci_dev->device, name,
5891 sizeof(struct bnxt_vf_representor),
5893 bnxt_vf_representor_init,
5897 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5898 if (!vf_rep_eth_dev) {
5899 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5900 " for VF-Rep: %s.", name);
5901 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5905 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5907 backing_bp->num_reps++;
5909 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5910 "representor %s.", name);
5911 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5918 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5919 struct rte_pci_device *pci_dev)
5921 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5922 struct rte_eth_dev *backing_eth_dev;
5926 if (pci_dev->device.devargs) {
5927 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5933 num_rep = eth_da.nb_representor_ports;
5934 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5937 /* We could come here after first level of probe is already invoked
5938 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5939 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5941 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5942 if (backing_eth_dev == NULL) {
5943 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5944 sizeof(struct bnxt),
5945 eth_dev_pci_specific_init, pci_dev,
5946 bnxt_dev_init, NULL);
5948 if (ret || !num_rep)
5951 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5954 /* probe representor ports now */
5955 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
5960 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5962 struct rte_eth_dev *eth_dev;
5964 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5966 return 0; /* Invoked typically only by OVS-DPDK, by the
5967 * time it comes here the eth_dev is already
5968 * deleted by rte_eth_dev_close(), so returning
5969 * +ve value will at least help in proper cleanup
5972 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5973 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5974 return rte_eth_dev_destroy(eth_dev,
5975 bnxt_vf_representor_uninit);
5977 return rte_eth_dev_destroy(eth_dev,
5980 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5984 static struct rte_pci_driver bnxt_rte_pmd = {
5985 .id_table = bnxt_pci_id_map,
5986 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5987 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5990 .probe = bnxt_pci_probe,
5991 .remove = bnxt_pci_remove,
5995 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5997 if (strcmp(dev->device->driver->name, drv->driver.name))
6003 bool is_bnxt_supported(struct rte_eth_dev *dev)
6005 return is_device_supported(dev, &bnxt_rte_pmd);
6008 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6009 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6010 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6011 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");