1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
41 #define BROADCOM_DEV_ID_57301 0x16c8
42 #define BROADCOM_DEV_ID_57302 0x16c9
43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
46 #define BROADCOM_DEV_ID_NS2 0x16cd
47 #define BROADCOM_DEV_ID_57311 0x16ce
48 #define BROADCOM_DEV_ID_57312 0x16cf
49 #define BROADCOM_DEV_ID_57402 0x16d0
50 #define BROADCOM_DEV_ID_57404 0x16d1
51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
55 #define BROADCOM_DEV_ID_57412 0x16d6
56 #define BROADCOM_DEV_ID_57414 0x16d7
57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
60 #define BROADCOM_DEV_ID_57412_MF 0x16de
61 #define BROADCOM_DEV_ID_57314 0x16df
62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 #define BROADCOM_DEV_ID_58802 0xd802
74 #define BROADCOM_DEV_ID_58804 0xd804
75 #define BROADCOM_DEV_ID_58808 0x16f0
77 static const struct rte_pci_id bnxt_pci_id_map[] = {
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
79 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
119 { .vendor_id = 0, /* sentinel */ },
122 #define BNXT_ETH_RSS_SUPPORT ( \
124 ETH_RSS_NONFRAG_IPV4_TCP | \
125 ETH_RSS_NONFRAG_IPV4_UDP | \
127 ETH_RSS_NONFRAG_IPV6_TCP | \
128 ETH_RSS_NONFRAG_IPV6_UDP)
130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
131 DEV_TX_OFFLOAD_IPV4_CKSUM | \
132 DEV_TX_OFFLOAD_TCP_CKSUM | \
133 DEV_TX_OFFLOAD_UDP_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_TSO | \
135 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
136 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
137 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
138 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
139 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
140 DEV_TX_OFFLOAD_MULTI_SEGS)
142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
143 DEV_RX_OFFLOAD_VLAN_STRIP | \
144 DEV_RX_OFFLOAD_IPV4_CKSUM | \
145 DEV_RX_OFFLOAD_UDP_CKSUM | \
146 DEV_RX_OFFLOAD_TCP_CKSUM | \
147 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_JUMBO_FRAME | \
149 DEV_RX_OFFLOAD_CRC_STRIP | \
150 DEV_RX_OFFLOAD_TCP_LRO)
152 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
153 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
154 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
156 /***********************/
159 * High level utility functions
162 static void bnxt_free_mem(struct bnxt *bp)
164 bnxt_free_filter_mem(bp);
165 bnxt_free_vnic_attributes(bp);
166 bnxt_free_vnic_mem(bp);
169 bnxt_free_tx_rings(bp);
170 bnxt_free_rx_rings(bp);
173 static int bnxt_alloc_mem(struct bnxt *bp)
177 rc = bnxt_alloc_vnic_mem(bp);
181 rc = bnxt_alloc_vnic_attributes(bp);
185 rc = bnxt_alloc_filter_mem(bp);
196 static int bnxt_init_chip(struct bnxt *bp)
199 struct rte_eth_link new;
200 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
201 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
202 uint32_t intr_vector = 0;
203 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
204 uint32_t vec = BNXT_MISC_VEC_ID;
207 /* disable uio/vfio intr/eventfd mapping */
208 rte_intr_disable(intr_handle);
210 if (bp->eth_dev->data->mtu > ETHER_MTU) {
211 bp->eth_dev->data->dev_conf.rxmode.offloads |=
212 DEV_RX_OFFLOAD_JUMBO_FRAME;
213 bp->flags |= BNXT_FLAG_JUMBO;
215 bp->eth_dev->data->dev_conf.rxmode.offloads &=
216 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
217 bp->flags &= ~BNXT_FLAG_JUMBO;
220 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
222 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
226 rc = bnxt_alloc_hwrm_rings(bp);
228 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
232 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
234 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
238 rc = bnxt_mq_rx_configure(bp);
240 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
244 /* VNIC configuration */
245 for (i = 0; i < bp->nr_vnics; i++) {
246 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
248 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
250 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
255 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
258 "HWRM vnic %d ctx alloc failure rc: %x\n",
263 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
265 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
270 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
273 "HWRM vnic %d filter failure rc: %x\n",
278 rc = bnxt_vnic_rss_configure(bp, vnic);
281 "HWRM vnic set RSS failure rc: %x\n", rc);
285 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
287 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
288 DEV_RX_OFFLOAD_TCP_LRO)
289 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
291 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
293 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
296 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
300 /* check and configure queue intr-vector mapping */
301 if ((rte_intr_cap_multiple(intr_handle) ||
302 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
303 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
304 intr_vector = bp->eth_dev->data->nb_rx_queues;
305 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
306 if (intr_vector > bp->rx_cp_nr_rings) {
307 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
311 if (rte_intr_efd_enable(intr_handle, intr_vector))
315 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
316 intr_handle->intr_vec =
317 rte_zmalloc("intr_vec",
318 bp->eth_dev->data->nb_rx_queues *
320 if (intr_handle->intr_vec == NULL) {
321 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
322 " intr_vec", bp->eth_dev->data->nb_rx_queues);
325 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
326 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
327 intr_handle->intr_vec, intr_handle->nb_efd,
328 intr_handle->max_intr);
331 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
333 intr_handle->intr_vec[queue_id] = vec;
334 if (vec < base + intr_handle->nb_efd - 1)
338 /* enable uio/vfio intr/eventfd mapping */
339 rte_intr_enable(intr_handle);
341 rc = bnxt_get_hwrm_link_config(bp, &new);
343 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
347 if (!bp->link_info.link_up) {
348 rc = bnxt_set_hwrm_link_config(bp, true);
351 "HWRM link config failure rc: %x\n", rc);
355 bnxt_print_link_info(bp->eth_dev);
360 bnxt_free_all_hwrm_resources(bp);
362 /* Some of the error status returned by FW may not be from errno.h */
369 static int bnxt_shutdown_nic(struct bnxt *bp)
371 bnxt_free_all_hwrm_resources(bp);
372 bnxt_free_all_filters(bp);
373 bnxt_free_all_vnics(bp);
377 static int bnxt_init_nic(struct bnxt *bp)
381 rc = bnxt_init_ring_grps(bp);
386 bnxt_init_filters(bp);
392 * Device configuration and status function
395 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
396 struct rte_eth_dev_info *dev_info)
398 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
399 uint16_t max_vnics, i, j, vpool, vrxq;
400 unsigned int max_rx_rings;
403 dev_info->max_mac_addrs = bp->max_l2_ctx;
404 dev_info->max_hash_mac_addrs = 0;
406 /* PF/VF specifics */
408 dev_info->max_vfs = bp->pdev->max_vfs;
409 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
410 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
411 dev_info->max_rx_queues = max_rx_rings;
412 dev_info->max_tx_queues = max_rx_rings;
413 dev_info->reta_size = bp->max_rsscos_ctx;
414 dev_info->hash_key_size = 40;
415 max_vnics = bp->max_vnics;
417 /* Fast path specifics */
418 dev_info->min_rx_bufsize = 1;
419 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
422 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
423 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
424 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
425 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
426 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
429 dev_info->default_rxconf = (struct rte_eth_rxconf) {
435 .rx_free_thresh = 32,
436 /* If no descriptors available, pkts are dropped by default */
440 dev_info->default_txconf = (struct rte_eth_txconf) {
446 .tx_free_thresh = 32,
449 eth_dev->data->dev_conf.intr_conf.lsc = 1;
451 eth_dev->data->dev_conf.intr_conf.rxq = 1;
456 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
457 * need further investigation.
461 vpool = 64; /* ETH_64_POOLS */
462 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
463 for (i = 0; i < 4; vpool >>= 1, i++) {
464 if (max_vnics > vpool) {
465 for (j = 0; j < 5; vrxq >>= 1, j++) {
466 if (dev_info->max_rx_queues > vrxq) {
472 /* Not enough resources to support VMDq */
476 /* Not enough resources to support VMDq */
480 dev_info->max_vmdq_pools = vpool;
481 dev_info->vmdq_queue_num = vrxq;
483 dev_info->vmdq_pool_base = 0;
484 dev_info->vmdq_queue_base = 0;
487 /* Configure the device based on the configuration provided */
488 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
490 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
491 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
493 bp->rx_queues = (void *)eth_dev->data->rx_queues;
494 bp->tx_queues = (void *)eth_dev->data->tx_queues;
495 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
496 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
498 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
501 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
503 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
507 /* legacy driver needs to get updated values */
508 rc = bnxt_hwrm_func_qcaps(bp);
510 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
515 /* Inherit new configurations */
516 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
517 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
518 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
520 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
522 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
524 "Insufficient resources to support requested config\n");
526 "Num Queues Requested: Tx %d, Rx %d\n",
527 eth_dev->data->nb_tx_queues,
528 eth_dev->data->nb_rx_queues);
530 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
531 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
532 bp->max_stat_ctx, bp->max_ring_grps);
536 bp->rx_cp_nr_rings = bp->rx_nr_rings;
537 bp->tx_cp_nr_rings = bp->tx_nr_rings;
539 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
541 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
542 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
544 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
549 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
551 struct rte_eth_link *link = ð_dev->data->dev_link;
553 if (link->link_status)
554 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
555 eth_dev->data->port_id,
556 (uint32_t)link->link_speed,
557 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
558 ("full-duplex") : ("half-duplex\n"));
560 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
561 eth_dev->data->port_id);
564 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
566 bnxt_print_link_info(eth_dev);
570 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
572 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
573 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
577 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
579 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
580 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
584 rc = bnxt_init_chip(bp);
588 bnxt_link_update_op(eth_dev, 1);
590 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
591 vlan_mask |= ETH_VLAN_FILTER_MASK;
592 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
593 vlan_mask |= ETH_VLAN_STRIP_MASK;
594 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
598 bp->flags |= BNXT_FLAG_INIT_DONE;
602 bnxt_shutdown_nic(bp);
603 bnxt_free_tx_mbufs(bp);
604 bnxt_free_rx_mbufs(bp);
608 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
610 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
613 if (!bp->link_info.link_up)
614 rc = bnxt_set_hwrm_link_config(bp, true);
616 eth_dev->data->dev_link.link_status = 1;
618 bnxt_print_link_info(eth_dev);
622 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
624 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
626 eth_dev->data->dev_link.link_status = 0;
627 bnxt_set_hwrm_link_config(bp, false);
628 bp->link_info.link_up = 0;
633 /* Unload the driver, release resources */
634 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
636 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
638 bp->flags &= ~BNXT_FLAG_INIT_DONE;
639 if (bp->eth_dev->data->dev_started) {
640 /* TBD: STOP HW queues DMA */
641 eth_dev->data->dev_link.link_status = 0;
643 bnxt_set_hwrm_link_config(bp, false);
644 bnxt_hwrm_port_clr_stats(bp);
645 bnxt_free_tx_mbufs(bp);
646 bnxt_free_rx_mbufs(bp);
647 bnxt_shutdown_nic(bp);
651 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
653 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
655 if (bp->dev_stopped == 0)
656 bnxt_dev_stop_op(eth_dev);
659 if (eth_dev->data->mac_addrs != NULL) {
660 rte_free(eth_dev->data->mac_addrs);
661 eth_dev->data->mac_addrs = NULL;
663 if (bp->grp_info != NULL) {
664 rte_free(bp->grp_info);
669 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
672 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
673 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
674 struct bnxt_vnic_info *vnic;
675 struct bnxt_filter_info *filter, *temp_filter;
676 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
680 * Loop through all VNICs from the specified filter flow pools to
681 * remove the corresponding MAC addr filter
683 for (i = 0; i < pool; i++) {
684 if (!(pool_mask & (1ULL << i)))
687 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
688 filter = STAILQ_FIRST(&vnic->filter);
690 temp_filter = STAILQ_NEXT(filter, next);
691 if (filter->mac_index == index) {
692 STAILQ_REMOVE(&vnic->filter, filter,
693 bnxt_filter_info, next);
694 bnxt_hwrm_clear_l2_filter(bp, filter);
695 filter->mac_index = INVALID_MAC_INDEX;
696 memset(&filter->l2_addr, 0,
699 &bp->free_filter_list,
702 filter = temp_filter;
708 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
709 struct ether_addr *mac_addr,
710 uint32_t index, uint32_t pool)
712 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
713 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
714 struct bnxt_filter_info *filter;
717 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
722 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
725 /* Attach requested MAC address to the new l2_filter */
726 STAILQ_FOREACH(filter, &vnic->filter, next) {
727 if (filter->mac_index == index) {
729 "MAC addr already existed for pool %d\n", pool);
733 filter = bnxt_alloc_filter(bp);
735 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
738 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
739 filter->mac_index = index;
740 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
741 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
744 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
747 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
748 struct rte_eth_link new;
749 unsigned int cnt = BNXT_LINK_WAIT_CNT;
751 memset(&new, 0, sizeof(new));
753 /* Retrieve link info from hardware */
754 rc = bnxt_get_hwrm_link_config(bp, &new);
756 new.link_speed = ETH_LINK_SPEED_100M;
757 new.link_duplex = ETH_LINK_FULL_DUPLEX;
759 "Failed to retrieve link rc = 0x%x!\n", rc);
762 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
764 if (!wait_to_complete)
766 } while (!new.link_status && cnt--);
769 /* Timed out or success */
770 if (new.link_status != eth_dev->data->dev_link.link_status ||
771 new.link_speed != eth_dev->data->dev_link.link_speed) {
772 memcpy(ð_dev->data->dev_link, &new,
773 sizeof(struct rte_eth_link));
775 _rte_eth_dev_callback_process(eth_dev,
776 RTE_ETH_EVENT_INTR_LSC,
779 bnxt_print_link_info(eth_dev);
785 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
787 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
788 struct bnxt_vnic_info *vnic;
790 if (bp->vnic_info == NULL)
793 vnic = &bp->vnic_info[0];
795 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
796 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
799 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
801 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
802 struct bnxt_vnic_info *vnic;
804 if (bp->vnic_info == NULL)
807 vnic = &bp->vnic_info[0];
809 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
810 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
813 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
815 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
816 struct bnxt_vnic_info *vnic;
818 if (bp->vnic_info == NULL)
821 vnic = &bp->vnic_info[0];
823 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
824 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
827 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
829 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
830 struct bnxt_vnic_info *vnic;
832 if (bp->vnic_info == NULL)
835 vnic = &bp->vnic_info[0];
837 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
838 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
841 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
842 struct rte_eth_rss_reta_entry64 *reta_conf,
845 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
846 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
847 struct bnxt_vnic_info *vnic;
850 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
853 if (reta_size != HW_HASH_INDEX_SIZE) {
854 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
855 "(%d) must equal the size supported by the hardware "
856 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
859 /* Update the RSS VNIC(s) */
860 for (i = 0; i < MAX_FF_POOLS; i++) {
861 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
862 memcpy(vnic->rss_table, reta_conf, reta_size);
864 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
870 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
871 struct rte_eth_rss_reta_entry64 *reta_conf,
874 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
875 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
876 struct rte_intr_handle *intr_handle
877 = &bp->pdev->intr_handle;
879 /* Retrieve from the default VNIC */
882 if (!vnic->rss_table)
885 if (reta_size != HW_HASH_INDEX_SIZE) {
886 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
887 "(%d) must equal the size supported by the hardware "
888 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
891 /* EW - need to revisit here copying from uint64_t to uint16_t */
892 memcpy(reta_conf, vnic->rss_table, reta_size);
894 if (rte_intr_allow_others(intr_handle)) {
895 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
896 bnxt_dev_lsc_intr_setup(eth_dev);
902 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
903 struct rte_eth_rss_conf *rss_conf)
905 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
906 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
907 struct bnxt_vnic_info *vnic;
908 uint16_t hash_type = 0;
912 * If RSS enablement were different than dev_configure,
913 * then return -EINVAL
915 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
916 if (!rss_conf->rss_hf)
917 PMD_DRV_LOG(ERR, "Hash type NONE\n");
919 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
923 bp->flags |= BNXT_FLAG_UPDATE_HASH;
924 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
926 if (rss_conf->rss_hf & ETH_RSS_IPV4)
927 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
928 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
929 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
930 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
931 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
932 if (rss_conf->rss_hf & ETH_RSS_IPV6)
933 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
934 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
935 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
936 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
937 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
939 /* Update the RSS VNIC(s) */
940 for (i = 0; i < MAX_FF_POOLS; i++) {
941 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
942 vnic->hash_type = hash_type;
945 * Use the supplied key if the key length is
946 * acceptable and the rss_key is not NULL
948 if (rss_conf->rss_key &&
949 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
950 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
951 rss_conf->rss_key_len);
953 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
959 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
960 struct rte_eth_rss_conf *rss_conf)
962 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
963 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
967 /* RSS configuration is the same for all VNICs */
968 if (vnic && vnic->rss_hash_key) {
969 if (rss_conf->rss_key) {
970 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
971 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
972 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
975 hash_types = vnic->hash_type;
976 rss_conf->rss_hf = 0;
977 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
978 rss_conf->rss_hf |= ETH_RSS_IPV4;
979 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
981 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
982 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
984 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
986 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
987 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
989 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
991 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
992 rss_conf->rss_hf |= ETH_RSS_IPV6;
993 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
995 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
996 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
998 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1000 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1001 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1003 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1007 "Unknwon RSS config from firmware (%08x), RSS disabled",
1012 rss_conf->rss_hf = 0;
1017 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1018 struct rte_eth_fc_conf *fc_conf)
1020 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1021 struct rte_eth_link link_info;
1024 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1028 memset(fc_conf, 0, sizeof(*fc_conf));
1029 if (bp->link_info.auto_pause)
1030 fc_conf->autoneg = 1;
1031 switch (bp->link_info.pause) {
1033 fc_conf->mode = RTE_FC_NONE;
1035 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1036 fc_conf->mode = RTE_FC_TX_PAUSE;
1038 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1039 fc_conf->mode = RTE_FC_RX_PAUSE;
1041 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1042 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1043 fc_conf->mode = RTE_FC_FULL;
1049 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1050 struct rte_eth_fc_conf *fc_conf)
1052 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1054 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1055 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1059 switch (fc_conf->mode) {
1061 bp->link_info.auto_pause = 0;
1062 bp->link_info.force_pause = 0;
1064 case RTE_FC_RX_PAUSE:
1065 if (fc_conf->autoneg) {
1066 bp->link_info.auto_pause =
1067 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1068 bp->link_info.force_pause = 0;
1070 bp->link_info.auto_pause = 0;
1071 bp->link_info.force_pause =
1072 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1075 case RTE_FC_TX_PAUSE:
1076 if (fc_conf->autoneg) {
1077 bp->link_info.auto_pause =
1078 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1079 bp->link_info.force_pause = 0;
1081 bp->link_info.auto_pause = 0;
1082 bp->link_info.force_pause =
1083 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1087 if (fc_conf->autoneg) {
1088 bp->link_info.auto_pause =
1089 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1090 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1091 bp->link_info.force_pause = 0;
1093 bp->link_info.auto_pause = 0;
1094 bp->link_info.force_pause =
1095 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1096 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1100 return bnxt_set_hwrm_link_config(bp, true);
1103 /* Add UDP tunneling port */
1105 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1106 struct rte_eth_udp_tunnel *udp_tunnel)
1108 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1109 uint16_t tunnel_type = 0;
1112 switch (udp_tunnel->prot_type) {
1113 case RTE_TUNNEL_TYPE_VXLAN:
1114 if (bp->vxlan_port_cnt) {
1115 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1116 udp_tunnel->udp_port);
1117 if (bp->vxlan_port != udp_tunnel->udp_port) {
1118 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1121 bp->vxlan_port_cnt++;
1125 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1126 bp->vxlan_port_cnt++;
1128 case RTE_TUNNEL_TYPE_GENEVE:
1129 if (bp->geneve_port_cnt) {
1130 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1131 udp_tunnel->udp_port);
1132 if (bp->geneve_port != udp_tunnel->udp_port) {
1133 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1136 bp->geneve_port_cnt++;
1140 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1141 bp->geneve_port_cnt++;
1144 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1147 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1153 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1154 struct rte_eth_udp_tunnel *udp_tunnel)
1156 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1157 uint16_t tunnel_type = 0;
1161 switch (udp_tunnel->prot_type) {
1162 case RTE_TUNNEL_TYPE_VXLAN:
1163 if (!bp->vxlan_port_cnt) {
1164 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1167 if (bp->vxlan_port != udp_tunnel->udp_port) {
1168 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1169 udp_tunnel->udp_port, bp->vxlan_port);
1172 if (--bp->vxlan_port_cnt)
1176 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1177 port = bp->vxlan_fw_dst_port_id;
1179 case RTE_TUNNEL_TYPE_GENEVE:
1180 if (!bp->geneve_port_cnt) {
1181 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1184 if (bp->geneve_port != udp_tunnel->udp_port) {
1185 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1186 udp_tunnel->udp_port, bp->geneve_port);
1189 if (--bp->geneve_port_cnt)
1193 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1194 port = bp->geneve_fw_dst_port_id;
1197 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1201 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1204 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1207 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1208 bp->geneve_port = 0;
1213 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1215 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1216 struct bnxt_vnic_info *vnic;
1219 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1221 /* Cycle through all VNICs */
1222 for (i = 0; i < bp->nr_vnics; i++) {
1224 * For each VNIC and each associated filter(s)
1225 * if VLAN exists && VLAN matches vlan_id
1226 * remove the MAC+VLAN filter
1227 * add a new MAC only filter
1229 * VLAN filter doesn't exist, just skip and continue
1231 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1232 filter = STAILQ_FIRST(&vnic->filter);
1234 temp_filter = STAILQ_NEXT(filter, next);
1236 if (filter->enables & chk &&
1237 filter->l2_ovlan == vlan_id) {
1238 /* Must delete the filter */
1239 STAILQ_REMOVE(&vnic->filter, filter,
1240 bnxt_filter_info, next);
1241 bnxt_hwrm_clear_l2_filter(bp, filter);
1243 &bp->free_filter_list,
1247 * Need to examine to see if the MAC
1248 * filter already existed or not before
1249 * allocating a new one
1252 new_filter = bnxt_alloc_filter(bp);
1255 "MAC/VLAN filter alloc failed\n");
1259 STAILQ_INSERT_TAIL(&vnic->filter,
1261 /* Inherit MAC from previous filter */
1262 new_filter->mac_index =
1264 memcpy(new_filter->l2_addr,
1265 filter->l2_addr, ETHER_ADDR_LEN);
1266 /* MAC only filter */
1267 rc = bnxt_hwrm_set_l2_filter(bp,
1273 "Del Vlan filter for %d\n",
1276 filter = temp_filter;
1284 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1286 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1287 struct bnxt_vnic_info *vnic;
1290 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1291 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1292 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1294 /* Cycle through all VNICs */
1295 for (i = 0; i < bp->nr_vnics; i++) {
1297 * For each VNIC and each associated filter(s)
1299 * if VLAN matches vlan_id
1300 * VLAN filter already exists, just skip and continue
1302 * add a new MAC+VLAN filter
1304 * Remove the old MAC only filter
1305 * Add a new MAC+VLAN filter
1307 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1308 filter = STAILQ_FIRST(&vnic->filter);
1310 temp_filter = STAILQ_NEXT(filter, next);
1312 if (filter->enables & chk) {
1313 if (filter->l2_ovlan == vlan_id)
1316 /* Must delete the MAC filter */
1317 STAILQ_REMOVE(&vnic->filter, filter,
1318 bnxt_filter_info, next);
1319 bnxt_hwrm_clear_l2_filter(bp, filter);
1320 filter->l2_ovlan = 0;
1322 &bp->free_filter_list,
1325 new_filter = bnxt_alloc_filter(bp);
1328 "MAC/VLAN filter alloc failed\n");
1332 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1334 /* Inherit MAC from the previous filter */
1335 new_filter->mac_index = filter->mac_index;
1336 memcpy(new_filter->l2_addr, filter->l2_addr,
1338 /* MAC + VLAN ID filter */
1339 new_filter->l2_ovlan = vlan_id;
1340 new_filter->l2_ovlan_mask = 0xF000;
1341 new_filter->enables |= en;
1342 rc = bnxt_hwrm_set_l2_filter(bp,
1348 "Added Vlan filter for %d\n", vlan_id);
1350 filter = temp_filter;
1358 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1359 uint16_t vlan_id, int on)
1361 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1363 /* These operations apply to ALL existing MAC/VLAN filters */
1365 return bnxt_add_vlan_filter(bp, vlan_id);
1367 return bnxt_del_vlan_filter(bp, vlan_id);
1371 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1373 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1374 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1377 if (mask & ETH_VLAN_FILTER_MASK) {
1378 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1379 /* Remove any VLAN filters programmed */
1380 for (i = 0; i < 4095; i++)
1381 bnxt_del_vlan_filter(bp, i);
1383 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1384 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1387 if (mask & ETH_VLAN_STRIP_MASK) {
1388 /* Enable or disable VLAN stripping */
1389 for (i = 0; i < bp->nr_vnics; i++) {
1390 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1391 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1392 vnic->vlan_strip = true;
1394 vnic->vlan_strip = false;
1395 bnxt_hwrm_vnic_cfg(bp, vnic);
1397 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1398 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1401 if (mask & ETH_VLAN_EXTEND_MASK)
1402 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1408 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1410 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1411 /* Default Filter is tied to VNIC 0 */
1412 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1413 struct bnxt_filter_info *filter;
1419 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1421 STAILQ_FOREACH(filter, &vnic->filter, next) {
1422 /* Default Filter is at Index 0 */
1423 if (filter->mac_index != 0)
1425 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1428 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1429 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1430 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1433 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1434 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1437 filter->mac_index = 0;
1438 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1445 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1446 struct ether_addr *mc_addr_set,
1447 uint32_t nb_mc_addr)
1449 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1450 char *mc_addr_list = (char *)mc_addr_set;
1451 struct bnxt_vnic_info *vnic;
1452 uint32_t off = 0, i = 0;
1454 vnic = &bp->vnic_info[0];
1456 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1457 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1461 /* TODO Check for Duplicate mcast addresses */
1462 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1463 for (i = 0; i < nb_mc_addr; i++) {
1464 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1465 off += ETHER_ADDR_LEN;
1468 vnic->mc_addr_cnt = i;
1471 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1475 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1477 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1478 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1479 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1480 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1483 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1484 fw_major, fw_minor, fw_updt);
1486 ret += 1; /* add the size of '\0' */
1487 if (fw_size < (uint32_t)ret)
1494 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1495 struct rte_eth_rxq_info *qinfo)
1497 struct bnxt_rx_queue *rxq;
1499 rxq = dev->data->rx_queues[queue_id];
1501 qinfo->mp = rxq->mb_pool;
1502 qinfo->scattered_rx = dev->data->scattered_rx;
1503 qinfo->nb_desc = rxq->nb_rx_desc;
1505 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1506 qinfo->conf.rx_drop_en = 0;
1507 qinfo->conf.rx_deferred_start = 0;
1511 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1512 struct rte_eth_txq_info *qinfo)
1514 struct bnxt_tx_queue *txq;
1516 txq = dev->data->tx_queues[queue_id];
1518 qinfo->nb_desc = txq->nb_tx_desc;
1520 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1521 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1522 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1524 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1525 qinfo->conf.tx_rs_thresh = 0;
1526 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1529 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1531 struct bnxt *bp = eth_dev->data->dev_private;
1532 struct rte_eth_dev_info dev_info;
1533 uint32_t max_dev_mtu;
1537 bnxt_dev_info_get_op(eth_dev, &dev_info);
1538 max_dev_mtu = dev_info.max_rx_pktlen -
1539 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1541 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1542 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1543 ETHER_MIN_MTU, max_dev_mtu);
1548 if (new_mtu > ETHER_MTU) {
1549 bp->flags |= BNXT_FLAG_JUMBO;
1550 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1551 DEV_RX_OFFLOAD_JUMBO_FRAME;
1553 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1554 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1555 bp->flags &= ~BNXT_FLAG_JUMBO;
1558 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1559 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1561 eth_dev->data->mtu = new_mtu;
1562 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1564 for (i = 0; i < bp->nr_vnics; i++) {
1565 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1567 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1568 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1569 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1573 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1582 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1584 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1585 uint16_t vlan = bp->vlan;
1588 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1590 "PVID cannot be modified for this function\n");
1593 bp->vlan = on ? pvid : 0;
1595 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1602 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1604 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1606 return bnxt_hwrm_port_led_cfg(bp, true);
1610 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1612 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1614 return bnxt_hwrm_port_led_cfg(bp, false);
1618 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1620 uint32_t desc = 0, raw_cons = 0, cons;
1621 struct bnxt_cp_ring_info *cpr;
1622 struct bnxt_rx_queue *rxq;
1623 struct rx_pkt_cmpl *rxcmp;
1628 rxq = dev->data->rx_queues[rx_queue_id];
1632 while (raw_cons < rxq->nb_rx_desc) {
1633 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1634 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1636 if (!CMPL_VALID(rxcmp, valid))
1638 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1639 cmp_type = CMP_TYPE(rxcmp);
1640 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1641 cmp = (rte_le_to_cpu_32(
1642 ((struct rx_tpa_end_cmpl *)
1643 (rxcmp))->agg_bufs_v1) &
1644 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1645 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1647 } else if (cmp_type == 0x11) {
1649 cmp = (rxcmp->agg_bufs_v1 &
1650 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1651 RX_PKT_CMPL_AGG_BUFS_SFT;
1656 raw_cons += cmp ? cmp : 2;
1663 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1665 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1666 struct bnxt_rx_ring_info *rxr;
1667 struct bnxt_cp_ring_info *cpr;
1668 struct bnxt_sw_rx_bd *rx_buf;
1669 struct rx_pkt_cmpl *rxcmp;
1670 uint32_t cons, cp_cons;
1678 if (offset >= rxq->nb_rx_desc)
1681 cons = RING_CMP(cpr->cp_ring_struct, offset);
1682 cp_cons = cpr->cp_raw_cons;
1683 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1685 if (cons > cp_cons) {
1686 if (CMPL_VALID(rxcmp, cpr->valid))
1687 return RTE_ETH_RX_DESC_DONE;
1689 if (CMPL_VALID(rxcmp, !cpr->valid))
1690 return RTE_ETH_RX_DESC_DONE;
1692 rx_buf = &rxr->rx_buf_ring[cons];
1693 if (rx_buf->mbuf == NULL)
1694 return RTE_ETH_RX_DESC_UNAVAIL;
1697 return RTE_ETH_RX_DESC_AVAIL;
1701 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1703 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1704 struct bnxt_tx_ring_info *txr;
1705 struct bnxt_cp_ring_info *cpr;
1706 struct bnxt_sw_tx_bd *tx_buf;
1707 struct tx_pkt_cmpl *txcmp;
1708 uint32_t cons, cp_cons;
1716 if (offset >= txq->nb_tx_desc)
1719 cons = RING_CMP(cpr->cp_ring_struct, offset);
1720 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1721 cp_cons = cpr->cp_raw_cons;
1723 if (cons > cp_cons) {
1724 if (CMPL_VALID(txcmp, cpr->valid))
1725 return RTE_ETH_TX_DESC_UNAVAIL;
1727 if (CMPL_VALID(txcmp, !cpr->valid))
1728 return RTE_ETH_TX_DESC_UNAVAIL;
1730 tx_buf = &txr->tx_buf_ring[cons];
1731 if (tx_buf->mbuf == NULL)
1732 return RTE_ETH_TX_DESC_DONE;
1734 return RTE_ETH_TX_DESC_FULL;
1737 static struct bnxt_filter_info *
1738 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1739 struct rte_eth_ethertype_filter *efilter,
1740 struct bnxt_vnic_info *vnic0,
1741 struct bnxt_vnic_info *vnic,
1744 struct bnxt_filter_info *mfilter = NULL;
1748 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1749 efilter->ether_type == ETHER_TYPE_IPv6) {
1750 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1751 " ethertype filter.", efilter->ether_type);
1755 if (efilter->queue >= bp->rx_nr_rings) {
1756 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1761 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1762 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1764 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1769 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1770 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1771 if ((!memcmp(efilter->mac_addr.addr_bytes,
1772 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1774 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1775 mfilter->ethertype == efilter->ether_type)) {
1781 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1782 if ((!memcmp(efilter->mac_addr.addr_bytes,
1783 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1784 mfilter->ethertype == efilter->ether_type &&
1786 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1800 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1801 enum rte_filter_op filter_op,
1804 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1805 struct rte_eth_ethertype_filter *efilter =
1806 (struct rte_eth_ethertype_filter *)arg;
1807 struct bnxt_filter_info *bfilter, *filter1;
1808 struct bnxt_vnic_info *vnic, *vnic0;
1811 if (filter_op == RTE_ETH_FILTER_NOP)
1815 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1820 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1821 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1823 switch (filter_op) {
1824 case RTE_ETH_FILTER_ADD:
1825 bnxt_match_and_validate_ether_filter(bp, efilter,
1830 bfilter = bnxt_get_unused_filter(bp);
1831 if (bfilter == NULL) {
1833 "Not enough resources for a new filter.\n");
1836 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1837 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1839 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1841 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1842 bfilter->ethertype = efilter->ether_type;
1843 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1845 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1846 if (filter1 == NULL) {
1851 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1852 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1854 bfilter->dst_id = vnic->fw_vnic_id;
1856 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1858 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1861 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1864 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1866 case RTE_ETH_FILTER_DELETE:
1867 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1869 if (ret == -EEXIST) {
1870 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1872 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1874 bnxt_free_filter(bp, filter1);
1875 } else if (ret == 0) {
1876 PMD_DRV_LOG(ERR, "No matching filter found\n");
1880 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1886 bnxt_free_filter(bp, bfilter);
1892 parse_ntuple_filter(struct bnxt *bp,
1893 struct rte_eth_ntuple_filter *nfilter,
1894 struct bnxt_filter_info *bfilter)
1898 if (nfilter->queue >= bp->rx_nr_rings) {
1899 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1903 switch (nfilter->dst_port_mask) {
1905 bfilter->dst_port_mask = -1;
1906 bfilter->dst_port = nfilter->dst_port;
1907 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1908 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1911 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1915 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1916 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1918 switch (nfilter->proto_mask) {
1920 if (nfilter->proto == 17) /* IPPROTO_UDP */
1921 bfilter->ip_protocol = 17;
1922 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1923 bfilter->ip_protocol = 6;
1926 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1929 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1933 switch (nfilter->dst_ip_mask) {
1935 bfilter->dst_ipaddr_mask[0] = -1;
1936 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1937 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1938 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1941 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1945 switch (nfilter->src_ip_mask) {
1947 bfilter->src_ipaddr_mask[0] = -1;
1948 bfilter->src_ipaddr[0] = nfilter->src_ip;
1949 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1950 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1953 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1957 switch (nfilter->src_port_mask) {
1959 bfilter->src_port_mask = -1;
1960 bfilter->src_port = nfilter->src_port;
1961 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1962 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1965 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1970 //nfilter->priority = (uint8_t)filter->priority;
1972 bfilter->enables = en;
1976 static struct bnxt_filter_info*
1977 bnxt_match_ntuple_filter(struct bnxt *bp,
1978 struct bnxt_filter_info *bfilter,
1979 struct bnxt_vnic_info **mvnic)
1981 struct bnxt_filter_info *mfilter = NULL;
1984 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1985 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1986 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1987 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1988 bfilter->src_ipaddr_mask[0] ==
1989 mfilter->src_ipaddr_mask[0] &&
1990 bfilter->src_port == mfilter->src_port &&
1991 bfilter->src_port_mask == mfilter->src_port_mask &&
1992 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1993 bfilter->dst_ipaddr_mask[0] ==
1994 mfilter->dst_ipaddr_mask[0] &&
1995 bfilter->dst_port == mfilter->dst_port &&
1996 bfilter->dst_port_mask == mfilter->dst_port_mask &&
1997 bfilter->flags == mfilter->flags &&
1998 bfilter->enables == mfilter->enables) {
2009 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2010 struct rte_eth_ntuple_filter *nfilter,
2011 enum rte_filter_op filter_op)
2013 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2014 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2017 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2018 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2022 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2023 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2027 bfilter = bnxt_get_unused_filter(bp);
2028 if (bfilter == NULL) {
2030 "Not enough resources for a new filter.\n");
2033 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2037 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2038 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2039 filter1 = STAILQ_FIRST(&vnic0->filter);
2040 if (filter1 == NULL) {
2045 bfilter->dst_id = vnic->fw_vnic_id;
2046 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2049 bfilter->ethertype = 0x800;
2050 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2052 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2054 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2055 bfilter->dst_id == mfilter->dst_id) {
2056 PMD_DRV_LOG(ERR, "filter exists.\n");
2059 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2060 bfilter->dst_id != mfilter->dst_id) {
2061 mfilter->dst_id = vnic->fw_vnic_id;
2062 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2063 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2064 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2065 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2066 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2069 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2070 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2075 if (filter_op == RTE_ETH_FILTER_ADD) {
2076 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2077 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2080 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2082 if (mfilter == NULL) {
2083 /* This should not happen. But for Coverity! */
2087 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2089 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2090 bnxt_free_filter(bp, mfilter);
2091 mfilter->fw_l2_filter_id = -1;
2092 bnxt_free_filter(bp, bfilter);
2093 bfilter->fw_l2_filter_id = -1;
2098 bfilter->fw_l2_filter_id = -1;
2099 bnxt_free_filter(bp, bfilter);
2104 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2105 enum rte_filter_op filter_op,
2108 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2111 if (filter_op == RTE_ETH_FILTER_NOP)
2115 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2120 switch (filter_op) {
2121 case RTE_ETH_FILTER_ADD:
2122 ret = bnxt_cfg_ntuple_filter(bp,
2123 (struct rte_eth_ntuple_filter *)arg,
2126 case RTE_ETH_FILTER_DELETE:
2127 ret = bnxt_cfg_ntuple_filter(bp,
2128 (struct rte_eth_ntuple_filter *)arg,
2132 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2140 bnxt_parse_fdir_filter(struct bnxt *bp,
2141 struct rte_eth_fdir_filter *fdir,
2142 struct bnxt_filter_info *filter)
2144 enum rte_fdir_mode fdir_mode =
2145 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2146 struct bnxt_vnic_info *vnic0, *vnic;
2147 struct bnxt_filter_info *filter1;
2151 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2154 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2155 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2157 switch (fdir->input.flow_type) {
2158 case RTE_ETH_FLOW_IPV4:
2159 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2161 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2163 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2164 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2165 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2166 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2167 filter->ip_addr_type =
2168 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2169 filter->src_ipaddr_mask[0] = 0xffffffff;
2170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2171 filter->dst_ipaddr_mask[0] = 0xffffffff;
2172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2173 filter->ethertype = 0x800;
2174 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2176 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2177 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2179 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2180 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2181 filter->dst_port_mask = 0xffff;
2182 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2183 filter->src_port_mask = 0xffff;
2184 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2185 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2187 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2189 filter->ip_protocol = 6;
2190 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2191 filter->ip_addr_type =
2192 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2193 filter->src_ipaddr_mask[0] = 0xffffffff;
2194 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2195 filter->dst_ipaddr_mask[0] = 0xffffffff;
2196 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2197 filter->ethertype = 0x800;
2198 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2200 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2201 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2203 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2205 filter->dst_port_mask = 0xffff;
2206 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2207 filter->src_port_mask = 0xffff;
2208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2209 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2211 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2213 filter->ip_protocol = 17;
2214 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2215 filter->ip_addr_type =
2216 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2217 filter->src_ipaddr_mask[0] = 0xffffffff;
2218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2219 filter->dst_ipaddr_mask[0] = 0xffffffff;
2220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2221 filter->ethertype = 0x800;
2222 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2224 case RTE_ETH_FLOW_IPV6:
2225 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2227 filter->ip_addr_type =
2228 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2229 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2230 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2231 rte_memcpy(filter->src_ipaddr,
2232 fdir->input.flow.ipv6_flow.src_ip, 16);
2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2234 rte_memcpy(filter->dst_ipaddr,
2235 fdir->input.flow.ipv6_flow.dst_ip, 16);
2236 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2237 memset(filter->dst_ipaddr_mask, 0xff, 16);
2238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2239 memset(filter->src_ipaddr_mask, 0xff, 16);
2240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2241 filter->ethertype = 0x86dd;
2242 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2244 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2245 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2246 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2247 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2248 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2249 filter->dst_port_mask = 0xffff;
2250 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2251 filter->src_port_mask = 0xffff;
2252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2253 filter->ip_addr_type =
2254 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2255 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2256 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2257 rte_memcpy(filter->src_ipaddr,
2258 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2259 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2260 rte_memcpy(filter->dst_ipaddr,
2261 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2262 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2263 memset(filter->dst_ipaddr_mask, 0xff, 16);
2264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2265 memset(filter->src_ipaddr_mask, 0xff, 16);
2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2267 filter->ethertype = 0x86dd;
2268 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2270 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2271 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2272 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2273 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2274 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2275 filter->dst_port_mask = 0xffff;
2276 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2277 filter->src_port_mask = 0xffff;
2278 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2279 filter->ip_addr_type =
2280 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2281 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2282 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2283 rte_memcpy(filter->src_ipaddr,
2284 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2285 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2286 rte_memcpy(filter->dst_ipaddr,
2287 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2288 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2289 memset(filter->dst_ipaddr_mask, 0xff, 16);
2290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2291 memset(filter->src_ipaddr_mask, 0xff, 16);
2292 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2293 filter->ethertype = 0x86dd;
2294 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2296 case RTE_ETH_FLOW_L2_PAYLOAD:
2297 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2300 case RTE_ETH_FLOW_VXLAN:
2301 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2303 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2304 filter->tunnel_type =
2305 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2306 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2308 case RTE_ETH_FLOW_NVGRE:
2309 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2311 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2312 filter->tunnel_type =
2313 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2314 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2316 case RTE_ETH_FLOW_UNKNOWN:
2317 case RTE_ETH_FLOW_RAW:
2318 case RTE_ETH_FLOW_FRAG_IPV4:
2319 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2320 case RTE_ETH_FLOW_FRAG_IPV6:
2321 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2322 case RTE_ETH_FLOW_IPV6_EX:
2323 case RTE_ETH_FLOW_IPV6_TCP_EX:
2324 case RTE_ETH_FLOW_IPV6_UDP_EX:
2325 case RTE_ETH_FLOW_GENEVE:
2331 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2332 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2334 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2339 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2340 rte_memcpy(filter->dst_macaddr,
2341 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2342 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2345 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2346 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2347 filter1 = STAILQ_FIRST(&vnic0->filter);
2348 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2350 filter->dst_id = vnic->fw_vnic_id;
2351 for (i = 0; i < ETHER_ADDR_LEN; i++)
2352 if (filter->dst_macaddr[i] == 0x00)
2353 filter1 = STAILQ_FIRST(&vnic0->filter);
2355 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2358 if (filter1 == NULL)
2361 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2362 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2364 filter->enables = en;
2369 static struct bnxt_filter_info *
2370 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2371 struct bnxt_vnic_info **mvnic)
2373 struct bnxt_filter_info *mf = NULL;
2376 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2377 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2379 STAILQ_FOREACH(mf, &vnic->filter, next) {
2380 if (mf->filter_type == nf->filter_type &&
2381 mf->flags == nf->flags &&
2382 mf->src_port == nf->src_port &&
2383 mf->src_port_mask == nf->src_port_mask &&
2384 mf->dst_port == nf->dst_port &&
2385 mf->dst_port_mask == nf->dst_port_mask &&
2386 mf->ip_protocol == nf->ip_protocol &&
2387 mf->ip_addr_type == nf->ip_addr_type &&
2388 mf->ethertype == nf->ethertype &&
2389 mf->vni == nf->vni &&
2390 mf->tunnel_type == nf->tunnel_type &&
2391 mf->l2_ovlan == nf->l2_ovlan &&
2392 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2393 mf->l2_ivlan == nf->l2_ivlan &&
2394 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2395 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2396 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2398 !memcmp(mf->src_macaddr, nf->src_macaddr,
2400 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2402 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2403 sizeof(nf->src_ipaddr)) &&
2404 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2405 sizeof(nf->src_ipaddr_mask)) &&
2406 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2407 sizeof(nf->dst_ipaddr)) &&
2408 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2409 sizeof(nf->dst_ipaddr_mask))) {
2420 bnxt_fdir_filter(struct rte_eth_dev *dev,
2421 enum rte_filter_op filter_op,
2424 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2425 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2426 struct bnxt_filter_info *filter, *match;
2427 struct bnxt_vnic_info *vnic, *mvnic;
2430 if (filter_op == RTE_ETH_FILTER_NOP)
2433 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2436 switch (filter_op) {
2437 case RTE_ETH_FILTER_ADD:
2438 case RTE_ETH_FILTER_DELETE:
2440 filter = bnxt_get_unused_filter(bp);
2441 if (filter == NULL) {
2443 "Not enough resources for a new flow.\n");
2447 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2450 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2452 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2453 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2455 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2457 match = bnxt_match_fdir(bp, filter, &mvnic);
2458 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2459 if (match->dst_id == vnic->fw_vnic_id) {
2460 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2464 match->dst_id = vnic->fw_vnic_id;
2465 ret = bnxt_hwrm_set_ntuple_filter(bp,
2468 STAILQ_REMOVE(&mvnic->filter, match,
2469 bnxt_filter_info, next);
2470 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2472 "Filter with matching pattern exist\n");
2474 "Updated it to new destination q\n");
2478 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2479 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2484 if (filter_op == RTE_ETH_FILTER_ADD) {
2485 ret = bnxt_hwrm_set_ntuple_filter(bp,
2490 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2492 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2493 STAILQ_REMOVE(&vnic->filter, match,
2494 bnxt_filter_info, next);
2495 bnxt_free_filter(bp, match);
2496 filter->fw_l2_filter_id = -1;
2497 bnxt_free_filter(bp, filter);
2500 case RTE_ETH_FILTER_FLUSH:
2501 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2502 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2504 STAILQ_FOREACH(filter, &vnic->filter, next) {
2505 if (filter->filter_type ==
2506 HWRM_CFA_NTUPLE_FILTER) {
2508 bnxt_hwrm_clear_ntuple_filter(bp,
2510 STAILQ_REMOVE(&vnic->filter, filter,
2511 bnxt_filter_info, next);
2516 case RTE_ETH_FILTER_UPDATE:
2517 case RTE_ETH_FILTER_STATS:
2518 case RTE_ETH_FILTER_INFO:
2519 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2522 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2529 filter->fw_l2_filter_id = -1;
2530 bnxt_free_filter(bp, filter);
2535 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2536 enum rte_filter_type filter_type,
2537 enum rte_filter_op filter_op, void *arg)
2541 switch (filter_type) {
2542 case RTE_ETH_FILTER_TUNNEL:
2544 "filter type: %d: To be implemented\n", filter_type);
2546 case RTE_ETH_FILTER_FDIR:
2547 ret = bnxt_fdir_filter(dev, filter_op, arg);
2549 case RTE_ETH_FILTER_NTUPLE:
2550 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2552 case RTE_ETH_FILTER_ETHERTYPE:
2553 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2555 case RTE_ETH_FILTER_GENERIC:
2556 if (filter_op != RTE_ETH_FILTER_GET)
2558 *(const void **)arg = &bnxt_flow_ops;
2562 "Filter type (%d) not supported", filter_type);
2569 static const uint32_t *
2570 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2572 static const uint32_t ptypes[] = {
2573 RTE_PTYPE_L2_ETHER_VLAN,
2574 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2575 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2579 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2580 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2581 RTE_PTYPE_INNER_L4_ICMP,
2582 RTE_PTYPE_INNER_L4_TCP,
2583 RTE_PTYPE_INNER_L4_UDP,
2587 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2592 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2595 uint32_t reg_base = *reg_arr & 0xfffff000;
2599 for (i = 0; i < count; i++) {
2600 if ((reg_arr[i] & 0xfffff000) != reg_base)
2603 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2604 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2608 static int bnxt_map_ptp_regs(struct bnxt *bp)
2610 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2614 reg_arr = ptp->rx_regs;
2615 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2619 reg_arr = ptp->tx_regs;
2620 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2624 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2625 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2627 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2628 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2633 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2635 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2636 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2637 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2638 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2641 static uint64_t bnxt_cc_read(struct bnxt *bp)
2645 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2646 BNXT_GRCPF_REG_SYNC_TIME));
2647 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2648 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2652 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2654 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2657 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2658 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2659 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2662 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2663 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2664 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2665 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2666 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2667 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2672 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2674 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2675 struct bnxt_pf_info *pf = &bp->pf;
2682 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2683 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2684 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2687 port_id = pf->port_id;
2688 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2689 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2691 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2692 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2693 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2694 /* bnxt_clr_rx_ts(bp); TBD */
2698 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2699 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2700 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2701 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2707 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2710 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2711 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2716 ns = rte_timespec_to_ns(ts);
2717 /* Set the timecounters to a new value. */
2724 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2726 uint64_t ns, systime_cycles;
2727 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2728 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2733 systime_cycles = bnxt_cc_read(bp);
2734 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2735 *ts = rte_ns_to_timespec(ns);
2740 bnxt_timesync_enable(struct rte_eth_dev *dev)
2742 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2743 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2750 ptp->tx_tstamp_en = 1;
2751 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2753 if (!bnxt_hwrm_ptp_cfg(bp))
2754 bnxt_map_ptp_regs(bp);
2756 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2757 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2758 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2760 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2761 ptp->tc.cc_shift = shift;
2762 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2764 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2765 ptp->rx_tstamp_tc.cc_shift = shift;
2766 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2768 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2769 ptp->tx_tstamp_tc.cc_shift = shift;
2770 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2776 bnxt_timesync_disable(struct rte_eth_dev *dev)
2778 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2779 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2785 ptp->tx_tstamp_en = 0;
2788 bnxt_hwrm_ptp_cfg(bp);
2790 bnxt_unmap_ptp_regs(bp);
2796 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2797 struct timespec *timestamp,
2798 uint32_t flags __rte_unused)
2800 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2801 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2802 uint64_t rx_tstamp_cycles = 0;
2808 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2809 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2810 *timestamp = rte_ns_to_timespec(ns);
2815 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2816 struct timespec *timestamp)
2818 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2819 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2820 uint64_t tx_tstamp_cycles = 0;
2826 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2827 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2828 *timestamp = rte_ns_to_timespec(ns);
2834 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2836 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2837 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2842 ptp->tc.nsec += delta;
2848 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2850 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2852 uint32_t dir_entries;
2853 uint32_t entry_length;
2855 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2856 bp->pdev->addr.domain, bp->pdev->addr.bus,
2857 bp->pdev->addr.devid, bp->pdev->addr.function);
2859 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2863 return dir_entries * entry_length;
2867 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2868 struct rte_dev_eeprom_info *in_eeprom)
2870 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2874 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2875 "len = %d\n", bp->pdev->addr.domain,
2876 bp->pdev->addr.bus, bp->pdev->addr.devid,
2877 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2879 if (in_eeprom->offset == 0) /* special offset value to get directory */
2880 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2883 index = in_eeprom->offset >> 24;
2884 offset = in_eeprom->offset & 0xffffff;
2887 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2888 in_eeprom->length, in_eeprom->data);
2893 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2896 case BNX_DIR_TYPE_CHIMP_PATCH:
2897 case BNX_DIR_TYPE_BOOTCODE:
2898 case BNX_DIR_TYPE_BOOTCODE_2:
2899 case BNX_DIR_TYPE_APE_FW:
2900 case BNX_DIR_TYPE_APE_PATCH:
2901 case BNX_DIR_TYPE_KONG_FW:
2902 case BNX_DIR_TYPE_KONG_PATCH:
2903 case BNX_DIR_TYPE_BONO_FW:
2904 case BNX_DIR_TYPE_BONO_PATCH:
2912 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2915 case BNX_DIR_TYPE_AVS:
2916 case BNX_DIR_TYPE_EXP_ROM_MBA:
2917 case BNX_DIR_TYPE_PCIE:
2918 case BNX_DIR_TYPE_TSCF_UCODE:
2919 case BNX_DIR_TYPE_EXT_PHY:
2920 case BNX_DIR_TYPE_CCM:
2921 case BNX_DIR_TYPE_ISCSI_BOOT:
2922 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2923 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2931 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2933 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2934 bnxt_dir_type_is_other_exec_format(dir_type);
2938 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2939 struct rte_dev_eeprom_info *in_eeprom)
2941 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2942 uint8_t index, dir_op;
2943 uint16_t type, ext, ordinal, attr;
2945 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2946 "len = %d\n", bp->pdev->addr.domain,
2947 bp->pdev->addr.bus, bp->pdev->addr.devid,
2948 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2951 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2955 type = in_eeprom->magic >> 16;
2957 if (type == 0xffff) { /* special value for directory operations */
2958 index = in_eeprom->magic & 0xff;
2959 dir_op = in_eeprom->magic >> 8;
2963 case 0x0e: /* erase */
2964 if (in_eeprom->offset != ~in_eeprom->magic)
2966 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2972 /* Create or re-write an NVM item: */
2973 if (bnxt_dir_type_is_executable(type) == true)
2975 ext = in_eeprom->magic & 0xffff;
2976 ordinal = in_eeprom->offset >> 16;
2977 attr = in_eeprom->offset & 0xffff;
2979 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2980 in_eeprom->data, in_eeprom->length);
2988 static const struct eth_dev_ops bnxt_dev_ops = {
2989 .dev_infos_get = bnxt_dev_info_get_op,
2990 .dev_close = bnxt_dev_close_op,
2991 .dev_configure = bnxt_dev_configure_op,
2992 .dev_start = bnxt_dev_start_op,
2993 .dev_stop = bnxt_dev_stop_op,
2994 .dev_set_link_up = bnxt_dev_set_link_up_op,
2995 .dev_set_link_down = bnxt_dev_set_link_down_op,
2996 .stats_get = bnxt_stats_get_op,
2997 .stats_reset = bnxt_stats_reset_op,
2998 .rx_queue_setup = bnxt_rx_queue_setup_op,
2999 .rx_queue_release = bnxt_rx_queue_release_op,
3000 .tx_queue_setup = bnxt_tx_queue_setup_op,
3001 .tx_queue_release = bnxt_tx_queue_release_op,
3002 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3003 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3004 .reta_update = bnxt_reta_update_op,
3005 .reta_query = bnxt_reta_query_op,
3006 .rss_hash_update = bnxt_rss_hash_update_op,
3007 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3008 .link_update = bnxt_link_update_op,
3009 .promiscuous_enable = bnxt_promiscuous_enable_op,
3010 .promiscuous_disable = bnxt_promiscuous_disable_op,
3011 .allmulticast_enable = bnxt_allmulticast_enable_op,
3012 .allmulticast_disable = bnxt_allmulticast_disable_op,
3013 .mac_addr_add = bnxt_mac_addr_add_op,
3014 .mac_addr_remove = bnxt_mac_addr_remove_op,
3015 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3016 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3017 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3018 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3019 .vlan_filter_set = bnxt_vlan_filter_set_op,
3020 .vlan_offload_set = bnxt_vlan_offload_set_op,
3021 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3022 .mtu_set = bnxt_mtu_set_op,
3023 .mac_addr_set = bnxt_set_default_mac_addr_op,
3024 .xstats_get = bnxt_dev_xstats_get_op,
3025 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3026 .xstats_reset = bnxt_dev_xstats_reset_op,
3027 .fw_version_get = bnxt_fw_version_get,
3028 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3029 .rxq_info_get = bnxt_rxq_info_get_op,
3030 .txq_info_get = bnxt_txq_info_get_op,
3031 .dev_led_on = bnxt_dev_led_on_op,
3032 .dev_led_off = bnxt_dev_led_off_op,
3033 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3034 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3035 .rx_queue_count = bnxt_rx_queue_count_op,
3036 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3037 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3038 .rx_queue_start = bnxt_rx_queue_start,
3039 .rx_queue_stop = bnxt_rx_queue_stop,
3040 .tx_queue_start = bnxt_tx_queue_start,
3041 .tx_queue_stop = bnxt_tx_queue_stop,
3042 .filter_ctrl = bnxt_filter_ctrl_op,
3043 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3044 .get_eeprom_length = bnxt_get_eeprom_length_op,
3045 .get_eeprom = bnxt_get_eeprom_op,
3046 .set_eeprom = bnxt_set_eeprom_op,
3047 .timesync_enable = bnxt_timesync_enable,
3048 .timesync_disable = bnxt_timesync_disable,
3049 .timesync_read_time = bnxt_timesync_read_time,
3050 .timesync_write_time = bnxt_timesync_write_time,
3051 .timesync_adjust_time = bnxt_timesync_adjust_time,
3052 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3053 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3056 static bool bnxt_vf_pciid(uint16_t id)
3058 if (id == BROADCOM_DEV_ID_57304_VF ||
3059 id == BROADCOM_DEV_ID_57406_VF ||
3060 id == BROADCOM_DEV_ID_5731X_VF ||
3061 id == BROADCOM_DEV_ID_5741X_VF ||
3062 id == BROADCOM_DEV_ID_57414_VF ||
3063 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3064 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3069 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3071 struct bnxt *bp = eth_dev->data->dev_private;
3072 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3075 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3076 if (!pci_dev->mem_resource[0].addr) {
3078 "Cannot find PCI device base address, aborting\n");
3080 goto init_err_disable;
3083 bp->eth_dev = eth_dev;
3086 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3088 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3090 goto init_err_release;
3093 if (!pci_dev->mem_resource[2].addr) {
3095 "Cannot find PCI device BAR 2 address, aborting\n");
3097 goto init_err_release;
3099 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3107 if (bp->doorbell_base)
3108 bp->doorbell_base = NULL;
3115 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3117 #define ALLOW_FUNC(x) \
3119 typeof(x) arg = (x); \
3120 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3121 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3124 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3126 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3127 char mz_name[RTE_MEMZONE_NAMESIZE];
3128 const struct rte_memzone *mz = NULL;
3129 static int version_printed;
3130 uint32_t total_alloc_len;
3131 rte_iova_t mz_phys_addr;
3135 if (version_printed++ == 0)
3136 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3138 rte_eth_copy_pci_info(eth_dev, pci_dev);
3140 bp = eth_dev->data->dev_private;
3142 bp->dev_stopped = 1;
3144 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3147 if (bnxt_vf_pciid(pci_dev->id.device_id))
3148 bp->flags |= BNXT_FLAG_VF;
3150 rc = bnxt_init_board(eth_dev);
3153 "Board initialization failed rc: %x\n", rc);
3157 eth_dev->dev_ops = &bnxt_dev_ops;
3158 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3159 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3160 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3163 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3164 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3165 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3166 pci_dev->addr.bus, pci_dev->addr.devid,
3167 pci_dev->addr.function, "rx_port_stats");
3168 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3169 mz = rte_memzone_lookup(mz_name);
3170 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3171 sizeof(struct rx_port_stats) + 512);
3173 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3176 RTE_MEMZONE_SIZE_HINT_ONLY |
3177 RTE_MEMZONE_IOVA_CONTIG);
3181 memset(mz->addr, 0, mz->len);
3182 mz_phys_addr = mz->iova;
3183 if ((unsigned long)mz->addr == mz_phys_addr) {
3184 PMD_DRV_LOG(WARNING,
3185 "Memzone physical address same as virtual.\n");
3186 PMD_DRV_LOG(WARNING,
3187 "Using rte_mem_virt2iova()\n");
3188 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3189 if (mz_phys_addr == 0) {
3191 "unable to map address to physical memory\n");
3196 bp->rx_mem_zone = (const void *)mz;
3197 bp->hw_rx_port_stats = mz->addr;
3198 bp->hw_rx_port_stats_map = mz_phys_addr;
3200 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3201 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3202 pci_dev->addr.bus, pci_dev->addr.devid,
3203 pci_dev->addr.function, "tx_port_stats");
3204 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3205 mz = rte_memzone_lookup(mz_name);
3206 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3207 sizeof(struct tx_port_stats) + 512);
3209 mz = rte_memzone_reserve(mz_name,
3213 RTE_MEMZONE_SIZE_HINT_ONLY |
3214 RTE_MEMZONE_IOVA_CONTIG);
3218 memset(mz->addr, 0, mz->len);
3219 mz_phys_addr = mz->iova;
3220 if ((unsigned long)mz->addr == mz_phys_addr) {
3221 PMD_DRV_LOG(WARNING,
3222 "Memzone physical address same as virtual.\n");
3223 PMD_DRV_LOG(WARNING,
3224 "Using rte_mem_virt2iova()\n");
3225 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3226 if (mz_phys_addr == 0) {
3228 "unable to map address to physical memory\n");
3233 bp->tx_mem_zone = (const void *)mz;
3234 bp->hw_tx_port_stats = mz->addr;
3235 bp->hw_tx_port_stats_map = mz_phys_addr;
3237 bp->flags |= BNXT_FLAG_PORT_STATS;
3240 rc = bnxt_alloc_hwrm_resources(bp);
3243 "hwrm resource allocation failure rc: %x\n", rc);
3246 rc = bnxt_hwrm_ver_get(bp);
3249 rc = bnxt_hwrm_queue_qportcfg(bp);
3251 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3255 rc = bnxt_hwrm_func_qcfg(bp);
3257 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3261 /* Get the MAX capabilities for this function */
3262 rc = bnxt_hwrm_func_qcaps(bp);
3264 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3267 if (bp->max_tx_rings == 0) {
3268 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3272 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3273 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3274 if (eth_dev->data->mac_addrs == NULL) {
3276 "Failed to alloc %u bytes needed to store MAC addr tbl",
3277 ETHER_ADDR_LEN * bp->max_l2_ctx);
3282 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3284 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3285 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3286 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3287 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3291 /* Copy the permanent MAC from the qcap response address now. */
3292 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3293 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3295 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3296 /* 1 ring is for default completion ring */
3297 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3302 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3303 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3304 if (!bp->grp_info) {
3306 "Failed to alloc %zu bytes to store group info table\n",
3307 sizeof(*bp->grp_info) * bp->max_ring_grps);
3312 /* Forward all requests if firmware is new enough */
3313 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3314 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3315 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3316 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3318 PMD_DRV_LOG(WARNING,
3319 "Firmware too old for VF mailbox functionality\n");
3320 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3324 * The following are used for driver cleanup. If we disallow these,
3325 * VF drivers can't clean up cleanly.
3327 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3328 ALLOW_FUNC(HWRM_VNIC_FREE);
3329 ALLOW_FUNC(HWRM_RING_FREE);
3330 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3331 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3332 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3333 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3334 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3335 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3336 rc = bnxt_hwrm_func_driver_register(bp);
3339 "Failed to register driver");
3345 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3346 pci_dev->mem_resource[0].phys_addr,
3347 pci_dev->mem_resource[0].addr);
3349 rc = bnxt_hwrm_func_reset(bp);
3351 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3357 //if (bp->pf.active_vfs) {
3358 // TODO: Deallocate VF resources?
3360 if (bp->pdev->max_vfs) {
3361 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3363 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3367 rc = bnxt_hwrm_allocate_pf_only(bp);
3370 "Failed to allocate PF resources\n");
3376 bnxt_hwrm_port_led_qcaps(bp);
3378 rc = bnxt_setup_int(bp);
3382 rc = bnxt_alloc_mem(bp);
3384 goto error_free_int;
3386 rc = bnxt_request_int(bp);
3388 goto error_free_int;
3390 bnxt_enable_int(bp);
3396 bnxt_disable_int(bp);
3397 bnxt_hwrm_func_buf_unrgtr(bp);
3401 bnxt_dev_uninit(eth_dev);
3407 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3408 struct bnxt *bp = eth_dev->data->dev_private;
3411 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3414 bnxt_disable_int(bp);
3417 if (eth_dev->data->mac_addrs != NULL) {
3418 rte_free(eth_dev->data->mac_addrs);
3419 eth_dev->data->mac_addrs = NULL;
3421 if (bp->grp_info != NULL) {
3422 rte_free(bp->grp_info);
3423 bp->grp_info = NULL;
3425 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3426 bnxt_free_hwrm_resources(bp);
3427 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3428 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3429 if (bp->dev_stopped == 0)
3430 bnxt_dev_close_op(eth_dev);
3432 rte_free(bp->pf.vf_info);
3433 eth_dev->dev_ops = NULL;
3434 eth_dev->rx_pkt_burst = NULL;
3435 eth_dev->tx_pkt_burst = NULL;
3440 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3441 struct rte_pci_device *pci_dev)
3443 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3447 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3449 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3452 static struct rte_pci_driver bnxt_rte_pmd = {
3453 .id_table = bnxt_pci_id_map,
3454 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3455 RTE_PCI_DRV_INTR_LSC,
3456 .probe = bnxt_pci_probe,
3457 .remove = bnxt_pci_remove,
3461 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3463 if (strcmp(dev->device->driver->name, drv->driver.name))
3469 bool is_bnxt_supported(struct rte_eth_dev *dev)
3471 return is_device_supported(dev, &bnxt_rte_pmd);
3474 RTE_INIT(bnxt_init_log);
3478 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3479 if (bnxt_logtype_driver >= 0)
3480 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3483 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3484 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3485 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");