4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56 #include "bnxt_nvm_defs.h"
58 #define DRV_MODULE_NAME "bnxt"
59 static const char bnxt_version[] =
60 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
62 #define PCI_VENDOR_ID_BROADCOM 0x14E4
64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
66 #define BROADCOM_DEV_ID_57414_VF 0x16c1
67 #define BROADCOM_DEV_ID_57301 0x16c8
68 #define BROADCOM_DEV_ID_57302 0x16c9
69 #define BROADCOM_DEV_ID_57304_PF 0x16ca
70 #define BROADCOM_DEV_ID_57304_VF 0x16cb
71 #define BROADCOM_DEV_ID_57417_MF 0x16cc
72 #define BROADCOM_DEV_ID_NS2 0x16cd
73 #define BROADCOM_DEV_ID_57311 0x16ce
74 #define BROADCOM_DEV_ID_57312 0x16cf
75 #define BROADCOM_DEV_ID_57402 0x16d0
76 #define BROADCOM_DEV_ID_57404 0x16d1
77 #define BROADCOM_DEV_ID_57406_PF 0x16d2
78 #define BROADCOM_DEV_ID_57406_VF 0x16d3
79 #define BROADCOM_DEV_ID_57402_MF 0x16d4
80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
81 #define BROADCOM_DEV_ID_57412 0x16d6
82 #define BROADCOM_DEV_ID_57414 0x16d7
83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
86 #define BROADCOM_DEV_ID_57412_MF 0x16de
87 #define BROADCOM_DEV_ID_57314 0x16df
88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
93 #define BROADCOM_DEV_ID_57404_MF 0x16e7
94 #define BROADCOM_DEV_ID_57406_MF 0x16e8
95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
96 #define BROADCOM_DEV_ID_57407_MF 0x16ea
97 #define BROADCOM_DEV_ID_57414_MF 0x16ec
98 #define BROADCOM_DEV_ID_57416_MF 0x16ee
100 static const struct rte_pci_id bnxt_pci_id_map[] = {
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
102 BROADCOM_DEV_ID_STRATUS_NIC_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
133 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
136 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
137 { .vendor_id = 0, /* sentinel */ },
140 #define BNXT_ETH_RSS_SUPPORT ( \
142 ETH_RSS_NONFRAG_IPV4_TCP | \
143 ETH_RSS_NONFRAG_IPV4_UDP | \
145 ETH_RSS_NONFRAG_IPV6_TCP | \
146 ETH_RSS_NONFRAG_IPV6_UDP)
148 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
150 /***********************/
153 * High level utility functions
156 static void bnxt_free_mem(struct bnxt *bp)
158 bnxt_free_filter_mem(bp);
159 bnxt_free_vnic_attributes(bp);
160 bnxt_free_vnic_mem(bp);
163 bnxt_free_tx_rings(bp);
164 bnxt_free_rx_rings(bp);
165 bnxt_free_def_cp_ring(bp);
168 static int bnxt_alloc_mem(struct bnxt *bp)
172 /* Default completion ring */
173 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
177 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
178 bp->def_cp_ring, "def_cp");
182 rc = bnxt_alloc_vnic_mem(bp);
186 rc = bnxt_alloc_vnic_attributes(bp);
190 rc = bnxt_alloc_filter_mem(bp);
201 static int bnxt_init_chip(struct bnxt *bp)
203 unsigned int i, rss_idx, fw_idx;
204 struct rte_eth_link new;
205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint32_t intr_vector = 0;
208 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
209 uint32_t vec = BNXT_MISC_VEC_ID;
212 /* disable uio/vfio intr/eventfd mapping */
213 rte_intr_disable(intr_handle);
215 if (bp->eth_dev->data->mtu > ETHER_MTU) {
216 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
217 bp->flags |= BNXT_FLAG_JUMBO;
219 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
220 bp->flags &= ~BNXT_FLAG_JUMBO;
223 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
225 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
229 rc = bnxt_alloc_hwrm_rings(bp);
231 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
235 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
237 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
241 rc = bnxt_mq_rx_configure(bp);
243 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
247 /* VNIC configuration */
248 for (i = 0; i < bp->nr_vnics; i++) {
249 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
251 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
253 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
261 "HWRM vnic %d ctx alloc failure rc: %x\n",
266 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
268 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
273 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
276 "HWRM vnic %d filter failure rc: %x\n",
280 if (vnic->rss_table && vnic->hash_type) {
282 * Fill the RSS hash & redirection table with
283 * ring group ids for all VNICs
285 for (rss_idx = 0, fw_idx = 0;
286 rss_idx < HW_HASH_INDEX_SIZE;
287 rss_idx++, fw_idx++) {
288 if (vnic->fw_grp_ids[fw_idx] ==
291 vnic->rss_table[rss_idx] =
292 vnic->fw_grp_ids[fw_idx];
294 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
297 "HWRM vnic %d set RSS failure rc: %x\n",
303 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
305 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
306 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
308 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
310 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
313 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
317 /* check and configure queue intr-vector mapping */
318 if ((rte_intr_cap_multiple(intr_handle) ||
319 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
320 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
321 intr_vector = bp->eth_dev->data->nb_rx_queues;
322 RTE_LOG(INFO, PMD, "%s(): intr_vector = %d\n", __func__,
324 if (intr_vector > bp->rx_cp_nr_rings) {
325 RTE_LOG(ERR, PMD, "At most %d intr queues supported",
329 if (rte_intr_efd_enable(intr_handle, intr_vector))
333 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
334 intr_handle->intr_vec =
335 rte_zmalloc("intr_vec",
336 bp->eth_dev->data->nb_rx_queues *
338 if (intr_handle->intr_vec == NULL) {
339 RTE_LOG(ERR, PMD, "Failed to allocate %d rx_queues"
340 " intr_vec", bp->eth_dev->data->nb_rx_queues);
343 RTE_LOG(DEBUG, PMD, "%s(): intr_handle->intr_vec = %p "
344 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
345 __func__, intr_handle->intr_vec, intr_handle->nb_efd,
346 intr_handle->max_intr);
349 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
351 intr_handle->intr_vec[queue_id] = vec;
352 if (vec < base + intr_handle->nb_efd - 1)
356 /* enable uio/vfio intr/eventfd mapping */
357 rte_intr_enable(intr_handle);
359 rc = bnxt_get_hwrm_link_config(bp, &new);
361 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
365 if (!bp->link_info.link_up) {
366 rc = bnxt_set_hwrm_link_config(bp, true);
369 "HWRM link config failure rc: %x\n", rc);
377 bnxt_free_all_hwrm_resources(bp);
382 static int bnxt_shutdown_nic(struct bnxt *bp)
384 bnxt_free_all_hwrm_resources(bp);
385 bnxt_free_all_filters(bp);
386 bnxt_free_all_vnics(bp);
390 static int bnxt_init_nic(struct bnxt *bp)
394 bnxt_init_ring_grps(bp);
396 bnxt_init_filters(bp);
398 rc = bnxt_init_chip(bp);
406 * Device configuration and status function
409 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
410 struct rte_eth_dev_info *dev_info)
412 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
413 uint16_t max_vnics, i, j, vpool, vrxq;
414 unsigned int max_rx_rings;
416 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
419 dev_info->max_mac_addrs = bp->max_l2_ctx;
420 dev_info->max_hash_mac_addrs = 0;
422 /* PF/VF specifics */
424 dev_info->max_vfs = bp->pdev->max_vfs;
425 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
426 RTE_MIN(bp->max_rsscos_ctx,
428 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
429 dev_info->max_rx_queues = max_rx_rings;
430 dev_info->max_tx_queues = max_rx_rings;
431 dev_info->reta_size = bp->max_rsscos_ctx;
432 dev_info->hash_key_size = 40;
433 max_vnics = bp->max_vnics;
435 /* Fast path specifics */
436 dev_info->min_rx_bufsize = 1;
437 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
439 dev_info->rx_offload_capa = 0;
440 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
441 DEV_TX_OFFLOAD_TCP_CKSUM |
442 DEV_TX_OFFLOAD_UDP_CKSUM |
443 DEV_TX_OFFLOAD_TCP_TSO |
444 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
445 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
446 DEV_TX_OFFLOAD_GRE_TNL_TSO |
447 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
448 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
451 dev_info->default_rxconf = (struct rte_eth_rxconf) {
457 .rx_free_thresh = 32,
461 dev_info->default_txconf = (struct rte_eth_txconf) {
467 .tx_free_thresh = 32,
469 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
470 ETH_TXQ_FLAGS_NOOFFLOADS,
472 eth_dev->data->dev_conf.intr_conf.lsc = 1;
474 eth_dev->data->dev_conf.intr_conf.rxq = 1;
479 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
480 * need further investigation.
484 vpool = 64; /* ETH_64_POOLS */
485 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
486 for (i = 0; i < 4; vpool >>= 1, i++) {
487 if (max_vnics > vpool) {
488 for (j = 0; j < 5; vrxq >>= 1, j++) {
489 if (dev_info->max_rx_queues > vrxq) {
495 /* Not enough resources to support VMDq */
499 /* Not enough resources to support VMDq */
503 dev_info->max_vmdq_pools = vpool;
504 dev_info->vmdq_queue_num = vrxq;
506 dev_info->vmdq_pool_base = 0;
507 dev_info->vmdq_queue_base = 0;
510 /* Configure the device based on the configuration provided */
511 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
513 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
515 bp->rx_queues = (void *)eth_dev->data->rx_queues;
516 bp->tx_queues = (void *)eth_dev->data->tx_queues;
518 /* Inherit new configurations */
519 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
520 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
521 bp->rx_cp_nr_rings = bp->rx_nr_rings;
522 bp->tx_cp_nr_rings = bp->tx_nr_rings;
524 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
526 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
527 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
532 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
533 struct rte_eth_link *link)
535 struct rte_eth_link *dst = ð_dev->data->dev_link;
536 struct rte_eth_link *src = link;
538 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
539 *(uint64_t *)src) == 0)
545 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
547 struct rte_eth_link *link = ð_dev->data->dev_link;
549 if (link->link_status)
550 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
551 eth_dev->data->port_id,
552 (uint32_t)link->link_speed,
553 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
554 ("full-duplex") : ("half-duplex\n"));
556 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
557 eth_dev->data->port_id);
560 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
562 bnxt_print_link_info(eth_dev);
566 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
568 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
574 rc = bnxt_init_nic(bp);
578 bnxt_link_update_op(eth_dev, 0);
580 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
581 vlan_mask |= ETH_VLAN_FILTER_MASK;
582 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
583 vlan_mask |= ETH_VLAN_STRIP_MASK;
584 bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
589 bnxt_shutdown_nic(bp);
590 bnxt_free_tx_mbufs(bp);
591 bnxt_free_rx_mbufs(bp);
595 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
597 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
599 eth_dev->data->dev_link.link_status = 1;
600 bnxt_set_hwrm_link_config(bp, true);
604 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
606 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
608 eth_dev->data->dev_link.link_status = 0;
609 bnxt_set_hwrm_link_config(bp, false);
613 /* Unload the driver, release resources */
614 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
616 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
618 if (bp->eth_dev->data->dev_started) {
619 /* TBD: STOP HW queues DMA */
620 eth_dev->data->dev_link.link_status = 0;
622 bnxt_set_hwrm_link_config(bp, false);
623 bnxt_hwrm_port_clr_stats(bp);
624 bnxt_shutdown_nic(bp);
628 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
630 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
632 if (bp->dev_stopped == 0)
633 bnxt_dev_stop_op(eth_dev);
635 bnxt_free_tx_mbufs(bp);
636 bnxt_free_rx_mbufs(bp);
638 if (eth_dev->data->mac_addrs != NULL) {
639 rte_free(eth_dev->data->mac_addrs);
640 eth_dev->data->mac_addrs = NULL;
642 if (bp->grp_info != NULL) {
643 rte_free(bp->grp_info);
648 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
651 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
652 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
653 struct bnxt_vnic_info *vnic;
654 struct bnxt_filter_info *filter, *temp_filter;
658 * Loop through all VNICs from the specified filter flow pools to
659 * remove the corresponding MAC addr filter
661 for (i = 0; i < MAX_FF_POOLS; i++) {
662 if (!(pool_mask & (1ULL << i)))
665 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
666 filter = STAILQ_FIRST(&vnic->filter);
668 temp_filter = STAILQ_NEXT(filter, next);
669 if (filter->mac_index == index) {
670 STAILQ_REMOVE(&vnic->filter, filter,
671 bnxt_filter_info, next);
672 bnxt_hwrm_clear_l2_filter(bp, filter);
673 filter->mac_index = INVALID_MAC_INDEX;
674 memset(&filter->l2_addr, 0,
677 &bp->free_filter_list,
680 filter = temp_filter;
686 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
687 struct ether_addr *mac_addr,
688 uint32_t index, uint32_t pool)
690 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
691 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
692 struct bnxt_filter_info *filter;
695 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
700 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
703 /* Attach requested MAC address to the new l2_filter */
704 STAILQ_FOREACH(filter, &vnic->filter, next) {
705 if (filter->mac_index == index) {
707 "MAC addr already existed for pool %d\n", pool);
711 filter = bnxt_alloc_filter(bp);
713 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
716 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
717 filter->mac_index = index;
718 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
719 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
722 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
725 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
726 struct rte_eth_link new;
727 unsigned int cnt = BNXT_LINK_WAIT_CNT;
729 memset(&new, 0, sizeof(new));
731 /* Retrieve link info from hardware */
732 rc = bnxt_get_hwrm_link_config(bp, &new);
734 new.link_speed = ETH_LINK_SPEED_100M;
735 new.link_duplex = ETH_LINK_FULL_DUPLEX;
737 "Failed to retrieve link rc = 0x%x!\n", rc);
740 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
742 if (!wait_to_complete)
744 } while (!new.link_status && cnt--);
747 /* Timed out or success */
748 if (new.link_status != eth_dev->data->dev_link.link_status ||
749 new.link_speed != eth_dev->data->dev_link.link_speed) {
750 rte_bnxt_atomic_write_link_status(eth_dev, &new);
751 bnxt_print_link_info(eth_dev);
757 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
759 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
760 struct bnxt_vnic_info *vnic;
762 if (bp->vnic_info == NULL)
765 vnic = &bp->vnic_info[0];
767 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
768 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
771 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
773 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
774 struct bnxt_vnic_info *vnic;
776 if (bp->vnic_info == NULL)
779 vnic = &bp->vnic_info[0];
781 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
782 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
785 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
787 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
788 struct bnxt_vnic_info *vnic;
790 if (bp->vnic_info == NULL)
793 vnic = &bp->vnic_info[0];
795 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
796 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
799 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
801 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
802 struct bnxt_vnic_info *vnic;
804 if (bp->vnic_info == NULL)
807 vnic = &bp->vnic_info[0];
809 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
810 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
813 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
814 struct rte_eth_rss_reta_entry64 *reta_conf,
817 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
818 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
819 struct bnxt_vnic_info *vnic;
822 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
825 if (reta_size != HW_HASH_INDEX_SIZE) {
826 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
827 "(%d) must equal the size supported by the hardware "
828 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
831 /* Update the RSS VNIC(s) */
832 for (i = 0; i < MAX_FF_POOLS; i++) {
833 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
834 memcpy(vnic->rss_table, reta_conf, reta_size);
836 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
842 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
843 struct rte_eth_rss_reta_entry64 *reta_conf,
846 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
847 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
848 struct rte_intr_handle *intr_handle
849 = &bp->pdev->intr_handle;
851 /* Retrieve from the default VNIC */
854 if (!vnic->rss_table)
857 if (reta_size != HW_HASH_INDEX_SIZE) {
858 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
859 "(%d) must equal the size supported by the hardware "
860 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
863 /* EW - need to revisit here copying from u64 to u16 */
864 memcpy(reta_conf, vnic->rss_table, reta_size);
866 if (rte_intr_allow_others(intr_handle)) {
867 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
868 bnxt_dev_lsc_intr_setup(eth_dev);
874 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
875 struct rte_eth_rss_conf *rss_conf)
877 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
878 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
879 struct bnxt_vnic_info *vnic;
880 uint16_t hash_type = 0;
884 * If RSS enablement were different than dev_configure,
885 * then return -EINVAL
887 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
888 if (!rss_conf->rss_hf)
889 RTE_LOG(ERR, PMD, "Hash type NONE\n");
891 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
895 bp->flags |= BNXT_FLAG_UPDATE_HASH;
896 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
898 if (rss_conf->rss_hf & ETH_RSS_IPV4)
899 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
900 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
901 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
902 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
903 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
904 if (rss_conf->rss_hf & ETH_RSS_IPV6)
905 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
906 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
907 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
908 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
909 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
911 /* Update the RSS VNIC(s) */
912 for (i = 0; i < MAX_FF_POOLS; i++) {
913 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
914 vnic->hash_type = hash_type;
917 * Use the supplied key if the key length is
918 * acceptable and the rss_key is not NULL
920 if (rss_conf->rss_key &&
921 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
922 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
923 rss_conf->rss_key_len);
925 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
931 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
932 struct rte_eth_rss_conf *rss_conf)
934 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
935 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
939 /* RSS configuration is the same for all VNICs */
940 if (vnic && vnic->rss_hash_key) {
941 if (rss_conf->rss_key) {
942 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
943 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
944 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
947 hash_types = vnic->hash_type;
948 rss_conf->rss_hf = 0;
949 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
950 rss_conf->rss_hf |= ETH_RSS_IPV4;
951 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
953 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
954 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
956 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
958 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
959 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
961 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
963 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
964 rss_conf->rss_hf |= ETH_RSS_IPV6;
965 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
967 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
968 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
970 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
972 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
973 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
975 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
979 "Unknwon RSS config from firmware (%08x), RSS disabled",
984 rss_conf->rss_hf = 0;
989 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
990 struct rte_eth_fc_conf *fc_conf)
992 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
993 struct rte_eth_link link_info;
996 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1000 memset(fc_conf, 0, sizeof(*fc_conf));
1001 if (bp->link_info.auto_pause)
1002 fc_conf->autoneg = 1;
1003 switch (bp->link_info.pause) {
1005 fc_conf->mode = RTE_FC_NONE;
1007 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1008 fc_conf->mode = RTE_FC_TX_PAUSE;
1010 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1011 fc_conf->mode = RTE_FC_RX_PAUSE;
1013 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1014 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1015 fc_conf->mode = RTE_FC_FULL;
1021 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1022 struct rte_eth_fc_conf *fc_conf)
1024 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1026 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1027 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
1031 switch (fc_conf->mode) {
1033 bp->link_info.auto_pause = 0;
1034 bp->link_info.force_pause = 0;
1036 case RTE_FC_RX_PAUSE:
1037 if (fc_conf->autoneg) {
1038 bp->link_info.auto_pause =
1039 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1040 bp->link_info.force_pause = 0;
1042 bp->link_info.auto_pause = 0;
1043 bp->link_info.force_pause =
1044 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1047 case RTE_FC_TX_PAUSE:
1048 if (fc_conf->autoneg) {
1049 bp->link_info.auto_pause =
1050 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1051 bp->link_info.force_pause = 0;
1053 bp->link_info.auto_pause = 0;
1054 bp->link_info.force_pause =
1055 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1059 if (fc_conf->autoneg) {
1060 bp->link_info.auto_pause =
1061 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1062 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1063 bp->link_info.force_pause = 0;
1065 bp->link_info.auto_pause = 0;
1066 bp->link_info.force_pause =
1067 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1068 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1072 return bnxt_set_hwrm_link_config(bp, true);
1075 /* Add UDP tunneling port */
1077 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1078 struct rte_eth_udp_tunnel *udp_tunnel)
1080 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1081 uint16_t tunnel_type = 0;
1084 switch (udp_tunnel->prot_type) {
1085 case RTE_TUNNEL_TYPE_VXLAN:
1086 if (bp->vxlan_port_cnt) {
1087 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1088 udp_tunnel->udp_port);
1089 if (bp->vxlan_port != udp_tunnel->udp_port) {
1090 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1093 bp->vxlan_port_cnt++;
1097 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1098 bp->vxlan_port_cnt++;
1100 case RTE_TUNNEL_TYPE_GENEVE:
1101 if (bp->geneve_port_cnt) {
1102 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1103 udp_tunnel->udp_port);
1104 if (bp->geneve_port != udp_tunnel->udp_port) {
1105 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1108 bp->geneve_port_cnt++;
1112 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1113 bp->geneve_port_cnt++;
1116 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1119 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1125 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1126 struct rte_eth_udp_tunnel *udp_tunnel)
1128 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1129 uint16_t tunnel_type = 0;
1133 switch (udp_tunnel->prot_type) {
1134 case RTE_TUNNEL_TYPE_VXLAN:
1135 if (!bp->vxlan_port_cnt) {
1136 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1139 if (bp->vxlan_port != udp_tunnel->udp_port) {
1140 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1141 udp_tunnel->udp_port, bp->vxlan_port);
1144 if (--bp->vxlan_port_cnt)
1148 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1149 port = bp->vxlan_fw_dst_port_id;
1151 case RTE_TUNNEL_TYPE_GENEVE:
1152 if (!bp->geneve_port_cnt) {
1153 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1156 if (bp->geneve_port != udp_tunnel->udp_port) {
1157 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1158 udp_tunnel->udp_port, bp->geneve_port);
1161 if (--bp->geneve_port_cnt)
1165 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1166 port = bp->geneve_fw_dst_port_id;
1169 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1173 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1176 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1179 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1180 bp->geneve_port = 0;
1185 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1187 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1188 struct bnxt_vnic_info *vnic;
1191 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1193 /* Cycle through all VNICs */
1194 for (i = 0; i < bp->nr_vnics; i++) {
1196 * For each VNIC and each associated filter(s)
1197 * if VLAN exists && VLAN matches vlan_id
1198 * remove the MAC+VLAN filter
1199 * add a new MAC only filter
1201 * VLAN filter doesn't exist, just skip and continue
1203 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1204 filter = STAILQ_FIRST(&vnic->filter);
1206 temp_filter = STAILQ_NEXT(filter, next);
1208 if (filter->enables & chk &&
1209 filter->l2_ovlan == vlan_id) {
1210 /* Must delete the filter */
1211 STAILQ_REMOVE(&vnic->filter, filter,
1212 bnxt_filter_info, next);
1213 bnxt_hwrm_clear_l2_filter(bp, filter);
1215 &bp->free_filter_list,
1219 * Need to examine to see if the MAC
1220 * filter already existed or not before
1221 * allocating a new one
1224 new_filter = bnxt_alloc_filter(bp);
1227 "MAC/VLAN filter alloc failed\n");
1231 STAILQ_INSERT_TAIL(&vnic->filter,
1233 /* Inherit MAC from previous filter */
1234 new_filter->mac_index =
1236 memcpy(new_filter->l2_addr,
1237 filter->l2_addr, ETHER_ADDR_LEN);
1238 /* MAC only filter */
1239 rc = bnxt_hwrm_set_l2_filter(bp,
1245 "Del Vlan filter for %d\n",
1248 filter = temp_filter;
1256 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1258 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1259 struct bnxt_vnic_info *vnic;
1262 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1263 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1264 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1266 /* Cycle through all VNICs */
1267 for (i = 0; i < bp->nr_vnics; i++) {
1269 * For each VNIC and each associated filter(s)
1271 * if VLAN matches vlan_id
1272 * VLAN filter already exists, just skip and continue
1274 * add a new MAC+VLAN filter
1276 * Remove the old MAC only filter
1277 * Add a new MAC+VLAN filter
1279 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1280 filter = STAILQ_FIRST(&vnic->filter);
1282 temp_filter = STAILQ_NEXT(filter, next);
1284 if (filter->enables & chk) {
1285 if (filter->l2_ovlan == vlan_id)
1288 /* Must delete the MAC filter */
1289 STAILQ_REMOVE(&vnic->filter, filter,
1290 bnxt_filter_info, next);
1291 bnxt_hwrm_clear_l2_filter(bp, filter);
1292 filter->l2_ovlan = 0;
1294 &bp->free_filter_list,
1297 new_filter = bnxt_alloc_filter(bp);
1300 "MAC/VLAN filter alloc failed\n");
1304 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1306 /* Inherit MAC from the previous filter */
1307 new_filter->mac_index = filter->mac_index;
1308 memcpy(new_filter->l2_addr, filter->l2_addr,
1310 /* MAC + VLAN ID filter */
1311 new_filter->l2_ovlan = vlan_id;
1312 new_filter->l2_ovlan_mask = 0xF000;
1313 new_filter->enables |= en;
1314 rc = bnxt_hwrm_set_l2_filter(bp,
1320 "Added Vlan filter for %d\n", vlan_id);
1322 filter = temp_filter;
1330 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1331 uint16_t vlan_id, int on)
1333 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1335 /* These operations apply to ALL existing MAC/VLAN filters */
1337 return bnxt_add_vlan_filter(bp, vlan_id);
1339 return bnxt_del_vlan_filter(bp, vlan_id);
1343 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1345 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1348 if (mask & ETH_VLAN_FILTER_MASK) {
1349 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1350 /* Remove any VLAN filters programmed */
1351 for (i = 0; i < 4095; i++)
1352 bnxt_del_vlan_filter(bp, i);
1354 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1355 dev->data->dev_conf.rxmode.hw_vlan_filter);
1358 if (mask & ETH_VLAN_STRIP_MASK) {
1359 /* Enable or disable VLAN stripping */
1360 for (i = 0; i < bp->nr_vnics; i++) {
1361 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1362 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1363 vnic->vlan_strip = true;
1365 vnic->vlan_strip = false;
1366 bnxt_hwrm_vnic_cfg(bp, vnic);
1368 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1369 dev->data->dev_conf.rxmode.hw_vlan_strip);
1372 if (mask & ETH_VLAN_EXTEND_MASK)
1373 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1377 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1379 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1380 /* Default Filter is tied to VNIC 0 */
1381 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1382 struct bnxt_filter_info *filter;
1388 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1389 memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1391 STAILQ_FOREACH(filter, &vnic->filter, next) {
1392 /* Default Filter is at Index 0 */
1393 if (filter->mac_index != 0)
1395 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1398 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1399 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1400 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1402 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1404 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1407 filter->mac_index = 0;
1408 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1413 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1414 struct ether_addr *mc_addr_set,
1415 uint32_t nb_mc_addr)
1417 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1418 char *mc_addr_list = (char *)mc_addr_set;
1419 struct bnxt_vnic_info *vnic;
1420 uint32_t off = 0, i = 0;
1422 vnic = &bp->vnic_info[0];
1424 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1425 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1429 /* TODO Check for Duplicate mcast addresses */
1430 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1431 for (i = 0; i < nb_mc_addr; i++) {
1432 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1433 off += ETHER_ADDR_LEN;
1436 vnic->mc_addr_cnt = i;
1439 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1443 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1445 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1446 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1447 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1448 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1451 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1452 fw_major, fw_minor, fw_updt);
1454 ret += 1; /* add the size of '\0' */
1455 if (fw_size < (uint32_t)ret)
1462 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1463 struct rte_eth_rxq_info *qinfo)
1465 struct bnxt_rx_queue *rxq;
1467 rxq = dev->data->rx_queues[queue_id];
1469 qinfo->mp = rxq->mb_pool;
1470 qinfo->scattered_rx = dev->data->scattered_rx;
1471 qinfo->nb_desc = rxq->nb_rx_desc;
1473 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1474 qinfo->conf.rx_drop_en = 0;
1475 qinfo->conf.rx_deferred_start = 0;
1479 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1480 struct rte_eth_txq_info *qinfo)
1482 struct bnxt_tx_queue *txq;
1484 txq = dev->data->tx_queues[queue_id];
1486 qinfo->nb_desc = txq->nb_tx_desc;
1488 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1489 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1490 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1492 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1493 qinfo->conf.tx_rs_thresh = 0;
1494 qinfo->conf.txq_flags = txq->txq_flags;
1495 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1498 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1500 struct bnxt *bp = eth_dev->data->dev_private;
1501 struct rte_eth_dev_info dev_info;
1502 uint32_t max_dev_mtu;
1506 bnxt_dev_info_get_op(eth_dev, &dev_info);
1507 max_dev_mtu = dev_info.max_rx_pktlen -
1508 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1510 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1511 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1512 ETHER_MIN_MTU, max_dev_mtu);
1517 if (new_mtu > ETHER_MTU) {
1518 bp->flags |= BNXT_FLAG_JUMBO;
1519 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1521 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1522 bp->flags &= ~BNXT_FLAG_JUMBO;
1525 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1526 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1528 eth_dev->data->mtu = new_mtu;
1529 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1531 for (i = 0; i < bp->nr_vnics; i++) {
1532 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1534 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1535 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1536 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1540 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1549 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1551 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1552 uint16_t vlan = bp->vlan;
1555 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1557 "PVID cannot be modified for this function\n");
1560 bp->vlan = on ? pvid : 0;
1562 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1569 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1571 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1573 return bnxt_hwrm_port_led_cfg(bp, true);
1577 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1579 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1581 return bnxt_hwrm_port_led_cfg(bp, false);
1585 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1587 uint32_t desc = 0, raw_cons = 0, cons;
1588 struct bnxt_cp_ring_info *cpr;
1589 struct bnxt_rx_queue *rxq;
1590 struct rx_pkt_cmpl *rxcmp;
1595 rxq = dev->data->rx_queues[rx_queue_id];
1599 while (raw_cons < rxq->nb_rx_desc) {
1600 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1601 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1603 if (!CMPL_VALID(rxcmp, valid))
1605 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1606 cmp_type = CMP_TYPE(rxcmp);
1607 if (cmp_type == RX_PKT_CMPL_TYPE_RX_L2_TPA_END) {
1608 cmp = (rte_le_to_cpu_32(
1609 ((struct rx_tpa_end_cmpl *)
1610 (rxcmp))->agg_bufs_v1) &
1611 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1612 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1614 } else if (cmp_type == 0x11) {
1616 cmp = (rxcmp->agg_bufs_v1 &
1617 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1618 RX_PKT_CMPL_AGG_BUFS_SFT;
1623 raw_cons += cmp ? cmp : 2;
1630 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1632 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1633 struct bnxt_rx_ring_info *rxr;
1634 struct bnxt_cp_ring_info *cpr;
1635 struct bnxt_sw_rx_bd *rx_buf;
1636 struct rx_pkt_cmpl *rxcmp;
1637 uint32_t cons, cp_cons;
1645 if (offset >= rxq->nb_rx_desc)
1648 cons = RING_CMP(cpr->cp_ring_struct, offset);
1649 cp_cons = cpr->cp_raw_cons;
1650 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1652 if (cons > cp_cons) {
1653 if (CMPL_VALID(rxcmp, cpr->valid))
1654 return RTE_ETH_RX_DESC_DONE;
1656 if (CMPL_VALID(rxcmp, !cpr->valid))
1657 return RTE_ETH_RX_DESC_DONE;
1659 rx_buf = &rxr->rx_buf_ring[cons];
1660 if (rx_buf->mbuf == NULL)
1661 return RTE_ETH_RX_DESC_UNAVAIL;
1664 return RTE_ETH_RX_DESC_AVAIL;
1668 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1670 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1671 struct bnxt_tx_ring_info *txr;
1672 struct bnxt_cp_ring_info *cpr;
1673 struct bnxt_sw_tx_bd *tx_buf;
1674 struct tx_pkt_cmpl *txcmp;
1675 uint32_t cons, cp_cons;
1683 if (offset >= txq->nb_tx_desc)
1686 cons = RING_CMP(cpr->cp_ring_struct, offset);
1687 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1688 cp_cons = cpr->cp_raw_cons;
1690 if (cons > cp_cons) {
1691 if (CMPL_VALID(txcmp, cpr->valid))
1692 return RTE_ETH_TX_DESC_UNAVAIL;
1694 if (CMPL_VALID(txcmp, !cpr->valid))
1695 return RTE_ETH_TX_DESC_UNAVAIL;
1697 tx_buf = &txr->tx_buf_ring[cons];
1698 if (tx_buf->mbuf == NULL)
1699 return RTE_ETH_TX_DESC_DONE;
1701 return RTE_ETH_TX_DESC_FULL;
1704 static struct bnxt_filter_info *
1705 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1706 struct rte_eth_ethertype_filter *efilter,
1707 struct bnxt_vnic_info *vnic0,
1708 struct bnxt_vnic_info *vnic,
1711 struct bnxt_filter_info *mfilter = NULL;
1715 if (efilter->ether_type != ETHER_TYPE_IPv4 &&
1716 efilter->ether_type != ETHER_TYPE_IPv6) {
1717 RTE_LOG(ERR, PMD, "unsupported ether_type(0x%04x) in"
1718 " ethertype filter.", efilter->ether_type);
1721 if (efilter->queue >= bp->rx_nr_rings) {
1722 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1726 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1727 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1729 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1733 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1734 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1735 if ((!memcmp(efilter->mac_addr.addr_bytes,
1736 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1738 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1739 mfilter->ethertype == efilter->ether_type)) {
1745 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1746 if ((!memcmp(efilter->mac_addr.addr_bytes,
1747 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1748 mfilter->ethertype == efilter->ether_type &&
1750 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1763 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1764 enum rte_filter_op filter_op,
1767 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1768 struct rte_eth_ethertype_filter *efilter =
1769 (struct rte_eth_ethertype_filter *)arg;
1770 struct bnxt_filter_info *bfilter, *filter1;
1771 struct bnxt_vnic_info *vnic, *vnic0;
1774 if (filter_op == RTE_ETH_FILTER_NOP)
1778 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
1783 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1784 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1786 switch (filter_op) {
1787 case RTE_ETH_FILTER_ADD:
1788 bnxt_match_and_validate_ether_filter(bp, efilter,
1793 bfilter = bnxt_get_unused_filter(bp);
1794 if (bfilter == NULL) {
1796 "Not enough resources for a new filter.\n");
1799 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1800 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1802 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1804 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1805 bfilter->ethertype = efilter->ether_type;
1806 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1808 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1809 if (filter1 == NULL) {
1814 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1815 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1817 bfilter->dst_id = vnic->fw_vnic_id;
1819 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1821 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1824 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1827 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1829 case RTE_ETH_FILTER_DELETE:
1830 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1832 if (ret == -EEXIST) {
1833 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1835 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1837 bnxt_free_filter(bp, filter1);
1838 } else if (ret == 0) {
1839 RTE_LOG(ERR, PMD, "No matching filter found\n");
1843 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
1849 bnxt_free_filter(bp, bfilter);
1855 parse_ntuple_filter(struct bnxt *bp,
1856 struct rte_eth_ntuple_filter *nfilter,
1857 struct bnxt_filter_info *bfilter)
1861 if (nfilter->queue >= bp->rx_nr_rings) {
1862 RTE_LOG(ERR, PMD, "Invalid queue %d\n", nfilter->queue);
1866 switch (nfilter->dst_port_mask) {
1868 bfilter->dst_port_mask = -1;
1869 bfilter->dst_port = nfilter->dst_port;
1870 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1871 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1874 RTE_LOG(ERR, PMD, "invalid dst_port mask.");
1878 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1879 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1881 switch (nfilter->proto_mask) {
1883 if (nfilter->proto == 17) /* IPPROTO_UDP */
1884 bfilter->ip_protocol = 17;
1885 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1886 bfilter->ip_protocol = 6;
1889 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1892 RTE_LOG(ERR, PMD, "invalid protocol mask.");
1896 switch (nfilter->dst_ip_mask) {
1898 bfilter->dst_ipaddr_mask[0] = -1;
1899 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1901 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1904 RTE_LOG(ERR, PMD, "invalid dst_ip mask.");
1908 switch (nfilter->src_ip_mask) {
1910 bfilter->src_ipaddr_mask[0] = -1;
1911 bfilter->src_ipaddr[0] = nfilter->src_ip;
1912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1913 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1916 RTE_LOG(ERR, PMD, "invalid src_ip mask.");
1920 switch (nfilter->src_port_mask) {
1922 bfilter->src_port_mask = -1;
1923 bfilter->src_port = nfilter->src_port;
1924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1925 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1928 RTE_LOG(ERR, PMD, "invalid src_port mask.");
1933 //nfilter->priority = (uint8_t)filter->priority;
1935 bfilter->enables = en;
1939 static struct bnxt_filter_info*
1940 bnxt_match_ntuple_filter(struct bnxt_vnic_info *vnic,
1941 struct bnxt_filter_info *bfilter)
1943 struct bnxt_filter_info *mfilter = NULL;
1945 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1946 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1947 bfilter->src_ipaddr_mask[0] ==
1948 mfilter->src_ipaddr_mask[0] &&
1949 bfilter->src_port == mfilter->src_port &&
1950 bfilter->src_port_mask == mfilter->src_port_mask &&
1951 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1952 bfilter->dst_ipaddr_mask[0] ==
1953 mfilter->dst_ipaddr_mask[0] &&
1954 bfilter->dst_port == mfilter->dst_port &&
1955 bfilter->dst_port_mask == mfilter->dst_port_mask &&
1956 bfilter->flags == mfilter->flags &&
1957 bfilter->enables == mfilter->enables)
1964 bnxt_cfg_ntuple_filter(struct bnxt *bp,
1965 struct rte_eth_ntuple_filter *nfilter,
1966 enum rte_filter_op filter_op)
1968 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
1969 struct bnxt_vnic_info *vnic, *vnic0;
1972 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
1973 RTE_LOG(ERR, PMD, "only 5tuple is supported.");
1977 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
1978 RTE_LOG(ERR, PMD, "Ntuple filter: TCP flags not supported\n");
1982 bfilter = bnxt_get_unused_filter(bp);
1983 if (bfilter == NULL) {
1985 "Not enough resources for a new filter.\n");
1988 ret = parse_ntuple_filter(bp, nfilter, bfilter);
1992 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
1993 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1994 filter1 = STAILQ_FIRST(&vnic0->filter);
1995 if (filter1 == NULL) {
2000 bfilter->dst_id = vnic->fw_vnic_id;
2001 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2003 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2004 bfilter->ethertype = 0x800;
2005 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2007 mfilter = bnxt_match_ntuple_filter(vnic, bfilter);
2009 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2010 RTE_LOG(ERR, PMD, "filter exists.");
2014 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2015 RTE_LOG(ERR, PMD, "filter doesn't exist.");
2020 if (filter_op == RTE_ETH_FILTER_ADD) {
2021 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2022 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2025 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2027 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2029 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info,
2031 bnxt_free_filter(bp, mfilter);
2032 bfilter->fw_l2_filter_id = -1;
2033 bnxt_free_filter(bp, bfilter);
2038 bfilter->fw_l2_filter_id = -1;
2039 bnxt_free_filter(bp, bfilter);
2044 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2045 enum rte_filter_op filter_op,
2048 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2051 if (filter_op == RTE_ETH_FILTER_NOP)
2055 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
2060 switch (filter_op) {
2061 case RTE_ETH_FILTER_ADD:
2062 ret = bnxt_cfg_ntuple_filter(bp,
2063 (struct rte_eth_ntuple_filter *)arg,
2066 case RTE_ETH_FILTER_DELETE:
2067 ret = bnxt_cfg_ntuple_filter(bp,
2068 (struct rte_eth_ntuple_filter *)arg,
2072 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
2079 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2080 enum rte_filter_type filter_type,
2081 enum rte_filter_op filter_op, void *arg)
2085 switch (filter_type) {
2086 case RTE_ETH_FILTER_FDIR:
2087 case RTE_ETH_FILTER_TUNNEL:
2090 "filter type: %d: To be implemented\n", filter_type);
2092 case RTE_ETH_FILTER_NTUPLE:
2093 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2095 case RTE_ETH_FILTER_ETHERTYPE:
2096 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2098 case RTE_ETH_FILTER_GENERIC:
2099 if (filter_op != RTE_ETH_FILTER_GET)
2101 *(const void **)arg = &bnxt_flow_ops;
2105 "Filter type (%d) not supported", filter_type);
2112 static const uint32_t *
2113 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2115 static const uint32_t ptypes[] = {
2116 RTE_PTYPE_L2_ETHER_VLAN,
2117 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2118 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2122 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2123 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2124 RTE_PTYPE_INNER_L4_ICMP,
2125 RTE_PTYPE_INNER_L4_TCP,
2126 RTE_PTYPE_INNER_L4_UDP,
2130 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2138 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2140 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2142 uint32_t dir_entries;
2143 uint32_t entry_length;
2145 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n",
2146 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus,
2147 bp->pdev->addr.devid, bp->pdev->addr.function);
2149 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2153 return dir_entries * entry_length;
2157 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2158 struct rte_dev_eeprom_info *in_eeprom)
2160 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2164 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2165 "len = %d\n", __func__, bp->pdev->addr.domain,
2166 bp->pdev->addr.bus, bp->pdev->addr.devid,
2167 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2169 if (in_eeprom->offset == 0) /* special offset value to get directory */
2170 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2173 index = in_eeprom->offset >> 24;
2174 offset = in_eeprom->offset & 0xffffff;
2177 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2178 in_eeprom->length, in_eeprom->data);
2183 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2186 case BNX_DIR_TYPE_CHIMP_PATCH:
2187 case BNX_DIR_TYPE_BOOTCODE:
2188 case BNX_DIR_TYPE_BOOTCODE_2:
2189 case BNX_DIR_TYPE_APE_FW:
2190 case BNX_DIR_TYPE_APE_PATCH:
2191 case BNX_DIR_TYPE_KONG_FW:
2192 case BNX_DIR_TYPE_KONG_PATCH:
2193 case BNX_DIR_TYPE_BONO_FW:
2194 case BNX_DIR_TYPE_BONO_PATCH:
2201 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2204 case BNX_DIR_TYPE_AVS:
2205 case BNX_DIR_TYPE_EXP_ROM_MBA:
2206 case BNX_DIR_TYPE_PCIE:
2207 case BNX_DIR_TYPE_TSCF_UCODE:
2208 case BNX_DIR_TYPE_EXT_PHY:
2209 case BNX_DIR_TYPE_CCM:
2210 case BNX_DIR_TYPE_ISCSI_BOOT:
2211 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2212 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2219 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2221 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2222 bnxt_dir_type_is_other_exec_format(dir_type);
2226 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2227 struct rte_dev_eeprom_info *in_eeprom)
2229 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2230 uint8_t index, dir_op;
2231 uint16_t type, ext, ordinal, attr;
2233 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
2234 "len = %d\n", __func__, bp->pdev->addr.domain,
2235 bp->pdev->addr.bus, bp->pdev->addr.devid,
2236 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2239 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n");
2243 type = in_eeprom->magic >> 16;
2245 if (type == 0xffff) { /* special value for directory operations */
2246 index = in_eeprom->magic & 0xff;
2247 dir_op = in_eeprom->magic >> 8;
2251 case 0x0e: /* erase */
2252 if (in_eeprom->offset != ~in_eeprom->magic)
2254 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2260 /* Create or re-write an NVM item: */
2261 if (bnxt_dir_type_is_executable(type) == true)
2263 ext = in_eeprom->magic & 0xffff;
2264 ordinal = in_eeprom->offset >> 16;
2265 attr = in_eeprom->offset & 0xffff;
2267 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2268 in_eeprom->data, in_eeprom->length);
2276 static const struct eth_dev_ops bnxt_dev_ops = {
2277 .dev_infos_get = bnxt_dev_info_get_op,
2278 .dev_close = bnxt_dev_close_op,
2279 .dev_configure = bnxt_dev_configure_op,
2280 .dev_start = bnxt_dev_start_op,
2281 .dev_stop = bnxt_dev_stop_op,
2282 .dev_set_link_up = bnxt_dev_set_link_up_op,
2283 .dev_set_link_down = bnxt_dev_set_link_down_op,
2284 .stats_get = bnxt_stats_get_op,
2285 .stats_reset = bnxt_stats_reset_op,
2286 .rx_queue_setup = bnxt_rx_queue_setup_op,
2287 .rx_queue_release = bnxt_rx_queue_release_op,
2288 .tx_queue_setup = bnxt_tx_queue_setup_op,
2289 .tx_queue_release = bnxt_tx_queue_release_op,
2290 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
2291 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
2292 .reta_update = bnxt_reta_update_op,
2293 .reta_query = bnxt_reta_query_op,
2294 .rss_hash_update = bnxt_rss_hash_update_op,
2295 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
2296 .link_update = bnxt_link_update_op,
2297 .promiscuous_enable = bnxt_promiscuous_enable_op,
2298 .promiscuous_disable = bnxt_promiscuous_disable_op,
2299 .allmulticast_enable = bnxt_allmulticast_enable_op,
2300 .allmulticast_disable = bnxt_allmulticast_disable_op,
2301 .mac_addr_add = bnxt_mac_addr_add_op,
2302 .mac_addr_remove = bnxt_mac_addr_remove_op,
2303 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
2304 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
2305 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
2306 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
2307 .vlan_filter_set = bnxt_vlan_filter_set_op,
2308 .vlan_offload_set = bnxt_vlan_offload_set_op,
2309 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
2310 .mtu_set = bnxt_mtu_set_op,
2311 .mac_addr_set = bnxt_set_default_mac_addr_op,
2312 .xstats_get = bnxt_dev_xstats_get_op,
2313 .xstats_get_names = bnxt_dev_xstats_get_names_op,
2314 .xstats_reset = bnxt_dev_xstats_reset_op,
2315 .fw_version_get = bnxt_fw_version_get,
2316 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
2317 .rxq_info_get = bnxt_rxq_info_get_op,
2318 .txq_info_get = bnxt_txq_info_get_op,
2319 .dev_led_on = bnxt_dev_led_on_op,
2320 .dev_led_off = bnxt_dev_led_off_op,
2321 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
2322 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
2323 .rx_queue_count = bnxt_rx_queue_count_op,
2324 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
2325 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
2326 .filter_ctrl = bnxt_filter_ctrl_op,
2327 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
2328 .get_eeprom_length = bnxt_get_eeprom_length_op,
2329 .get_eeprom = bnxt_get_eeprom_op,
2330 .set_eeprom = bnxt_set_eeprom_op,
2333 static bool bnxt_vf_pciid(uint16_t id)
2335 if (id == BROADCOM_DEV_ID_57304_VF ||
2336 id == BROADCOM_DEV_ID_57406_VF ||
2337 id == BROADCOM_DEV_ID_5731X_VF ||
2338 id == BROADCOM_DEV_ID_5741X_VF ||
2339 id == BROADCOM_DEV_ID_57414_VF ||
2340 id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
2345 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
2347 struct bnxt *bp = eth_dev->data->dev_private;
2348 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2351 /* enable device (incl. PCI PM wakeup), and bus-mastering */
2352 if (!pci_dev->mem_resource[0].addr) {
2354 "Cannot find PCI device base address, aborting\n");
2356 goto init_err_disable;
2359 bp->eth_dev = eth_dev;
2362 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
2364 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
2366 goto init_err_release;
2379 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
2381 #define ALLOW_FUNC(x) \
2383 typeof(x) arg = (x); \
2384 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
2385 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
2388 bnxt_dev_init(struct rte_eth_dev *eth_dev)
2390 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2391 char mz_name[RTE_MEMZONE_NAMESIZE];
2392 const struct rte_memzone *mz = NULL;
2393 static int version_printed;
2394 uint32_t total_alloc_len;
2395 phys_addr_t mz_phys_addr;
2399 if (version_printed++ == 0)
2400 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
2402 rte_eth_copy_pci_info(eth_dev, pci_dev);
2403 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2405 bp = eth_dev->data->dev_private;
2407 rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
2408 bp->dev_stopped = 1;
2410 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2413 if (bnxt_vf_pciid(pci_dev->id.device_id))
2414 bp->flags |= BNXT_FLAG_VF;
2416 rc = bnxt_init_board(eth_dev);
2419 "Board initialization failed rc: %x\n", rc);
2423 eth_dev->dev_ops = &bnxt_dev_ops;
2424 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2426 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
2427 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
2429 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
2430 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2431 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2432 pci_dev->addr.bus, pci_dev->addr.devid,
2433 pci_dev->addr.function, "rx_port_stats");
2434 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2435 mz = rte_memzone_lookup(mz_name);
2436 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2437 sizeof(struct rx_port_stats) + 512);
2439 mz = rte_memzone_reserve(mz_name, total_alloc_len,
2442 RTE_MEMZONE_SIZE_HINT_ONLY);
2446 memset(mz->addr, 0, mz->len);
2447 mz_phys_addr = mz->phys_addr;
2448 if ((unsigned long)mz->addr == mz_phys_addr) {
2449 RTE_LOG(WARNING, PMD,
2450 "Memzone physical address same as virtual.\n");
2451 RTE_LOG(WARNING, PMD,
2452 "Using rte_mem_virt2phy()\n");
2453 mz_phys_addr = rte_mem_virt2phy(mz->addr);
2454 if (mz_phys_addr == 0) {
2456 "unable to map address to physical memory\n");
2461 bp->rx_mem_zone = (const void *)mz;
2462 bp->hw_rx_port_stats = mz->addr;
2463 bp->hw_rx_port_stats_map = mz_phys_addr;
2465 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2466 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2467 pci_dev->addr.bus, pci_dev->addr.devid,
2468 pci_dev->addr.function, "tx_port_stats");
2469 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2470 mz = rte_memzone_lookup(mz_name);
2471 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2472 sizeof(struct tx_port_stats) + 512);
2474 mz = rte_memzone_reserve(mz_name, total_alloc_len,
2477 RTE_MEMZONE_SIZE_HINT_ONLY);
2481 memset(mz->addr, 0, mz->len);
2482 mz_phys_addr = mz->phys_addr;
2483 if ((unsigned long)mz->addr == mz_phys_addr) {
2484 RTE_LOG(WARNING, PMD,
2485 "Memzone physical address same as virtual.\n");
2486 RTE_LOG(WARNING, PMD,
2487 "Using rte_mem_virt2phy()\n");
2488 mz_phys_addr = rte_mem_virt2phy(mz->addr);
2489 if (mz_phys_addr == 0) {
2491 "unable to map address to physical memory\n");
2496 bp->tx_mem_zone = (const void *)mz;
2497 bp->hw_tx_port_stats = mz->addr;
2498 bp->hw_tx_port_stats_map = mz_phys_addr;
2500 bp->flags |= BNXT_FLAG_PORT_STATS;
2503 rc = bnxt_alloc_hwrm_resources(bp);
2506 "hwrm resource allocation failure rc: %x\n", rc);
2509 rc = bnxt_hwrm_ver_get(bp);
2512 bnxt_hwrm_queue_qportcfg(bp);
2514 bnxt_hwrm_func_qcfg(bp);
2516 /* Get the MAX capabilities for this function */
2517 rc = bnxt_hwrm_func_qcaps(bp);
2519 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
2522 if (bp->max_tx_rings == 0) {
2523 RTE_LOG(ERR, PMD, "No TX rings available!\n");
2527 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
2528 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
2529 if (eth_dev->data->mac_addrs == NULL) {
2531 "Failed to alloc %u bytes needed to store MAC addr tbl",
2532 ETHER_ADDR_LEN * bp->max_l2_ctx);
2536 /* Copy the permanent MAC from the qcap response address now. */
2537 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
2538 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
2539 bp->grp_info = rte_zmalloc("bnxt_grp_info",
2540 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
2541 if (!bp->grp_info) {
2543 "Failed to alloc %zu bytes needed to store group info table\n",
2544 sizeof(*bp->grp_info) * bp->max_ring_grps);
2549 /* Forward all requests if firmware is new enough */
2550 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
2551 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
2552 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
2553 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
2555 RTE_LOG(WARNING, PMD,
2556 "Firmware too old for VF mailbox functionality\n");
2557 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
2561 * The following are used for driver cleanup. If we disallow these,
2562 * VF drivers can't clean up cleanly.
2564 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
2565 ALLOW_FUNC(HWRM_VNIC_FREE);
2566 ALLOW_FUNC(HWRM_RING_FREE);
2567 ALLOW_FUNC(HWRM_RING_GRP_FREE);
2568 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
2569 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
2570 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
2571 rc = bnxt_hwrm_func_driver_register(bp);
2574 "Failed to register driver");
2580 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
2581 pci_dev->mem_resource[0].phys_addr,
2582 pci_dev->mem_resource[0].addr);
2584 rc = bnxt_hwrm_func_reset(bp);
2586 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
2592 //if (bp->pf.active_vfs) {
2593 // TODO: Deallocate VF resources?
2595 if (bp->pdev->max_vfs) {
2596 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
2598 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
2602 rc = bnxt_hwrm_allocate_pf_only(bp);
2605 "Failed to allocate PF resources\n");
2611 bnxt_hwrm_port_led_qcaps(bp);
2613 rc = bnxt_setup_int(bp);
2617 rc = bnxt_alloc_mem(bp);
2619 goto error_free_int;
2621 rc = bnxt_request_int(bp);
2623 goto error_free_int;
2625 rc = bnxt_alloc_def_cp_ring(bp);
2627 goto error_free_int;
2629 bnxt_enable_int(bp);
2634 bnxt_disable_int(bp);
2635 bnxt_free_def_cp_ring(bp);
2636 bnxt_hwrm_func_buf_unrgtr(bp);
2640 bnxt_dev_uninit(eth_dev);
2646 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
2647 struct bnxt *bp = eth_dev->data->dev_private;
2650 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2653 bnxt_disable_int(bp);
2656 if (eth_dev->data->mac_addrs != NULL) {
2657 rte_free(eth_dev->data->mac_addrs);
2658 eth_dev->data->mac_addrs = NULL;
2660 if (bp->grp_info != NULL) {
2661 rte_free(bp->grp_info);
2662 bp->grp_info = NULL;
2664 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
2665 bnxt_free_hwrm_resources(bp);
2666 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
2667 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
2668 if (bp->dev_stopped == 0)
2669 bnxt_dev_close_op(eth_dev);
2671 rte_free(bp->pf.vf_info);
2672 eth_dev->dev_ops = NULL;
2673 eth_dev->rx_pkt_burst = NULL;
2674 eth_dev->tx_pkt_burst = NULL;
2679 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2680 struct rte_pci_device *pci_dev)
2682 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
2686 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
2688 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
2691 static struct rte_pci_driver bnxt_rte_pmd = {
2692 .id_table = bnxt_pci_id_map,
2693 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
2694 RTE_PCI_DRV_INTR_LSC,
2695 .probe = bnxt_pci_probe,
2696 .remove = bnxt_pci_remove,
2700 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
2702 if (strcmp(dev->device->driver->name, drv->driver.name))
2708 bool is_bnxt_supported(struct rte_eth_dev *dev)
2710 return is_device_supported(dev, &bnxt_rte_pmd);
2713 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
2714 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
2715 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");