4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
57 #define DRV_MODULE_NAME "bnxt"
58 static const char bnxt_version[] =
59 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
63 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
64 #define BROADCOM_DEV_ID_57414_VF 0x16c1
65 #define BROADCOM_DEV_ID_57301 0x16c8
66 #define BROADCOM_DEV_ID_57302 0x16c9
67 #define BROADCOM_DEV_ID_57304_PF 0x16ca
68 #define BROADCOM_DEV_ID_57304_VF 0x16cb
69 #define BROADCOM_DEV_ID_57417_MF 0x16cc
70 #define BROADCOM_DEV_ID_NS2 0x16cd
71 #define BROADCOM_DEV_ID_57311 0x16ce
72 #define BROADCOM_DEV_ID_57312 0x16cf
73 #define BROADCOM_DEV_ID_57402 0x16d0
74 #define BROADCOM_DEV_ID_57404 0x16d1
75 #define BROADCOM_DEV_ID_57406_PF 0x16d2
76 #define BROADCOM_DEV_ID_57406_VF 0x16d3
77 #define BROADCOM_DEV_ID_57402_MF 0x16d4
78 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
79 #define BROADCOM_DEV_ID_57412 0x16d6
80 #define BROADCOM_DEV_ID_57414 0x16d7
81 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
82 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
83 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
84 #define BROADCOM_DEV_ID_57412_MF 0x16de
85 #define BROADCOM_DEV_ID_57314 0x16df
86 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
87 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
88 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
89 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
90 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
91 #define BROADCOM_DEV_ID_57404_MF 0x16e7
92 #define BROADCOM_DEV_ID_57406_MF 0x16e8
93 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
94 #define BROADCOM_DEV_ID_57407_MF 0x16ea
95 #define BROADCOM_DEV_ID_57414_MF 0x16ec
96 #define BROADCOM_DEV_ID_57416_MF 0x16ee
98 static const struct rte_pci_id bnxt_pci_id_map[] = {
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
146 /***********************/
149 * High level utility functions
152 static void bnxt_free_mem(struct bnxt *bp)
154 bnxt_free_filter_mem(bp);
155 bnxt_free_vnic_attributes(bp);
156 bnxt_free_vnic_mem(bp);
159 bnxt_free_tx_rings(bp);
160 bnxt_free_rx_rings(bp);
161 bnxt_free_def_cp_ring(bp);
164 static int bnxt_alloc_mem(struct bnxt *bp)
168 /* Default completion ring */
169 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
173 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
174 bp->def_cp_ring, "def_cp");
178 rc = bnxt_alloc_vnic_mem(bp);
182 rc = bnxt_alloc_vnic_attributes(bp);
186 rc = bnxt_alloc_filter_mem(bp);
197 static int bnxt_init_chip(struct bnxt *bp)
199 unsigned int i, rss_idx, fw_idx;
200 struct rte_eth_link new;
203 if (bp->eth_dev->data->mtu > ETHER_MTU) {
204 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
205 bp->flags |= BNXT_FLAG_JUMBO;
207 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
208 bp->flags &= ~BNXT_FLAG_JUMBO;
211 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
213 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
217 rc = bnxt_alloc_hwrm_rings(bp);
219 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
223 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
225 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
229 rc = bnxt_mq_rx_configure(bp);
231 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
235 /* VNIC configuration */
236 for (i = 0; i < bp->nr_vnics; i++) {
237 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
239 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
241 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
246 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
249 "HWRM vnic %d ctx alloc failure rc: %x\n",
254 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
256 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
261 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
264 "HWRM vnic %d filter failure rc: %x\n",
268 if (vnic->rss_table && vnic->hash_type) {
270 * Fill the RSS hash & redirection table with
271 * ring group ids for all VNICs
273 for (rss_idx = 0, fw_idx = 0;
274 rss_idx < HW_HASH_INDEX_SIZE;
275 rss_idx++, fw_idx++) {
276 if (vnic->fw_grp_ids[fw_idx] ==
279 vnic->rss_table[rss_idx] =
280 vnic->fw_grp_ids[fw_idx];
282 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
285 "HWRM vnic %d set RSS failure rc: %x\n",
291 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
293 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
294 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
296 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
298 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
301 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
305 rc = bnxt_get_hwrm_link_config(bp, &new);
307 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
311 if (!bp->link_info.link_up) {
312 rc = bnxt_set_hwrm_link_config(bp, true);
315 "HWRM link config failure rc: %x\n", rc);
323 bnxt_free_all_hwrm_resources(bp);
328 static int bnxt_shutdown_nic(struct bnxt *bp)
330 bnxt_free_all_hwrm_resources(bp);
331 bnxt_free_all_filters(bp);
332 bnxt_free_all_vnics(bp);
336 static int bnxt_init_nic(struct bnxt *bp)
340 bnxt_init_ring_grps(bp);
342 bnxt_init_filters(bp);
344 rc = bnxt_init_chip(bp);
352 * Device configuration and status function
355 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
356 struct rte_eth_dev_info *dev_info)
358 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
359 uint16_t max_vnics, i, j, vpool, vrxq;
361 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
364 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
365 dev_info->max_hash_mac_addrs = 0;
367 /* PF/VF specifics */
369 dev_info->max_vfs = bp->pdev->max_vfs;
370 dev_info->max_rx_queues = bp->max_rx_rings;
371 dev_info->max_tx_queues = bp->max_tx_rings;
372 dev_info->reta_size = bp->max_rsscos_ctx;
373 max_vnics = bp->max_vnics;
375 /* Fast path specifics */
376 dev_info->min_rx_bufsize = 1;
377 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
379 dev_info->rx_offload_capa = 0;
380 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
381 DEV_TX_OFFLOAD_TCP_CKSUM |
382 DEV_TX_OFFLOAD_UDP_CKSUM |
383 DEV_TX_OFFLOAD_TCP_TSO |
384 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
385 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
386 DEV_TX_OFFLOAD_GRE_TNL_TSO |
387 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
388 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
391 dev_info->default_rxconf = (struct rte_eth_rxconf) {
397 .rx_free_thresh = 32,
401 dev_info->default_txconf = (struct rte_eth_txconf) {
407 .tx_free_thresh = 32,
409 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
410 ETH_TXQ_FLAGS_NOOFFLOADS,
412 eth_dev->data->dev_conf.intr_conf.lsc = 1;
417 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
418 * need further investigation.
422 vpool = 64; /* ETH_64_POOLS */
423 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
424 for (i = 0; i < 4; vpool >>= 1, i++) {
425 if (max_vnics > vpool) {
426 for (j = 0; j < 5; vrxq >>= 1, j++) {
427 if (dev_info->max_rx_queues > vrxq) {
433 /* Not enough resources to support VMDq */
437 /* Not enough resources to support VMDq */
441 dev_info->max_vmdq_pools = vpool;
442 dev_info->vmdq_queue_num = vrxq;
444 dev_info->vmdq_pool_base = 0;
445 dev_info->vmdq_queue_base = 0;
448 /* Configure the device based on the configuration provided */
449 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
451 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
453 bp->rx_queues = (void *)eth_dev->data->rx_queues;
454 bp->tx_queues = (void *)eth_dev->data->tx_queues;
456 /* Inherit new configurations */
457 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
458 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
459 bp->rx_cp_nr_rings = bp->rx_nr_rings;
460 bp->tx_cp_nr_rings = bp->tx_nr_rings;
462 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
464 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
465 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
470 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
471 struct rte_eth_link *link)
473 struct rte_eth_link *dst = ð_dev->data->dev_link;
474 struct rte_eth_link *src = link;
476 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
477 *(uint64_t *)src) == 0)
483 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
485 struct rte_eth_link *link = ð_dev->data->dev_link;
487 if (link->link_status)
488 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
489 (uint8_t)(eth_dev->data->port_id),
490 (uint32_t)link->link_speed,
491 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
492 ("full-duplex") : ("half-duplex\n"));
494 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
495 (uint8_t)(eth_dev->data->port_id));
498 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
500 bnxt_print_link_info(eth_dev);
504 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
506 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
512 rc = bnxt_init_nic(bp);
516 bnxt_link_update_op(eth_dev, 0);
518 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
519 vlan_mask |= ETH_VLAN_FILTER_MASK;
520 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
521 vlan_mask |= ETH_VLAN_STRIP_MASK;
522 bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
527 bnxt_shutdown_nic(bp);
528 bnxt_free_tx_mbufs(bp);
529 bnxt_free_rx_mbufs(bp);
533 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
535 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
537 eth_dev->data->dev_link.link_status = 1;
538 bnxt_set_hwrm_link_config(bp, true);
542 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
544 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
546 eth_dev->data->dev_link.link_status = 0;
547 bnxt_set_hwrm_link_config(bp, false);
551 /* Unload the driver, release resources */
552 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
554 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
556 if (bp->eth_dev->data->dev_started) {
557 /* TBD: STOP HW queues DMA */
558 eth_dev->data->dev_link.link_status = 0;
560 bnxt_set_hwrm_link_config(bp, false);
561 bnxt_hwrm_port_clr_stats(bp);
562 bnxt_shutdown_nic(bp);
566 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
568 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
570 if (bp->dev_stopped == 0)
571 bnxt_dev_stop_op(eth_dev);
573 bnxt_free_tx_mbufs(bp);
574 bnxt_free_rx_mbufs(bp);
576 if (eth_dev->data->mac_addrs != NULL) {
577 rte_free(eth_dev->data->mac_addrs);
578 eth_dev->data->mac_addrs = NULL;
580 if (bp->grp_info != NULL) {
581 rte_free(bp->grp_info);
586 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
589 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
590 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
591 struct bnxt_vnic_info *vnic;
592 struct bnxt_filter_info *filter, *temp_filter;
596 * Loop through all VNICs from the specified filter flow pools to
597 * remove the corresponding MAC addr filter
599 for (i = 0; i < MAX_FF_POOLS; i++) {
600 if (!(pool_mask & (1ULL << i)))
603 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
604 filter = STAILQ_FIRST(&vnic->filter);
606 temp_filter = STAILQ_NEXT(filter, next);
607 if (filter->mac_index == index) {
608 STAILQ_REMOVE(&vnic->filter, filter,
609 bnxt_filter_info, next);
610 bnxt_hwrm_clear_filter(bp, filter);
611 filter->mac_index = INVALID_MAC_INDEX;
612 memset(&filter->l2_addr, 0,
615 &bp->free_filter_list,
618 filter = temp_filter;
624 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
625 struct ether_addr *mac_addr,
626 uint32_t index, uint32_t pool)
628 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
629 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
630 struct bnxt_filter_info *filter;
633 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
638 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
641 /* Attach requested MAC address to the new l2_filter */
642 STAILQ_FOREACH(filter, &vnic->filter, next) {
643 if (filter->mac_index == index) {
645 "MAC addr already existed for pool %d\n", pool);
649 filter = bnxt_alloc_filter(bp);
651 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
654 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
655 filter->mac_index = index;
656 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
657 return bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
660 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
663 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
664 struct rte_eth_link new;
665 unsigned int cnt = BNXT_LINK_WAIT_CNT;
667 memset(&new, 0, sizeof(new));
669 /* Retrieve link info from hardware */
670 rc = bnxt_get_hwrm_link_config(bp, &new);
672 new.link_speed = ETH_LINK_SPEED_100M;
673 new.link_duplex = ETH_LINK_FULL_DUPLEX;
675 "Failed to retrieve link rc = 0x%x!\n", rc);
678 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
680 if (!wait_to_complete)
682 } while (!new.link_status && cnt--);
685 /* Timed out or success */
686 if (new.link_status != eth_dev->data->dev_link.link_status ||
687 new.link_speed != eth_dev->data->dev_link.link_speed) {
688 rte_bnxt_atomic_write_link_status(eth_dev, &new);
689 bnxt_print_link_info(eth_dev);
695 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
697 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
698 struct bnxt_vnic_info *vnic;
700 if (bp->vnic_info == NULL)
703 vnic = &bp->vnic_info[0];
705 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
706 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
709 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
711 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
712 struct bnxt_vnic_info *vnic;
714 if (bp->vnic_info == NULL)
717 vnic = &bp->vnic_info[0];
719 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
720 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
723 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
725 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
726 struct bnxt_vnic_info *vnic;
728 if (bp->vnic_info == NULL)
731 vnic = &bp->vnic_info[0];
733 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
734 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
737 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
739 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
740 struct bnxt_vnic_info *vnic;
742 if (bp->vnic_info == NULL)
745 vnic = &bp->vnic_info[0];
747 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
748 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
751 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
752 struct rte_eth_rss_reta_entry64 *reta_conf,
755 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
756 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
757 struct bnxt_vnic_info *vnic;
760 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
763 if (reta_size != HW_HASH_INDEX_SIZE) {
764 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
765 "(%d) must equal the size supported by the hardware "
766 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
769 /* Update the RSS VNIC(s) */
770 for (i = 0; i < MAX_FF_POOLS; i++) {
771 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
772 memcpy(vnic->rss_table, reta_conf, reta_size);
774 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
780 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
781 struct rte_eth_rss_reta_entry64 *reta_conf,
784 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
785 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
786 struct rte_intr_handle *intr_handle
787 = &bp->pdev->intr_handle;
789 /* Retrieve from the default VNIC */
792 if (!vnic->rss_table)
795 if (reta_size != HW_HASH_INDEX_SIZE) {
796 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
797 "(%d) must equal the size supported by the hardware "
798 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
801 /* EW - need to revisit here copying from u64 to u16 */
802 memcpy(reta_conf, vnic->rss_table, reta_size);
804 if (rte_intr_allow_others(intr_handle)) {
805 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
806 bnxt_dev_lsc_intr_setup(eth_dev);
812 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
813 struct rte_eth_rss_conf *rss_conf)
815 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
816 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
817 struct bnxt_vnic_info *vnic;
818 uint16_t hash_type = 0;
822 * If RSS enablement were different than dev_configure,
823 * then return -EINVAL
825 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
826 if (!rss_conf->rss_hf)
829 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
832 if (rss_conf->rss_hf & ETH_RSS_IPV4)
833 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
834 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
835 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
836 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
837 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
838 if (rss_conf->rss_hf & ETH_RSS_IPV6)
839 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
840 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
841 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
842 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
843 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
845 /* Update the RSS VNIC(s) */
846 for (i = 0; i < MAX_FF_POOLS; i++) {
847 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
848 vnic->hash_type = hash_type;
851 * Use the supplied key if the key length is
852 * acceptable and the rss_key is not NULL
854 if (rss_conf->rss_key &&
855 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
856 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
857 rss_conf->rss_key_len);
859 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
865 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
866 struct rte_eth_rss_conf *rss_conf)
868 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
869 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
873 /* RSS configuration is the same for all VNICs */
874 if (vnic && vnic->rss_hash_key) {
875 if (rss_conf->rss_key) {
876 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
877 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
878 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
881 hash_types = vnic->hash_type;
882 rss_conf->rss_hf = 0;
883 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
884 rss_conf->rss_hf |= ETH_RSS_IPV4;
885 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
887 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
888 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
890 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
892 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
893 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
895 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
897 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
898 rss_conf->rss_hf |= ETH_RSS_IPV6;
899 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
901 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
902 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
904 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
906 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
907 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
909 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
913 "Unknwon RSS config from firmware (%08x), RSS disabled",
918 rss_conf->rss_hf = 0;
923 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
924 struct rte_eth_fc_conf *fc_conf)
926 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
927 struct rte_eth_link link_info;
930 rc = bnxt_get_hwrm_link_config(bp, &link_info);
934 memset(fc_conf, 0, sizeof(*fc_conf));
935 if (bp->link_info.auto_pause)
936 fc_conf->autoneg = 1;
937 switch (bp->link_info.pause) {
939 fc_conf->mode = RTE_FC_NONE;
941 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
942 fc_conf->mode = RTE_FC_TX_PAUSE;
944 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
945 fc_conf->mode = RTE_FC_RX_PAUSE;
947 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
948 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
949 fc_conf->mode = RTE_FC_FULL;
955 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
956 struct rte_eth_fc_conf *fc_conf)
958 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
960 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
961 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
965 switch (fc_conf->mode) {
967 bp->link_info.auto_pause = 0;
968 bp->link_info.force_pause = 0;
970 case RTE_FC_RX_PAUSE:
971 if (fc_conf->autoneg) {
972 bp->link_info.auto_pause =
973 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
974 bp->link_info.force_pause = 0;
976 bp->link_info.auto_pause = 0;
977 bp->link_info.force_pause =
978 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
981 case RTE_FC_TX_PAUSE:
982 if (fc_conf->autoneg) {
983 bp->link_info.auto_pause =
984 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
985 bp->link_info.force_pause = 0;
987 bp->link_info.auto_pause = 0;
988 bp->link_info.force_pause =
989 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
993 if (fc_conf->autoneg) {
994 bp->link_info.auto_pause =
995 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
996 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
997 bp->link_info.force_pause = 0;
999 bp->link_info.auto_pause = 0;
1000 bp->link_info.force_pause =
1001 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1002 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1006 return bnxt_set_hwrm_link_config(bp, true);
1009 /* Add UDP tunneling port */
1011 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1012 struct rte_eth_udp_tunnel *udp_tunnel)
1014 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1015 uint16_t tunnel_type = 0;
1018 switch (udp_tunnel->prot_type) {
1019 case RTE_TUNNEL_TYPE_VXLAN:
1020 if (bp->vxlan_port_cnt) {
1021 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1022 udp_tunnel->udp_port);
1023 if (bp->vxlan_port != udp_tunnel->udp_port) {
1024 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1027 bp->vxlan_port_cnt++;
1031 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1032 bp->vxlan_port_cnt++;
1034 case RTE_TUNNEL_TYPE_GENEVE:
1035 if (bp->geneve_port_cnt) {
1036 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1037 udp_tunnel->udp_port);
1038 if (bp->geneve_port != udp_tunnel->udp_port) {
1039 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1042 bp->geneve_port_cnt++;
1046 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1047 bp->geneve_port_cnt++;
1050 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1053 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1059 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1060 struct rte_eth_udp_tunnel *udp_tunnel)
1062 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1063 uint16_t tunnel_type = 0;
1067 switch (udp_tunnel->prot_type) {
1068 case RTE_TUNNEL_TYPE_VXLAN:
1069 if (!bp->vxlan_port_cnt) {
1070 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1073 if (bp->vxlan_port != udp_tunnel->udp_port) {
1074 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1075 udp_tunnel->udp_port, bp->vxlan_port);
1078 if (--bp->vxlan_port_cnt)
1082 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1083 port = bp->vxlan_fw_dst_port_id;
1085 case RTE_TUNNEL_TYPE_GENEVE:
1086 if (!bp->geneve_port_cnt) {
1087 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1090 if (bp->geneve_port != udp_tunnel->udp_port) {
1091 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1092 udp_tunnel->udp_port, bp->geneve_port);
1095 if (--bp->geneve_port_cnt)
1099 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1100 port = bp->geneve_fw_dst_port_id;
1103 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1107 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1110 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1113 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1114 bp->geneve_port = 0;
1119 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1121 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1122 struct bnxt_vnic_info *vnic;
1125 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1127 /* Cycle through all VNICs */
1128 for (i = 0; i < bp->nr_vnics; i++) {
1130 * For each VNIC and each associated filter(s)
1131 * if VLAN exists && VLAN matches vlan_id
1132 * remove the MAC+VLAN filter
1133 * add a new MAC only filter
1135 * VLAN filter doesn't exist, just skip and continue
1137 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1138 filter = STAILQ_FIRST(&vnic->filter);
1140 temp_filter = STAILQ_NEXT(filter, next);
1142 if (filter->enables & chk &&
1143 filter->l2_ovlan == vlan_id) {
1144 /* Must delete the filter */
1145 STAILQ_REMOVE(&vnic->filter, filter,
1146 bnxt_filter_info, next);
1147 bnxt_hwrm_clear_filter(bp, filter);
1149 &bp->free_filter_list,
1153 * Need to examine to see if the MAC
1154 * filter already existed or not before
1155 * allocating a new one
1158 new_filter = bnxt_alloc_filter(bp);
1161 "MAC/VLAN filter alloc failed\n");
1165 STAILQ_INSERT_TAIL(&vnic->filter,
1167 /* Inherit MAC from previous filter */
1168 new_filter->mac_index =
1170 memcpy(new_filter->l2_addr,
1171 filter->l2_addr, ETHER_ADDR_LEN);
1172 /* MAC only filter */
1173 rc = bnxt_hwrm_set_filter(bp,
1179 "Del Vlan filter for %d\n",
1182 filter = temp_filter;
1190 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1192 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1193 struct bnxt_vnic_info *vnic;
1196 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1197 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1198 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1200 /* Cycle through all VNICs */
1201 for (i = 0; i < bp->nr_vnics; i++) {
1203 * For each VNIC and each associated filter(s)
1205 * if VLAN matches vlan_id
1206 * VLAN filter already exists, just skip and continue
1208 * add a new MAC+VLAN filter
1210 * Remove the old MAC only filter
1211 * Add a new MAC+VLAN filter
1213 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1214 filter = STAILQ_FIRST(&vnic->filter);
1216 temp_filter = STAILQ_NEXT(filter, next);
1218 if (filter->enables & chk) {
1219 if (filter->l2_ovlan == vlan_id)
1222 /* Must delete the MAC filter */
1223 STAILQ_REMOVE(&vnic->filter, filter,
1224 bnxt_filter_info, next);
1225 bnxt_hwrm_clear_filter(bp, filter);
1226 filter->l2_ovlan = 0;
1228 &bp->free_filter_list,
1231 new_filter = bnxt_alloc_filter(bp);
1234 "MAC/VLAN filter alloc failed\n");
1238 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1240 /* Inherit MAC from the previous filter */
1241 new_filter->mac_index = filter->mac_index;
1242 memcpy(new_filter->l2_addr, filter->l2_addr,
1244 /* MAC + VLAN ID filter */
1245 new_filter->l2_ovlan = vlan_id;
1246 new_filter->l2_ovlan_mask = 0xF000;
1247 new_filter->enables |= en;
1248 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id,
1253 "Added Vlan filter for %d\n", vlan_id);
1255 filter = temp_filter;
1263 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1264 uint16_t vlan_id, int on)
1266 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1268 /* These operations apply to ALL existing MAC/VLAN filters */
1270 return bnxt_add_vlan_filter(bp, vlan_id);
1272 return bnxt_del_vlan_filter(bp, vlan_id);
1276 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1278 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1281 if (mask & ETH_VLAN_FILTER_MASK) {
1282 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1283 /* Remove any VLAN filters programmed */
1284 for (i = 0; i < 4095; i++)
1285 bnxt_del_vlan_filter(bp, i);
1287 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1288 dev->data->dev_conf.rxmode.hw_vlan_filter);
1291 if (mask & ETH_VLAN_STRIP_MASK) {
1292 /* Enable or disable VLAN stripping */
1293 for (i = 0; i < bp->nr_vnics; i++) {
1294 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1295 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1296 vnic->vlan_strip = true;
1298 vnic->vlan_strip = false;
1299 bnxt_hwrm_vnic_cfg(bp, vnic);
1301 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1302 dev->data->dev_conf.rxmode.hw_vlan_strip);
1305 if (mask & ETH_VLAN_EXTEND_MASK)
1306 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1310 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1312 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1313 /* Default Filter is tied to VNIC 0 */
1314 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1315 struct bnxt_filter_info *filter;
1321 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1322 memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1324 STAILQ_FOREACH(filter, &vnic->filter, next) {
1325 /* Default Filter is at Index 0 */
1326 if (filter->mac_index != 0)
1328 rc = bnxt_hwrm_clear_filter(bp, filter);
1331 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1332 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1333 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1335 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1336 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1337 rc = bnxt_hwrm_set_filter(bp, vnic->fw_vnic_id, filter);
1340 filter->mac_index = 0;
1341 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1346 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1347 struct ether_addr *mc_addr_set,
1348 uint32_t nb_mc_addr)
1350 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1351 char *mc_addr_list = (char *)mc_addr_set;
1352 struct bnxt_vnic_info *vnic;
1353 uint32_t off = 0, i = 0;
1355 vnic = &bp->vnic_info[0];
1357 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1358 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1362 /* TODO Check for Duplicate mcast addresses */
1363 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1364 for (i = 0; i < nb_mc_addr; i++) {
1365 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1366 off += ETHER_ADDR_LEN;
1369 vnic->mc_addr_cnt = i;
1372 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
1376 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1378 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1379 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1380 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1381 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1384 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1385 fw_major, fw_minor, fw_updt);
1387 ret += 1; /* add the size of '\0' */
1388 if (fw_size < (uint32_t)ret)
1395 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1396 struct rte_eth_rxq_info *qinfo)
1398 struct bnxt_rx_queue *rxq;
1400 rxq = dev->data->rx_queues[queue_id];
1402 qinfo->mp = rxq->mb_pool;
1403 qinfo->scattered_rx = dev->data->scattered_rx;
1404 qinfo->nb_desc = rxq->nb_rx_desc;
1406 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1407 qinfo->conf.rx_drop_en = 0;
1408 qinfo->conf.rx_deferred_start = 0;
1412 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1413 struct rte_eth_txq_info *qinfo)
1415 struct bnxt_tx_queue *txq;
1417 txq = dev->data->tx_queues[queue_id];
1419 qinfo->nb_desc = txq->nb_tx_desc;
1421 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1422 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1423 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1425 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1426 qinfo->conf.tx_rs_thresh = 0;
1427 qinfo->conf.txq_flags = txq->txq_flags;
1428 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1431 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1433 struct bnxt *bp = eth_dev->data->dev_private;
1434 struct rte_eth_dev_info dev_info;
1435 uint32_t max_dev_mtu;
1439 bnxt_dev_info_get_op(eth_dev, &dev_info);
1440 max_dev_mtu = dev_info.max_rx_pktlen -
1441 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1443 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1444 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1445 ETHER_MIN_MTU, max_dev_mtu);
1450 if (new_mtu > ETHER_MTU) {
1451 bp->flags |= BNXT_FLAG_JUMBO;
1452 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1454 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1455 bp->flags &= ~BNXT_FLAG_JUMBO;
1458 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1459 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1461 eth_dev->data->mtu = new_mtu;
1462 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1464 for (i = 0; i < bp->nr_vnics; i++) {
1465 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1467 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1468 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1469 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1473 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1482 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1484 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1485 uint16_t vlan = bp->vlan;
1488 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1490 "PVID cannot be modified for this function\n");
1493 bp->vlan = on ? pvid : 0;
1495 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1502 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1504 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1506 return bnxt_hwrm_port_led_cfg(bp, true);
1510 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1512 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1514 return bnxt_hwrm_port_led_cfg(bp, false);
1521 static const struct eth_dev_ops bnxt_dev_ops = {
1522 .dev_infos_get = bnxt_dev_info_get_op,
1523 .dev_close = bnxt_dev_close_op,
1524 .dev_configure = bnxt_dev_configure_op,
1525 .dev_start = bnxt_dev_start_op,
1526 .dev_stop = bnxt_dev_stop_op,
1527 .dev_set_link_up = bnxt_dev_set_link_up_op,
1528 .dev_set_link_down = bnxt_dev_set_link_down_op,
1529 .stats_get = bnxt_stats_get_op,
1530 .stats_reset = bnxt_stats_reset_op,
1531 .rx_queue_setup = bnxt_rx_queue_setup_op,
1532 .rx_queue_release = bnxt_rx_queue_release_op,
1533 .tx_queue_setup = bnxt_tx_queue_setup_op,
1534 .tx_queue_release = bnxt_tx_queue_release_op,
1535 .reta_update = bnxt_reta_update_op,
1536 .reta_query = bnxt_reta_query_op,
1537 .rss_hash_update = bnxt_rss_hash_update_op,
1538 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1539 .link_update = bnxt_link_update_op,
1540 .promiscuous_enable = bnxt_promiscuous_enable_op,
1541 .promiscuous_disable = bnxt_promiscuous_disable_op,
1542 .allmulticast_enable = bnxt_allmulticast_enable_op,
1543 .allmulticast_disable = bnxt_allmulticast_disable_op,
1544 .mac_addr_add = bnxt_mac_addr_add_op,
1545 .mac_addr_remove = bnxt_mac_addr_remove_op,
1546 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1547 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1548 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
1549 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
1550 .vlan_filter_set = bnxt_vlan_filter_set_op,
1551 .vlan_offload_set = bnxt_vlan_offload_set_op,
1552 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
1553 .mtu_set = bnxt_mtu_set_op,
1554 .mac_addr_set = bnxt_set_default_mac_addr_op,
1555 .xstats_get = bnxt_dev_xstats_get_op,
1556 .xstats_get_names = bnxt_dev_xstats_get_names_op,
1557 .xstats_reset = bnxt_dev_xstats_reset_op,
1558 .fw_version_get = bnxt_fw_version_get,
1559 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
1560 .rxq_info_get = bnxt_rxq_info_get_op,
1561 .txq_info_get = bnxt_txq_info_get_op,
1562 .dev_led_on = bnxt_dev_led_on_op,
1563 .dev_led_off = bnxt_dev_led_off_op,
1566 static bool bnxt_vf_pciid(uint16_t id)
1568 if (id == BROADCOM_DEV_ID_57304_VF ||
1569 id == BROADCOM_DEV_ID_57406_VF ||
1570 id == BROADCOM_DEV_ID_5731X_VF ||
1571 id == BROADCOM_DEV_ID_5741X_VF ||
1572 id == BROADCOM_DEV_ID_57414_VF)
1577 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1579 struct bnxt *bp = eth_dev->data->dev_private;
1580 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1583 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1584 if (!pci_dev->mem_resource[0].addr) {
1586 "Cannot find PCI device base address, aborting\n");
1588 goto init_err_disable;
1591 bp->eth_dev = eth_dev;
1594 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1596 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1598 goto init_err_release;
1611 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1613 #define ALLOW_FUNC(x) \
1615 typeof(x) arg = (x); \
1616 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
1617 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
1620 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1622 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1623 char mz_name[RTE_MEMZONE_NAMESIZE];
1624 const struct rte_memzone *mz = NULL;
1625 static int version_printed;
1626 uint32_t total_alloc_len;
1627 phys_addr_t mz_phys_addr;
1631 if (version_printed++ == 0)
1632 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
1634 rte_eth_copy_pci_info(eth_dev, pci_dev);
1635 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1637 bp = eth_dev->data->dev_private;
1639 rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
1640 bp->dev_stopped = 1;
1642 if (bnxt_vf_pciid(pci_dev->id.device_id))
1643 bp->flags |= BNXT_FLAG_VF;
1645 rc = bnxt_init_board(eth_dev);
1648 "Board initialization failed rc: %x\n", rc);
1651 eth_dev->dev_ops = &bnxt_dev_ops;
1652 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1653 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1655 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
1656 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1657 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1658 pci_dev->addr.bus, pci_dev->addr.devid,
1659 pci_dev->addr.function, "rx_port_stats");
1660 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1661 mz = rte_memzone_lookup(mz_name);
1662 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1663 sizeof(struct rx_port_stats) + 512);
1665 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1668 RTE_MEMZONE_SIZE_HINT_ONLY);
1672 memset(mz->addr, 0, mz->len);
1673 mz_phys_addr = mz->phys_addr;
1674 if ((unsigned long)mz->addr == mz_phys_addr) {
1675 RTE_LOG(WARNING, PMD,
1676 "Memzone physical address same as virtual.\n");
1677 RTE_LOG(WARNING, PMD,
1678 "Using rte_mem_virt2phy()\n");
1679 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1680 if (mz_phys_addr == 0) {
1682 "unable to map address to physical memory\n");
1687 bp->rx_mem_zone = (const void *)mz;
1688 bp->hw_rx_port_stats = mz->addr;
1689 bp->hw_rx_port_stats_map = mz_phys_addr;
1691 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1692 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1693 pci_dev->addr.bus, pci_dev->addr.devid,
1694 pci_dev->addr.function, "tx_port_stats");
1695 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1696 mz = rte_memzone_lookup(mz_name);
1697 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1698 sizeof(struct tx_port_stats) + 512);
1700 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1703 RTE_MEMZONE_SIZE_HINT_ONLY);
1707 memset(mz->addr, 0, mz->len);
1708 mz_phys_addr = mz->phys_addr;
1709 if ((unsigned long)mz->addr == mz_phys_addr) {
1710 RTE_LOG(WARNING, PMD,
1711 "Memzone physical address same as virtual.\n");
1712 RTE_LOG(WARNING, PMD,
1713 "Using rte_mem_virt2phy()\n");
1714 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1715 if (mz_phys_addr == 0) {
1717 "unable to map address to physical memory\n");
1722 bp->tx_mem_zone = (const void *)mz;
1723 bp->hw_tx_port_stats = mz->addr;
1724 bp->hw_tx_port_stats_map = mz_phys_addr;
1726 bp->flags |= BNXT_FLAG_PORT_STATS;
1729 rc = bnxt_alloc_hwrm_resources(bp);
1732 "hwrm resource allocation failure rc: %x\n", rc);
1735 rc = bnxt_hwrm_ver_get(bp);
1738 bnxt_hwrm_queue_qportcfg(bp);
1740 bnxt_hwrm_func_qcfg(bp);
1742 /* Get the MAX capabilities for this function */
1743 rc = bnxt_hwrm_func_qcaps(bp);
1745 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1748 if (bp->max_tx_rings == 0) {
1749 RTE_LOG(ERR, PMD, "No TX rings available!\n");
1753 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1754 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1755 if (eth_dev->data->mac_addrs == NULL) {
1757 "Failed to alloc %u bytes needed to store MAC addr tbl",
1758 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1762 /* Copy the permanent MAC from the qcap response address now. */
1763 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
1764 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1765 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1766 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1767 if (!bp->grp_info) {
1769 "Failed to alloc %zu bytes needed to store group info table\n",
1770 sizeof(*bp->grp_info) * bp->max_ring_grps);
1775 /* Forward all requests if firmware is new enough */
1776 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
1777 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
1778 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
1779 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
1781 RTE_LOG(WARNING, PMD,
1782 "Firmware too old for VF mailbox functionality\n");
1783 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
1787 * The following are used for driver cleanup. If we disallow these,
1788 * VF drivers can't clean up cleanly.
1790 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
1791 ALLOW_FUNC(HWRM_VNIC_FREE);
1792 ALLOW_FUNC(HWRM_RING_FREE);
1793 ALLOW_FUNC(HWRM_RING_GRP_FREE);
1794 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
1795 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
1796 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
1797 rc = bnxt_hwrm_func_driver_register(bp);
1800 "Failed to register driver");
1806 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1807 pci_dev->mem_resource[0].phys_addr,
1808 pci_dev->mem_resource[0].addr);
1810 rc = bnxt_hwrm_func_reset(bp);
1812 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
1818 //if (bp->pf.active_vfs) {
1819 // TODO: Deallocate VF resources?
1821 if (bp->pdev->max_vfs) {
1822 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
1824 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
1828 rc = bnxt_hwrm_allocate_pf_only(bp);
1831 "Failed to allocate PF resources\n");
1837 bnxt_hwrm_port_led_qcaps(bp);
1839 rc = bnxt_setup_int(bp);
1843 rc = bnxt_alloc_mem(bp);
1845 goto error_free_int;
1847 rc = bnxt_request_int(bp);
1849 goto error_free_int;
1851 rc = bnxt_alloc_def_cp_ring(bp);
1853 goto error_free_int;
1855 bnxt_enable_int(bp);
1860 bnxt_disable_int(bp);
1861 bnxt_free_def_cp_ring(bp);
1862 bnxt_hwrm_func_buf_unrgtr(bp);
1866 bnxt_dev_uninit(eth_dev);
1872 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1873 struct bnxt *bp = eth_dev->data->dev_private;
1876 bnxt_disable_int(bp);
1879 if (eth_dev->data->mac_addrs != NULL) {
1880 rte_free(eth_dev->data->mac_addrs);
1881 eth_dev->data->mac_addrs = NULL;
1883 if (bp->grp_info != NULL) {
1884 rte_free(bp->grp_info);
1885 bp->grp_info = NULL;
1887 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1888 bnxt_free_hwrm_resources(bp);
1889 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1890 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1891 if (bp->dev_stopped == 0)
1892 bnxt_dev_close_op(eth_dev);
1894 rte_free(bp->pf.vf_info);
1895 eth_dev->dev_ops = NULL;
1896 eth_dev->rx_pkt_burst = NULL;
1897 eth_dev->tx_pkt_burst = NULL;
1902 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg)
1904 struct rte_pmd_bnxt_mb_event_param cb_param;
1906 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_PROCEED;
1907 cb_param.vf_id = vf_id;
1910 _rte_eth_dev_callback_process(bp->eth_dev, RTE_ETH_EVENT_VF_MBOX,
1913 /* Default to approve */
1914 if (cb_param.retval == RTE_PMD_BNXT_MB_EVENT_PROCEED)
1915 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_NOOP_ACK;
1917 return cb_param.retval == RTE_PMD_BNXT_MB_EVENT_NOOP_ACK ? true : false;
1920 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1921 struct rte_pci_device *pci_dev)
1923 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1927 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1929 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1932 static struct rte_pci_driver bnxt_rte_pmd = {
1933 .id_table = bnxt_pci_id_map,
1934 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1935 RTE_PCI_DRV_INTR_LSC,
1936 .probe = bnxt_pci_probe,
1937 .remove = bnxt_pci_remove,
1941 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
1943 if (strcmp(dev->data->drv_name, drv->driver.name))
1949 bool is_bnxt_supported(struct rte_eth_dev *dev)
1951 return is_device_supported(dev, &bnxt_rte_pmd);
1954 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1955 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1956 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");