1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_MULTI_SEGS)
156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
157 DEV_RX_OFFLOAD_VLAN_STRIP | \
158 DEV_RX_OFFLOAD_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_UDP_CKSUM | \
160 DEV_RX_OFFLOAD_TCP_CKSUM | \
161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
162 DEV_RX_OFFLOAD_JUMBO_FRAME | \
163 DEV_RX_OFFLOAD_KEEP_CRC | \
164 DEV_RX_OFFLOAD_TCP_LRO)
166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
173 int is_bnxt_in_error(struct bnxt *bp)
175 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
177 if (bp->flags & BNXT_FLAG_FW_RESET)
183 /***********************/
186 * High level utility functions
189 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
191 if (!BNXT_CHIP_THOR(bp))
194 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
195 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
196 BNXT_RSS_ENTRIES_PER_CTX_THOR;
199 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
201 if (!BNXT_CHIP_THOR(bp))
202 return HW_HASH_INDEX_SIZE;
204 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
207 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
209 bnxt_free_filter_mem(bp);
210 bnxt_free_vnic_attributes(bp);
211 bnxt_free_vnic_mem(bp);
213 /* tx/rx rings are configured as part of *_queue_setup callbacks.
214 * If the number of rings change across fw update,
215 * we don't have much choice except to warn the user.
219 bnxt_free_tx_rings(bp);
220 bnxt_free_rx_rings(bp);
222 bnxt_free_async_cp_ring(bp);
225 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
229 rc = bnxt_alloc_ring_grps(bp);
233 rc = bnxt_alloc_async_ring_struct(bp);
237 rc = bnxt_alloc_vnic_mem(bp);
241 rc = bnxt_alloc_vnic_attributes(bp);
245 rc = bnxt_alloc_filter_mem(bp);
249 rc = bnxt_alloc_async_cp_ring(bp);
256 bnxt_free_mem(bp, reconfig);
260 static int bnxt_init_chip(struct bnxt *bp)
262 struct bnxt_rx_queue *rxq;
263 struct rte_eth_link new;
264 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
265 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
266 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
267 uint64_t rx_offloads = dev_conf->rxmode.offloads;
268 uint32_t intr_vector = 0;
269 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
270 uint32_t vec = BNXT_MISC_VEC_ID;
274 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
275 bp->eth_dev->data->dev_conf.rxmode.offloads |=
276 DEV_RX_OFFLOAD_JUMBO_FRAME;
277 bp->flags |= BNXT_FLAG_JUMBO;
279 bp->eth_dev->data->dev_conf.rxmode.offloads &=
280 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
281 bp->flags &= ~BNXT_FLAG_JUMBO;
284 /* THOR does not support ring groups.
285 * But we will use the array to save RSS context IDs.
287 if (BNXT_CHIP_THOR(bp))
288 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
290 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
292 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
296 rc = bnxt_alloc_hwrm_rings(bp);
298 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
302 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
304 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
308 rc = bnxt_mq_rx_configure(bp);
310 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
314 /* VNIC configuration */
315 for (i = 0; i < bp->nr_vnics; i++) {
316 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
317 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
318 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
320 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
321 if (!vnic->fw_grp_ids) {
323 "Failed to alloc %d bytes for group ids\n",
328 memset(vnic->fw_grp_ids, -1, size);
330 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
331 i, vnic, vnic->fw_grp_ids);
333 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
335 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
340 /* Alloc RSS context only if RSS mode is enabled */
341 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
342 int j, nr_ctxs = bnxt_rss_ctxts(bp);
345 for (j = 0; j < nr_ctxs; j++) {
346 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
352 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
356 vnic->num_lb_ctxts = nr_ctxs;
360 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
361 * setting is not available at this time, it will not be
362 * configured correctly in the CFA.
364 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
365 vnic->vlan_strip = true;
367 vnic->vlan_strip = false;
369 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
371 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
376 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
379 "HWRM vnic %d filter failure rc: %x\n",
384 for (j = 0; j < bp->rx_nr_rings; j++) {
385 rxq = bp->eth_dev->data->rx_queues[j];
388 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
389 j, rxq->vnic, rxq->vnic->fw_grp_ids);
391 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
392 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
395 rc = bnxt_vnic_rss_configure(bp, vnic);
398 "HWRM vnic set RSS failure rc: %x\n", rc);
402 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
404 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
405 DEV_RX_OFFLOAD_TCP_LRO)
406 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
408 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
410 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
413 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
417 /* check and configure queue intr-vector mapping */
418 if ((rte_intr_cap_multiple(intr_handle) ||
419 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
420 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
421 intr_vector = bp->eth_dev->data->nb_rx_queues;
422 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
423 if (intr_vector > bp->rx_cp_nr_rings) {
424 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
428 rc = rte_intr_efd_enable(intr_handle, intr_vector);
433 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
434 intr_handle->intr_vec =
435 rte_zmalloc("intr_vec",
436 bp->eth_dev->data->nb_rx_queues *
438 if (intr_handle->intr_vec == NULL) {
439 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
440 " intr_vec", bp->eth_dev->data->nb_rx_queues);
444 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
445 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
446 intr_handle->intr_vec, intr_handle->nb_efd,
447 intr_handle->max_intr);
448 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
450 intr_handle->intr_vec[queue_id] =
451 vec + BNXT_RX_VEC_START;
452 if (vec < base + intr_handle->nb_efd - 1)
457 /* enable uio/vfio intr/eventfd mapping */
458 rc = rte_intr_enable(intr_handle);
462 rc = bnxt_get_hwrm_link_config(bp, &new);
464 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
468 if (!bp->link_info.link_up) {
469 rc = bnxt_set_hwrm_link_config(bp, true);
472 "HWRM link config failure rc: %x\n", rc);
476 bnxt_print_link_info(bp->eth_dev);
481 rte_free(intr_handle->intr_vec);
483 rte_intr_efd_disable(intr_handle);
485 /* Some of the error status returned by FW may not be from errno.h */
492 static int bnxt_shutdown_nic(struct bnxt *bp)
494 bnxt_free_all_hwrm_resources(bp);
495 bnxt_free_all_filters(bp);
496 bnxt_free_all_vnics(bp);
500 static int bnxt_init_nic(struct bnxt *bp)
504 if (BNXT_HAS_RING_GRPS(bp)) {
505 rc = bnxt_init_ring_grps(bp);
511 bnxt_init_filters(bp);
517 * Device configuration and status function
520 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
521 struct rte_eth_dev_info *dev_info)
523 struct bnxt *bp = eth_dev->data->dev_private;
524 uint16_t max_vnics, i, j, vpool, vrxq;
525 unsigned int max_rx_rings;
528 rc = is_bnxt_in_error(bp);
533 dev_info->max_mac_addrs = bp->max_l2_ctx;
534 dev_info->max_hash_mac_addrs = 0;
536 /* PF/VF specifics */
538 dev_info->max_vfs = bp->pdev->max_vfs;
539 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
540 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
541 dev_info->max_rx_queues = max_rx_rings;
542 dev_info->max_tx_queues = max_rx_rings;
543 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
544 dev_info->hash_key_size = 40;
545 max_vnics = bp->max_vnics;
547 /* Fast path specifics */
548 dev_info->min_rx_bufsize = 1;
549 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
550 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
552 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
553 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
554 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
555 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
556 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
559 dev_info->default_rxconf = (struct rte_eth_rxconf) {
565 .rx_free_thresh = 32,
566 /* If no descriptors available, pkts are dropped by default */
570 dev_info->default_txconf = (struct rte_eth_txconf) {
576 .tx_free_thresh = 32,
579 eth_dev->data->dev_conf.intr_conf.lsc = 1;
581 eth_dev->data->dev_conf.intr_conf.rxq = 1;
582 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
583 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
584 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
585 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
590 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
591 * need further investigation.
595 vpool = 64; /* ETH_64_POOLS */
596 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
597 for (i = 0; i < 4; vpool >>= 1, i++) {
598 if (max_vnics > vpool) {
599 for (j = 0; j < 5; vrxq >>= 1, j++) {
600 if (dev_info->max_rx_queues > vrxq) {
606 /* Not enough resources to support VMDq */
610 /* Not enough resources to support VMDq */
614 dev_info->max_vmdq_pools = vpool;
615 dev_info->vmdq_queue_num = vrxq;
617 dev_info->vmdq_pool_base = 0;
618 dev_info->vmdq_queue_base = 0;
623 /* Configure the device based on the configuration provided */
624 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
626 struct bnxt *bp = eth_dev->data->dev_private;
627 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
630 bp->rx_queues = (void *)eth_dev->data->rx_queues;
631 bp->tx_queues = (void *)eth_dev->data->tx_queues;
632 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
633 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
635 rc = is_bnxt_in_error(bp);
639 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
640 rc = bnxt_hwrm_check_vf_rings(bp);
642 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
646 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
648 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
652 /* legacy driver needs to get updated values */
653 rc = bnxt_hwrm_func_qcaps(bp);
655 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
660 /* Inherit new configurations */
661 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
662 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
663 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
664 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
665 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
669 if (BNXT_HAS_RING_GRPS(bp) &&
670 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
673 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
674 bp->max_vnics < eth_dev->data->nb_rx_queues)
677 bp->rx_cp_nr_rings = bp->rx_nr_rings;
678 bp->tx_cp_nr_rings = bp->tx_nr_rings;
680 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
682 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
683 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
685 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
691 "Insufficient resources to support requested config\n");
693 "Num Queues Requested: Tx %d, Rx %d\n",
694 eth_dev->data->nb_tx_queues,
695 eth_dev->data->nb_rx_queues);
697 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
698 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
699 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
703 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
705 struct rte_eth_link *link = ð_dev->data->dev_link;
707 if (link->link_status)
708 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
709 eth_dev->data->port_id,
710 (uint32_t)link->link_speed,
711 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
712 ("full-duplex") : ("half-duplex\n"));
714 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
715 eth_dev->data->port_id);
719 * Determine whether the current configuration requires support for scattered
720 * receive; return 1 if scattered receive is required and 0 if not.
722 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
727 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
728 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
730 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
731 RTE_PKTMBUF_HEADROOM);
732 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
738 static eth_rx_burst_t
739 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
743 * Vector mode receive can be enabled only if scatter rx is not
744 * in use and rx offloads are limited to VLAN stripping and
747 if (!eth_dev->data->scattered_rx &&
748 !(eth_dev->data->dev_conf.rxmode.offloads &
749 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
750 DEV_RX_OFFLOAD_KEEP_CRC |
751 DEV_RX_OFFLOAD_JUMBO_FRAME |
752 DEV_RX_OFFLOAD_IPV4_CKSUM |
753 DEV_RX_OFFLOAD_UDP_CKSUM |
754 DEV_RX_OFFLOAD_TCP_CKSUM |
755 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
756 DEV_RX_OFFLOAD_VLAN_FILTER))) {
757 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
758 eth_dev->data->port_id);
759 return bnxt_recv_pkts_vec;
761 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
762 eth_dev->data->port_id);
764 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
765 eth_dev->data->port_id,
766 eth_dev->data->scattered_rx,
767 eth_dev->data->dev_conf.rxmode.offloads);
769 return bnxt_recv_pkts;
772 static eth_tx_burst_t
773 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
777 * Vector mode transmit can be enabled only if not using scatter rx
780 if (!eth_dev->data->scattered_rx &&
781 !eth_dev->data->dev_conf.txmode.offloads) {
782 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
783 eth_dev->data->port_id);
784 return bnxt_xmit_pkts_vec;
786 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
787 eth_dev->data->port_id);
789 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
790 eth_dev->data->port_id,
791 eth_dev->data->scattered_rx,
792 eth_dev->data->dev_conf.txmode.offloads);
794 return bnxt_xmit_pkts;
797 static int bnxt_handle_if_change_status(struct bnxt *bp)
801 /* Since fw has undergone a reset and lost all contexts,
802 * set fatal flag to not issue hwrm during cleanup
804 bp->flags |= BNXT_FLAG_FATAL_ERROR;
805 bnxt_uninit_resources(bp, true);
807 /* clear fatal flag so that re-init happens */
808 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
809 rc = bnxt_init_resources(bp, true);
811 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
816 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
818 struct bnxt *bp = eth_dev->data->dev_private;
819 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
823 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
825 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
826 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
829 rc = bnxt_hwrm_if_change(bp, 1);
831 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
832 rc = bnxt_handle_if_change_status(bp);
838 rc = bnxt_init_chip(bp);
842 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
844 bnxt_link_update_op(eth_dev, 1);
846 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
847 vlan_mask |= ETH_VLAN_FILTER_MASK;
848 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
849 vlan_mask |= ETH_VLAN_STRIP_MASK;
850 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
854 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
855 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
858 bp->flags |= BNXT_FLAG_INIT_DONE;
859 eth_dev->data->dev_started = 1;
864 bnxt_hwrm_if_change(bp, 0);
865 bnxt_shutdown_nic(bp);
866 bnxt_free_tx_mbufs(bp);
867 bnxt_free_rx_mbufs(bp);
871 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
873 struct bnxt *bp = eth_dev->data->dev_private;
876 if (!bp->link_info.link_up)
877 rc = bnxt_set_hwrm_link_config(bp, true);
879 eth_dev->data->dev_link.link_status = 1;
881 bnxt_print_link_info(eth_dev);
885 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
887 struct bnxt *bp = eth_dev->data->dev_private;
889 eth_dev->data->dev_link.link_status = 0;
890 bnxt_set_hwrm_link_config(bp, false);
891 bp->link_info.link_up = 0;
896 /* Unload the driver, release resources */
897 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
899 struct bnxt *bp = eth_dev->data->dev_private;
900 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
901 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
903 eth_dev->data->dev_started = 0;
904 /* Prevent crashes when queues are still in use */
905 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
906 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
908 bnxt_disable_int(bp);
910 /* disable uio/vfio intr/eventfd mapping */
911 rte_intr_disable(intr_handle);
913 bp->flags &= ~BNXT_FLAG_INIT_DONE;
914 if (bp->eth_dev->data->dev_started) {
915 /* TBD: STOP HW queues DMA */
916 eth_dev->data->dev_link.link_status = 0;
918 bnxt_set_hwrm_link_config(bp, false);
920 /* Clean queue intr-vector mapping */
921 rte_intr_efd_disable(intr_handle);
922 if (intr_handle->intr_vec != NULL) {
923 rte_free(intr_handle->intr_vec);
924 intr_handle->intr_vec = NULL;
927 bnxt_hwrm_port_clr_stats(bp);
928 bnxt_free_tx_mbufs(bp);
929 bnxt_free_rx_mbufs(bp);
930 bnxt_shutdown_nic(bp);
931 bnxt_hwrm_if_change(bp, 0);
935 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
937 struct bnxt *bp = eth_dev->data->dev_private;
939 if (bp->dev_stopped == 0)
940 bnxt_dev_stop_op(eth_dev);
942 if (eth_dev->data->mac_addrs != NULL) {
943 rte_free(eth_dev->data->mac_addrs);
944 eth_dev->data->mac_addrs = NULL;
946 if (bp->grp_info != NULL) {
947 rte_free(bp->grp_info);
951 bnxt_dev_uninit(eth_dev);
954 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
957 struct bnxt *bp = eth_dev->data->dev_private;
958 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
959 struct bnxt_vnic_info *vnic;
960 struct bnxt_filter_info *filter, *temp_filter;
963 if (is_bnxt_in_error(bp))
967 * Loop through all VNICs from the specified filter flow pools to
968 * remove the corresponding MAC addr filter
970 for (i = 0; i < bp->nr_vnics; i++) {
971 if (!(pool_mask & (1ULL << i)))
974 vnic = &bp->vnic_info[i];
975 filter = STAILQ_FIRST(&vnic->filter);
977 temp_filter = STAILQ_NEXT(filter, next);
978 if (filter->mac_index == index) {
979 STAILQ_REMOVE(&vnic->filter, filter,
980 bnxt_filter_info, next);
981 bnxt_hwrm_clear_l2_filter(bp, filter);
982 filter->mac_index = INVALID_MAC_INDEX;
983 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
984 STAILQ_INSERT_TAIL(&bp->free_filter_list,
987 filter = temp_filter;
992 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
993 struct rte_ether_addr *mac_addr,
994 uint32_t index, uint32_t pool)
996 struct bnxt *bp = eth_dev->data->dev_private;
997 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
998 struct bnxt_filter_info *filter;
1001 rc = is_bnxt_in_error(bp);
1005 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1006 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1011 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1014 /* Attach requested MAC address to the new l2_filter */
1015 STAILQ_FOREACH(filter, &vnic->filter, next) {
1016 if (filter->mac_index == index) {
1018 "MAC addr already existed for pool %d\n", pool);
1022 filter = bnxt_alloc_filter(bp);
1024 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1028 filter->mac_index = index;
1029 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1031 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1033 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1035 filter->mac_index = INVALID_MAC_INDEX;
1036 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1037 bnxt_free_filter(bp, filter);
1043 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1046 struct bnxt *bp = eth_dev->data->dev_private;
1047 struct rte_eth_link new;
1048 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1050 rc = is_bnxt_in_error(bp);
1054 memset(&new, 0, sizeof(new));
1056 /* Retrieve link info from hardware */
1057 rc = bnxt_get_hwrm_link_config(bp, &new);
1059 new.link_speed = ETH_LINK_SPEED_100M;
1060 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1062 "Failed to retrieve link rc = 0x%x!\n", rc);
1066 if (!wait_to_complete || new.link_status)
1069 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1073 /* Timed out or success */
1074 if (new.link_status != eth_dev->data->dev_link.link_status ||
1075 new.link_speed != eth_dev->data->dev_link.link_speed) {
1076 memcpy(ð_dev->data->dev_link, &new,
1077 sizeof(struct rte_eth_link));
1079 _rte_eth_dev_callback_process(eth_dev,
1080 RTE_ETH_EVENT_INTR_LSC,
1083 bnxt_print_link_info(eth_dev);
1089 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1091 struct bnxt *bp = eth_dev->data->dev_private;
1092 struct bnxt_vnic_info *vnic;
1096 rc = is_bnxt_in_error(bp);
1100 if (bp->vnic_info == NULL)
1103 vnic = &bp->vnic_info[0];
1105 old_flags = vnic->flags;
1106 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1107 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1109 vnic->flags = old_flags;
1114 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1116 struct bnxt *bp = eth_dev->data->dev_private;
1117 struct bnxt_vnic_info *vnic;
1121 rc = is_bnxt_in_error(bp);
1125 if (bp->vnic_info == NULL)
1128 vnic = &bp->vnic_info[0];
1130 old_flags = vnic->flags;
1131 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1132 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1134 vnic->flags = old_flags;
1139 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1141 struct bnxt *bp = eth_dev->data->dev_private;
1142 struct bnxt_vnic_info *vnic;
1146 rc = is_bnxt_in_error(bp);
1150 if (bp->vnic_info == NULL)
1153 vnic = &bp->vnic_info[0];
1155 old_flags = vnic->flags;
1156 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1157 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1159 vnic->flags = old_flags;
1164 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1166 struct bnxt *bp = eth_dev->data->dev_private;
1167 struct bnxt_vnic_info *vnic;
1171 rc = is_bnxt_in_error(bp);
1175 if (bp->vnic_info == NULL)
1178 vnic = &bp->vnic_info[0];
1180 old_flags = vnic->flags;
1181 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1182 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1184 vnic->flags = old_flags;
1189 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1190 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1192 if (qid >= bp->rx_nr_rings)
1195 return bp->eth_dev->data->rx_queues[qid];
1198 /* Return rxq corresponding to a given rss table ring/group ID. */
1199 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1201 struct bnxt_rx_queue *rxq;
1204 if (!BNXT_HAS_RING_GRPS(bp)) {
1205 for (i = 0; i < bp->rx_nr_rings; i++) {
1206 rxq = bp->eth_dev->data->rx_queues[i];
1207 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1211 for (i = 0; i < bp->rx_nr_rings; i++) {
1212 if (bp->grp_info[i].fw_grp_id == fwr)
1217 return INVALID_HW_RING_ID;
1220 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1221 struct rte_eth_rss_reta_entry64 *reta_conf,
1224 struct bnxt *bp = eth_dev->data->dev_private;
1225 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1226 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1227 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1231 rc = is_bnxt_in_error(bp);
1235 if (!vnic->rss_table)
1238 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1241 if (reta_size != tbl_size) {
1242 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1243 "(%d) must equal the size supported by the hardware "
1244 "(%d)\n", reta_size, tbl_size);
1248 for (i = 0; i < reta_size; i++) {
1249 struct bnxt_rx_queue *rxq;
1251 idx = i / RTE_RETA_GROUP_SIZE;
1252 sft = i % RTE_RETA_GROUP_SIZE;
1254 if (!(reta_conf[idx].mask & (1ULL << sft)))
1257 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1259 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1263 if (BNXT_CHIP_THOR(bp)) {
1264 vnic->rss_table[i * 2] =
1265 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1266 vnic->rss_table[i * 2 + 1] =
1267 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1269 vnic->rss_table[i] =
1270 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1273 vnic->rss_table[i] =
1274 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1277 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1281 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1282 struct rte_eth_rss_reta_entry64 *reta_conf,
1285 struct bnxt *bp = eth_dev->data->dev_private;
1286 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1287 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1288 uint16_t idx, sft, i;
1291 rc = is_bnxt_in_error(bp);
1295 /* Retrieve from the default VNIC */
1298 if (!vnic->rss_table)
1301 if (reta_size != tbl_size) {
1302 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1303 "(%d) must equal the size supported by the hardware "
1304 "(%d)\n", reta_size, tbl_size);
1308 for (idx = 0, i = 0; i < reta_size; i++) {
1309 idx = i / RTE_RETA_GROUP_SIZE;
1310 sft = i % RTE_RETA_GROUP_SIZE;
1312 if (reta_conf[idx].mask & (1ULL << sft)) {
1315 if (BNXT_CHIP_THOR(bp))
1316 qid = bnxt_rss_to_qid(bp,
1317 vnic->rss_table[i * 2]);
1319 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1321 if (qid == INVALID_HW_RING_ID) {
1322 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1325 reta_conf[idx].reta[sft] = qid;
1332 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1333 struct rte_eth_rss_conf *rss_conf)
1335 struct bnxt *bp = eth_dev->data->dev_private;
1336 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1337 struct bnxt_vnic_info *vnic;
1338 uint16_t hash_type = 0;
1342 rc = is_bnxt_in_error(bp);
1347 * If RSS enablement were different than dev_configure,
1348 * then return -EINVAL
1350 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1351 if (!rss_conf->rss_hf)
1352 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1354 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1358 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1359 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1361 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1362 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1363 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1364 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1365 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1366 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1367 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1368 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1369 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1370 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1371 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1372 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1374 /* Update the RSS VNIC(s) */
1375 for (i = 0; i < bp->nr_vnics; i++) {
1376 vnic = &bp->vnic_info[i];
1377 vnic->hash_type = hash_type;
1380 * Use the supplied key if the key length is
1381 * acceptable and the rss_key is not NULL
1383 if (rss_conf->rss_key &&
1384 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1385 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1386 rss_conf->rss_key_len);
1388 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1393 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1394 struct rte_eth_rss_conf *rss_conf)
1396 struct bnxt *bp = eth_dev->data->dev_private;
1397 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1399 uint32_t hash_types;
1401 rc = is_bnxt_in_error(bp);
1405 /* RSS configuration is the same for all VNICs */
1406 if (vnic && vnic->rss_hash_key) {
1407 if (rss_conf->rss_key) {
1408 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1409 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1410 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1413 hash_types = vnic->hash_type;
1414 rss_conf->rss_hf = 0;
1415 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1416 rss_conf->rss_hf |= ETH_RSS_IPV4;
1417 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1419 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1420 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1422 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1424 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1425 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1427 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1429 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1430 rss_conf->rss_hf |= ETH_RSS_IPV6;
1431 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1433 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1434 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1436 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1438 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1439 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1441 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1445 "Unknwon RSS config from firmware (%08x), RSS disabled",
1450 rss_conf->rss_hf = 0;
1455 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1456 struct rte_eth_fc_conf *fc_conf)
1458 struct bnxt *bp = dev->data->dev_private;
1459 struct rte_eth_link link_info;
1462 rc = is_bnxt_in_error(bp);
1466 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1470 memset(fc_conf, 0, sizeof(*fc_conf));
1471 if (bp->link_info.auto_pause)
1472 fc_conf->autoneg = 1;
1473 switch (bp->link_info.pause) {
1475 fc_conf->mode = RTE_FC_NONE;
1477 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1478 fc_conf->mode = RTE_FC_TX_PAUSE;
1480 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1481 fc_conf->mode = RTE_FC_RX_PAUSE;
1483 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1484 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1485 fc_conf->mode = RTE_FC_FULL;
1491 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1492 struct rte_eth_fc_conf *fc_conf)
1494 struct bnxt *bp = dev->data->dev_private;
1497 rc = is_bnxt_in_error(bp);
1501 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1502 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1506 switch (fc_conf->mode) {
1508 bp->link_info.auto_pause = 0;
1509 bp->link_info.force_pause = 0;
1511 case RTE_FC_RX_PAUSE:
1512 if (fc_conf->autoneg) {
1513 bp->link_info.auto_pause =
1514 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1515 bp->link_info.force_pause = 0;
1517 bp->link_info.auto_pause = 0;
1518 bp->link_info.force_pause =
1519 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1522 case RTE_FC_TX_PAUSE:
1523 if (fc_conf->autoneg) {
1524 bp->link_info.auto_pause =
1525 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1526 bp->link_info.force_pause = 0;
1528 bp->link_info.auto_pause = 0;
1529 bp->link_info.force_pause =
1530 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1534 if (fc_conf->autoneg) {
1535 bp->link_info.auto_pause =
1536 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1537 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1538 bp->link_info.force_pause = 0;
1540 bp->link_info.auto_pause = 0;
1541 bp->link_info.force_pause =
1542 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1543 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1547 return bnxt_set_hwrm_link_config(bp, true);
1550 /* Add UDP tunneling port */
1552 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1553 struct rte_eth_udp_tunnel *udp_tunnel)
1555 struct bnxt *bp = eth_dev->data->dev_private;
1556 uint16_t tunnel_type = 0;
1559 rc = is_bnxt_in_error(bp);
1563 switch (udp_tunnel->prot_type) {
1564 case RTE_TUNNEL_TYPE_VXLAN:
1565 if (bp->vxlan_port_cnt) {
1566 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1567 udp_tunnel->udp_port);
1568 if (bp->vxlan_port != udp_tunnel->udp_port) {
1569 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1572 bp->vxlan_port_cnt++;
1576 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1577 bp->vxlan_port_cnt++;
1579 case RTE_TUNNEL_TYPE_GENEVE:
1580 if (bp->geneve_port_cnt) {
1581 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1582 udp_tunnel->udp_port);
1583 if (bp->geneve_port != udp_tunnel->udp_port) {
1584 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1587 bp->geneve_port_cnt++;
1591 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1592 bp->geneve_port_cnt++;
1595 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1598 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1604 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1605 struct rte_eth_udp_tunnel *udp_tunnel)
1607 struct bnxt *bp = eth_dev->data->dev_private;
1608 uint16_t tunnel_type = 0;
1612 rc = is_bnxt_in_error(bp);
1616 switch (udp_tunnel->prot_type) {
1617 case RTE_TUNNEL_TYPE_VXLAN:
1618 if (!bp->vxlan_port_cnt) {
1619 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1622 if (bp->vxlan_port != udp_tunnel->udp_port) {
1623 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1624 udp_tunnel->udp_port, bp->vxlan_port);
1627 if (--bp->vxlan_port_cnt)
1631 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1632 port = bp->vxlan_fw_dst_port_id;
1634 case RTE_TUNNEL_TYPE_GENEVE:
1635 if (!bp->geneve_port_cnt) {
1636 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1639 if (bp->geneve_port != udp_tunnel->udp_port) {
1640 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1641 udp_tunnel->udp_port, bp->geneve_port);
1644 if (--bp->geneve_port_cnt)
1648 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1649 port = bp->geneve_fw_dst_port_id;
1652 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1656 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1659 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1662 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1663 bp->geneve_port = 0;
1668 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1670 struct bnxt_filter_info *filter;
1671 struct bnxt_vnic_info *vnic;
1673 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1675 /* if VLAN exists && VLAN matches vlan_id
1676 * remove the MAC+VLAN filter
1677 * add a new MAC only filter
1679 * VLAN filter doesn't exist, just skip and continue
1681 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1682 filter = STAILQ_FIRST(&vnic->filter);
1684 /* Search for this matching MAC+VLAN filter */
1685 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1686 !memcmp(filter->l2_addr,
1688 RTE_ETHER_ADDR_LEN)) {
1689 /* Delete the filter */
1690 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1693 STAILQ_REMOVE(&vnic->filter, filter,
1694 bnxt_filter_info, next);
1695 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1698 "Del Vlan filter for %d\n",
1702 filter = STAILQ_NEXT(filter, next);
1707 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1709 struct bnxt_filter_info *filter;
1710 struct bnxt_vnic_info *vnic;
1712 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1713 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1714 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1716 /* Implementation notes on the use of VNIC in this command:
1718 * By default, these filters belong to default vnic for the function.
1719 * Once these filters are set up, only destination VNIC can be modified.
1720 * If the destination VNIC is not specified in this command,
1721 * then the HWRM shall only create an l2 context id.
1724 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1725 filter = STAILQ_FIRST(&vnic->filter);
1726 /* Check if the VLAN has already been added */
1728 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1729 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1732 filter = STAILQ_NEXT(filter, next);
1735 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1736 * command to create MAC+VLAN filter with the right flags, enables set.
1738 filter = bnxt_alloc_filter(bp);
1741 "MAC/VLAN filter alloc failed\n");
1744 /* MAC + VLAN ID filter */
1745 filter->l2_ivlan = vlan_id;
1746 filter->l2_ivlan_mask = 0x0FFF;
1747 filter->enables |= en;
1748 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1750 /* Free the newly allocated filter as we were
1751 * not able to create the filter in hardware.
1753 filter->fw_l2_filter_id = UINT64_MAX;
1754 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1758 /* Add this new filter to the list */
1759 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1761 "Added Vlan filter for %d\n", vlan_id);
1765 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1766 uint16_t vlan_id, int on)
1768 struct bnxt *bp = eth_dev->data->dev_private;
1771 rc = is_bnxt_in_error(bp);
1775 /* These operations apply to ALL existing MAC/VLAN filters */
1777 return bnxt_add_vlan_filter(bp, vlan_id);
1779 return bnxt_del_vlan_filter(bp, vlan_id);
1783 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1785 struct bnxt *bp = dev->data->dev_private;
1786 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1790 rc = is_bnxt_in_error(bp);
1794 if (mask & ETH_VLAN_FILTER_MASK) {
1795 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1796 /* Remove any VLAN filters programmed */
1797 for (i = 0; i < 4095; i++)
1798 bnxt_del_vlan_filter(bp, i);
1800 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1801 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1804 if (mask & ETH_VLAN_STRIP_MASK) {
1805 /* Enable or disable VLAN stripping */
1806 for (i = 0; i < bp->nr_vnics; i++) {
1807 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1808 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1809 vnic->vlan_strip = true;
1811 vnic->vlan_strip = false;
1812 bnxt_hwrm_vnic_cfg(bp, vnic);
1814 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1815 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1818 if (mask & ETH_VLAN_EXTEND_MASK)
1819 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1825 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1826 struct rte_ether_addr *addr)
1828 struct bnxt *bp = dev->data->dev_private;
1829 /* Default Filter is tied to VNIC 0 */
1830 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1831 struct bnxt_filter_info *filter;
1834 rc = is_bnxt_in_error(bp);
1838 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1841 if (rte_is_zero_ether_addr(addr))
1844 STAILQ_FOREACH(filter, &vnic->filter, next) {
1845 /* Default Filter is at Index 0 */
1846 if (filter->mac_index != 0)
1849 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1850 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1851 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1853 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1854 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1856 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1860 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1861 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1869 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1870 struct rte_ether_addr *mc_addr_set,
1871 uint32_t nb_mc_addr)
1873 struct bnxt *bp = eth_dev->data->dev_private;
1874 char *mc_addr_list = (char *)mc_addr_set;
1875 struct bnxt_vnic_info *vnic;
1876 uint32_t off = 0, i = 0;
1879 rc = is_bnxt_in_error(bp);
1883 vnic = &bp->vnic_info[0];
1885 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1886 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1890 /* TODO Check for Duplicate mcast addresses */
1891 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1892 for (i = 0; i < nb_mc_addr; i++) {
1893 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1894 RTE_ETHER_ADDR_LEN);
1895 off += RTE_ETHER_ADDR_LEN;
1898 vnic->mc_addr_cnt = i;
1901 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1905 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1907 struct bnxt *bp = dev->data->dev_private;
1908 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1909 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1910 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1913 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1914 fw_major, fw_minor, fw_updt);
1916 ret += 1; /* add the size of '\0' */
1917 if (fw_size < (uint32_t)ret)
1924 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1925 struct rte_eth_rxq_info *qinfo)
1927 struct bnxt_rx_queue *rxq;
1929 rxq = dev->data->rx_queues[queue_id];
1931 qinfo->mp = rxq->mb_pool;
1932 qinfo->scattered_rx = dev->data->scattered_rx;
1933 qinfo->nb_desc = rxq->nb_rx_desc;
1935 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1936 qinfo->conf.rx_drop_en = 0;
1937 qinfo->conf.rx_deferred_start = 0;
1941 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1942 struct rte_eth_txq_info *qinfo)
1944 struct bnxt_tx_queue *txq;
1946 txq = dev->data->tx_queues[queue_id];
1948 qinfo->nb_desc = txq->nb_tx_desc;
1950 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1951 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1952 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1954 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1955 qinfo->conf.tx_rs_thresh = 0;
1956 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1959 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1961 struct bnxt *bp = eth_dev->data->dev_private;
1962 struct rte_eth_dev_info dev_info;
1963 uint32_t new_pkt_size;
1967 rc = is_bnxt_in_error(bp);
1971 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1972 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1974 rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1976 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1980 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1981 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1982 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1988 * If vector-mode tx/rx is active, disallow any MTU change that would
1989 * require scattered receive support.
1991 if (eth_dev->data->dev_started &&
1992 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1993 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1995 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1997 "MTU change would require scattered rx support. ");
1998 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2003 if (new_mtu > RTE_ETHER_MTU) {
2004 bp->flags |= BNXT_FLAG_JUMBO;
2005 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2006 DEV_RX_OFFLOAD_JUMBO_FRAME;
2008 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2009 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2010 bp->flags &= ~BNXT_FLAG_JUMBO;
2013 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2015 eth_dev->data->mtu = new_mtu;
2016 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
2018 for (i = 0; i < bp->nr_vnics; i++) {
2019 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2022 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2023 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2024 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2028 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2029 size -= RTE_PKTMBUF_HEADROOM;
2031 if (size < new_mtu) {
2032 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2042 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2044 struct bnxt *bp = dev->data->dev_private;
2045 uint16_t vlan = bp->vlan;
2048 rc = is_bnxt_in_error(bp);
2052 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2054 "PVID cannot be modified for this function\n");
2057 bp->vlan = on ? pvid : 0;
2059 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2066 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2068 struct bnxt *bp = dev->data->dev_private;
2071 rc = is_bnxt_in_error(bp);
2075 return bnxt_hwrm_port_led_cfg(bp, true);
2079 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2081 struct bnxt *bp = dev->data->dev_private;
2084 rc = is_bnxt_in_error(bp);
2088 return bnxt_hwrm_port_led_cfg(bp, false);
2092 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2094 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2095 uint32_t desc = 0, raw_cons = 0, cons;
2096 struct bnxt_cp_ring_info *cpr;
2097 struct bnxt_rx_queue *rxq;
2098 struct rx_pkt_cmpl *rxcmp;
2104 rc = is_bnxt_in_error(bp);
2108 rxq = dev->data->rx_queues[rx_queue_id];
2112 while (raw_cons < rxq->nb_rx_desc) {
2113 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2114 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2116 if (!CMPL_VALID(rxcmp, valid))
2118 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2119 cmp_type = CMP_TYPE(rxcmp);
2120 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2121 cmp = (rte_le_to_cpu_32(
2122 ((struct rx_tpa_end_cmpl *)
2123 (rxcmp))->agg_bufs_v1) &
2124 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2125 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2127 } else if (cmp_type == 0x11) {
2129 cmp = (rxcmp->agg_bufs_v1 &
2130 RX_PKT_CMPL_AGG_BUFS_MASK) >>
2131 RX_PKT_CMPL_AGG_BUFS_SFT;
2136 raw_cons += cmp ? cmp : 2;
2143 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2145 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2146 struct bnxt_rx_ring_info *rxr;
2147 struct bnxt_cp_ring_info *cpr;
2148 struct bnxt_sw_rx_bd *rx_buf;
2149 struct rx_pkt_cmpl *rxcmp;
2150 uint32_t cons, cp_cons;
2156 rc = is_bnxt_in_error(rxq->bp);
2163 if (offset >= rxq->nb_rx_desc)
2166 cons = RING_CMP(cpr->cp_ring_struct, offset);
2167 cp_cons = cpr->cp_raw_cons;
2168 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2170 if (cons > cp_cons) {
2171 if (CMPL_VALID(rxcmp, cpr->valid))
2172 return RTE_ETH_RX_DESC_DONE;
2174 if (CMPL_VALID(rxcmp, !cpr->valid))
2175 return RTE_ETH_RX_DESC_DONE;
2177 rx_buf = &rxr->rx_buf_ring[cons];
2178 if (rx_buf->mbuf == NULL)
2179 return RTE_ETH_RX_DESC_UNAVAIL;
2182 return RTE_ETH_RX_DESC_AVAIL;
2186 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2188 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2189 struct bnxt_tx_ring_info *txr;
2190 struct bnxt_cp_ring_info *cpr;
2191 struct bnxt_sw_tx_bd *tx_buf;
2192 struct tx_pkt_cmpl *txcmp;
2193 uint32_t cons, cp_cons;
2199 rc = is_bnxt_in_error(txq->bp);
2206 if (offset >= txq->nb_tx_desc)
2209 cons = RING_CMP(cpr->cp_ring_struct, offset);
2210 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2211 cp_cons = cpr->cp_raw_cons;
2213 if (cons > cp_cons) {
2214 if (CMPL_VALID(txcmp, cpr->valid))
2215 return RTE_ETH_TX_DESC_UNAVAIL;
2217 if (CMPL_VALID(txcmp, !cpr->valid))
2218 return RTE_ETH_TX_DESC_UNAVAIL;
2220 tx_buf = &txr->tx_buf_ring[cons];
2221 if (tx_buf->mbuf == NULL)
2222 return RTE_ETH_TX_DESC_DONE;
2224 return RTE_ETH_TX_DESC_FULL;
2227 static struct bnxt_filter_info *
2228 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2229 struct rte_eth_ethertype_filter *efilter,
2230 struct bnxt_vnic_info *vnic0,
2231 struct bnxt_vnic_info *vnic,
2234 struct bnxt_filter_info *mfilter = NULL;
2238 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2239 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2240 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2241 " ethertype filter.", efilter->ether_type);
2245 if (efilter->queue >= bp->rx_nr_rings) {
2246 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2251 vnic0 = &bp->vnic_info[0];
2252 vnic = &bp->vnic_info[efilter->queue];
2254 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2259 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2260 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2261 if ((!memcmp(efilter->mac_addr.addr_bytes,
2262 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2264 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2265 mfilter->ethertype == efilter->ether_type)) {
2271 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2272 if ((!memcmp(efilter->mac_addr.addr_bytes,
2273 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2274 mfilter->ethertype == efilter->ether_type &&
2276 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2290 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2291 enum rte_filter_op filter_op,
2294 struct bnxt *bp = dev->data->dev_private;
2295 struct rte_eth_ethertype_filter *efilter =
2296 (struct rte_eth_ethertype_filter *)arg;
2297 struct bnxt_filter_info *bfilter, *filter1;
2298 struct bnxt_vnic_info *vnic, *vnic0;
2301 if (filter_op == RTE_ETH_FILTER_NOP)
2305 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2310 vnic0 = &bp->vnic_info[0];
2311 vnic = &bp->vnic_info[efilter->queue];
2313 switch (filter_op) {
2314 case RTE_ETH_FILTER_ADD:
2315 bnxt_match_and_validate_ether_filter(bp, efilter,
2320 bfilter = bnxt_get_unused_filter(bp);
2321 if (bfilter == NULL) {
2323 "Not enough resources for a new filter.\n");
2326 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2327 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2328 RTE_ETHER_ADDR_LEN);
2329 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2330 RTE_ETHER_ADDR_LEN);
2331 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2332 bfilter->ethertype = efilter->ether_type;
2333 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2335 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2336 if (filter1 == NULL) {
2341 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2342 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2344 bfilter->dst_id = vnic->fw_vnic_id;
2346 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2348 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2351 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2354 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2356 case RTE_ETH_FILTER_DELETE:
2357 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2359 if (ret == -EEXIST) {
2360 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2362 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2364 bnxt_free_filter(bp, filter1);
2365 } else if (ret == 0) {
2366 PMD_DRV_LOG(ERR, "No matching filter found\n");
2370 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2376 bnxt_free_filter(bp, bfilter);
2382 parse_ntuple_filter(struct bnxt *bp,
2383 struct rte_eth_ntuple_filter *nfilter,
2384 struct bnxt_filter_info *bfilter)
2388 if (nfilter->queue >= bp->rx_nr_rings) {
2389 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2393 switch (nfilter->dst_port_mask) {
2395 bfilter->dst_port_mask = -1;
2396 bfilter->dst_port = nfilter->dst_port;
2397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2398 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2401 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2405 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2406 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2408 switch (nfilter->proto_mask) {
2410 if (nfilter->proto == 17) /* IPPROTO_UDP */
2411 bfilter->ip_protocol = 17;
2412 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2413 bfilter->ip_protocol = 6;
2416 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2419 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2423 switch (nfilter->dst_ip_mask) {
2425 bfilter->dst_ipaddr_mask[0] = -1;
2426 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2428 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2431 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2435 switch (nfilter->src_ip_mask) {
2437 bfilter->src_ipaddr_mask[0] = -1;
2438 bfilter->src_ipaddr[0] = nfilter->src_ip;
2439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2440 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2443 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2447 switch (nfilter->src_port_mask) {
2449 bfilter->src_port_mask = -1;
2450 bfilter->src_port = nfilter->src_port;
2451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2452 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2455 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2460 //nfilter->priority = (uint8_t)filter->priority;
2462 bfilter->enables = en;
2466 static struct bnxt_filter_info*
2467 bnxt_match_ntuple_filter(struct bnxt *bp,
2468 struct bnxt_filter_info *bfilter,
2469 struct bnxt_vnic_info **mvnic)
2471 struct bnxt_filter_info *mfilter = NULL;
2474 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2475 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2476 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2477 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2478 bfilter->src_ipaddr_mask[0] ==
2479 mfilter->src_ipaddr_mask[0] &&
2480 bfilter->src_port == mfilter->src_port &&
2481 bfilter->src_port_mask == mfilter->src_port_mask &&
2482 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2483 bfilter->dst_ipaddr_mask[0] ==
2484 mfilter->dst_ipaddr_mask[0] &&
2485 bfilter->dst_port == mfilter->dst_port &&
2486 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2487 bfilter->flags == mfilter->flags &&
2488 bfilter->enables == mfilter->enables) {
2499 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2500 struct rte_eth_ntuple_filter *nfilter,
2501 enum rte_filter_op filter_op)
2503 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2504 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2507 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2508 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2512 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2513 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2517 bfilter = bnxt_get_unused_filter(bp);
2518 if (bfilter == NULL) {
2520 "Not enough resources for a new filter.\n");
2523 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2527 vnic = &bp->vnic_info[nfilter->queue];
2528 vnic0 = &bp->vnic_info[0];
2529 filter1 = STAILQ_FIRST(&vnic0->filter);
2530 if (filter1 == NULL) {
2535 bfilter->dst_id = vnic->fw_vnic_id;
2536 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2538 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2539 bfilter->ethertype = 0x800;
2540 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2542 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2544 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2545 bfilter->dst_id == mfilter->dst_id) {
2546 PMD_DRV_LOG(ERR, "filter exists.\n");
2549 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2550 bfilter->dst_id != mfilter->dst_id) {
2551 mfilter->dst_id = vnic->fw_vnic_id;
2552 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2553 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2554 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2555 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2556 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2559 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2560 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2565 if (filter_op == RTE_ETH_FILTER_ADD) {
2566 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2567 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2570 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2572 if (mfilter == NULL) {
2573 /* This should not happen. But for Coverity! */
2577 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2579 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2580 bnxt_free_filter(bp, mfilter);
2581 mfilter->fw_l2_filter_id = -1;
2582 bnxt_free_filter(bp, bfilter);
2583 bfilter->fw_l2_filter_id = -1;
2588 bfilter->fw_l2_filter_id = -1;
2589 bnxt_free_filter(bp, bfilter);
2594 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2595 enum rte_filter_op filter_op,
2598 struct bnxt *bp = dev->data->dev_private;
2601 if (filter_op == RTE_ETH_FILTER_NOP)
2605 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2610 switch (filter_op) {
2611 case RTE_ETH_FILTER_ADD:
2612 ret = bnxt_cfg_ntuple_filter(bp,
2613 (struct rte_eth_ntuple_filter *)arg,
2616 case RTE_ETH_FILTER_DELETE:
2617 ret = bnxt_cfg_ntuple_filter(bp,
2618 (struct rte_eth_ntuple_filter *)arg,
2622 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2630 bnxt_parse_fdir_filter(struct bnxt *bp,
2631 struct rte_eth_fdir_filter *fdir,
2632 struct bnxt_filter_info *filter)
2634 enum rte_fdir_mode fdir_mode =
2635 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2636 struct bnxt_vnic_info *vnic0, *vnic;
2637 struct bnxt_filter_info *filter1;
2641 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2644 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2645 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2647 switch (fdir->input.flow_type) {
2648 case RTE_ETH_FLOW_IPV4:
2649 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2651 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2652 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2653 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2654 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2655 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2656 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2657 filter->ip_addr_type =
2658 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2659 filter->src_ipaddr_mask[0] = 0xffffffff;
2660 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2661 filter->dst_ipaddr_mask[0] = 0xffffffff;
2662 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2663 filter->ethertype = 0x800;
2664 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2666 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2667 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2668 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2669 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2670 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2671 filter->dst_port_mask = 0xffff;
2672 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2673 filter->src_port_mask = 0xffff;
2674 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2675 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2676 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2677 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2678 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2679 filter->ip_protocol = 6;
2680 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2681 filter->ip_addr_type =
2682 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2683 filter->src_ipaddr_mask[0] = 0xffffffff;
2684 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2685 filter->dst_ipaddr_mask[0] = 0xffffffff;
2686 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2687 filter->ethertype = 0x800;
2688 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2690 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2691 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2692 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2693 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2694 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2695 filter->dst_port_mask = 0xffff;
2696 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2697 filter->src_port_mask = 0xffff;
2698 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2699 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2700 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2701 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2702 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2703 filter->ip_protocol = 17;
2704 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2705 filter->ip_addr_type =
2706 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2707 filter->src_ipaddr_mask[0] = 0xffffffff;
2708 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2709 filter->dst_ipaddr_mask[0] = 0xffffffff;
2710 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2711 filter->ethertype = 0x800;
2712 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2714 case RTE_ETH_FLOW_IPV6:
2715 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2717 filter->ip_addr_type =
2718 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2719 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2720 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2721 rte_memcpy(filter->src_ipaddr,
2722 fdir->input.flow.ipv6_flow.src_ip, 16);
2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2724 rte_memcpy(filter->dst_ipaddr,
2725 fdir->input.flow.ipv6_flow.dst_ip, 16);
2726 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2727 memset(filter->dst_ipaddr_mask, 0xff, 16);
2728 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2729 memset(filter->src_ipaddr_mask, 0xff, 16);
2730 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2731 filter->ethertype = 0x86dd;
2732 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2734 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2735 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2736 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2737 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2738 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2739 filter->dst_port_mask = 0xffff;
2740 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2741 filter->src_port_mask = 0xffff;
2742 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2743 filter->ip_addr_type =
2744 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2745 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2746 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2747 rte_memcpy(filter->src_ipaddr,
2748 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2749 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2750 rte_memcpy(filter->dst_ipaddr,
2751 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2752 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2753 memset(filter->dst_ipaddr_mask, 0xff, 16);
2754 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2755 memset(filter->src_ipaddr_mask, 0xff, 16);
2756 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2757 filter->ethertype = 0x86dd;
2758 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2760 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2761 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2762 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2763 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2764 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2765 filter->dst_port_mask = 0xffff;
2766 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2767 filter->src_port_mask = 0xffff;
2768 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2769 filter->ip_addr_type =
2770 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2771 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2772 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2773 rte_memcpy(filter->src_ipaddr,
2774 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2775 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2776 rte_memcpy(filter->dst_ipaddr,
2777 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2778 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2779 memset(filter->dst_ipaddr_mask, 0xff, 16);
2780 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2781 memset(filter->src_ipaddr_mask, 0xff, 16);
2782 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2783 filter->ethertype = 0x86dd;
2784 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2786 case RTE_ETH_FLOW_L2_PAYLOAD:
2787 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2788 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2790 case RTE_ETH_FLOW_VXLAN:
2791 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2793 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2794 filter->tunnel_type =
2795 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2796 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2798 case RTE_ETH_FLOW_NVGRE:
2799 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2801 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2802 filter->tunnel_type =
2803 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2804 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2806 case RTE_ETH_FLOW_UNKNOWN:
2807 case RTE_ETH_FLOW_RAW:
2808 case RTE_ETH_FLOW_FRAG_IPV4:
2809 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2810 case RTE_ETH_FLOW_FRAG_IPV6:
2811 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2812 case RTE_ETH_FLOW_IPV6_EX:
2813 case RTE_ETH_FLOW_IPV6_TCP_EX:
2814 case RTE_ETH_FLOW_IPV6_UDP_EX:
2815 case RTE_ETH_FLOW_GENEVE:
2821 vnic0 = &bp->vnic_info[0];
2822 vnic = &bp->vnic_info[fdir->action.rx_queue];
2824 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2829 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2830 rte_memcpy(filter->dst_macaddr,
2831 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2832 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2835 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2836 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2837 filter1 = STAILQ_FIRST(&vnic0->filter);
2838 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2840 filter->dst_id = vnic->fw_vnic_id;
2841 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2842 if (filter->dst_macaddr[i] == 0x00)
2843 filter1 = STAILQ_FIRST(&vnic0->filter);
2845 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2848 if (filter1 == NULL)
2851 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2852 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2854 filter->enables = en;
2859 static struct bnxt_filter_info *
2860 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2861 struct bnxt_vnic_info **mvnic)
2863 struct bnxt_filter_info *mf = NULL;
2866 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2867 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2869 STAILQ_FOREACH(mf, &vnic->filter, next) {
2870 if (mf->filter_type == nf->filter_type &&
2871 mf->flags == nf->flags &&
2872 mf->src_port == nf->src_port &&
2873 mf->src_port_mask == nf->src_port_mask &&
2874 mf->dst_port == nf->dst_port &&
2875 mf->dst_port_mask == nf->dst_port_mask &&
2876 mf->ip_protocol == nf->ip_protocol &&
2877 mf->ip_addr_type == nf->ip_addr_type &&
2878 mf->ethertype == nf->ethertype &&
2879 mf->vni == nf->vni &&
2880 mf->tunnel_type == nf->tunnel_type &&
2881 mf->l2_ovlan == nf->l2_ovlan &&
2882 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2883 mf->l2_ivlan == nf->l2_ivlan &&
2884 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2885 !memcmp(mf->l2_addr, nf->l2_addr,
2886 RTE_ETHER_ADDR_LEN) &&
2887 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2888 RTE_ETHER_ADDR_LEN) &&
2889 !memcmp(mf->src_macaddr, nf->src_macaddr,
2890 RTE_ETHER_ADDR_LEN) &&
2891 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2892 RTE_ETHER_ADDR_LEN) &&
2893 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2894 sizeof(nf->src_ipaddr)) &&
2895 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2896 sizeof(nf->src_ipaddr_mask)) &&
2897 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2898 sizeof(nf->dst_ipaddr)) &&
2899 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2900 sizeof(nf->dst_ipaddr_mask))) {
2911 bnxt_fdir_filter(struct rte_eth_dev *dev,
2912 enum rte_filter_op filter_op,
2915 struct bnxt *bp = dev->data->dev_private;
2916 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2917 struct bnxt_filter_info *filter, *match;
2918 struct bnxt_vnic_info *vnic, *mvnic;
2921 if (filter_op == RTE_ETH_FILTER_NOP)
2924 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2927 switch (filter_op) {
2928 case RTE_ETH_FILTER_ADD:
2929 case RTE_ETH_FILTER_DELETE:
2931 filter = bnxt_get_unused_filter(bp);
2932 if (filter == NULL) {
2934 "Not enough resources for a new flow.\n");
2938 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2941 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2943 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2944 vnic = &bp->vnic_info[0];
2946 vnic = &bp->vnic_info[fdir->action.rx_queue];
2948 match = bnxt_match_fdir(bp, filter, &mvnic);
2949 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2950 if (match->dst_id == vnic->fw_vnic_id) {
2951 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2955 match->dst_id = vnic->fw_vnic_id;
2956 ret = bnxt_hwrm_set_ntuple_filter(bp,
2959 STAILQ_REMOVE(&mvnic->filter, match,
2960 bnxt_filter_info, next);
2961 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2963 "Filter with matching pattern exist\n");
2965 "Updated it to new destination q\n");
2969 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2970 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2975 if (filter_op == RTE_ETH_FILTER_ADD) {
2976 ret = bnxt_hwrm_set_ntuple_filter(bp,
2981 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2983 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2984 STAILQ_REMOVE(&vnic->filter, match,
2985 bnxt_filter_info, next);
2986 bnxt_free_filter(bp, match);
2987 filter->fw_l2_filter_id = -1;
2988 bnxt_free_filter(bp, filter);
2991 case RTE_ETH_FILTER_FLUSH:
2992 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2993 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2995 STAILQ_FOREACH(filter, &vnic->filter, next) {
2996 if (filter->filter_type ==
2997 HWRM_CFA_NTUPLE_FILTER) {
2999 bnxt_hwrm_clear_ntuple_filter(bp,
3001 STAILQ_REMOVE(&vnic->filter, filter,
3002 bnxt_filter_info, next);
3007 case RTE_ETH_FILTER_UPDATE:
3008 case RTE_ETH_FILTER_STATS:
3009 case RTE_ETH_FILTER_INFO:
3010 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3013 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3020 filter->fw_l2_filter_id = -1;
3021 bnxt_free_filter(bp, filter);
3026 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3027 enum rte_filter_type filter_type,
3028 enum rte_filter_op filter_op, void *arg)
3032 ret = is_bnxt_in_error(dev->data->dev_private);
3036 switch (filter_type) {
3037 case RTE_ETH_FILTER_TUNNEL:
3039 "filter type: %d: To be implemented\n", filter_type);
3041 case RTE_ETH_FILTER_FDIR:
3042 ret = bnxt_fdir_filter(dev, filter_op, arg);
3044 case RTE_ETH_FILTER_NTUPLE:
3045 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3047 case RTE_ETH_FILTER_ETHERTYPE:
3048 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3050 case RTE_ETH_FILTER_GENERIC:
3051 if (filter_op != RTE_ETH_FILTER_GET)
3053 *(const void **)arg = &bnxt_flow_ops;
3057 "Filter type (%d) not supported", filter_type);
3064 static const uint32_t *
3065 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3067 static const uint32_t ptypes[] = {
3068 RTE_PTYPE_L2_ETHER_VLAN,
3069 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3070 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3074 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3075 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3076 RTE_PTYPE_INNER_L4_ICMP,
3077 RTE_PTYPE_INNER_L4_TCP,
3078 RTE_PTYPE_INNER_L4_UDP,
3082 if (!dev->rx_pkt_burst)
3088 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3091 uint32_t reg_base = *reg_arr & 0xfffff000;
3095 for (i = 0; i < count; i++) {
3096 if ((reg_arr[i] & 0xfffff000) != reg_base)
3099 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3100 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3104 static int bnxt_map_ptp_regs(struct bnxt *bp)
3106 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3110 reg_arr = ptp->rx_regs;
3111 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3115 reg_arr = ptp->tx_regs;
3116 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3120 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3121 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3123 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3124 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3129 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3131 rte_write32(0, (uint8_t *)bp->bar0 +
3132 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3133 rte_write32(0, (uint8_t *)bp->bar0 +
3134 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3137 static uint64_t bnxt_cc_read(struct bnxt *bp)
3141 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142 BNXT_GRCPF_REG_SYNC_TIME));
3143 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3148 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3150 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3153 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3154 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3155 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3158 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3159 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3160 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3161 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3162 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3163 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3168 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3170 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3171 struct bnxt_pf_info *pf = &bp->pf;
3178 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3180 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3183 port_id = pf->port_id;
3184 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3185 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3187 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3188 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3189 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3190 /* bnxt_clr_rx_ts(bp); TBD */
3194 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3195 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3196 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3197 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3203 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3206 struct bnxt *bp = dev->data->dev_private;
3207 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3212 ns = rte_timespec_to_ns(ts);
3213 /* Set the timecounters to a new value. */
3220 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3222 uint64_t ns, systime_cycles;
3223 struct bnxt *bp = dev->data->dev_private;
3224 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3229 systime_cycles = bnxt_cc_read(bp);
3230 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3231 *ts = rte_ns_to_timespec(ns);
3236 bnxt_timesync_enable(struct rte_eth_dev *dev)
3238 struct bnxt *bp = dev->data->dev_private;
3239 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3246 ptp->tx_tstamp_en = 1;
3247 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3249 if (!bnxt_hwrm_ptp_cfg(bp))
3250 bnxt_map_ptp_regs(bp);
3252 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3253 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3254 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3256 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3257 ptp->tc.cc_shift = shift;
3258 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3260 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3261 ptp->rx_tstamp_tc.cc_shift = shift;
3262 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3264 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3265 ptp->tx_tstamp_tc.cc_shift = shift;
3266 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3272 bnxt_timesync_disable(struct rte_eth_dev *dev)
3274 struct bnxt *bp = dev->data->dev_private;
3275 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3281 ptp->tx_tstamp_en = 0;
3284 bnxt_hwrm_ptp_cfg(bp);
3286 bnxt_unmap_ptp_regs(bp);
3292 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3293 struct timespec *timestamp,
3294 uint32_t flags __rte_unused)
3296 struct bnxt *bp = dev->data->dev_private;
3297 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3298 uint64_t rx_tstamp_cycles = 0;
3304 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3305 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3306 *timestamp = rte_ns_to_timespec(ns);
3311 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3312 struct timespec *timestamp)
3314 struct bnxt *bp = dev->data->dev_private;
3315 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3316 uint64_t tx_tstamp_cycles = 0;
3322 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3323 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3324 *timestamp = rte_ns_to_timespec(ns);
3330 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3332 struct bnxt *bp = dev->data->dev_private;
3333 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3338 ptp->tc.nsec += delta;
3344 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3346 struct bnxt *bp = dev->data->dev_private;
3348 uint32_t dir_entries;
3349 uint32_t entry_length;
3351 rc = is_bnxt_in_error(bp);
3355 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3356 bp->pdev->addr.domain, bp->pdev->addr.bus,
3357 bp->pdev->addr.devid, bp->pdev->addr.function);
3359 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3363 return dir_entries * entry_length;
3367 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3368 struct rte_dev_eeprom_info *in_eeprom)
3370 struct bnxt *bp = dev->data->dev_private;
3375 rc = is_bnxt_in_error(bp);
3379 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3380 "len = %d\n", bp->pdev->addr.domain,
3381 bp->pdev->addr.bus, bp->pdev->addr.devid,
3382 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3384 if (in_eeprom->offset == 0) /* special offset value to get directory */
3385 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3388 index = in_eeprom->offset >> 24;
3389 offset = in_eeprom->offset & 0xffffff;
3392 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3393 in_eeprom->length, in_eeprom->data);
3398 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3401 case BNX_DIR_TYPE_CHIMP_PATCH:
3402 case BNX_DIR_TYPE_BOOTCODE:
3403 case BNX_DIR_TYPE_BOOTCODE_2:
3404 case BNX_DIR_TYPE_APE_FW:
3405 case BNX_DIR_TYPE_APE_PATCH:
3406 case BNX_DIR_TYPE_KONG_FW:
3407 case BNX_DIR_TYPE_KONG_PATCH:
3408 case BNX_DIR_TYPE_BONO_FW:
3409 case BNX_DIR_TYPE_BONO_PATCH:
3417 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3420 case BNX_DIR_TYPE_AVS:
3421 case BNX_DIR_TYPE_EXP_ROM_MBA:
3422 case BNX_DIR_TYPE_PCIE:
3423 case BNX_DIR_TYPE_TSCF_UCODE:
3424 case BNX_DIR_TYPE_EXT_PHY:
3425 case BNX_DIR_TYPE_CCM:
3426 case BNX_DIR_TYPE_ISCSI_BOOT:
3427 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3428 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3436 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3438 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3439 bnxt_dir_type_is_other_exec_format(dir_type);
3443 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3444 struct rte_dev_eeprom_info *in_eeprom)
3446 struct bnxt *bp = dev->data->dev_private;
3447 uint8_t index, dir_op;
3448 uint16_t type, ext, ordinal, attr;
3451 rc = is_bnxt_in_error(bp);
3455 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3456 "len = %d\n", bp->pdev->addr.domain,
3457 bp->pdev->addr.bus, bp->pdev->addr.devid,
3458 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3461 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3465 type = in_eeprom->magic >> 16;
3467 if (type == 0xffff) { /* special value for directory operations */
3468 index = in_eeprom->magic & 0xff;
3469 dir_op = in_eeprom->magic >> 8;
3473 case 0x0e: /* erase */
3474 if (in_eeprom->offset != ~in_eeprom->magic)
3476 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3482 /* Create or re-write an NVM item: */
3483 if (bnxt_dir_type_is_executable(type) == true)
3485 ext = in_eeprom->magic & 0xffff;
3486 ordinal = in_eeprom->offset >> 16;
3487 attr = in_eeprom->offset & 0xffff;
3489 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3490 in_eeprom->data, in_eeprom->length);
3497 static const struct eth_dev_ops bnxt_dev_ops = {
3498 .dev_infos_get = bnxt_dev_info_get_op,
3499 .dev_close = bnxt_dev_close_op,
3500 .dev_configure = bnxt_dev_configure_op,
3501 .dev_start = bnxt_dev_start_op,
3502 .dev_stop = bnxt_dev_stop_op,
3503 .dev_set_link_up = bnxt_dev_set_link_up_op,
3504 .dev_set_link_down = bnxt_dev_set_link_down_op,
3505 .stats_get = bnxt_stats_get_op,
3506 .stats_reset = bnxt_stats_reset_op,
3507 .rx_queue_setup = bnxt_rx_queue_setup_op,
3508 .rx_queue_release = bnxt_rx_queue_release_op,
3509 .tx_queue_setup = bnxt_tx_queue_setup_op,
3510 .tx_queue_release = bnxt_tx_queue_release_op,
3511 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3512 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3513 .reta_update = bnxt_reta_update_op,
3514 .reta_query = bnxt_reta_query_op,
3515 .rss_hash_update = bnxt_rss_hash_update_op,
3516 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3517 .link_update = bnxt_link_update_op,
3518 .promiscuous_enable = bnxt_promiscuous_enable_op,
3519 .promiscuous_disable = bnxt_promiscuous_disable_op,
3520 .allmulticast_enable = bnxt_allmulticast_enable_op,
3521 .allmulticast_disable = bnxt_allmulticast_disable_op,
3522 .mac_addr_add = bnxt_mac_addr_add_op,
3523 .mac_addr_remove = bnxt_mac_addr_remove_op,
3524 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3525 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3526 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3527 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3528 .vlan_filter_set = bnxt_vlan_filter_set_op,
3529 .vlan_offload_set = bnxt_vlan_offload_set_op,
3530 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3531 .mtu_set = bnxt_mtu_set_op,
3532 .mac_addr_set = bnxt_set_default_mac_addr_op,
3533 .xstats_get = bnxt_dev_xstats_get_op,
3534 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3535 .xstats_reset = bnxt_dev_xstats_reset_op,
3536 .fw_version_get = bnxt_fw_version_get,
3537 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3538 .rxq_info_get = bnxt_rxq_info_get_op,
3539 .txq_info_get = bnxt_txq_info_get_op,
3540 .dev_led_on = bnxt_dev_led_on_op,
3541 .dev_led_off = bnxt_dev_led_off_op,
3542 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3543 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3544 .rx_queue_count = bnxt_rx_queue_count_op,
3545 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3546 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3547 .rx_queue_start = bnxt_rx_queue_start,
3548 .rx_queue_stop = bnxt_rx_queue_stop,
3549 .tx_queue_start = bnxt_tx_queue_start,
3550 .tx_queue_stop = bnxt_tx_queue_stop,
3551 .filter_ctrl = bnxt_filter_ctrl_op,
3552 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3553 .get_eeprom_length = bnxt_get_eeprom_length_op,
3554 .get_eeprom = bnxt_get_eeprom_op,
3555 .set_eeprom = bnxt_set_eeprom_op,
3556 .timesync_enable = bnxt_timesync_enable,
3557 .timesync_disable = bnxt_timesync_disable,
3558 .timesync_read_time = bnxt_timesync_read_time,
3559 .timesync_write_time = bnxt_timesync_write_time,
3560 .timesync_adjust_time = bnxt_timesync_adjust_time,
3561 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3562 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3565 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3567 struct bnxt_error_recovery_info *info = bp->recovery_info;
3568 uint32_t reg_base = 0xffffffff;
3571 /* Only pre-map the monitoring GRC registers using window 2 */
3572 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3573 uint32_t reg = info->status_regs[i];
3575 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3578 if (reg_base == 0xffffffff)
3579 reg_base = reg & 0xfffff000;
3580 if ((reg & 0xfffff000) != reg_base)
3583 /* Use mask 0xffc as the Lower 2 bits indicates
3584 * address space location
3586 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3590 if (reg_base == 0xffffffff)
3593 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3594 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3599 static void bnxt_dev_cleanup(struct bnxt *bp)
3601 bnxt_set_hwrm_link_config(bp, false);
3602 bp->link_info.link_up = 0;
3603 if (bp->dev_stopped == 0)
3604 bnxt_dev_stop_op(bp->eth_dev);
3606 bnxt_uninit_resources(bp, true);
3609 static int bnxt_restore_filters(struct bnxt *bp)
3611 struct rte_eth_dev *dev = bp->eth_dev;
3614 if (dev->data->all_multicast)
3615 ret = bnxt_allmulticast_enable_op(dev);
3616 if (dev->data->promiscuous)
3617 ret = bnxt_promiscuous_enable_op(dev);
3619 /* TODO restore other filters as well */
3623 static void bnxt_dev_recover(void *arg)
3625 struct bnxt *bp = arg;
3626 int timeout = bp->fw_reset_max_msecs;
3629 /* Clear Error flag so that device re-init should happen */
3630 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3633 rc = bnxt_hwrm_ver_get(bp);
3636 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3637 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3638 } while (rc && timeout);
3641 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3645 rc = bnxt_init_resources(bp, true);
3648 "Failed to initialize resources after reset\n");
3651 /* clear reset flag as the device is initialized now */
3652 bp->flags &= ~BNXT_FLAG_FW_RESET;
3654 rc = bnxt_dev_start_op(bp->eth_dev);
3656 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3660 rc = bnxt_restore_filters(bp);
3664 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3667 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3668 bnxt_uninit_resources(bp, false);
3669 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3672 void bnxt_dev_reset_and_resume(void *arg)
3674 struct bnxt *bp = arg;
3677 bnxt_dev_cleanup(bp);
3679 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3680 bnxt_dev_recover, (void *)bp);
3682 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3685 static bool bnxt_vf_pciid(uint16_t id)
3687 if (id == BROADCOM_DEV_ID_57304_VF ||
3688 id == BROADCOM_DEV_ID_57406_VF ||
3689 id == BROADCOM_DEV_ID_5731X_VF ||
3690 id == BROADCOM_DEV_ID_5741X_VF ||
3691 id == BROADCOM_DEV_ID_57414_VF ||
3692 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3693 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3694 id == BROADCOM_DEV_ID_58802_VF ||
3695 id == BROADCOM_DEV_ID_57500_VF1 ||
3696 id == BROADCOM_DEV_ID_57500_VF2)
3701 bool bnxt_stratus_device(struct bnxt *bp)
3703 uint16_t id = bp->pdev->id.device_id;
3705 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3706 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3707 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3712 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3714 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3715 struct bnxt *bp = eth_dev->data->dev_private;
3717 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3718 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3719 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3720 if (!bp->bar0 || !bp->doorbell_base) {
3721 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3725 bp->eth_dev = eth_dev;
3731 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3732 struct bnxt_ctx_pg_info *ctx_pg,
3737 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3738 const struct rte_memzone *mz = NULL;
3739 char mz_name[RTE_MEMZONE_NAMESIZE];
3740 rte_iova_t mz_phys_addr;
3741 uint64_t valid_bits = 0;
3748 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3750 rmem->page_size = BNXT_PAGE_SIZE;
3751 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3752 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3753 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3755 valid_bits = PTU_PTE_VALID;
3757 if (rmem->nr_pages > 1) {
3758 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3759 "bnxt_ctx_pg_tbl%s_%x_%d",
3760 suffix, idx, bp->eth_dev->data->port_id);
3761 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3762 mz = rte_memzone_lookup(mz_name);
3764 mz = rte_memzone_reserve_aligned(mz_name,
3768 RTE_MEMZONE_SIZE_HINT_ONLY |
3769 RTE_MEMZONE_IOVA_CONTIG,
3775 memset(mz->addr, 0, mz->len);
3776 mz_phys_addr = mz->iova;
3777 if ((unsigned long)mz->addr == mz_phys_addr) {
3778 PMD_DRV_LOG(WARNING,
3779 "Memzone physical address same as virtual.\n");
3780 PMD_DRV_LOG(WARNING,
3781 "Using rte_mem_virt2iova()\n");
3782 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3783 if (mz_phys_addr == RTE_BAD_IOVA) {
3785 "unable to map addr to phys memory\n");
3789 rte_mem_lock_page(((char *)mz->addr));
3791 rmem->pg_tbl = mz->addr;
3792 rmem->pg_tbl_map = mz_phys_addr;
3793 rmem->pg_tbl_mz = mz;
3796 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3797 suffix, idx, bp->eth_dev->data->port_id);
3798 mz = rte_memzone_lookup(mz_name);
3800 mz = rte_memzone_reserve_aligned(mz_name,
3804 RTE_MEMZONE_SIZE_HINT_ONLY |
3805 RTE_MEMZONE_IOVA_CONTIG,
3811 memset(mz->addr, 0, mz->len);
3812 mz_phys_addr = mz->iova;
3813 if ((unsigned long)mz->addr == mz_phys_addr) {
3814 PMD_DRV_LOG(WARNING,
3815 "Memzone physical address same as virtual.\n");
3816 PMD_DRV_LOG(WARNING,
3817 "Using rte_mem_virt2iova()\n");
3818 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3819 rte_mem_lock_page(((char *)mz->addr) + sz);
3820 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3821 if (mz_phys_addr == RTE_BAD_IOVA) {
3823 "unable to map addr to phys memory\n");
3828 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3829 rte_mem_lock_page(((char *)mz->addr) + sz);
3830 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3831 rmem->dma_arr[i] = mz_phys_addr + sz;
3833 if (rmem->nr_pages > 1) {
3834 if (i == rmem->nr_pages - 2 &&
3835 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3836 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3837 else if (i == rmem->nr_pages - 1 &&
3838 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3839 valid_bits |= PTU_PTE_LAST;
3841 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3847 if (rmem->vmem_size)
3848 rmem->vmem = (void **)mz->addr;
3849 rmem->dma_arr[0] = mz_phys_addr;
3853 static void bnxt_free_ctx_mem(struct bnxt *bp)
3857 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3860 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3861 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3862 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3863 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3864 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3865 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3866 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3867 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3868 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3869 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3870 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3872 for (i = 0; i < BNXT_MAX_Q; i++) {
3873 if (bp->ctx->tqm_mem[i])
3874 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3881 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3883 #define min_t(type, x, y) ({ \
3884 type __min1 = (x); \
3885 type __min2 = (y); \
3886 __min1 < __min2 ? __min1 : __min2; })
3888 #define max_t(type, x, y) ({ \
3889 type __max1 = (x); \
3890 type __max2 = (y); \
3891 __max1 > __max2 ? __max1 : __max2; })
3893 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3895 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3897 struct bnxt_ctx_pg_info *ctx_pg;
3898 struct bnxt_ctx_mem_info *ctx;
3899 uint32_t mem_size, ena, entries;
3902 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3904 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3908 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3911 ctx_pg = &ctx->qp_mem;
3912 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3913 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3914 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3918 ctx_pg = &ctx->srq_mem;
3919 ctx_pg->entries = ctx->srq_max_l2_entries;
3920 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3921 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3925 ctx_pg = &ctx->cq_mem;
3926 ctx_pg->entries = ctx->cq_max_l2_entries;
3927 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3928 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3932 ctx_pg = &ctx->vnic_mem;
3933 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3934 ctx->vnic_max_ring_table_entries;
3935 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3936 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3940 ctx_pg = &ctx->stat_mem;
3941 ctx_pg->entries = ctx->stat_max_entries;
3942 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3943 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3947 entries = ctx->qp_max_l2_entries;
3948 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3949 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3950 ctx->tqm_max_entries_per_ring);
3951 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3952 ctx_pg = ctx->tqm_mem[i];
3953 /* use min tqm entries for now. */
3954 ctx_pg->entries = entries;
3955 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3956 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3959 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3962 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3963 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3966 "Failed to configure context mem: rc = %d\n", rc);
3968 ctx->flags |= BNXT_CTX_FLAG_INITED;
3973 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3975 struct rte_pci_device *pci_dev = bp->pdev;
3976 char mz_name[RTE_MEMZONE_NAMESIZE];
3977 const struct rte_memzone *mz = NULL;
3978 uint32_t total_alloc_len;
3979 rte_iova_t mz_phys_addr;
3981 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3984 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3985 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3986 pci_dev->addr.bus, pci_dev->addr.devid,
3987 pci_dev->addr.function, "rx_port_stats");
3988 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3989 mz = rte_memzone_lookup(mz_name);
3991 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3992 sizeof(struct rx_port_stats_ext) + 512);
3994 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3997 RTE_MEMZONE_SIZE_HINT_ONLY |
3998 RTE_MEMZONE_IOVA_CONTIG);
4002 memset(mz->addr, 0, mz->len);
4003 mz_phys_addr = mz->iova;
4004 if ((unsigned long)mz->addr == mz_phys_addr) {
4005 PMD_DRV_LOG(WARNING,
4006 "Memzone physical address same as virtual.\n");
4007 PMD_DRV_LOG(WARNING,
4008 "Using rte_mem_virt2iova()\n");
4009 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4010 if (mz_phys_addr == RTE_BAD_IOVA) {
4012 "Can't map address to physical memory\n");
4017 bp->rx_mem_zone = (const void *)mz;
4018 bp->hw_rx_port_stats = mz->addr;
4019 bp->hw_rx_port_stats_map = mz_phys_addr;
4021 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4022 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4023 pci_dev->addr.bus, pci_dev->addr.devid,
4024 pci_dev->addr.function, "tx_port_stats");
4025 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4026 mz = rte_memzone_lookup(mz_name);
4028 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4029 sizeof(struct tx_port_stats_ext) + 512);
4031 mz = rte_memzone_reserve(mz_name,
4035 RTE_MEMZONE_SIZE_HINT_ONLY |
4036 RTE_MEMZONE_IOVA_CONTIG);
4040 memset(mz->addr, 0, mz->len);
4041 mz_phys_addr = mz->iova;
4042 if ((unsigned long)mz->addr == mz_phys_addr) {
4043 PMD_DRV_LOG(WARNING,
4044 "Memzone physical address same as virtual\n");
4045 PMD_DRV_LOG(WARNING,
4046 "Using rte_mem_virt2iova()\n");
4047 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4048 if (mz_phys_addr == RTE_BAD_IOVA) {
4050 "Can't map address to physical memory\n");
4055 bp->tx_mem_zone = (const void *)mz;
4056 bp->hw_tx_port_stats = mz->addr;
4057 bp->hw_tx_port_stats_map = mz_phys_addr;
4058 bp->flags |= BNXT_FLAG_PORT_STATS;
4060 /* Display extended statistics if FW supports it */
4061 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4062 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4063 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4066 bp->hw_rx_port_stats_ext = (void *)
4067 ((uint8_t *)bp->hw_rx_port_stats +
4068 sizeof(struct rx_port_stats));
4069 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4070 sizeof(struct rx_port_stats);
4071 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4073 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4074 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4075 bp->hw_tx_port_stats_ext = (void *)
4076 ((uint8_t *)bp->hw_tx_port_stats +
4077 sizeof(struct tx_port_stats));
4078 bp->hw_tx_port_stats_ext_map =
4079 bp->hw_tx_port_stats_map +
4080 sizeof(struct tx_port_stats);
4081 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4087 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4089 struct bnxt *bp = eth_dev->data->dev_private;
4092 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4093 RTE_ETHER_ADDR_LEN *
4096 if (eth_dev->data->mac_addrs == NULL) {
4097 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4101 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4105 /* Generate a random MAC address, if none was assigned by PF */
4106 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4107 bnxt_eth_hw_addr_random(bp->mac_addr);
4109 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4110 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4111 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4113 rc = bnxt_hwrm_set_mac(bp);
4115 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4116 RTE_ETHER_ADDR_LEN);
4120 /* Copy the permanent MAC from the FUNC_QCAPS response */
4121 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4122 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4127 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4131 /* MAC is already configured in FW */
4132 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4135 /* Restore the old MAC configured */
4136 rc = bnxt_hwrm_set_mac(bp);
4138 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4143 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4148 #define ALLOW_FUNC(x) \
4150 uint32_t arg = (x); \
4151 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4152 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4155 /* Forward all requests if firmware is new enough */
4156 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4157 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4158 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4159 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4161 PMD_DRV_LOG(WARNING,
4162 "Firmware too old for VF mailbox functionality\n");
4163 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4167 * The following are used for driver cleanup. If we disallow these,
4168 * VF drivers can't clean up cleanly.
4170 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4171 ALLOW_FUNC(HWRM_VNIC_FREE);
4172 ALLOW_FUNC(HWRM_RING_FREE);
4173 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4174 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4175 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4176 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4177 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4178 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4181 static int bnxt_init_fw(struct bnxt *bp)
4186 rc = bnxt_hwrm_ver_get(bp);
4190 rc = bnxt_hwrm_func_reset(bp);
4194 rc = bnxt_hwrm_queue_qportcfg(bp);
4198 /* Get the MAX capabilities for this function */
4199 rc = bnxt_hwrm_func_qcaps(bp);
4203 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4207 /* Get the adapter error recovery support info */
4208 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4210 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4212 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4213 mtu != bp->eth_dev->data->mtu)
4214 bp->eth_dev->data->mtu = mtu;
4216 bnxt_hwrm_port_led_qcaps(bp);
4221 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4225 rc = bnxt_init_fw(bp);
4229 if (!reconfig_dev) {
4230 rc = bnxt_setup_mac_addr(bp->eth_dev);
4234 rc = bnxt_restore_dflt_mac(bp);
4239 bnxt_config_vf_req_fwd(bp);
4241 rc = bnxt_hwrm_func_driver_register(bp);
4243 PMD_DRV_LOG(ERR, "Failed to register driver");
4248 if (bp->pdev->max_vfs) {
4249 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4251 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4255 rc = bnxt_hwrm_allocate_pf_only(bp);
4258 "Failed to allocate PF resources");
4264 rc = bnxt_alloc_mem(bp, reconfig_dev);
4268 rc = bnxt_setup_int(bp);
4274 rc = bnxt_request_int(bp);
4282 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4284 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4285 static int version_printed;
4289 if (version_printed++ == 0)
4290 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4292 rte_eth_copy_pci_info(eth_dev, pci_dev);
4294 bp = eth_dev->data->dev_private;
4296 bp->dev_stopped = 1;
4298 eth_dev->dev_ops = &bnxt_dev_ops;
4299 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4300 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4303 * For secondary processes, we don't initialise any further
4304 * as primary has already done this work.
4306 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4309 if (bnxt_vf_pciid(pci_dev->id.device_id))
4310 bp->flags |= BNXT_FLAG_VF;
4312 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4313 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4314 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4315 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4316 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4317 bp->flags |= BNXT_FLAG_THOR_CHIP;
4319 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4320 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4321 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4322 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4323 bp->flags |= BNXT_FLAG_STINGRAY;
4325 rc = bnxt_init_board(eth_dev);
4328 "Failed to initialize board rc: %x\n", rc);
4332 rc = bnxt_alloc_hwrm_resources(bp);
4335 "Failed to allocate hwrm resource rc: %x\n", rc);
4338 rc = bnxt_init_resources(bp, false);
4342 rc = bnxt_alloc_stats_mem(bp);
4347 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4348 pci_dev->mem_resource[0].phys_addr,
4349 pci_dev->mem_resource[0].addr);
4354 bnxt_dev_uninit(eth_dev);
4359 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4363 bnxt_disable_int(bp);
4365 bnxt_free_mem(bp, reconfig_dev);
4366 bnxt_hwrm_func_buf_unrgtr(bp);
4367 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4368 bp->flags &= ~BNXT_FLAG_REGISTERED;
4369 bnxt_free_ctx_mem(bp);
4370 if (!reconfig_dev) {
4371 bnxt_free_hwrm_resources(bp);
4373 if (bp->recovery_info != NULL) {
4374 rte_free(bp->recovery_info);
4375 bp->recovery_info = NULL;
4383 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4385 struct bnxt *bp = eth_dev->data->dev_private;
4388 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4391 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4393 rc = bnxt_uninit_resources(bp, false);
4395 if (bp->grp_info != NULL) {
4396 rte_free(bp->grp_info);
4397 bp->grp_info = NULL;
4400 if (bp->tx_mem_zone) {
4401 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4402 bp->tx_mem_zone = NULL;
4405 if (bp->rx_mem_zone) {
4406 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4407 bp->rx_mem_zone = NULL;
4410 if (bp->dev_stopped == 0)
4411 bnxt_dev_close_op(eth_dev);
4413 rte_free(bp->pf.vf_info);
4414 eth_dev->dev_ops = NULL;
4415 eth_dev->rx_pkt_burst = NULL;
4416 eth_dev->tx_pkt_burst = NULL;
4421 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4422 struct rte_pci_device *pci_dev)
4424 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4428 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4430 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4431 return rte_eth_dev_pci_generic_remove(pci_dev,
4434 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4437 static struct rte_pci_driver bnxt_rte_pmd = {
4438 .id_table = bnxt_pci_id_map,
4439 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4440 .probe = bnxt_pci_probe,
4441 .remove = bnxt_pci_remove,
4445 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4447 if (strcmp(dev->device->driver->name, drv->driver.name))
4453 bool is_bnxt_supported(struct rte_eth_dev *dev)
4455 return is_device_supported(dev, &bnxt_rte_pmd);
4458 RTE_INIT(bnxt_init_log)
4460 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4461 if (bnxt_logtype_driver >= 0)
4462 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4465 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4466 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4467 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");