1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { .vendor_id = 0, /* sentinel */ },
89 #define BNXT_ETH_RSS_SUPPORT ( \
91 ETH_RSS_NONFRAG_IPV4_TCP | \
92 ETH_RSS_NONFRAG_IPV4_UDP | \
94 ETH_RSS_NONFRAG_IPV6_TCP | \
95 ETH_RSS_NONFRAG_IPV6_UDP)
97 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
98 DEV_TX_OFFLOAD_IPV4_CKSUM | \
99 DEV_TX_OFFLOAD_TCP_CKSUM | \
100 DEV_TX_OFFLOAD_UDP_CKSUM | \
101 DEV_TX_OFFLOAD_TCP_TSO | \
102 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
103 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
104 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
105 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
106 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
107 DEV_TX_OFFLOAD_QINQ_INSERT | \
108 DEV_TX_OFFLOAD_MULTI_SEGS)
110 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
111 DEV_RX_OFFLOAD_VLAN_STRIP | \
112 DEV_RX_OFFLOAD_IPV4_CKSUM | \
113 DEV_RX_OFFLOAD_UDP_CKSUM | \
114 DEV_RX_OFFLOAD_TCP_CKSUM | \
115 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
116 DEV_RX_OFFLOAD_JUMBO_FRAME | \
117 DEV_RX_OFFLOAD_KEEP_CRC | \
118 DEV_RX_OFFLOAD_VLAN_EXTEND | \
119 DEV_RX_OFFLOAD_TCP_LRO | \
120 DEV_RX_OFFLOAD_SCATTER)
122 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
123 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
124 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
125 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
126 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
127 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
128 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
130 int is_bnxt_in_error(struct bnxt *bp)
132 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
134 if (bp->flags & BNXT_FLAG_FW_RESET)
140 /***********************/
143 * High level utility functions
146 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
148 if (!BNXT_CHIP_THOR(bp))
151 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
152 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
153 BNXT_RSS_ENTRIES_PER_CTX_THOR;
156 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
158 if (!BNXT_CHIP_THOR(bp))
159 return HW_HASH_INDEX_SIZE;
161 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
164 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
166 bnxt_free_filter_mem(bp);
167 bnxt_free_vnic_attributes(bp);
168 bnxt_free_vnic_mem(bp);
170 /* tx/rx rings are configured as part of *_queue_setup callbacks.
171 * If the number of rings change across fw update,
172 * we don't have much choice except to warn the user.
176 bnxt_free_tx_rings(bp);
177 bnxt_free_rx_rings(bp);
179 bnxt_free_async_cp_ring(bp);
180 bnxt_free_rxtx_nq_ring(bp);
183 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
187 rc = bnxt_alloc_ring_grps(bp);
191 rc = bnxt_alloc_async_ring_struct(bp);
195 rc = bnxt_alloc_vnic_mem(bp);
199 rc = bnxt_alloc_vnic_attributes(bp);
203 rc = bnxt_alloc_filter_mem(bp);
207 rc = bnxt_alloc_async_cp_ring(bp);
211 rc = bnxt_alloc_rxtx_nq_ring(bp);
218 bnxt_free_mem(bp, reconfig);
222 static int bnxt_init_chip(struct bnxt *bp)
224 struct bnxt_rx_queue *rxq;
225 struct rte_eth_link new;
226 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
227 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
228 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
229 uint64_t rx_offloads = dev_conf->rxmode.offloads;
230 uint32_t intr_vector = 0;
231 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
232 uint32_t vec = BNXT_MISC_VEC_ID;
236 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
237 bp->eth_dev->data->dev_conf.rxmode.offloads |=
238 DEV_RX_OFFLOAD_JUMBO_FRAME;
239 bp->flags |= BNXT_FLAG_JUMBO;
241 bp->eth_dev->data->dev_conf.rxmode.offloads &=
242 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
243 bp->flags &= ~BNXT_FLAG_JUMBO;
246 /* THOR does not support ring groups.
247 * But we will use the array to save RSS context IDs.
249 if (BNXT_CHIP_THOR(bp))
250 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
252 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
254 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
258 rc = bnxt_alloc_hwrm_rings(bp);
260 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
264 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
266 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
270 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
273 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
274 if (bp->rx_cos_queue[i].id != 0xff) {
275 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
279 "Num pools more than FW profile\n");
283 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
289 rc = bnxt_mq_rx_configure(bp);
291 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
295 /* VNIC configuration */
296 for (i = 0; i < bp->nr_vnics; i++) {
297 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
298 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
300 rc = bnxt_vnic_grp_alloc(bp, vnic);
304 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
305 i, vnic, vnic->fw_grp_ids);
307 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
309 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
314 /* Alloc RSS context only if RSS mode is enabled */
315 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
316 int j, nr_ctxs = bnxt_rss_ctxts(bp);
319 for (j = 0; j < nr_ctxs; j++) {
320 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
326 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
330 vnic->num_lb_ctxts = nr_ctxs;
334 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
335 * setting is not available at this time, it will not be
336 * configured correctly in the CFA.
338 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
339 vnic->vlan_strip = true;
341 vnic->vlan_strip = false;
343 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
345 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
350 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
353 "HWRM vnic %d filter failure rc: %x\n",
358 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
359 rxq = bp->eth_dev->data->rx_queues[j];
362 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
363 j, rxq->vnic, rxq->vnic->fw_grp_ids);
365 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
366 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
369 rc = bnxt_vnic_rss_configure(bp, vnic);
372 "HWRM vnic set RSS failure rc: %x\n", rc);
376 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
378 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
379 DEV_RX_OFFLOAD_TCP_LRO)
380 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
382 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
384 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
387 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
391 /* check and configure queue intr-vector mapping */
392 if ((rte_intr_cap_multiple(intr_handle) ||
393 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
394 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
395 intr_vector = bp->eth_dev->data->nb_rx_queues;
396 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
397 if (intr_vector > bp->rx_cp_nr_rings) {
398 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
402 rc = rte_intr_efd_enable(intr_handle, intr_vector);
407 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
408 intr_handle->intr_vec =
409 rte_zmalloc("intr_vec",
410 bp->eth_dev->data->nb_rx_queues *
412 if (intr_handle->intr_vec == NULL) {
413 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
414 " intr_vec", bp->eth_dev->data->nb_rx_queues);
418 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
419 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
420 intr_handle->intr_vec, intr_handle->nb_efd,
421 intr_handle->max_intr);
422 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
424 intr_handle->intr_vec[queue_id] =
425 vec + BNXT_RX_VEC_START;
426 if (vec < base + intr_handle->nb_efd - 1)
431 /* enable uio/vfio intr/eventfd mapping */
432 rc = rte_intr_enable(intr_handle);
436 rc = bnxt_get_hwrm_link_config(bp, &new);
438 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
442 if (!bp->link_info.link_up) {
443 rc = bnxt_set_hwrm_link_config(bp, true);
446 "HWRM link config failure rc: %x\n", rc);
450 bnxt_print_link_info(bp->eth_dev);
455 rte_free(intr_handle->intr_vec);
457 rte_intr_efd_disable(intr_handle);
459 /* Some of the error status returned by FW may not be from errno.h */
466 static int bnxt_shutdown_nic(struct bnxt *bp)
468 bnxt_free_all_hwrm_resources(bp);
469 bnxt_free_all_filters(bp);
470 bnxt_free_all_vnics(bp);
474 static int bnxt_init_nic(struct bnxt *bp)
478 if (BNXT_HAS_RING_GRPS(bp)) {
479 rc = bnxt_init_ring_grps(bp);
485 bnxt_init_filters(bp);
491 * Device configuration and status function
494 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
495 struct rte_eth_dev_info *dev_info)
497 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
498 struct bnxt *bp = eth_dev->data->dev_private;
499 uint16_t max_vnics, i, j, vpool, vrxq;
500 unsigned int max_rx_rings;
503 rc = is_bnxt_in_error(bp);
508 dev_info->max_mac_addrs = bp->max_l2_ctx;
509 dev_info->max_hash_mac_addrs = 0;
511 /* PF/VF specifics */
513 dev_info->max_vfs = pdev->max_vfs;
515 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
516 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
517 dev_info->max_rx_queues = max_rx_rings;
518 dev_info->max_tx_queues = max_rx_rings;
519 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
520 dev_info->hash_key_size = 40;
521 max_vnics = bp->max_vnics;
524 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
525 dev_info->max_mtu = BNXT_MAX_MTU;
527 /* Fast path specifics */
528 dev_info->min_rx_bufsize = 1;
529 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
531 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
532 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
533 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
534 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
535 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
538 dev_info->default_rxconf = (struct rte_eth_rxconf) {
544 .rx_free_thresh = 32,
545 /* If no descriptors available, pkts are dropped by default */
549 dev_info->default_txconf = (struct rte_eth_txconf) {
555 .tx_free_thresh = 32,
558 eth_dev->data->dev_conf.intr_conf.lsc = 1;
560 eth_dev->data->dev_conf.intr_conf.rxq = 1;
561 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
562 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
563 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
564 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
569 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
570 * need further investigation.
574 vpool = 64; /* ETH_64_POOLS */
575 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
576 for (i = 0; i < 4; vpool >>= 1, i++) {
577 if (max_vnics > vpool) {
578 for (j = 0; j < 5; vrxq >>= 1, j++) {
579 if (dev_info->max_rx_queues > vrxq) {
585 /* Not enough resources to support VMDq */
589 /* Not enough resources to support VMDq */
593 dev_info->max_vmdq_pools = vpool;
594 dev_info->vmdq_queue_num = vrxq;
596 dev_info->vmdq_pool_base = 0;
597 dev_info->vmdq_queue_base = 0;
602 /* Configure the device based on the configuration provided */
603 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
605 struct bnxt *bp = eth_dev->data->dev_private;
606 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
609 bp->rx_queues = (void *)eth_dev->data->rx_queues;
610 bp->tx_queues = (void *)eth_dev->data->tx_queues;
611 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
612 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
614 rc = is_bnxt_in_error(bp);
618 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
619 rc = bnxt_hwrm_check_vf_rings(bp);
621 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
625 /* If a resource has already been allocated - in this case
626 * it is the async completion ring, free it. Reallocate it after
627 * resource reservation. This will ensure the resource counts
628 * are calculated correctly.
631 pthread_mutex_lock(&bp->def_cp_lock);
633 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
634 bnxt_disable_int(bp);
635 bnxt_free_cp_ring(bp, bp->async_cp_ring);
638 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
640 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
641 pthread_mutex_unlock(&bp->def_cp_lock);
645 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
646 rc = bnxt_alloc_async_cp_ring(bp);
648 pthread_mutex_unlock(&bp->def_cp_lock);
654 pthread_mutex_unlock(&bp->def_cp_lock);
656 /* legacy driver needs to get updated values */
657 rc = bnxt_hwrm_func_qcaps(bp);
659 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
664 /* Inherit new configurations */
665 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
666 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
667 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
668 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
673 if (BNXT_HAS_RING_GRPS(bp) &&
674 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
677 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
678 bp->max_vnics < eth_dev->data->nb_rx_queues)
681 bp->rx_cp_nr_rings = bp->rx_nr_rings;
682 bp->tx_cp_nr_rings = bp->tx_nr_rings;
684 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
686 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
687 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
689 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
695 "Insufficient resources to support requested config\n");
697 "Num Queues Requested: Tx %d, Rx %d\n",
698 eth_dev->data->nb_tx_queues,
699 eth_dev->data->nb_rx_queues);
701 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
702 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
703 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
709 struct rte_eth_link *link = ð_dev->data->dev_link;
711 if (link->link_status)
712 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
713 eth_dev->data->port_id,
714 (uint32_t)link->link_speed,
715 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
716 ("full-duplex") : ("half-duplex\n"));
718 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
719 eth_dev->data->port_id);
723 * Determine whether the current configuration requires support for scattered
724 * receive; return 1 if scattered receive is required and 0 if not.
726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
731 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
734 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
735 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
737 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
738 RTE_PKTMBUF_HEADROOM);
739 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
745 static eth_rx_burst_t
746 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
749 #ifndef RTE_LIBRTE_IEEE1588
751 * Vector mode receive can be enabled only if scatter rx is not
752 * in use and rx offloads are limited to VLAN stripping and
755 if (!eth_dev->data->scattered_rx &&
756 !(eth_dev->data->dev_conf.rxmode.offloads &
757 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
758 DEV_RX_OFFLOAD_KEEP_CRC |
759 DEV_RX_OFFLOAD_JUMBO_FRAME |
760 DEV_RX_OFFLOAD_IPV4_CKSUM |
761 DEV_RX_OFFLOAD_UDP_CKSUM |
762 DEV_RX_OFFLOAD_TCP_CKSUM |
763 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
764 DEV_RX_OFFLOAD_VLAN_FILTER))) {
765 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
766 eth_dev->data->port_id);
767 return bnxt_recv_pkts_vec;
769 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
770 eth_dev->data->port_id);
772 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
773 eth_dev->data->port_id,
774 eth_dev->data->scattered_rx,
775 eth_dev->data->dev_conf.rxmode.offloads);
778 return bnxt_recv_pkts;
781 static eth_tx_burst_t
782 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
785 #ifndef RTE_LIBRTE_IEEE1588
787 * Vector mode transmit can be enabled only if not using scatter rx
790 if (!eth_dev->data->scattered_rx &&
791 !eth_dev->data->dev_conf.txmode.offloads) {
792 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
793 eth_dev->data->port_id);
794 return bnxt_xmit_pkts_vec;
796 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
797 eth_dev->data->port_id);
799 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
800 eth_dev->data->port_id,
801 eth_dev->data->scattered_rx,
802 eth_dev->data->dev_conf.txmode.offloads);
805 return bnxt_xmit_pkts;
808 static int bnxt_handle_if_change_status(struct bnxt *bp)
812 /* Since fw has undergone a reset and lost all contexts,
813 * set fatal flag to not issue hwrm during cleanup
815 bp->flags |= BNXT_FLAG_FATAL_ERROR;
816 bnxt_uninit_resources(bp, true);
818 /* clear fatal flag so that re-init happens */
819 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
820 rc = bnxt_init_resources(bp, true);
822 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
827 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
829 struct bnxt *bp = eth_dev->data->dev_private;
830 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
834 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
836 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
837 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
840 rc = bnxt_hwrm_if_change(bp, 1);
842 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
843 rc = bnxt_handle_if_change_status(bp);
850 rc = bnxt_init_chip(bp);
854 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
856 bnxt_link_update_op(eth_dev, 1);
858 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
859 vlan_mask |= ETH_VLAN_FILTER_MASK;
860 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
861 vlan_mask |= ETH_VLAN_STRIP_MASK;
862 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
866 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
867 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
869 bp->flags |= BNXT_FLAG_INIT_DONE;
870 eth_dev->data->dev_started = 1;
872 bnxt_schedule_fw_health_check(bp);
876 bnxt_hwrm_if_change(bp, 0);
877 bnxt_shutdown_nic(bp);
878 bnxt_free_tx_mbufs(bp);
879 bnxt_free_rx_mbufs(bp);
883 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
885 struct bnxt *bp = eth_dev->data->dev_private;
888 if (!bp->link_info.link_up)
889 rc = bnxt_set_hwrm_link_config(bp, true);
891 eth_dev->data->dev_link.link_status = 1;
893 bnxt_print_link_info(eth_dev);
897 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
899 struct bnxt *bp = eth_dev->data->dev_private;
901 eth_dev->data->dev_link.link_status = 0;
902 bnxt_set_hwrm_link_config(bp, false);
903 bp->link_info.link_up = 0;
908 /* Unload the driver, release resources */
909 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
911 struct bnxt *bp = eth_dev->data->dev_private;
912 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
913 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
915 eth_dev->data->dev_started = 0;
916 /* Prevent crashes when queues are still in use */
917 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
918 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
920 bnxt_disable_int(bp);
922 /* disable uio/vfio intr/eventfd mapping */
923 rte_intr_disable(intr_handle);
925 bnxt_cancel_fw_health_check(bp);
927 bp->flags &= ~BNXT_FLAG_INIT_DONE;
928 if (bp->eth_dev->data->dev_started) {
929 /* TBD: STOP HW queues DMA */
930 eth_dev->data->dev_link.link_status = 0;
932 bnxt_dev_set_link_down_op(eth_dev);
934 /* Wait for link to be reset and the async notification to process.
935 * During reset recovery, there is no need to wait
937 if (!is_bnxt_in_error(bp))
938 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
940 /* Clean queue intr-vector mapping */
941 rte_intr_efd_disable(intr_handle);
942 if (intr_handle->intr_vec != NULL) {
943 rte_free(intr_handle->intr_vec);
944 intr_handle->intr_vec = NULL;
947 bnxt_hwrm_port_clr_stats(bp);
948 bnxt_free_tx_mbufs(bp);
949 bnxt_free_rx_mbufs(bp);
950 /* Process any remaining notifications in default completion queue */
951 bnxt_int_handler(eth_dev);
952 bnxt_shutdown_nic(bp);
953 bnxt_hwrm_if_change(bp, 0);
957 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
959 struct bnxt *bp = eth_dev->data->dev_private;
961 if (bp->dev_stopped == 0)
962 bnxt_dev_stop_op(eth_dev);
964 if (eth_dev->data->mac_addrs != NULL) {
965 rte_free(eth_dev->data->mac_addrs);
966 eth_dev->data->mac_addrs = NULL;
968 if (bp->grp_info != NULL) {
969 rte_free(bp->grp_info);
973 bnxt_dev_uninit(eth_dev);
976 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
979 struct bnxt *bp = eth_dev->data->dev_private;
980 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
981 struct bnxt_vnic_info *vnic;
982 struct bnxt_filter_info *filter, *temp_filter;
985 if (is_bnxt_in_error(bp))
989 * Loop through all VNICs from the specified filter flow pools to
990 * remove the corresponding MAC addr filter
992 for (i = 0; i < bp->nr_vnics; i++) {
993 if (!(pool_mask & (1ULL << i)))
996 vnic = &bp->vnic_info[i];
997 filter = STAILQ_FIRST(&vnic->filter);
999 temp_filter = STAILQ_NEXT(filter, next);
1000 if (filter->mac_index == index) {
1001 STAILQ_REMOVE(&vnic->filter, filter,
1002 bnxt_filter_info, next);
1003 bnxt_hwrm_clear_l2_filter(bp, filter);
1004 filter->mac_index = INVALID_MAC_INDEX;
1005 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1006 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1009 filter = temp_filter;
1014 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1015 struct rte_ether_addr *mac_addr, uint32_t index)
1017 struct bnxt_filter_info *filter;
1020 filter = STAILQ_FIRST(&vnic->filter);
1021 /* During bnxt_mac_addr_add_op, default MAC is
1022 * already programmed, so skip it. But, when
1023 * hw-vlan-filter is turned OFF from ON, default
1024 * MAC filter should be restored
1029 filter = bnxt_alloc_filter(bp);
1031 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1035 filter->mac_index = index;
1036 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1037 * if the MAC that's been programmed now is a different one, then,
1038 * copy that addr to filter->l2_addr
1041 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1044 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1046 if (filter->mac_index == 0) {
1047 filter->dflt = true;
1048 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1050 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1053 filter->mac_index = INVALID_MAC_INDEX;
1054 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1055 bnxt_free_filter(bp, filter);
1061 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1062 struct rte_ether_addr *mac_addr,
1063 uint32_t index, uint32_t pool)
1065 struct bnxt *bp = eth_dev->data->dev_private;
1066 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1067 struct bnxt_filter_info *filter;
1070 rc = is_bnxt_in_error(bp);
1074 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1075 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1080 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1083 /* Attach requested MAC address to the new l2_filter */
1084 STAILQ_FOREACH(filter, &vnic->filter, next) {
1085 if (filter->mac_index == index) {
1087 "MAC addr already existed for pool %d\n", pool);
1092 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1097 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1100 struct bnxt *bp = eth_dev->data->dev_private;
1101 struct rte_eth_link new;
1102 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1104 rc = is_bnxt_in_error(bp);
1108 memset(&new, 0, sizeof(new));
1110 /* Retrieve link info from hardware */
1111 rc = bnxt_get_hwrm_link_config(bp, &new);
1113 new.link_speed = ETH_LINK_SPEED_100M;
1114 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1116 "Failed to retrieve link rc = 0x%x!\n", rc);
1120 if (!wait_to_complete || new.link_status)
1123 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1127 /* Timed out or success */
1128 if (new.link_status != eth_dev->data->dev_link.link_status ||
1129 new.link_speed != eth_dev->data->dev_link.link_speed) {
1130 rte_eth_linkstatus_set(eth_dev, &new);
1132 _rte_eth_dev_callback_process(eth_dev,
1133 RTE_ETH_EVENT_INTR_LSC,
1136 bnxt_print_link_info(eth_dev);
1142 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1144 struct bnxt *bp = eth_dev->data->dev_private;
1145 struct bnxt_vnic_info *vnic;
1149 rc = is_bnxt_in_error(bp);
1153 if (bp->vnic_info == NULL)
1156 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1158 old_flags = vnic->flags;
1159 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1160 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1162 vnic->flags = old_flags;
1167 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1169 struct bnxt *bp = eth_dev->data->dev_private;
1170 struct bnxt_vnic_info *vnic;
1174 rc = is_bnxt_in_error(bp);
1178 if (bp->vnic_info == NULL)
1181 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1183 old_flags = vnic->flags;
1184 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1185 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1187 vnic->flags = old_flags;
1192 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1194 struct bnxt *bp = eth_dev->data->dev_private;
1195 struct bnxt_vnic_info *vnic;
1199 rc = is_bnxt_in_error(bp);
1203 if (bp->vnic_info == NULL)
1206 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1208 old_flags = vnic->flags;
1209 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1210 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1212 vnic->flags = old_flags;
1217 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1219 struct bnxt *bp = eth_dev->data->dev_private;
1220 struct bnxt_vnic_info *vnic;
1224 rc = is_bnxt_in_error(bp);
1228 if (bp->vnic_info == NULL)
1231 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1233 old_flags = vnic->flags;
1234 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1235 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1237 vnic->flags = old_flags;
1242 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1243 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1245 if (qid >= bp->rx_nr_rings)
1248 return bp->eth_dev->data->rx_queues[qid];
1251 /* Return rxq corresponding to a given rss table ring/group ID. */
1252 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1254 struct bnxt_rx_queue *rxq;
1257 if (!BNXT_HAS_RING_GRPS(bp)) {
1258 for (i = 0; i < bp->rx_nr_rings; i++) {
1259 rxq = bp->eth_dev->data->rx_queues[i];
1260 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1264 for (i = 0; i < bp->rx_nr_rings; i++) {
1265 if (bp->grp_info[i].fw_grp_id == fwr)
1270 return INVALID_HW_RING_ID;
1273 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1274 struct rte_eth_rss_reta_entry64 *reta_conf,
1277 struct bnxt *bp = eth_dev->data->dev_private;
1278 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1279 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1280 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1284 rc = is_bnxt_in_error(bp);
1288 if (!vnic->rss_table)
1291 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1294 if (reta_size != tbl_size) {
1295 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1296 "(%d) must equal the size supported by the hardware "
1297 "(%d)\n", reta_size, tbl_size);
1301 for (i = 0; i < reta_size; i++) {
1302 struct bnxt_rx_queue *rxq;
1304 idx = i / RTE_RETA_GROUP_SIZE;
1305 sft = i % RTE_RETA_GROUP_SIZE;
1307 if (!(reta_conf[idx].mask & (1ULL << sft)))
1310 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1312 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1316 if (BNXT_CHIP_THOR(bp)) {
1317 vnic->rss_table[i * 2] =
1318 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1319 vnic->rss_table[i * 2 + 1] =
1320 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1322 vnic->rss_table[i] =
1323 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1326 vnic->rss_table[i] =
1327 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1330 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1334 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1335 struct rte_eth_rss_reta_entry64 *reta_conf,
1338 struct bnxt *bp = eth_dev->data->dev_private;
1339 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1340 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1341 uint16_t idx, sft, i;
1344 rc = is_bnxt_in_error(bp);
1348 /* Retrieve from the default VNIC */
1351 if (!vnic->rss_table)
1354 if (reta_size != tbl_size) {
1355 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1356 "(%d) must equal the size supported by the hardware "
1357 "(%d)\n", reta_size, tbl_size);
1361 for (idx = 0, i = 0; i < reta_size; i++) {
1362 idx = i / RTE_RETA_GROUP_SIZE;
1363 sft = i % RTE_RETA_GROUP_SIZE;
1365 if (reta_conf[idx].mask & (1ULL << sft)) {
1368 if (BNXT_CHIP_THOR(bp))
1369 qid = bnxt_rss_to_qid(bp,
1370 vnic->rss_table[i * 2]);
1372 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1374 if (qid == INVALID_HW_RING_ID) {
1375 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1378 reta_conf[idx].reta[sft] = qid;
1385 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1386 struct rte_eth_rss_conf *rss_conf)
1388 struct bnxt *bp = eth_dev->data->dev_private;
1389 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1390 struct bnxt_vnic_info *vnic;
1393 rc = is_bnxt_in_error(bp);
1398 * If RSS enablement were different than dev_configure,
1399 * then return -EINVAL
1401 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1402 if (!rss_conf->rss_hf)
1403 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1405 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1409 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1410 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1412 /* Update the default RSS VNIC(s) */
1413 vnic = &bp->vnic_info[0];
1414 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1417 * If hashkey is not specified, use the previously configured
1420 if (!rss_conf->rss_key)
1423 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1425 "Invalid hashkey length, should be 16 bytes\n");
1428 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1431 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1435 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1436 struct rte_eth_rss_conf *rss_conf)
1438 struct bnxt *bp = eth_dev->data->dev_private;
1439 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1441 uint32_t hash_types;
1443 rc = is_bnxt_in_error(bp);
1447 /* RSS configuration is the same for all VNICs */
1448 if (vnic && vnic->rss_hash_key) {
1449 if (rss_conf->rss_key) {
1450 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1451 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1452 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1455 hash_types = vnic->hash_type;
1456 rss_conf->rss_hf = 0;
1457 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1458 rss_conf->rss_hf |= ETH_RSS_IPV4;
1459 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1461 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1462 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1464 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1466 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1467 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1469 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1471 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1472 rss_conf->rss_hf |= ETH_RSS_IPV6;
1473 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1475 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1476 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1478 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1480 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1481 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1483 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1487 "Unknwon RSS config from firmware (%08x), RSS disabled",
1492 rss_conf->rss_hf = 0;
1497 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1498 struct rte_eth_fc_conf *fc_conf)
1500 struct bnxt *bp = dev->data->dev_private;
1501 struct rte_eth_link link_info;
1504 rc = is_bnxt_in_error(bp);
1508 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1512 memset(fc_conf, 0, sizeof(*fc_conf));
1513 if (bp->link_info.auto_pause)
1514 fc_conf->autoneg = 1;
1515 switch (bp->link_info.pause) {
1517 fc_conf->mode = RTE_FC_NONE;
1519 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1520 fc_conf->mode = RTE_FC_TX_PAUSE;
1522 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1523 fc_conf->mode = RTE_FC_RX_PAUSE;
1525 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1526 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1527 fc_conf->mode = RTE_FC_FULL;
1533 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1534 struct rte_eth_fc_conf *fc_conf)
1536 struct bnxt *bp = dev->data->dev_private;
1539 rc = is_bnxt_in_error(bp);
1543 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1544 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1548 switch (fc_conf->mode) {
1550 bp->link_info.auto_pause = 0;
1551 bp->link_info.force_pause = 0;
1553 case RTE_FC_RX_PAUSE:
1554 if (fc_conf->autoneg) {
1555 bp->link_info.auto_pause =
1556 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1557 bp->link_info.force_pause = 0;
1559 bp->link_info.auto_pause = 0;
1560 bp->link_info.force_pause =
1561 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1564 case RTE_FC_TX_PAUSE:
1565 if (fc_conf->autoneg) {
1566 bp->link_info.auto_pause =
1567 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1568 bp->link_info.force_pause = 0;
1570 bp->link_info.auto_pause = 0;
1571 bp->link_info.force_pause =
1572 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1576 if (fc_conf->autoneg) {
1577 bp->link_info.auto_pause =
1578 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1579 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1580 bp->link_info.force_pause = 0;
1582 bp->link_info.auto_pause = 0;
1583 bp->link_info.force_pause =
1584 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1585 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1589 return bnxt_set_hwrm_link_config(bp, true);
1592 /* Add UDP tunneling port */
1594 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1595 struct rte_eth_udp_tunnel *udp_tunnel)
1597 struct bnxt *bp = eth_dev->data->dev_private;
1598 uint16_t tunnel_type = 0;
1601 rc = is_bnxt_in_error(bp);
1605 switch (udp_tunnel->prot_type) {
1606 case RTE_TUNNEL_TYPE_VXLAN:
1607 if (bp->vxlan_port_cnt) {
1608 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1609 udp_tunnel->udp_port);
1610 if (bp->vxlan_port != udp_tunnel->udp_port) {
1611 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1614 bp->vxlan_port_cnt++;
1618 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1619 bp->vxlan_port_cnt++;
1621 case RTE_TUNNEL_TYPE_GENEVE:
1622 if (bp->geneve_port_cnt) {
1623 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1624 udp_tunnel->udp_port);
1625 if (bp->geneve_port != udp_tunnel->udp_port) {
1626 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1629 bp->geneve_port_cnt++;
1633 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1634 bp->geneve_port_cnt++;
1637 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1640 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1646 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1647 struct rte_eth_udp_tunnel *udp_tunnel)
1649 struct bnxt *bp = eth_dev->data->dev_private;
1650 uint16_t tunnel_type = 0;
1654 rc = is_bnxt_in_error(bp);
1658 switch (udp_tunnel->prot_type) {
1659 case RTE_TUNNEL_TYPE_VXLAN:
1660 if (!bp->vxlan_port_cnt) {
1661 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1664 if (bp->vxlan_port != udp_tunnel->udp_port) {
1665 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1666 udp_tunnel->udp_port, bp->vxlan_port);
1669 if (--bp->vxlan_port_cnt)
1673 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1674 port = bp->vxlan_fw_dst_port_id;
1676 case RTE_TUNNEL_TYPE_GENEVE:
1677 if (!bp->geneve_port_cnt) {
1678 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1681 if (bp->geneve_port != udp_tunnel->udp_port) {
1682 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1683 udp_tunnel->udp_port, bp->geneve_port);
1686 if (--bp->geneve_port_cnt)
1690 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1691 port = bp->geneve_fw_dst_port_id;
1694 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1698 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1701 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1704 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1705 bp->geneve_port = 0;
1710 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1712 struct bnxt_filter_info *filter;
1713 struct bnxt_vnic_info *vnic;
1715 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1717 /* if VLAN exists && VLAN matches vlan_id
1718 * remove the MAC+VLAN filter
1719 * add a new MAC only filter
1721 * VLAN filter doesn't exist, just skip and continue
1723 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1724 filter = STAILQ_FIRST(&vnic->filter);
1726 /* Search for this matching MAC+VLAN filter */
1727 if ((filter->enables & chk) &&
1728 (filter->l2_ivlan == vlan_id &&
1729 filter->l2_ivlan_mask != 0) &&
1730 !memcmp(filter->l2_addr, bp->mac_addr,
1731 RTE_ETHER_ADDR_LEN)) {
1732 /* Delete the filter */
1733 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1736 STAILQ_REMOVE(&vnic->filter, filter,
1737 bnxt_filter_info, next);
1738 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1741 "Del Vlan filter for %d\n",
1745 filter = STAILQ_NEXT(filter, next);
1750 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1752 struct bnxt_filter_info *filter;
1753 struct bnxt_vnic_info *vnic;
1755 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1756 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1757 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1759 /* Implementation notes on the use of VNIC in this command:
1761 * By default, these filters belong to default vnic for the function.
1762 * Once these filters are set up, only destination VNIC can be modified.
1763 * If the destination VNIC is not specified in this command,
1764 * then the HWRM shall only create an l2 context id.
1767 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1768 filter = STAILQ_FIRST(&vnic->filter);
1769 /* Check if the VLAN has already been added */
1771 if ((filter->enables & chk) &&
1772 (filter->l2_ivlan == vlan_id &&
1773 filter->l2_ivlan_mask == 0x0FFF) &&
1774 !memcmp(filter->l2_addr, bp->mac_addr,
1775 RTE_ETHER_ADDR_LEN))
1778 filter = STAILQ_NEXT(filter, next);
1781 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1782 * command to create MAC+VLAN filter with the right flags, enables set.
1784 filter = bnxt_alloc_filter(bp);
1787 "MAC/VLAN filter alloc failed\n");
1790 /* MAC + VLAN ID filter */
1791 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1792 * untagged packets are received
1794 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1795 * packets and only the programmed vlan's packets are received
1797 filter->l2_ivlan = vlan_id;
1798 filter->l2_ivlan_mask = 0x0FFF;
1799 filter->enables |= en;
1800 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1802 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1804 /* Free the newly allocated filter as we were
1805 * not able to create the filter in hardware.
1807 filter->fw_l2_filter_id = UINT64_MAX;
1808 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1811 /* Add this new filter to the list */
1813 filter->dflt = true;
1814 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1816 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1821 "Added Vlan filter for %d\n", vlan_id);
1825 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1826 uint16_t vlan_id, int on)
1828 struct bnxt *bp = eth_dev->data->dev_private;
1831 rc = is_bnxt_in_error(bp);
1835 /* These operations apply to ALL existing MAC/VLAN filters */
1837 return bnxt_add_vlan_filter(bp, vlan_id);
1839 return bnxt_del_vlan_filter(bp, vlan_id);
1842 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1843 struct bnxt_vnic_info *vnic)
1845 struct bnxt_filter_info *filter;
1848 filter = STAILQ_FIRST(&vnic->filter);
1851 !memcmp(filter->l2_addr, bp->mac_addr,
1852 RTE_ETHER_ADDR_LEN)) {
1853 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1856 filter->dflt = false;
1857 STAILQ_REMOVE(&vnic->filter, filter,
1858 bnxt_filter_info, next);
1859 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1861 filter->fw_l2_filter_id = -1;
1864 filter = STAILQ_NEXT(filter, next);
1870 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1872 struct bnxt *bp = dev->data->dev_private;
1873 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1874 struct bnxt_vnic_info *vnic;
1878 rc = is_bnxt_in_error(bp);
1882 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1883 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1884 /* Remove any VLAN filters programmed */
1885 for (i = 0; i < 4095; i++)
1886 bnxt_del_vlan_filter(bp, i);
1888 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1892 /* Default filter will allow packets that match the
1893 * dest mac. So, it has to be deleted, otherwise, we
1894 * will endup receiving vlan packets for which the
1895 * filter is not programmed, when hw-vlan-filter
1896 * configuration is ON
1898 bnxt_del_dflt_mac_filter(bp, vnic);
1899 /* This filter will allow only untagged packets */
1900 bnxt_add_vlan_filter(bp, 0);
1902 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1903 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1905 if (mask & ETH_VLAN_STRIP_MASK) {
1906 /* Enable or disable VLAN stripping */
1907 for (i = 0; i < bp->nr_vnics; i++) {
1908 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1909 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1910 vnic->vlan_strip = true;
1912 vnic->vlan_strip = false;
1913 bnxt_hwrm_vnic_cfg(bp, vnic);
1915 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1916 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1919 if (mask & ETH_VLAN_EXTEND_MASK) {
1920 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1921 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1923 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1930 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1933 struct bnxt *bp = dev->data->dev_private;
1934 int qinq = dev->data->dev_conf.rxmode.offloads &
1935 DEV_RX_OFFLOAD_VLAN_EXTEND;
1937 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1938 vlan_type != ETH_VLAN_TYPE_OUTER) {
1940 "Unsupported vlan type.");
1945 "QinQ not enabled. Needs to be ON as we can "
1946 "accelerate only outer vlan\n");
1950 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1952 case RTE_ETHER_TYPE_QINQ:
1954 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1956 case RTE_ETHER_TYPE_VLAN:
1958 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1962 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1966 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1970 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1973 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1976 bp->outer_tpid_bd |= tpid;
1977 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1978 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1980 "Can accelerate only outer vlan in QinQ\n");
1988 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1989 struct rte_ether_addr *addr)
1991 struct bnxt *bp = dev->data->dev_private;
1992 /* Default Filter is tied to VNIC 0 */
1993 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1994 struct bnxt_filter_info *filter;
1997 rc = is_bnxt_in_error(bp);
2001 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2004 if (rte_is_zero_ether_addr(addr))
2007 STAILQ_FOREACH(filter, &vnic->filter, next) {
2008 /* Default Filter is at Index 0 */
2009 if (filter->mac_index != 0)
2012 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2013 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2014 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2015 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2017 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2018 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2020 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2022 memcpy(filter->l2_addr, bp->mac_addr,
2023 RTE_ETHER_ADDR_LEN);
2027 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2028 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2036 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2037 struct rte_ether_addr *mc_addr_set,
2038 uint32_t nb_mc_addr)
2040 struct bnxt *bp = eth_dev->data->dev_private;
2041 char *mc_addr_list = (char *)mc_addr_set;
2042 struct bnxt_vnic_info *vnic;
2043 uint32_t off = 0, i = 0;
2046 rc = is_bnxt_in_error(bp);
2050 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2052 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2053 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2057 /* TODO Check for Duplicate mcast addresses */
2058 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2059 for (i = 0; i < nb_mc_addr; i++) {
2060 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2061 RTE_ETHER_ADDR_LEN);
2062 off += RTE_ETHER_ADDR_LEN;
2065 vnic->mc_addr_cnt = i;
2066 if (vnic->mc_addr_cnt)
2067 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2069 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2072 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2076 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2078 struct bnxt *bp = dev->data->dev_private;
2079 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2080 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2081 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2084 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2085 fw_major, fw_minor, fw_updt);
2087 ret += 1; /* add the size of '\0' */
2088 if (fw_size < (uint32_t)ret)
2095 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2096 struct rte_eth_rxq_info *qinfo)
2098 struct bnxt_rx_queue *rxq;
2100 rxq = dev->data->rx_queues[queue_id];
2102 qinfo->mp = rxq->mb_pool;
2103 qinfo->scattered_rx = dev->data->scattered_rx;
2104 qinfo->nb_desc = rxq->nb_rx_desc;
2106 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2107 qinfo->conf.rx_drop_en = 0;
2108 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2112 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2113 struct rte_eth_txq_info *qinfo)
2115 struct bnxt_tx_queue *txq;
2117 txq = dev->data->tx_queues[queue_id];
2119 qinfo->nb_desc = txq->nb_tx_desc;
2121 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2122 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2123 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2125 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2126 qinfo->conf.tx_rs_thresh = 0;
2127 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2130 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2132 struct bnxt *bp = eth_dev->data->dev_private;
2133 uint32_t new_pkt_size;
2137 rc = is_bnxt_in_error(bp);
2141 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2142 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2146 * If vector-mode tx/rx is active, disallow any MTU change that would
2147 * require scattered receive support.
2149 if (eth_dev->data->dev_started &&
2150 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2151 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2153 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2155 "MTU change would require scattered rx support. ");
2156 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2161 if (new_mtu > RTE_ETHER_MTU) {
2162 bp->flags |= BNXT_FLAG_JUMBO;
2163 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2164 DEV_RX_OFFLOAD_JUMBO_FRAME;
2166 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2167 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2168 bp->flags &= ~BNXT_FLAG_JUMBO;
2171 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2173 for (i = 0; i < bp->nr_vnics; i++) {
2174 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2177 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2178 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2179 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2183 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2184 size -= RTE_PKTMBUF_HEADROOM;
2186 if (size < new_mtu) {
2187 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2193 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2199 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2201 struct bnxt *bp = dev->data->dev_private;
2202 uint16_t vlan = bp->vlan;
2205 rc = is_bnxt_in_error(bp);
2209 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2211 "PVID cannot be modified for this function\n");
2214 bp->vlan = on ? pvid : 0;
2216 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2223 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2225 struct bnxt *bp = dev->data->dev_private;
2228 rc = is_bnxt_in_error(bp);
2232 return bnxt_hwrm_port_led_cfg(bp, true);
2236 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2238 struct bnxt *bp = dev->data->dev_private;
2241 rc = is_bnxt_in_error(bp);
2245 return bnxt_hwrm_port_led_cfg(bp, false);
2249 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2251 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2252 uint32_t desc = 0, raw_cons = 0, cons;
2253 struct bnxt_cp_ring_info *cpr;
2254 struct bnxt_rx_queue *rxq;
2255 struct rx_pkt_cmpl *rxcmp;
2258 rc = is_bnxt_in_error(bp);
2262 rxq = dev->data->rx_queues[rx_queue_id];
2264 raw_cons = cpr->cp_raw_cons;
2267 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2268 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2269 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2271 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2283 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2285 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2286 struct bnxt_rx_ring_info *rxr;
2287 struct bnxt_cp_ring_info *cpr;
2288 struct bnxt_sw_rx_bd *rx_buf;
2289 struct rx_pkt_cmpl *rxcmp;
2290 uint32_t cons, cp_cons;
2296 rc = is_bnxt_in_error(rxq->bp);
2303 if (offset >= rxq->nb_rx_desc)
2306 cons = RING_CMP(cpr->cp_ring_struct, offset);
2307 cp_cons = cpr->cp_raw_cons;
2308 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2310 if (cons > cp_cons) {
2311 if (CMPL_VALID(rxcmp, cpr->valid))
2312 return RTE_ETH_RX_DESC_DONE;
2314 if (CMPL_VALID(rxcmp, !cpr->valid))
2315 return RTE_ETH_RX_DESC_DONE;
2317 rx_buf = &rxr->rx_buf_ring[cons];
2318 if (rx_buf->mbuf == NULL)
2319 return RTE_ETH_RX_DESC_UNAVAIL;
2322 return RTE_ETH_RX_DESC_AVAIL;
2326 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2328 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2329 struct bnxt_tx_ring_info *txr;
2330 struct bnxt_cp_ring_info *cpr;
2331 struct bnxt_sw_tx_bd *tx_buf;
2332 struct tx_pkt_cmpl *txcmp;
2333 uint32_t cons, cp_cons;
2339 rc = is_bnxt_in_error(txq->bp);
2346 if (offset >= txq->nb_tx_desc)
2349 cons = RING_CMP(cpr->cp_ring_struct, offset);
2350 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2351 cp_cons = cpr->cp_raw_cons;
2353 if (cons > cp_cons) {
2354 if (CMPL_VALID(txcmp, cpr->valid))
2355 return RTE_ETH_TX_DESC_UNAVAIL;
2357 if (CMPL_VALID(txcmp, !cpr->valid))
2358 return RTE_ETH_TX_DESC_UNAVAIL;
2360 tx_buf = &txr->tx_buf_ring[cons];
2361 if (tx_buf->mbuf == NULL)
2362 return RTE_ETH_TX_DESC_DONE;
2364 return RTE_ETH_TX_DESC_FULL;
2367 static struct bnxt_filter_info *
2368 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2369 struct rte_eth_ethertype_filter *efilter,
2370 struct bnxt_vnic_info *vnic0,
2371 struct bnxt_vnic_info *vnic,
2374 struct bnxt_filter_info *mfilter = NULL;
2378 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2379 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2380 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2381 " ethertype filter.", efilter->ether_type);
2385 if (efilter->queue >= bp->rx_nr_rings) {
2386 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2391 vnic0 = &bp->vnic_info[0];
2392 vnic = &bp->vnic_info[efilter->queue];
2394 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2399 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2400 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2401 if ((!memcmp(efilter->mac_addr.addr_bytes,
2402 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2404 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2405 mfilter->ethertype == efilter->ether_type)) {
2411 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2412 if ((!memcmp(efilter->mac_addr.addr_bytes,
2413 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2414 mfilter->ethertype == efilter->ether_type &&
2416 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2430 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2431 enum rte_filter_op filter_op,
2434 struct bnxt *bp = dev->data->dev_private;
2435 struct rte_eth_ethertype_filter *efilter =
2436 (struct rte_eth_ethertype_filter *)arg;
2437 struct bnxt_filter_info *bfilter, *filter1;
2438 struct bnxt_vnic_info *vnic, *vnic0;
2441 if (filter_op == RTE_ETH_FILTER_NOP)
2445 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2450 vnic0 = &bp->vnic_info[0];
2451 vnic = &bp->vnic_info[efilter->queue];
2453 switch (filter_op) {
2454 case RTE_ETH_FILTER_ADD:
2455 bnxt_match_and_validate_ether_filter(bp, efilter,
2460 bfilter = bnxt_get_unused_filter(bp);
2461 if (bfilter == NULL) {
2463 "Not enough resources for a new filter.\n");
2466 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2467 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2468 RTE_ETHER_ADDR_LEN);
2469 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2470 RTE_ETHER_ADDR_LEN);
2471 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2472 bfilter->ethertype = efilter->ether_type;
2473 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2475 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2476 if (filter1 == NULL) {
2481 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2482 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2484 bfilter->dst_id = vnic->fw_vnic_id;
2486 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2488 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2491 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2494 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2496 case RTE_ETH_FILTER_DELETE:
2497 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2499 if (ret == -EEXIST) {
2500 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2502 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2504 bnxt_free_filter(bp, filter1);
2505 } else if (ret == 0) {
2506 PMD_DRV_LOG(ERR, "No matching filter found\n");
2510 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2516 bnxt_free_filter(bp, bfilter);
2522 parse_ntuple_filter(struct bnxt *bp,
2523 struct rte_eth_ntuple_filter *nfilter,
2524 struct bnxt_filter_info *bfilter)
2528 if (nfilter->queue >= bp->rx_nr_rings) {
2529 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2533 switch (nfilter->dst_port_mask) {
2535 bfilter->dst_port_mask = -1;
2536 bfilter->dst_port = nfilter->dst_port;
2537 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2538 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2541 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2545 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2546 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2548 switch (nfilter->proto_mask) {
2550 if (nfilter->proto == 17) /* IPPROTO_UDP */
2551 bfilter->ip_protocol = 17;
2552 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2553 bfilter->ip_protocol = 6;
2556 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2559 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2563 switch (nfilter->dst_ip_mask) {
2565 bfilter->dst_ipaddr_mask[0] = -1;
2566 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2567 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2568 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2571 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2575 switch (nfilter->src_ip_mask) {
2577 bfilter->src_ipaddr_mask[0] = -1;
2578 bfilter->src_ipaddr[0] = nfilter->src_ip;
2579 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2580 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2583 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2587 switch (nfilter->src_port_mask) {
2589 bfilter->src_port_mask = -1;
2590 bfilter->src_port = nfilter->src_port;
2591 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2592 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2595 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2600 //nfilter->priority = (uint8_t)filter->priority;
2602 bfilter->enables = en;
2606 static struct bnxt_filter_info*
2607 bnxt_match_ntuple_filter(struct bnxt *bp,
2608 struct bnxt_filter_info *bfilter,
2609 struct bnxt_vnic_info **mvnic)
2611 struct bnxt_filter_info *mfilter = NULL;
2614 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2615 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2616 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2617 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2618 bfilter->src_ipaddr_mask[0] ==
2619 mfilter->src_ipaddr_mask[0] &&
2620 bfilter->src_port == mfilter->src_port &&
2621 bfilter->src_port_mask == mfilter->src_port_mask &&
2622 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2623 bfilter->dst_ipaddr_mask[0] ==
2624 mfilter->dst_ipaddr_mask[0] &&
2625 bfilter->dst_port == mfilter->dst_port &&
2626 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2627 bfilter->flags == mfilter->flags &&
2628 bfilter->enables == mfilter->enables) {
2639 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2640 struct rte_eth_ntuple_filter *nfilter,
2641 enum rte_filter_op filter_op)
2643 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2644 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2647 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2648 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2652 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2653 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2657 bfilter = bnxt_get_unused_filter(bp);
2658 if (bfilter == NULL) {
2660 "Not enough resources for a new filter.\n");
2663 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2667 vnic = &bp->vnic_info[nfilter->queue];
2668 vnic0 = &bp->vnic_info[0];
2669 filter1 = STAILQ_FIRST(&vnic0->filter);
2670 if (filter1 == NULL) {
2675 bfilter->dst_id = vnic->fw_vnic_id;
2676 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2678 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2679 bfilter->ethertype = 0x800;
2680 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2682 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2684 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2685 bfilter->dst_id == mfilter->dst_id) {
2686 PMD_DRV_LOG(ERR, "filter exists.\n");
2689 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2690 bfilter->dst_id != mfilter->dst_id) {
2691 mfilter->dst_id = vnic->fw_vnic_id;
2692 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2693 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2694 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2695 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2696 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2699 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2700 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2705 if (filter_op == RTE_ETH_FILTER_ADD) {
2706 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2707 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2710 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2712 if (mfilter == NULL) {
2713 /* This should not happen. But for Coverity! */
2717 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2719 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2720 bnxt_free_filter(bp, mfilter);
2721 mfilter->fw_l2_filter_id = -1;
2722 bnxt_free_filter(bp, bfilter);
2723 bfilter->fw_l2_filter_id = -1;
2728 bfilter->fw_l2_filter_id = -1;
2729 bnxt_free_filter(bp, bfilter);
2734 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2735 enum rte_filter_op filter_op,
2738 struct bnxt *bp = dev->data->dev_private;
2741 if (filter_op == RTE_ETH_FILTER_NOP)
2745 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2750 switch (filter_op) {
2751 case RTE_ETH_FILTER_ADD:
2752 ret = bnxt_cfg_ntuple_filter(bp,
2753 (struct rte_eth_ntuple_filter *)arg,
2756 case RTE_ETH_FILTER_DELETE:
2757 ret = bnxt_cfg_ntuple_filter(bp,
2758 (struct rte_eth_ntuple_filter *)arg,
2762 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2770 bnxt_parse_fdir_filter(struct bnxt *bp,
2771 struct rte_eth_fdir_filter *fdir,
2772 struct bnxt_filter_info *filter)
2774 enum rte_fdir_mode fdir_mode =
2775 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2776 struct bnxt_vnic_info *vnic0, *vnic;
2777 struct bnxt_filter_info *filter1;
2781 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2784 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2785 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2787 switch (fdir->input.flow_type) {
2788 case RTE_ETH_FLOW_IPV4:
2789 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2791 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2792 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2793 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2794 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2795 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2796 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2797 filter->ip_addr_type =
2798 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2799 filter->src_ipaddr_mask[0] = 0xffffffff;
2800 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2801 filter->dst_ipaddr_mask[0] = 0xffffffff;
2802 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2803 filter->ethertype = 0x800;
2804 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2806 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2807 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2808 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2809 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2810 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2811 filter->dst_port_mask = 0xffff;
2812 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2813 filter->src_port_mask = 0xffff;
2814 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2815 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2816 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2817 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2818 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2819 filter->ip_protocol = 6;
2820 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2821 filter->ip_addr_type =
2822 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2823 filter->src_ipaddr_mask[0] = 0xffffffff;
2824 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2825 filter->dst_ipaddr_mask[0] = 0xffffffff;
2826 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2827 filter->ethertype = 0x800;
2828 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2830 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2831 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2832 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2833 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2834 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2835 filter->dst_port_mask = 0xffff;
2836 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2837 filter->src_port_mask = 0xffff;
2838 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2839 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2840 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2841 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2842 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2843 filter->ip_protocol = 17;
2844 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2845 filter->ip_addr_type =
2846 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2847 filter->src_ipaddr_mask[0] = 0xffffffff;
2848 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2849 filter->dst_ipaddr_mask[0] = 0xffffffff;
2850 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2851 filter->ethertype = 0x800;
2852 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2854 case RTE_ETH_FLOW_IPV6:
2855 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2857 filter->ip_addr_type =
2858 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2859 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2860 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2861 rte_memcpy(filter->src_ipaddr,
2862 fdir->input.flow.ipv6_flow.src_ip, 16);
2863 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2864 rte_memcpy(filter->dst_ipaddr,
2865 fdir->input.flow.ipv6_flow.dst_ip, 16);
2866 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2867 memset(filter->dst_ipaddr_mask, 0xff, 16);
2868 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2869 memset(filter->src_ipaddr_mask, 0xff, 16);
2870 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2871 filter->ethertype = 0x86dd;
2872 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2874 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2875 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2876 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2877 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2878 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2879 filter->dst_port_mask = 0xffff;
2880 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2881 filter->src_port_mask = 0xffff;
2882 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2883 filter->ip_addr_type =
2884 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2885 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2886 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2887 rte_memcpy(filter->src_ipaddr,
2888 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2889 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2890 rte_memcpy(filter->dst_ipaddr,
2891 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2893 memset(filter->dst_ipaddr_mask, 0xff, 16);
2894 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2895 memset(filter->src_ipaddr_mask, 0xff, 16);
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2897 filter->ethertype = 0x86dd;
2898 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2900 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2901 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2902 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2903 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2905 filter->dst_port_mask = 0xffff;
2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2907 filter->src_port_mask = 0xffff;
2908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2909 filter->ip_addr_type =
2910 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2911 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2912 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2913 rte_memcpy(filter->src_ipaddr,
2914 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2915 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2916 rte_memcpy(filter->dst_ipaddr,
2917 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2919 memset(filter->dst_ipaddr_mask, 0xff, 16);
2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2921 memset(filter->src_ipaddr_mask, 0xff, 16);
2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2923 filter->ethertype = 0x86dd;
2924 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2926 case RTE_ETH_FLOW_L2_PAYLOAD:
2927 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2930 case RTE_ETH_FLOW_VXLAN:
2931 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2933 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2934 filter->tunnel_type =
2935 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2936 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2938 case RTE_ETH_FLOW_NVGRE:
2939 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2941 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2942 filter->tunnel_type =
2943 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2944 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2946 case RTE_ETH_FLOW_UNKNOWN:
2947 case RTE_ETH_FLOW_RAW:
2948 case RTE_ETH_FLOW_FRAG_IPV4:
2949 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2950 case RTE_ETH_FLOW_FRAG_IPV6:
2951 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2952 case RTE_ETH_FLOW_IPV6_EX:
2953 case RTE_ETH_FLOW_IPV6_TCP_EX:
2954 case RTE_ETH_FLOW_IPV6_UDP_EX:
2955 case RTE_ETH_FLOW_GENEVE:
2961 vnic0 = &bp->vnic_info[0];
2962 vnic = &bp->vnic_info[fdir->action.rx_queue];
2964 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2968 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2969 rte_memcpy(filter->dst_macaddr,
2970 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2971 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2974 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2975 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2976 filter1 = STAILQ_FIRST(&vnic0->filter);
2977 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2979 filter->dst_id = vnic->fw_vnic_id;
2980 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2981 if (filter->dst_macaddr[i] == 0x00)
2982 filter1 = STAILQ_FIRST(&vnic0->filter);
2984 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2987 if (filter1 == NULL)
2990 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2991 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2993 filter->enables = en;
2998 static struct bnxt_filter_info *
2999 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3000 struct bnxt_vnic_info **mvnic)
3002 struct bnxt_filter_info *mf = NULL;
3005 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3006 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3008 STAILQ_FOREACH(mf, &vnic->filter, next) {
3009 if (mf->filter_type == nf->filter_type &&
3010 mf->flags == nf->flags &&
3011 mf->src_port == nf->src_port &&
3012 mf->src_port_mask == nf->src_port_mask &&
3013 mf->dst_port == nf->dst_port &&
3014 mf->dst_port_mask == nf->dst_port_mask &&
3015 mf->ip_protocol == nf->ip_protocol &&
3016 mf->ip_addr_type == nf->ip_addr_type &&
3017 mf->ethertype == nf->ethertype &&
3018 mf->vni == nf->vni &&
3019 mf->tunnel_type == nf->tunnel_type &&
3020 mf->l2_ovlan == nf->l2_ovlan &&
3021 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3022 mf->l2_ivlan == nf->l2_ivlan &&
3023 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3024 !memcmp(mf->l2_addr, nf->l2_addr,
3025 RTE_ETHER_ADDR_LEN) &&
3026 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3027 RTE_ETHER_ADDR_LEN) &&
3028 !memcmp(mf->src_macaddr, nf->src_macaddr,
3029 RTE_ETHER_ADDR_LEN) &&
3030 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3031 RTE_ETHER_ADDR_LEN) &&
3032 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3033 sizeof(nf->src_ipaddr)) &&
3034 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3035 sizeof(nf->src_ipaddr_mask)) &&
3036 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3037 sizeof(nf->dst_ipaddr)) &&
3038 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3039 sizeof(nf->dst_ipaddr_mask))) {
3050 bnxt_fdir_filter(struct rte_eth_dev *dev,
3051 enum rte_filter_op filter_op,
3054 struct bnxt *bp = dev->data->dev_private;
3055 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3056 struct bnxt_filter_info *filter, *match;
3057 struct bnxt_vnic_info *vnic, *mvnic;
3060 if (filter_op == RTE_ETH_FILTER_NOP)
3063 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3066 switch (filter_op) {
3067 case RTE_ETH_FILTER_ADD:
3068 case RTE_ETH_FILTER_DELETE:
3070 filter = bnxt_get_unused_filter(bp);
3071 if (filter == NULL) {
3073 "Not enough resources for a new flow.\n");
3077 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3080 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3082 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3083 vnic = &bp->vnic_info[0];
3085 vnic = &bp->vnic_info[fdir->action.rx_queue];
3087 match = bnxt_match_fdir(bp, filter, &mvnic);
3088 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3089 if (match->dst_id == vnic->fw_vnic_id) {
3090 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3094 match->dst_id = vnic->fw_vnic_id;
3095 ret = bnxt_hwrm_set_ntuple_filter(bp,
3098 STAILQ_REMOVE(&mvnic->filter, match,
3099 bnxt_filter_info, next);
3100 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3102 "Filter with matching pattern exist\n");
3104 "Updated it to new destination q\n");
3108 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3109 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3114 if (filter_op == RTE_ETH_FILTER_ADD) {
3115 ret = bnxt_hwrm_set_ntuple_filter(bp,
3120 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3122 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3123 STAILQ_REMOVE(&vnic->filter, match,
3124 bnxt_filter_info, next);
3125 bnxt_free_filter(bp, match);
3126 filter->fw_l2_filter_id = -1;
3127 bnxt_free_filter(bp, filter);
3130 case RTE_ETH_FILTER_FLUSH:
3131 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3132 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3134 STAILQ_FOREACH(filter, &vnic->filter, next) {
3135 if (filter->filter_type ==
3136 HWRM_CFA_NTUPLE_FILTER) {
3138 bnxt_hwrm_clear_ntuple_filter(bp,
3140 STAILQ_REMOVE(&vnic->filter, filter,
3141 bnxt_filter_info, next);
3146 case RTE_ETH_FILTER_UPDATE:
3147 case RTE_ETH_FILTER_STATS:
3148 case RTE_ETH_FILTER_INFO:
3149 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3152 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3159 filter->fw_l2_filter_id = -1;
3160 bnxt_free_filter(bp, filter);
3165 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3166 enum rte_filter_type filter_type,
3167 enum rte_filter_op filter_op, void *arg)
3171 ret = is_bnxt_in_error(dev->data->dev_private);
3175 switch (filter_type) {
3176 case RTE_ETH_FILTER_TUNNEL:
3178 "filter type: %d: To be implemented\n", filter_type);
3180 case RTE_ETH_FILTER_FDIR:
3181 ret = bnxt_fdir_filter(dev, filter_op, arg);
3183 case RTE_ETH_FILTER_NTUPLE:
3184 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3186 case RTE_ETH_FILTER_ETHERTYPE:
3187 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3189 case RTE_ETH_FILTER_GENERIC:
3190 if (filter_op != RTE_ETH_FILTER_GET)
3192 *(const void **)arg = &bnxt_flow_ops;
3196 "Filter type (%d) not supported", filter_type);
3203 static const uint32_t *
3204 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3206 static const uint32_t ptypes[] = {
3207 RTE_PTYPE_L2_ETHER_VLAN,
3208 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3209 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3215 RTE_PTYPE_INNER_L4_ICMP,
3216 RTE_PTYPE_INNER_L4_TCP,
3217 RTE_PTYPE_INNER_L4_UDP,
3221 if (!dev->rx_pkt_burst)
3227 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3230 uint32_t reg_base = *reg_arr & 0xfffff000;
3234 for (i = 0; i < count; i++) {
3235 if ((reg_arr[i] & 0xfffff000) != reg_base)
3238 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3239 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3243 static int bnxt_map_ptp_regs(struct bnxt *bp)
3245 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3249 reg_arr = ptp->rx_regs;
3250 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3254 reg_arr = ptp->tx_regs;
3255 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3259 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3260 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3262 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3263 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3268 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3270 rte_write32(0, (uint8_t *)bp->bar0 +
3271 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3272 rte_write32(0, (uint8_t *)bp->bar0 +
3273 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3276 static uint64_t bnxt_cc_read(struct bnxt *bp)
3280 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3281 BNXT_GRCPF_REG_SYNC_TIME));
3282 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3283 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3287 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3289 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3292 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3293 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3294 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3297 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3298 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3299 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3300 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3301 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3302 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3307 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3309 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3310 struct bnxt_pf_info *pf = &bp->pf;
3317 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3318 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3319 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3322 port_id = pf->port_id;
3323 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3324 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3326 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3327 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3328 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3329 /* bnxt_clr_rx_ts(bp); TBD */
3333 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3334 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3335 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3336 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3342 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3345 struct bnxt *bp = dev->data->dev_private;
3346 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3351 ns = rte_timespec_to_ns(ts);
3352 /* Set the timecounters to a new value. */
3359 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3361 struct bnxt *bp = dev->data->dev_private;
3362 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3363 uint64_t ns, systime_cycles = 0;
3369 if (BNXT_CHIP_THOR(bp))
3370 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3373 systime_cycles = bnxt_cc_read(bp);
3375 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3376 *ts = rte_ns_to_timespec(ns);
3381 bnxt_timesync_enable(struct rte_eth_dev *dev)
3383 struct bnxt *bp = dev->data->dev_private;
3384 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3392 ptp->tx_tstamp_en = 1;
3393 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3395 rc = bnxt_hwrm_ptp_cfg(bp);
3399 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3400 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3401 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3403 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3404 ptp->tc.cc_shift = shift;
3405 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3407 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3408 ptp->rx_tstamp_tc.cc_shift = shift;
3409 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3411 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3412 ptp->tx_tstamp_tc.cc_shift = shift;
3413 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3415 if (!BNXT_CHIP_THOR(bp))
3416 bnxt_map_ptp_regs(bp);
3422 bnxt_timesync_disable(struct rte_eth_dev *dev)
3424 struct bnxt *bp = dev->data->dev_private;
3425 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3431 ptp->tx_tstamp_en = 0;
3434 bnxt_hwrm_ptp_cfg(bp);
3436 if (!BNXT_CHIP_THOR(bp))
3437 bnxt_unmap_ptp_regs(bp);
3443 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3444 struct timespec *timestamp,
3445 uint32_t flags __rte_unused)
3447 struct bnxt *bp = dev->data->dev_private;
3448 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3449 uint64_t rx_tstamp_cycles = 0;
3455 if (BNXT_CHIP_THOR(bp))
3456 rx_tstamp_cycles = ptp->rx_timestamp;
3458 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3460 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3461 *timestamp = rte_ns_to_timespec(ns);
3466 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3467 struct timespec *timestamp)
3469 struct bnxt *bp = dev->data->dev_private;
3470 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3471 uint64_t tx_tstamp_cycles = 0;
3478 if (BNXT_CHIP_THOR(bp))
3479 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3482 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3484 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3485 *timestamp = rte_ns_to_timespec(ns);
3491 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3493 struct bnxt *bp = dev->data->dev_private;
3494 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3499 ptp->tc.nsec += delta;
3505 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3507 struct bnxt *bp = dev->data->dev_private;
3509 uint32_t dir_entries;
3510 uint32_t entry_length;
3512 rc = is_bnxt_in_error(bp);
3516 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3517 bp->pdev->addr.domain, bp->pdev->addr.bus,
3518 bp->pdev->addr.devid, bp->pdev->addr.function);
3520 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3524 return dir_entries * entry_length;
3528 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3529 struct rte_dev_eeprom_info *in_eeprom)
3531 struct bnxt *bp = dev->data->dev_private;
3536 rc = is_bnxt_in_error(bp);
3540 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3541 "len = %d\n", bp->pdev->addr.domain,
3542 bp->pdev->addr.bus, bp->pdev->addr.devid,
3543 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3545 if (in_eeprom->offset == 0) /* special offset value to get directory */
3546 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3549 index = in_eeprom->offset >> 24;
3550 offset = in_eeprom->offset & 0xffffff;
3553 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3554 in_eeprom->length, in_eeprom->data);
3559 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3562 case BNX_DIR_TYPE_CHIMP_PATCH:
3563 case BNX_DIR_TYPE_BOOTCODE:
3564 case BNX_DIR_TYPE_BOOTCODE_2:
3565 case BNX_DIR_TYPE_APE_FW:
3566 case BNX_DIR_TYPE_APE_PATCH:
3567 case BNX_DIR_TYPE_KONG_FW:
3568 case BNX_DIR_TYPE_KONG_PATCH:
3569 case BNX_DIR_TYPE_BONO_FW:
3570 case BNX_DIR_TYPE_BONO_PATCH:
3578 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3581 case BNX_DIR_TYPE_AVS:
3582 case BNX_DIR_TYPE_EXP_ROM_MBA:
3583 case BNX_DIR_TYPE_PCIE:
3584 case BNX_DIR_TYPE_TSCF_UCODE:
3585 case BNX_DIR_TYPE_EXT_PHY:
3586 case BNX_DIR_TYPE_CCM:
3587 case BNX_DIR_TYPE_ISCSI_BOOT:
3588 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3589 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3597 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3599 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3600 bnxt_dir_type_is_other_exec_format(dir_type);
3604 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3605 struct rte_dev_eeprom_info *in_eeprom)
3607 struct bnxt *bp = dev->data->dev_private;
3608 uint8_t index, dir_op;
3609 uint16_t type, ext, ordinal, attr;
3612 rc = is_bnxt_in_error(bp);
3616 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3617 "len = %d\n", bp->pdev->addr.domain,
3618 bp->pdev->addr.bus, bp->pdev->addr.devid,
3619 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3622 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3626 type = in_eeprom->magic >> 16;
3628 if (type == 0xffff) { /* special value for directory operations */
3629 index = in_eeprom->magic & 0xff;
3630 dir_op = in_eeprom->magic >> 8;
3634 case 0x0e: /* erase */
3635 if (in_eeprom->offset != ~in_eeprom->magic)
3637 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3643 /* Create or re-write an NVM item: */
3644 if (bnxt_dir_type_is_executable(type) == true)
3646 ext = in_eeprom->magic & 0xffff;
3647 ordinal = in_eeprom->offset >> 16;
3648 attr = in_eeprom->offset & 0xffff;
3650 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3651 in_eeprom->data, in_eeprom->length);
3658 static const struct eth_dev_ops bnxt_dev_ops = {
3659 .dev_infos_get = bnxt_dev_info_get_op,
3660 .dev_close = bnxt_dev_close_op,
3661 .dev_configure = bnxt_dev_configure_op,
3662 .dev_start = bnxt_dev_start_op,
3663 .dev_stop = bnxt_dev_stop_op,
3664 .dev_set_link_up = bnxt_dev_set_link_up_op,
3665 .dev_set_link_down = bnxt_dev_set_link_down_op,
3666 .stats_get = bnxt_stats_get_op,
3667 .stats_reset = bnxt_stats_reset_op,
3668 .rx_queue_setup = bnxt_rx_queue_setup_op,
3669 .rx_queue_release = bnxt_rx_queue_release_op,
3670 .tx_queue_setup = bnxt_tx_queue_setup_op,
3671 .tx_queue_release = bnxt_tx_queue_release_op,
3672 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3673 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3674 .reta_update = bnxt_reta_update_op,
3675 .reta_query = bnxt_reta_query_op,
3676 .rss_hash_update = bnxt_rss_hash_update_op,
3677 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3678 .link_update = bnxt_link_update_op,
3679 .promiscuous_enable = bnxt_promiscuous_enable_op,
3680 .promiscuous_disable = bnxt_promiscuous_disable_op,
3681 .allmulticast_enable = bnxt_allmulticast_enable_op,
3682 .allmulticast_disable = bnxt_allmulticast_disable_op,
3683 .mac_addr_add = bnxt_mac_addr_add_op,
3684 .mac_addr_remove = bnxt_mac_addr_remove_op,
3685 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3686 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3687 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3688 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3689 .vlan_filter_set = bnxt_vlan_filter_set_op,
3690 .vlan_offload_set = bnxt_vlan_offload_set_op,
3691 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3692 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3693 .mtu_set = bnxt_mtu_set_op,
3694 .mac_addr_set = bnxt_set_default_mac_addr_op,
3695 .xstats_get = bnxt_dev_xstats_get_op,
3696 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3697 .xstats_reset = bnxt_dev_xstats_reset_op,
3698 .fw_version_get = bnxt_fw_version_get,
3699 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3700 .rxq_info_get = bnxt_rxq_info_get_op,
3701 .txq_info_get = bnxt_txq_info_get_op,
3702 .dev_led_on = bnxt_dev_led_on_op,
3703 .dev_led_off = bnxt_dev_led_off_op,
3704 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3705 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3706 .rx_queue_count = bnxt_rx_queue_count_op,
3707 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3708 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3709 .rx_queue_start = bnxt_rx_queue_start,
3710 .rx_queue_stop = bnxt_rx_queue_stop,
3711 .tx_queue_start = bnxt_tx_queue_start,
3712 .tx_queue_stop = bnxt_tx_queue_stop,
3713 .filter_ctrl = bnxt_filter_ctrl_op,
3714 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3715 .get_eeprom_length = bnxt_get_eeprom_length_op,
3716 .get_eeprom = bnxt_get_eeprom_op,
3717 .set_eeprom = bnxt_set_eeprom_op,
3718 .timesync_enable = bnxt_timesync_enable,
3719 .timesync_disable = bnxt_timesync_disable,
3720 .timesync_read_time = bnxt_timesync_read_time,
3721 .timesync_write_time = bnxt_timesync_write_time,
3722 .timesync_adjust_time = bnxt_timesync_adjust_time,
3723 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3724 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3727 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3731 /* Only pre-map the reset GRC registers using window 3 */
3732 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3733 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3735 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3740 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3742 struct bnxt_error_recovery_info *info = bp->recovery_info;
3743 uint32_t reg_base = 0xffffffff;
3746 /* Only pre-map the monitoring GRC registers using window 2 */
3747 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3748 uint32_t reg = info->status_regs[i];
3750 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3753 if (reg_base == 0xffffffff)
3754 reg_base = reg & 0xfffff000;
3755 if ((reg & 0xfffff000) != reg_base)
3758 /* Use mask 0xffc as the Lower 2 bits indicates
3759 * address space location
3761 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3765 if (reg_base == 0xffffffff)
3768 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3769 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3774 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3776 struct bnxt_error_recovery_info *info = bp->recovery_info;
3777 uint32_t delay = info->delay_after_reset[index];
3778 uint32_t val = info->reset_reg_val[index];
3779 uint32_t reg = info->reset_reg[index];
3780 uint32_t type, offset;
3782 type = BNXT_FW_STATUS_REG_TYPE(reg);
3783 offset = BNXT_FW_STATUS_REG_OFF(reg);
3786 case BNXT_FW_STATUS_REG_TYPE_CFG:
3787 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3789 case BNXT_FW_STATUS_REG_TYPE_GRC:
3790 offset = bnxt_map_reset_regs(bp, offset);
3791 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3793 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3794 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3797 /* wait on a specific interval of time until core reset is complete */
3799 rte_delay_ms(delay);
3802 static void bnxt_dev_cleanup(struct bnxt *bp)
3804 bnxt_set_hwrm_link_config(bp, false);
3805 bp->link_info.link_up = 0;
3806 if (bp->dev_stopped == 0)
3807 bnxt_dev_stop_op(bp->eth_dev);
3809 bnxt_uninit_resources(bp, true);
3812 static int bnxt_restore_filters(struct bnxt *bp)
3814 struct rte_eth_dev *dev = bp->eth_dev;
3817 if (dev->data->all_multicast)
3818 ret = bnxt_allmulticast_enable_op(dev);
3819 if (dev->data->promiscuous)
3820 ret = bnxt_promiscuous_enable_op(dev);
3822 /* TODO restore other filters as well */
3826 static void bnxt_dev_recover(void *arg)
3828 struct bnxt *bp = arg;
3829 int timeout = bp->fw_reset_max_msecs;
3832 /* Clear Error flag so that device re-init should happen */
3833 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3836 rc = bnxt_hwrm_ver_get(bp);
3839 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3840 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3841 } while (rc && timeout);
3844 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3848 rc = bnxt_init_resources(bp, true);
3851 "Failed to initialize resources after reset\n");
3854 /* clear reset flag as the device is initialized now */
3855 bp->flags &= ~BNXT_FLAG_FW_RESET;
3857 rc = bnxt_dev_start_op(bp->eth_dev);
3859 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3863 rc = bnxt_restore_filters(bp);
3867 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3870 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3871 bnxt_uninit_resources(bp, false);
3872 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3875 void bnxt_dev_reset_and_resume(void *arg)
3877 struct bnxt *bp = arg;
3880 bnxt_dev_cleanup(bp);
3882 bnxt_wait_for_device_shutdown(bp);
3884 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3885 bnxt_dev_recover, (void *)bp);
3887 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3890 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3892 struct bnxt_error_recovery_info *info = bp->recovery_info;
3893 uint32_t reg = info->status_regs[index];
3894 uint32_t type, offset, val = 0;
3896 type = BNXT_FW_STATUS_REG_TYPE(reg);
3897 offset = BNXT_FW_STATUS_REG_OFF(reg);
3900 case BNXT_FW_STATUS_REG_TYPE_CFG:
3901 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3903 case BNXT_FW_STATUS_REG_TYPE_GRC:
3904 offset = info->mapped_status_regs[index];
3906 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3907 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3915 static int bnxt_fw_reset_all(struct bnxt *bp)
3917 struct bnxt_error_recovery_info *info = bp->recovery_info;
3921 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3922 /* Reset through master function driver */
3923 for (i = 0; i < info->reg_array_cnt; i++)
3924 bnxt_write_fw_reset_reg(bp, i);
3925 /* Wait for time specified by FW after triggering reset */
3926 rte_delay_ms(info->master_func_wait_period_after_reset);
3927 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3928 /* Reset with the help of Kong processor */
3929 rc = bnxt_hwrm_fw_reset(bp);
3931 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3937 static void bnxt_fw_reset_cb(void *arg)
3939 struct bnxt *bp = arg;
3940 struct bnxt_error_recovery_info *info = bp->recovery_info;
3943 /* Only Master function can do FW reset */
3944 if (bnxt_is_master_func(bp) &&
3945 bnxt_is_recovery_enabled(bp)) {
3946 rc = bnxt_fw_reset_all(bp);
3948 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3953 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3954 * EXCEPTION_FATAL_ASYNC event to all the functions
3955 * (including MASTER FUNC). After receiving this Async, all the active
3956 * drivers should treat this case as FW initiated recovery
3958 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3959 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3960 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3962 /* To recover from error */
3963 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3968 /* Driver should poll FW heartbeat, reset_counter with the frequency
3969 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3970 * When the driver detects heartbeat stop or change in reset_counter,
3971 * it has to trigger a reset to recover from the error condition.
3972 * A “master PF” is the function who will have the privilege to
3973 * initiate the chimp reset. The master PF will be elected by the
3974 * firmware and will be notified through async message.
3976 static void bnxt_check_fw_health(void *arg)
3978 struct bnxt *bp = arg;
3979 struct bnxt_error_recovery_info *info = bp->recovery_info;
3980 uint32_t val = 0, wait_msec;
3982 if (!info || !bnxt_is_recovery_enabled(bp) ||
3983 is_bnxt_in_error(bp))
3986 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3987 if (val == info->last_heart_beat)
3990 info->last_heart_beat = val;
3992 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3993 if (val != info->last_reset_counter)
3996 info->last_reset_counter = val;
3998 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3999 bnxt_check_fw_health, (void *)bp);
4003 /* Stop DMA to/from device */
4004 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4005 bp->flags |= BNXT_FLAG_FW_RESET;
4007 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4009 if (bnxt_is_master_func(bp))
4010 wait_msec = info->master_func_wait_period;
4012 wait_msec = info->normal_func_wait_period;
4014 rte_eal_alarm_set(US_PER_MS * wait_msec,
4015 bnxt_fw_reset_cb, (void *)bp);
4018 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4020 uint32_t polling_freq;
4022 if (!bnxt_is_recovery_enabled(bp))
4025 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4028 polling_freq = bp->recovery_info->driver_polling_freq;
4030 rte_eal_alarm_set(US_PER_MS * polling_freq,
4031 bnxt_check_fw_health, (void *)bp);
4032 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4035 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4037 if (!bnxt_is_recovery_enabled(bp))
4040 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4041 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4044 static bool bnxt_vf_pciid(uint16_t id)
4046 if (id == BROADCOM_DEV_ID_57304_VF ||
4047 id == BROADCOM_DEV_ID_57406_VF ||
4048 id == BROADCOM_DEV_ID_5731X_VF ||
4049 id == BROADCOM_DEV_ID_5741X_VF ||
4050 id == BROADCOM_DEV_ID_57414_VF ||
4051 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4052 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4053 id == BROADCOM_DEV_ID_58802_VF ||
4054 id == BROADCOM_DEV_ID_57500_VF1 ||
4055 id == BROADCOM_DEV_ID_57500_VF2)
4060 bool bnxt_stratus_device(struct bnxt *bp)
4062 uint16_t id = bp->pdev->id.device_id;
4064 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4065 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4066 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4071 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4073 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4074 struct bnxt *bp = eth_dev->data->dev_private;
4076 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4077 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4078 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4079 if (!bp->bar0 || !bp->doorbell_base) {
4080 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4084 bp->eth_dev = eth_dev;
4090 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4091 struct bnxt_ctx_pg_info *ctx_pg,
4096 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4097 const struct rte_memzone *mz = NULL;
4098 char mz_name[RTE_MEMZONE_NAMESIZE];
4099 rte_iova_t mz_phys_addr;
4100 uint64_t valid_bits = 0;
4107 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4109 rmem->page_size = BNXT_PAGE_SIZE;
4110 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4111 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4112 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4114 valid_bits = PTU_PTE_VALID;
4116 if (rmem->nr_pages > 1) {
4117 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4118 "bnxt_ctx_pg_tbl%s_%x_%d",
4119 suffix, idx, bp->eth_dev->data->port_id);
4120 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4121 mz = rte_memzone_lookup(mz_name);
4123 mz = rte_memzone_reserve_aligned(mz_name,
4127 RTE_MEMZONE_SIZE_HINT_ONLY |
4128 RTE_MEMZONE_IOVA_CONTIG,
4134 memset(mz->addr, 0, mz->len);
4135 mz_phys_addr = mz->iova;
4136 if ((unsigned long)mz->addr == mz_phys_addr) {
4138 "physical address same as virtual\n");
4139 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4140 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4141 if (mz_phys_addr == RTE_BAD_IOVA) {
4143 "unable to map addr to phys memory\n");
4147 rte_mem_lock_page(((char *)mz->addr));
4149 rmem->pg_tbl = mz->addr;
4150 rmem->pg_tbl_map = mz_phys_addr;
4151 rmem->pg_tbl_mz = mz;
4154 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4155 suffix, idx, bp->eth_dev->data->port_id);
4156 mz = rte_memzone_lookup(mz_name);
4158 mz = rte_memzone_reserve_aligned(mz_name,
4162 RTE_MEMZONE_SIZE_HINT_ONLY |
4163 RTE_MEMZONE_IOVA_CONTIG,
4169 memset(mz->addr, 0, mz->len);
4170 mz_phys_addr = mz->iova;
4171 if ((unsigned long)mz->addr == mz_phys_addr) {
4173 "Memzone physical address same as virtual.\n");
4174 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4175 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4176 rte_mem_lock_page(((char *)mz->addr) + sz);
4177 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4178 if (mz_phys_addr == RTE_BAD_IOVA) {
4180 "unable to map addr to phys memory\n");
4185 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4186 rte_mem_lock_page(((char *)mz->addr) + sz);
4187 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4188 rmem->dma_arr[i] = mz_phys_addr + sz;
4190 if (rmem->nr_pages > 1) {
4191 if (i == rmem->nr_pages - 2 &&
4192 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4193 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4194 else if (i == rmem->nr_pages - 1 &&
4195 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4196 valid_bits |= PTU_PTE_LAST;
4198 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4204 if (rmem->vmem_size)
4205 rmem->vmem = (void **)mz->addr;
4206 rmem->dma_arr[0] = mz_phys_addr;
4210 static void bnxt_free_ctx_mem(struct bnxt *bp)
4214 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4217 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4218 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4219 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4220 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4221 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4222 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4223 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4224 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4225 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4226 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4227 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4229 for (i = 0; i < BNXT_MAX_Q; i++) {
4230 if (bp->ctx->tqm_mem[i])
4231 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4238 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4240 #define min_t(type, x, y) ({ \
4241 type __min1 = (x); \
4242 type __min2 = (y); \
4243 __min1 < __min2 ? __min1 : __min2; })
4245 #define max_t(type, x, y) ({ \
4246 type __max1 = (x); \
4247 type __max2 = (y); \
4248 __max1 > __max2 ? __max1 : __max2; })
4250 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4252 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4254 struct bnxt_ctx_pg_info *ctx_pg;
4255 struct bnxt_ctx_mem_info *ctx;
4256 uint32_t mem_size, ena, entries;
4259 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4261 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4265 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4268 ctx_pg = &ctx->qp_mem;
4269 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4270 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4271 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4275 ctx_pg = &ctx->srq_mem;
4276 ctx_pg->entries = ctx->srq_max_l2_entries;
4277 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4278 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4282 ctx_pg = &ctx->cq_mem;
4283 ctx_pg->entries = ctx->cq_max_l2_entries;
4284 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4285 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4289 ctx_pg = &ctx->vnic_mem;
4290 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4291 ctx->vnic_max_ring_table_entries;
4292 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4293 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4297 ctx_pg = &ctx->stat_mem;
4298 ctx_pg->entries = ctx->stat_max_entries;
4299 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4300 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4304 entries = ctx->qp_max_l2_entries +
4305 ctx->vnic_max_vnic_entries +
4306 ctx->tqm_min_entries_per_ring;
4307 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4308 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4309 ctx->tqm_max_entries_per_ring);
4310 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4311 ctx_pg = ctx->tqm_mem[i];
4312 /* use min tqm entries for now. */
4313 ctx_pg->entries = entries;
4314 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4315 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4318 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4321 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4322 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4325 "Failed to configure context mem: rc = %d\n", rc);
4327 ctx->flags |= BNXT_CTX_FLAG_INITED;
4332 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4334 struct rte_pci_device *pci_dev = bp->pdev;
4335 char mz_name[RTE_MEMZONE_NAMESIZE];
4336 const struct rte_memzone *mz = NULL;
4337 uint32_t total_alloc_len;
4338 rte_iova_t mz_phys_addr;
4340 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4343 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4344 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4345 pci_dev->addr.bus, pci_dev->addr.devid,
4346 pci_dev->addr.function, "rx_port_stats");
4347 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4348 mz = rte_memzone_lookup(mz_name);
4350 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4351 sizeof(struct rx_port_stats_ext) + 512);
4353 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4356 RTE_MEMZONE_SIZE_HINT_ONLY |
4357 RTE_MEMZONE_IOVA_CONTIG);
4361 memset(mz->addr, 0, mz->len);
4362 mz_phys_addr = mz->iova;
4363 if ((unsigned long)mz->addr == mz_phys_addr) {
4365 "Memzone physical address same as virtual.\n");
4367 "Using rte_mem_virt2iova()\n");
4368 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4369 if (mz_phys_addr == RTE_BAD_IOVA) {
4371 "Can't map address to physical memory\n");
4376 bp->rx_mem_zone = (const void *)mz;
4377 bp->hw_rx_port_stats = mz->addr;
4378 bp->hw_rx_port_stats_map = mz_phys_addr;
4380 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4381 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4382 pci_dev->addr.bus, pci_dev->addr.devid,
4383 pci_dev->addr.function, "tx_port_stats");
4384 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4385 mz = rte_memzone_lookup(mz_name);
4387 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4388 sizeof(struct tx_port_stats_ext) + 512);
4390 mz = rte_memzone_reserve(mz_name,
4394 RTE_MEMZONE_SIZE_HINT_ONLY |
4395 RTE_MEMZONE_IOVA_CONTIG);
4399 memset(mz->addr, 0, mz->len);
4400 mz_phys_addr = mz->iova;
4401 if ((unsigned long)mz->addr == mz_phys_addr) {
4403 "Memzone physical address same as virtual\n");
4404 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4405 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4406 if (mz_phys_addr == RTE_BAD_IOVA) {
4408 "Can't map address to physical memory\n");
4413 bp->tx_mem_zone = (const void *)mz;
4414 bp->hw_tx_port_stats = mz->addr;
4415 bp->hw_tx_port_stats_map = mz_phys_addr;
4416 bp->flags |= BNXT_FLAG_PORT_STATS;
4418 /* Display extended statistics if FW supports it */
4419 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4420 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4421 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4424 bp->hw_rx_port_stats_ext = (void *)
4425 ((uint8_t *)bp->hw_rx_port_stats +
4426 sizeof(struct rx_port_stats));
4427 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4428 sizeof(struct rx_port_stats);
4429 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4431 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4432 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4433 bp->hw_tx_port_stats_ext = (void *)
4434 ((uint8_t *)bp->hw_tx_port_stats +
4435 sizeof(struct tx_port_stats));
4436 bp->hw_tx_port_stats_ext_map =
4437 bp->hw_tx_port_stats_map +
4438 sizeof(struct tx_port_stats);
4439 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4445 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4447 struct bnxt *bp = eth_dev->data->dev_private;
4450 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4451 RTE_ETHER_ADDR_LEN *
4454 if (eth_dev->data->mac_addrs == NULL) {
4455 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4459 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4463 /* Generate a random MAC address, if none was assigned by PF */
4464 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4465 bnxt_eth_hw_addr_random(bp->mac_addr);
4467 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4468 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4469 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4471 rc = bnxt_hwrm_set_mac(bp);
4473 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4474 RTE_ETHER_ADDR_LEN);
4478 /* Copy the permanent MAC from the FUNC_QCAPS response */
4479 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4480 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4485 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4489 /* MAC is already configured in FW */
4490 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4493 /* Restore the old MAC configured */
4494 rc = bnxt_hwrm_set_mac(bp);
4496 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4501 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4506 #define ALLOW_FUNC(x) \
4508 uint32_t arg = (x); \
4509 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4510 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4513 /* Forward all requests if firmware is new enough */
4514 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4515 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4516 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4517 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4519 PMD_DRV_LOG(WARNING,
4520 "Firmware too old for VF mailbox functionality\n");
4521 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4525 * The following are used for driver cleanup. If we disallow these,
4526 * VF drivers can't clean up cleanly.
4528 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4529 ALLOW_FUNC(HWRM_VNIC_FREE);
4530 ALLOW_FUNC(HWRM_RING_FREE);
4531 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4532 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4533 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4534 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4535 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4536 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4539 static int bnxt_init_fw(struct bnxt *bp)
4544 rc = bnxt_hwrm_ver_get(bp);
4548 rc = bnxt_hwrm_func_reset(bp);
4552 rc = bnxt_hwrm_vnic_qcaps(bp);
4556 rc = bnxt_hwrm_queue_qportcfg(bp);
4560 /* Get the MAX capabilities for this function.
4561 * This function also allocates context memory for TQM rings and
4562 * informs the firmware about this allocated backing store memory.
4564 rc = bnxt_hwrm_func_qcaps(bp);
4568 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4572 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4576 /* Get the adapter error recovery support info */
4577 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4579 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4581 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4582 mtu != bp->eth_dev->data->mtu)
4583 bp->eth_dev->data->mtu = mtu;
4585 bnxt_hwrm_port_led_qcaps(bp);
4591 bnxt_init_locks(struct bnxt *bp)
4595 err = pthread_mutex_init(&bp->flow_lock, NULL);
4597 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4601 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4603 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4607 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4611 rc = bnxt_init_fw(bp);
4615 if (!reconfig_dev) {
4616 rc = bnxt_setup_mac_addr(bp->eth_dev);
4620 rc = bnxt_restore_dflt_mac(bp);
4625 bnxt_config_vf_req_fwd(bp);
4627 rc = bnxt_hwrm_func_driver_register(bp);
4629 PMD_DRV_LOG(ERR, "Failed to register driver");
4634 if (bp->pdev->max_vfs) {
4635 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4637 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4641 rc = bnxt_hwrm_allocate_pf_only(bp);
4644 "Failed to allocate PF resources");
4650 rc = bnxt_alloc_mem(bp, reconfig_dev);
4654 rc = bnxt_setup_int(bp);
4660 rc = bnxt_request_int(bp);
4664 rc = bnxt_init_locks(bp);
4672 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4674 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4675 static int version_printed;
4679 if (version_printed++ == 0)
4680 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4682 eth_dev->dev_ops = &bnxt_dev_ops;
4683 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4684 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4687 * For secondary processes, we don't initialise any further
4688 * as primary has already done this work.
4690 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4693 rte_eth_copy_pci_info(eth_dev, pci_dev);
4695 bp = eth_dev->data->dev_private;
4697 bp->dev_stopped = 1;
4699 if (bnxt_vf_pciid(pci_dev->id.device_id))
4700 bp->flags |= BNXT_FLAG_VF;
4702 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4703 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4704 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4705 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4706 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4707 bp->flags |= BNXT_FLAG_THOR_CHIP;
4709 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4710 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4711 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4712 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4713 bp->flags |= BNXT_FLAG_STINGRAY;
4715 rc = bnxt_init_board(eth_dev);
4718 "Failed to initialize board rc: %x\n", rc);
4722 rc = bnxt_alloc_hwrm_resources(bp);
4725 "Failed to allocate hwrm resource rc: %x\n", rc);
4728 rc = bnxt_init_resources(bp, false);
4732 rc = bnxt_alloc_stats_mem(bp);
4737 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4738 pci_dev->mem_resource[0].phys_addr,
4739 pci_dev->mem_resource[0].addr);
4744 bnxt_dev_uninit(eth_dev);
4749 bnxt_uninit_locks(struct bnxt *bp)
4751 pthread_mutex_destroy(&bp->flow_lock);
4752 pthread_mutex_destroy(&bp->def_cp_lock);
4756 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4761 bnxt_free_mem(bp, reconfig_dev);
4762 bnxt_hwrm_func_buf_unrgtr(bp);
4763 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4764 bp->flags &= ~BNXT_FLAG_REGISTERED;
4765 bnxt_free_ctx_mem(bp);
4766 if (!reconfig_dev) {
4767 bnxt_free_hwrm_resources(bp);
4769 if (bp->recovery_info != NULL) {
4770 rte_free(bp->recovery_info);
4771 bp->recovery_info = NULL;
4775 rte_free(bp->ptp_cfg);
4781 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4783 struct bnxt *bp = eth_dev->data->dev_private;
4786 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4789 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4791 rc = bnxt_uninit_resources(bp, false);
4793 if (bp->grp_info != NULL) {
4794 rte_free(bp->grp_info);
4795 bp->grp_info = NULL;
4798 if (bp->tx_mem_zone) {
4799 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4800 bp->tx_mem_zone = NULL;
4803 if (bp->rx_mem_zone) {
4804 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4805 bp->rx_mem_zone = NULL;
4808 if (bp->dev_stopped == 0)
4809 bnxt_dev_close_op(eth_dev);
4811 rte_free(bp->pf.vf_info);
4812 eth_dev->dev_ops = NULL;
4813 eth_dev->rx_pkt_burst = NULL;
4814 eth_dev->tx_pkt_burst = NULL;
4816 bnxt_uninit_locks(bp);
4821 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4822 struct rte_pci_device *pci_dev)
4824 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4828 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4830 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4831 return rte_eth_dev_pci_generic_remove(pci_dev,
4834 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4837 static struct rte_pci_driver bnxt_rte_pmd = {
4838 .id_table = bnxt_pci_id_map,
4839 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4840 .probe = bnxt_pci_probe,
4841 .remove = bnxt_pci_remove,
4845 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4847 if (strcmp(dev->device->driver->name, drv->driver.name))
4853 bool is_bnxt_supported(struct rte_eth_dev *dev)
4855 return is_device_supported(dev, &bnxt_rte_pmd);
4858 RTE_INIT(bnxt_init_log)
4860 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4861 if (bnxt_logtype_driver >= 0)
4862 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4865 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4866 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4867 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");