1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_MULTI_SEGS)
156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
157 DEV_RX_OFFLOAD_VLAN_STRIP | \
158 DEV_RX_OFFLOAD_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_UDP_CKSUM | \
160 DEV_RX_OFFLOAD_TCP_CKSUM | \
161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
162 DEV_RX_OFFLOAD_JUMBO_FRAME | \
163 DEV_RX_OFFLOAD_KEEP_CRC | \
164 DEV_RX_OFFLOAD_TCP_LRO)
166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
174 int is_bnxt_in_error(struct bnxt *bp)
176 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
178 if (bp->flags & BNXT_FLAG_FW_RESET)
184 /***********************/
187 * High level utility functions
190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
192 if (!BNXT_CHIP_THOR(bp))
195 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
196 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
197 BNXT_RSS_ENTRIES_PER_CTX_THOR;
200 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
202 if (!BNXT_CHIP_THOR(bp))
203 return HW_HASH_INDEX_SIZE;
205 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
210 bnxt_free_filter_mem(bp);
211 bnxt_free_vnic_attributes(bp);
212 bnxt_free_vnic_mem(bp);
214 /* tx/rx rings are configured as part of *_queue_setup callbacks.
215 * If the number of rings change across fw update,
216 * we don't have much choice except to warn the user.
220 bnxt_free_tx_rings(bp);
221 bnxt_free_rx_rings(bp);
223 bnxt_free_async_cp_ring(bp);
226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
230 rc = bnxt_alloc_ring_grps(bp);
234 rc = bnxt_alloc_async_ring_struct(bp);
238 rc = bnxt_alloc_vnic_mem(bp);
242 rc = bnxt_alloc_vnic_attributes(bp);
246 rc = bnxt_alloc_filter_mem(bp);
250 rc = bnxt_alloc_async_cp_ring(bp);
257 bnxt_free_mem(bp, reconfig);
261 static int bnxt_init_chip(struct bnxt *bp)
263 struct bnxt_rx_queue *rxq;
264 struct rte_eth_link new;
265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
266 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
268 uint64_t rx_offloads = dev_conf->rxmode.offloads;
269 uint32_t intr_vector = 0;
270 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
271 uint32_t vec = BNXT_MISC_VEC_ID;
275 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
276 bp->eth_dev->data->dev_conf.rxmode.offloads |=
277 DEV_RX_OFFLOAD_JUMBO_FRAME;
278 bp->flags |= BNXT_FLAG_JUMBO;
280 bp->eth_dev->data->dev_conf.rxmode.offloads &=
281 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
282 bp->flags &= ~BNXT_FLAG_JUMBO;
285 /* THOR does not support ring groups.
286 * But we will use the array to save RSS context IDs.
288 if (BNXT_CHIP_THOR(bp))
289 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
291 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
293 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
297 rc = bnxt_alloc_hwrm_rings(bp);
299 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
303 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
305 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
309 rc = bnxt_mq_rx_configure(bp);
311 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
315 /* VNIC configuration */
316 for (i = 0; i < bp->nr_vnics; i++) {
317 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
318 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
319 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
321 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
322 if (!vnic->fw_grp_ids) {
324 "Failed to alloc %d bytes for group ids\n",
329 memset(vnic->fw_grp_ids, -1, size);
331 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
332 i, vnic, vnic->fw_grp_ids);
334 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
336 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
341 /* Alloc RSS context only if RSS mode is enabled */
342 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
343 int j, nr_ctxs = bnxt_rss_ctxts(bp);
346 for (j = 0; j < nr_ctxs; j++) {
347 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
353 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
357 vnic->num_lb_ctxts = nr_ctxs;
361 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
362 * setting is not available at this time, it will not be
363 * configured correctly in the CFA.
365 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
366 vnic->vlan_strip = true;
368 vnic->vlan_strip = false;
370 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
372 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
377 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
380 "HWRM vnic %d filter failure rc: %x\n",
385 for (j = 0; j < bp->rx_nr_rings; j++) {
386 rxq = bp->eth_dev->data->rx_queues[j];
389 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
390 j, rxq->vnic, rxq->vnic->fw_grp_ids);
392 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
393 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
396 rc = bnxt_vnic_rss_configure(bp, vnic);
399 "HWRM vnic set RSS failure rc: %x\n", rc);
403 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
405 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
406 DEV_RX_OFFLOAD_TCP_LRO)
407 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
411 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
414 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
418 /* check and configure queue intr-vector mapping */
419 if ((rte_intr_cap_multiple(intr_handle) ||
420 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
421 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
422 intr_vector = bp->eth_dev->data->nb_rx_queues;
423 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
424 if (intr_vector > bp->rx_cp_nr_rings) {
425 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
429 rc = rte_intr_efd_enable(intr_handle, intr_vector);
434 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
435 intr_handle->intr_vec =
436 rte_zmalloc("intr_vec",
437 bp->eth_dev->data->nb_rx_queues *
439 if (intr_handle->intr_vec == NULL) {
440 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
441 " intr_vec", bp->eth_dev->data->nb_rx_queues);
445 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
446 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
447 intr_handle->intr_vec, intr_handle->nb_efd,
448 intr_handle->max_intr);
449 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
451 intr_handle->intr_vec[queue_id] =
452 vec + BNXT_RX_VEC_START;
453 if (vec < base + intr_handle->nb_efd - 1)
458 /* enable uio/vfio intr/eventfd mapping */
459 rc = rte_intr_enable(intr_handle);
463 rc = bnxt_get_hwrm_link_config(bp, &new);
465 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
469 if (!bp->link_info.link_up) {
470 rc = bnxt_set_hwrm_link_config(bp, true);
473 "HWRM link config failure rc: %x\n", rc);
477 bnxt_print_link_info(bp->eth_dev);
482 rte_free(intr_handle->intr_vec);
484 rte_intr_efd_disable(intr_handle);
486 /* Some of the error status returned by FW may not be from errno.h */
493 static int bnxt_shutdown_nic(struct bnxt *bp)
495 bnxt_free_all_hwrm_resources(bp);
496 bnxt_free_all_filters(bp);
497 bnxt_free_all_vnics(bp);
501 static int bnxt_init_nic(struct bnxt *bp)
505 if (BNXT_HAS_RING_GRPS(bp)) {
506 rc = bnxt_init_ring_grps(bp);
512 bnxt_init_filters(bp);
518 * Device configuration and status function
521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
522 struct rte_eth_dev_info *dev_info)
524 struct bnxt *bp = eth_dev->data->dev_private;
525 uint16_t max_vnics, i, j, vpool, vrxq;
526 unsigned int max_rx_rings;
529 rc = is_bnxt_in_error(bp);
534 dev_info->max_mac_addrs = bp->max_l2_ctx;
535 dev_info->max_hash_mac_addrs = 0;
537 /* PF/VF specifics */
539 dev_info->max_vfs = bp->pdev->max_vfs;
540 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
541 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
542 dev_info->max_rx_queues = max_rx_rings;
543 dev_info->max_tx_queues = max_rx_rings;
544 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
545 dev_info->hash_key_size = 40;
546 max_vnics = bp->max_vnics;
548 /* Fast path specifics */
549 dev_info->min_rx_bufsize = 1;
550 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
551 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
553 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
554 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
555 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
556 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
557 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
560 dev_info->default_rxconf = (struct rte_eth_rxconf) {
566 .rx_free_thresh = 32,
567 /* If no descriptors available, pkts are dropped by default */
571 dev_info->default_txconf = (struct rte_eth_txconf) {
577 .tx_free_thresh = 32,
580 eth_dev->data->dev_conf.intr_conf.lsc = 1;
582 eth_dev->data->dev_conf.intr_conf.rxq = 1;
583 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
584 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
585 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
586 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
591 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
592 * need further investigation.
596 vpool = 64; /* ETH_64_POOLS */
597 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
598 for (i = 0; i < 4; vpool >>= 1, i++) {
599 if (max_vnics > vpool) {
600 for (j = 0; j < 5; vrxq >>= 1, j++) {
601 if (dev_info->max_rx_queues > vrxq) {
607 /* Not enough resources to support VMDq */
611 /* Not enough resources to support VMDq */
615 dev_info->max_vmdq_pools = vpool;
616 dev_info->vmdq_queue_num = vrxq;
618 dev_info->vmdq_pool_base = 0;
619 dev_info->vmdq_queue_base = 0;
624 /* Configure the device based on the configuration provided */
625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
627 struct bnxt *bp = eth_dev->data->dev_private;
628 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
631 bp->rx_queues = (void *)eth_dev->data->rx_queues;
632 bp->tx_queues = (void *)eth_dev->data->tx_queues;
633 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
634 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
636 rc = is_bnxt_in_error(bp);
640 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
641 rc = bnxt_hwrm_check_vf_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
647 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
649 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
653 /* legacy driver needs to get updated values */
654 rc = bnxt_hwrm_func_qcaps(bp);
656 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
661 /* Inherit new configurations */
662 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
663 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
664 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
665 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
666 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
670 if (BNXT_HAS_RING_GRPS(bp) &&
671 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
674 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
675 bp->max_vnics < eth_dev->data->nb_rx_queues)
678 bp->rx_cp_nr_rings = bp->rx_nr_rings;
679 bp->tx_cp_nr_rings = bp->tx_nr_rings;
681 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
683 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
684 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
686 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
692 "Insufficient resources to support requested config\n");
694 "Num Queues Requested: Tx %d, Rx %d\n",
695 eth_dev->data->nb_tx_queues,
696 eth_dev->data->nb_rx_queues);
698 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
699 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
700 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
706 struct rte_eth_link *link = ð_dev->data->dev_link;
708 if (link->link_status)
709 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
710 eth_dev->data->port_id,
711 (uint32_t)link->link_speed,
712 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
713 ("full-duplex") : ("half-duplex\n"));
715 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
716 eth_dev->data->port_id);
720 * Determine whether the current configuration requires support for scattered
721 * receive; return 1 if scattered receive is required and 0 if not.
723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
728 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
729 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
731 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
732 RTE_PKTMBUF_HEADROOM);
733 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
739 static eth_rx_burst_t
740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
744 * Vector mode receive can be enabled only if scatter rx is not
745 * in use and rx offloads are limited to VLAN stripping and
748 if (!eth_dev->data->scattered_rx &&
749 !(eth_dev->data->dev_conf.rxmode.offloads &
750 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
751 DEV_RX_OFFLOAD_KEEP_CRC |
752 DEV_RX_OFFLOAD_JUMBO_FRAME |
753 DEV_RX_OFFLOAD_IPV4_CKSUM |
754 DEV_RX_OFFLOAD_UDP_CKSUM |
755 DEV_RX_OFFLOAD_TCP_CKSUM |
756 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
757 DEV_RX_OFFLOAD_VLAN_FILTER))) {
758 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
759 eth_dev->data->port_id);
760 return bnxt_recv_pkts_vec;
762 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
763 eth_dev->data->port_id);
765 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
766 eth_dev->data->port_id,
767 eth_dev->data->scattered_rx,
768 eth_dev->data->dev_conf.rxmode.offloads);
770 return bnxt_recv_pkts;
773 static eth_tx_burst_t
774 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
778 * Vector mode transmit can be enabled only if not using scatter rx
781 if (!eth_dev->data->scattered_rx &&
782 !eth_dev->data->dev_conf.txmode.offloads) {
783 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
784 eth_dev->data->port_id);
785 return bnxt_xmit_pkts_vec;
787 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
788 eth_dev->data->port_id);
790 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
791 eth_dev->data->port_id,
792 eth_dev->data->scattered_rx,
793 eth_dev->data->dev_conf.txmode.offloads);
795 return bnxt_xmit_pkts;
798 static int bnxt_handle_if_change_status(struct bnxt *bp)
802 /* Since fw has undergone a reset and lost all contexts,
803 * set fatal flag to not issue hwrm during cleanup
805 bp->flags |= BNXT_FLAG_FATAL_ERROR;
806 bnxt_uninit_resources(bp, true);
808 /* clear fatal flag so that re-init happens */
809 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
810 rc = bnxt_init_resources(bp, true);
812 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
817 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
819 struct bnxt *bp = eth_dev->data->dev_private;
820 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
824 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
826 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
827 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
830 rc = bnxt_hwrm_if_change(bp, 1);
832 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
833 rc = bnxt_handle_if_change_status(bp);
839 rc = bnxt_init_chip(bp);
843 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
845 bnxt_link_update_op(eth_dev, 1);
847 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
848 vlan_mask |= ETH_VLAN_FILTER_MASK;
849 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
850 vlan_mask |= ETH_VLAN_STRIP_MASK;
851 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
855 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
856 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
859 bp->flags |= BNXT_FLAG_INIT_DONE;
860 eth_dev->data->dev_started = 1;
862 bnxt_schedule_fw_health_check(bp);
866 bnxt_hwrm_if_change(bp, 0);
867 bnxt_shutdown_nic(bp);
868 bnxt_free_tx_mbufs(bp);
869 bnxt_free_rx_mbufs(bp);
873 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
875 struct bnxt *bp = eth_dev->data->dev_private;
878 if (!bp->link_info.link_up)
879 rc = bnxt_set_hwrm_link_config(bp, true);
881 eth_dev->data->dev_link.link_status = 1;
883 bnxt_print_link_info(eth_dev);
887 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
889 struct bnxt *bp = eth_dev->data->dev_private;
891 eth_dev->data->dev_link.link_status = 0;
892 bnxt_set_hwrm_link_config(bp, false);
893 bp->link_info.link_up = 0;
898 /* Unload the driver, release resources */
899 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
901 struct bnxt *bp = eth_dev->data->dev_private;
902 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
903 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
905 eth_dev->data->dev_started = 0;
906 /* Prevent crashes when queues are still in use */
907 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
908 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
910 bnxt_disable_int(bp);
912 /* disable uio/vfio intr/eventfd mapping */
913 rte_intr_disable(intr_handle);
915 bnxt_cancel_fw_health_check(bp);
917 bp->flags &= ~BNXT_FLAG_INIT_DONE;
918 if (bp->eth_dev->data->dev_started) {
919 /* TBD: STOP HW queues DMA */
920 eth_dev->data->dev_link.link_status = 0;
922 bnxt_set_hwrm_link_config(bp, false);
924 /* Clean queue intr-vector mapping */
925 rte_intr_efd_disable(intr_handle);
926 if (intr_handle->intr_vec != NULL) {
927 rte_free(intr_handle->intr_vec);
928 intr_handle->intr_vec = NULL;
931 bnxt_hwrm_port_clr_stats(bp);
932 bnxt_free_tx_mbufs(bp);
933 bnxt_free_rx_mbufs(bp);
934 bnxt_shutdown_nic(bp);
935 bnxt_hwrm_if_change(bp, 0);
939 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
941 struct bnxt *bp = eth_dev->data->dev_private;
943 if (bp->dev_stopped == 0)
944 bnxt_dev_stop_op(eth_dev);
946 if (eth_dev->data->mac_addrs != NULL) {
947 rte_free(eth_dev->data->mac_addrs);
948 eth_dev->data->mac_addrs = NULL;
950 if (bp->grp_info != NULL) {
951 rte_free(bp->grp_info);
955 bnxt_dev_uninit(eth_dev);
958 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
961 struct bnxt *bp = eth_dev->data->dev_private;
962 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
963 struct bnxt_vnic_info *vnic;
964 struct bnxt_filter_info *filter, *temp_filter;
967 if (is_bnxt_in_error(bp))
971 * Loop through all VNICs from the specified filter flow pools to
972 * remove the corresponding MAC addr filter
974 for (i = 0; i < bp->nr_vnics; i++) {
975 if (!(pool_mask & (1ULL << i)))
978 vnic = &bp->vnic_info[i];
979 filter = STAILQ_FIRST(&vnic->filter);
981 temp_filter = STAILQ_NEXT(filter, next);
982 if (filter->mac_index == index) {
983 STAILQ_REMOVE(&vnic->filter, filter,
984 bnxt_filter_info, next);
985 bnxt_hwrm_clear_l2_filter(bp, filter);
986 filter->mac_index = INVALID_MAC_INDEX;
987 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
988 STAILQ_INSERT_TAIL(&bp->free_filter_list,
991 filter = temp_filter;
996 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
997 struct rte_ether_addr *mac_addr,
998 uint32_t index, uint32_t pool)
1000 struct bnxt *bp = eth_dev->data->dev_private;
1001 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1002 struct bnxt_filter_info *filter;
1005 rc = is_bnxt_in_error(bp);
1009 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1010 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1015 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1018 /* Attach requested MAC address to the new l2_filter */
1019 STAILQ_FOREACH(filter, &vnic->filter, next) {
1020 if (filter->mac_index == index) {
1022 "MAC addr already existed for pool %d\n", pool);
1026 filter = bnxt_alloc_filter(bp);
1028 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1032 filter->mac_index = index;
1033 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1035 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1037 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1039 filter->mac_index = INVALID_MAC_INDEX;
1040 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1041 bnxt_free_filter(bp, filter);
1047 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1050 struct bnxt *bp = eth_dev->data->dev_private;
1051 struct rte_eth_link new;
1052 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1054 rc = is_bnxt_in_error(bp);
1058 memset(&new, 0, sizeof(new));
1060 /* Retrieve link info from hardware */
1061 rc = bnxt_get_hwrm_link_config(bp, &new);
1063 new.link_speed = ETH_LINK_SPEED_100M;
1064 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1066 "Failed to retrieve link rc = 0x%x!\n", rc);
1070 if (!wait_to_complete || new.link_status)
1073 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1077 /* Timed out or success */
1078 if (new.link_status != eth_dev->data->dev_link.link_status ||
1079 new.link_speed != eth_dev->data->dev_link.link_speed) {
1080 memcpy(ð_dev->data->dev_link, &new,
1081 sizeof(struct rte_eth_link));
1083 _rte_eth_dev_callback_process(eth_dev,
1084 RTE_ETH_EVENT_INTR_LSC,
1087 bnxt_print_link_info(eth_dev);
1093 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1095 struct bnxt *bp = eth_dev->data->dev_private;
1096 struct bnxt_vnic_info *vnic;
1100 rc = is_bnxt_in_error(bp);
1104 if (bp->vnic_info == NULL)
1107 vnic = &bp->vnic_info[0];
1109 old_flags = vnic->flags;
1110 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1111 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1113 vnic->flags = old_flags;
1118 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1120 struct bnxt *bp = eth_dev->data->dev_private;
1121 struct bnxt_vnic_info *vnic;
1125 rc = is_bnxt_in_error(bp);
1129 if (bp->vnic_info == NULL)
1132 vnic = &bp->vnic_info[0];
1134 old_flags = vnic->flags;
1135 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1136 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1138 vnic->flags = old_flags;
1143 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1145 struct bnxt *bp = eth_dev->data->dev_private;
1146 struct bnxt_vnic_info *vnic;
1150 rc = is_bnxt_in_error(bp);
1154 if (bp->vnic_info == NULL)
1157 vnic = &bp->vnic_info[0];
1159 old_flags = vnic->flags;
1160 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1161 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1163 vnic->flags = old_flags;
1168 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1170 struct bnxt *bp = eth_dev->data->dev_private;
1171 struct bnxt_vnic_info *vnic;
1175 rc = is_bnxt_in_error(bp);
1179 if (bp->vnic_info == NULL)
1182 vnic = &bp->vnic_info[0];
1184 old_flags = vnic->flags;
1185 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1186 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1188 vnic->flags = old_flags;
1193 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1194 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1196 if (qid >= bp->rx_nr_rings)
1199 return bp->eth_dev->data->rx_queues[qid];
1202 /* Return rxq corresponding to a given rss table ring/group ID. */
1203 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1205 struct bnxt_rx_queue *rxq;
1208 if (!BNXT_HAS_RING_GRPS(bp)) {
1209 for (i = 0; i < bp->rx_nr_rings; i++) {
1210 rxq = bp->eth_dev->data->rx_queues[i];
1211 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1215 for (i = 0; i < bp->rx_nr_rings; i++) {
1216 if (bp->grp_info[i].fw_grp_id == fwr)
1221 return INVALID_HW_RING_ID;
1224 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1225 struct rte_eth_rss_reta_entry64 *reta_conf,
1228 struct bnxt *bp = eth_dev->data->dev_private;
1229 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1230 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1231 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1235 rc = is_bnxt_in_error(bp);
1239 if (!vnic->rss_table)
1242 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1245 if (reta_size != tbl_size) {
1246 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1247 "(%d) must equal the size supported by the hardware "
1248 "(%d)\n", reta_size, tbl_size);
1252 for (i = 0; i < reta_size; i++) {
1253 struct bnxt_rx_queue *rxq;
1255 idx = i / RTE_RETA_GROUP_SIZE;
1256 sft = i % RTE_RETA_GROUP_SIZE;
1258 if (!(reta_conf[idx].mask & (1ULL << sft)))
1261 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1263 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1267 if (BNXT_CHIP_THOR(bp)) {
1268 vnic->rss_table[i * 2] =
1269 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1270 vnic->rss_table[i * 2 + 1] =
1271 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1273 vnic->rss_table[i] =
1274 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1277 vnic->rss_table[i] =
1278 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1281 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1285 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1286 struct rte_eth_rss_reta_entry64 *reta_conf,
1289 struct bnxt *bp = eth_dev->data->dev_private;
1290 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1291 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1292 uint16_t idx, sft, i;
1295 rc = is_bnxt_in_error(bp);
1299 /* Retrieve from the default VNIC */
1302 if (!vnic->rss_table)
1305 if (reta_size != tbl_size) {
1306 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1307 "(%d) must equal the size supported by the hardware "
1308 "(%d)\n", reta_size, tbl_size);
1312 for (idx = 0, i = 0; i < reta_size; i++) {
1313 idx = i / RTE_RETA_GROUP_SIZE;
1314 sft = i % RTE_RETA_GROUP_SIZE;
1316 if (reta_conf[idx].mask & (1ULL << sft)) {
1319 if (BNXT_CHIP_THOR(bp))
1320 qid = bnxt_rss_to_qid(bp,
1321 vnic->rss_table[i * 2]);
1323 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1325 if (qid == INVALID_HW_RING_ID) {
1326 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1329 reta_conf[idx].reta[sft] = qid;
1336 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1337 struct rte_eth_rss_conf *rss_conf)
1339 struct bnxt *bp = eth_dev->data->dev_private;
1340 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1341 struct bnxt_vnic_info *vnic;
1342 uint16_t hash_type = 0;
1346 rc = is_bnxt_in_error(bp);
1351 * If RSS enablement were different than dev_configure,
1352 * then return -EINVAL
1354 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1355 if (!rss_conf->rss_hf)
1356 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1358 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1362 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1363 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1365 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1366 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1367 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1368 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1369 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1370 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1371 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1372 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1373 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1374 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1375 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1376 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1378 /* Update the RSS VNIC(s) */
1379 for (i = 0; i < bp->nr_vnics; i++) {
1380 vnic = &bp->vnic_info[i];
1381 vnic->hash_type = hash_type;
1384 * Use the supplied key if the key length is
1385 * acceptable and the rss_key is not NULL
1387 if (rss_conf->rss_key &&
1388 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1389 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1390 rss_conf->rss_key_len);
1392 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1397 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1398 struct rte_eth_rss_conf *rss_conf)
1400 struct bnxt *bp = eth_dev->data->dev_private;
1401 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1403 uint32_t hash_types;
1405 rc = is_bnxt_in_error(bp);
1409 /* RSS configuration is the same for all VNICs */
1410 if (vnic && vnic->rss_hash_key) {
1411 if (rss_conf->rss_key) {
1412 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1413 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1414 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1417 hash_types = vnic->hash_type;
1418 rss_conf->rss_hf = 0;
1419 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1420 rss_conf->rss_hf |= ETH_RSS_IPV4;
1421 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1423 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1424 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1426 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1428 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1429 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1431 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1433 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1434 rss_conf->rss_hf |= ETH_RSS_IPV6;
1435 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1437 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1438 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1440 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1442 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1443 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1445 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1449 "Unknwon RSS config from firmware (%08x), RSS disabled",
1454 rss_conf->rss_hf = 0;
1459 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1460 struct rte_eth_fc_conf *fc_conf)
1462 struct bnxt *bp = dev->data->dev_private;
1463 struct rte_eth_link link_info;
1466 rc = is_bnxt_in_error(bp);
1470 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1474 memset(fc_conf, 0, sizeof(*fc_conf));
1475 if (bp->link_info.auto_pause)
1476 fc_conf->autoneg = 1;
1477 switch (bp->link_info.pause) {
1479 fc_conf->mode = RTE_FC_NONE;
1481 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1482 fc_conf->mode = RTE_FC_TX_PAUSE;
1484 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1485 fc_conf->mode = RTE_FC_RX_PAUSE;
1487 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1488 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1489 fc_conf->mode = RTE_FC_FULL;
1495 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1496 struct rte_eth_fc_conf *fc_conf)
1498 struct bnxt *bp = dev->data->dev_private;
1501 rc = is_bnxt_in_error(bp);
1505 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1506 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1510 switch (fc_conf->mode) {
1512 bp->link_info.auto_pause = 0;
1513 bp->link_info.force_pause = 0;
1515 case RTE_FC_RX_PAUSE:
1516 if (fc_conf->autoneg) {
1517 bp->link_info.auto_pause =
1518 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1519 bp->link_info.force_pause = 0;
1521 bp->link_info.auto_pause = 0;
1522 bp->link_info.force_pause =
1523 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1526 case RTE_FC_TX_PAUSE:
1527 if (fc_conf->autoneg) {
1528 bp->link_info.auto_pause =
1529 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1530 bp->link_info.force_pause = 0;
1532 bp->link_info.auto_pause = 0;
1533 bp->link_info.force_pause =
1534 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1538 if (fc_conf->autoneg) {
1539 bp->link_info.auto_pause =
1540 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1541 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1542 bp->link_info.force_pause = 0;
1544 bp->link_info.auto_pause = 0;
1545 bp->link_info.force_pause =
1546 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1547 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1551 return bnxt_set_hwrm_link_config(bp, true);
1554 /* Add UDP tunneling port */
1556 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1557 struct rte_eth_udp_tunnel *udp_tunnel)
1559 struct bnxt *bp = eth_dev->data->dev_private;
1560 uint16_t tunnel_type = 0;
1563 rc = is_bnxt_in_error(bp);
1567 switch (udp_tunnel->prot_type) {
1568 case RTE_TUNNEL_TYPE_VXLAN:
1569 if (bp->vxlan_port_cnt) {
1570 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1571 udp_tunnel->udp_port);
1572 if (bp->vxlan_port != udp_tunnel->udp_port) {
1573 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1576 bp->vxlan_port_cnt++;
1580 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1581 bp->vxlan_port_cnt++;
1583 case RTE_TUNNEL_TYPE_GENEVE:
1584 if (bp->geneve_port_cnt) {
1585 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1586 udp_tunnel->udp_port);
1587 if (bp->geneve_port != udp_tunnel->udp_port) {
1588 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1591 bp->geneve_port_cnt++;
1595 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1596 bp->geneve_port_cnt++;
1599 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1602 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1608 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1609 struct rte_eth_udp_tunnel *udp_tunnel)
1611 struct bnxt *bp = eth_dev->data->dev_private;
1612 uint16_t tunnel_type = 0;
1616 rc = is_bnxt_in_error(bp);
1620 switch (udp_tunnel->prot_type) {
1621 case RTE_TUNNEL_TYPE_VXLAN:
1622 if (!bp->vxlan_port_cnt) {
1623 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1626 if (bp->vxlan_port != udp_tunnel->udp_port) {
1627 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1628 udp_tunnel->udp_port, bp->vxlan_port);
1631 if (--bp->vxlan_port_cnt)
1635 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1636 port = bp->vxlan_fw_dst_port_id;
1638 case RTE_TUNNEL_TYPE_GENEVE:
1639 if (!bp->geneve_port_cnt) {
1640 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1643 if (bp->geneve_port != udp_tunnel->udp_port) {
1644 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1645 udp_tunnel->udp_port, bp->geneve_port);
1648 if (--bp->geneve_port_cnt)
1652 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1653 port = bp->geneve_fw_dst_port_id;
1656 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1660 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1663 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1666 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1667 bp->geneve_port = 0;
1672 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1674 struct bnxt_filter_info *filter;
1675 struct bnxt_vnic_info *vnic;
1677 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1679 /* if VLAN exists && VLAN matches vlan_id
1680 * remove the MAC+VLAN filter
1681 * add a new MAC only filter
1683 * VLAN filter doesn't exist, just skip and continue
1685 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1686 filter = STAILQ_FIRST(&vnic->filter);
1688 /* Search for this matching MAC+VLAN filter */
1689 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1690 !memcmp(filter->l2_addr,
1692 RTE_ETHER_ADDR_LEN)) {
1693 /* Delete the filter */
1694 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1697 STAILQ_REMOVE(&vnic->filter, filter,
1698 bnxt_filter_info, next);
1699 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1702 "Del Vlan filter for %d\n",
1706 filter = STAILQ_NEXT(filter, next);
1711 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1713 struct bnxt_filter_info *filter;
1714 struct bnxt_vnic_info *vnic;
1716 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1717 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1718 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1720 /* Implementation notes on the use of VNIC in this command:
1722 * By default, these filters belong to default vnic for the function.
1723 * Once these filters are set up, only destination VNIC can be modified.
1724 * If the destination VNIC is not specified in this command,
1725 * then the HWRM shall only create an l2 context id.
1728 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1729 filter = STAILQ_FIRST(&vnic->filter);
1730 /* Check if the VLAN has already been added */
1732 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1733 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1736 filter = STAILQ_NEXT(filter, next);
1739 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1740 * command to create MAC+VLAN filter with the right flags, enables set.
1742 filter = bnxt_alloc_filter(bp);
1745 "MAC/VLAN filter alloc failed\n");
1748 /* MAC + VLAN ID filter */
1749 filter->l2_ivlan = vlan_id;
1750 filter->l2_ivlan_mask = 0x0FFF;
1751 filter->enables |= en;
1752 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1754 /* Free the newly allocated filter as we were
1755 * not able to create the filter in hardware.
1757 filter->fw_l2_filter_id = UINT64_MAX;
1758 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1762 /* Add this new filter to the list */
1763 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1765 "Added Vlan filter for %d\n", vlan_id);
1769 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1770 uint16_t vlan_id, int on)
1772 struct bnxt *bp = eth_dev->data->dev_private;
1775 rc = is_bnxt_in_error(bp);
1779 /* These operations apply to ALL existing MAC/VLAN filters */
1781 return bnxt_add_vlan_filter(bp, vlan_id);
1783 return bnxt_del_vlan_filter(bp, vlan_id);
1787 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1789 struct bnxt *bp = dev->data->dev_private;
1790 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1794 rc = is_bnxt_in_error(bp);
1798 if (mask & ETH_VLAN_FILTER_MASK) {
1799 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1800 /* Remove any VLAN filters programmed */
1801 for (i = 0; i < 4095; i++)
1802 bnxt_del_vlan_filter(bp, i);
1804 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1805 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1808 if (mask & ETH_VLAN_STRIP_MASK) {
1809 /* Enable or disable VLAN stripping */
1810 for (i = 0; i < bp->nr_vnics; i++) {
1811 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1812 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1813 vnic->vlan_strip = true;
1815 vnic->vlan_strip = false;
1816 bnxt_hwrm_vnic_cfg(bp, vnic);
1818 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1819 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1822 if (mask & ETH_VLAN_EXTEND_MASK)
1823 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1829 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1830 struct rte_ether_addr *addr)
1832 struct bnxt *bp = dev->data->dev_private;
1833 /* Default Filter is tied to VNIC 0 */
1834 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1835 struct bnxt_filter_info *filter;
1838 rc = is_bnxt_in_error(bp);
1842 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1845 if (rte_is_zero_ether_addr(addr))
1848 STAILQ_FOREACH(filter, &vnic->filter, next) {
1849 /* Default Filter is at Index 0 */
1850 if (filter->mac_index != 0)
1853 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1854 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1855 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1857 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1858 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1860 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1864 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1865 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1873 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1874 struct rte_ether_addr *mc_addr_set,
1875 uint32_t nb_mc_addr)
1877 struct bnxt *bp = eth_dev->data->dev_private;
1878 char *mc_addr_list = (char *)mc_addr_set;
1879 struct bnxt_vnic_info *vnic;
1880 uint32_t off = 0, i = 0;
1883 rc = is_bnxt_in_error(bp);
1887 vnic = &bp->vnic_info[0];
1889 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1890 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1894 /* TODO Check for Duplicate mcast addresses */
1895 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1896 for (i = 0; i < nb_mc_addr; i++) {
1897 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1898 RTE_ETHER_ADDR_LEN);
1899 off += RTE_ETHER_ADDR_LEN;
1902 vnic->mc_addr_cnt = i;
1905 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1909 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1911 struct bnxt *bp = dev->data->dev_private;
1912 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1913 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1914 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1917 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1918 fw_major, fw_minor, fw_updt);
1920 ret += 1; /* add the size of '\0' */
1921 if (fw_size < (uint32_t)ret)
1928 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1929 struct rte_eth_rxq_info *qinfo)
1931 struct bnxt_rx_queue *rxq;
1933 rxq = dev->data->rx_queues[queue_id];
1935 qinfo->mp = rxq->mb_pool;
1936 qinfo->scattered_rx = dev->data->scattered_rx;
1937 qinfo->nb_desc = rxq->nb_rx_desc;
1939 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1940 qinfo->conf.rx_drop_en = 0;
1941 qinfo->conf.rx_deferred_start = 0;
1945 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1946 struct rte_eth_txq_info *qinfo)
1948 struct bnxt_tx_queue *txq;
1950 txq = dev->data->tx_queues[queue_id];
1952 qinfo->nb_desc = txq->nb_tx_desc;
1954 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1955 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1956 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1958 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1959 qinfo->conf.tx_rs_thresh = 0;
1960 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1963 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1965 struct bnxt *bp = eth_dev->data->dev_private;
1966 struct rte_eth_dev_info dev_info;
1967 uint32_t new_pkt_size;
1971 rc = is_bnxt_in_error(bp);
1975 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1976 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1978 rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1980 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1984 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1985 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1986 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1992 * If vector-mode tx/rx is active, disallow any MTU change that would
1993 * require scattered receive support.
1995 if (eth_dev->data->dev_started &&
1996 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1997 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1999 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2001 "MTU change would require scattered rx support. ");
2002 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2007 if (new_mtu > RTE_ETHER_MTU) {
2008 bp->flags |= BNXT_FLAG_JUMBO;
2009 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2010 DEV_RX_OFFLOAD_JUMBO_FRAME;
2012 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2013 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2014 bp->flags &= ~BNXT_FLAG_JUMBO;
2017 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2019 eth_dev->data->mtu = new_mtu;
2020 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
2022 for (i = 0; i < bp->nr_vnics; i++) {
2023 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2026 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2027 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2028 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2032 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2033 size -= RTE_PKTMBUF_HEADROOM;
2035 if (size < new_mtu) {
2036 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2046 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2048 struct bnxt *bp = dev->data->dev_private;
2049 uint16_t vlan = bp->vlan;
2052 rc = is_bnxt_in_error(bp);
2056 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2058 "PVID cannot be modified for this function\n");
2061 bp->vlan = on ? pvid : 0;
2063 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2070 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2072 struct bnxt *bp = dev->data->dev_private;
2075 rc = is_bnxt_in_error(bp);
2079 return bnxt_hwrm_port_led_cfg(bp, true);
2083 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2085 struct bnxt *bp = dev->data->dev_private;
2088 rc = is_bnxt_in_error(bp);
2092 return bnxt_hwrm_port_led_cfg(bp, false);
2096 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2098 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2099 uint32_t desc = 0, raw_cons = 0, cons;
2100 struct bnxt_cp_ring_info *cpr;
2101 struct bnxt_rx_queue *rxq;
2102 struct rx_pkt_cmpl *rxcmp;
2108 rc = is_bnxt_in_error(bp);
2112 rxq = dev->data->rx_queues[rx_queue_id];
2116 while (raw_cons < rxq->nb_rx_desc) {
2117 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2118 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2120 if (!CMPL_VALID(rxcmp, valid))
2122 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2123 cmp_type = CMP_TYPE(rxcmp);
2124 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2125 cmp = (rte_le_to_cpu_32(
2126 ((struct rx_tpa_end_cmpl *)
2127 (rxcmp))->agg_bufs_v1) &
2128 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2129 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2131 } else if (cmp_type == 0x11) {
2133 cmp = (rxcmp->agg_bufs_v1 &
2134 RX_PKT_CMPL_AGG_BUFS_MASK) >>
2135 RX_PKT_CMPL_AGG_BUFS_SFT;
2140 raw_cons += cmp ? cmp : 2;
2147 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2149 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2150 struct bnxt_rx_ring_info *rxr;
2151 struct bnxt_cp_ring_info *cpr;
2152 struct bnxt_sw_rx_bd *rx_buf;
2153 struct rx_pkt_cmpl *rxcmp;
2154 uint32_t cons, cp_cons;
2160 rc = is_bnxt_in_error(rxq->bp);
2167 if (offset >= rxq->nb_rx_desc)
2170 cons = RING_CMP(cpr->cp_ring_struct, offset);
2171 cp_cons = cpr->cp_raw_cons;
2172 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2174 if (cons > cp_cons) {
2175 if (CMPL_VALID(rxcmp, cpr->valid))
2176 return RTE_ETH_RX_DESC_DONE;
2178 if (CMPL_VALID(rxcmp, !cpr->valid))
2179 return RTE_ETH_RX_DESC_DONE;
2181 rx_buf = &rxr->rx_buf_ring[cons];
2182 if (rx_buf->mbuf == NULL)
2183 return RTE_ETH_RX_DESC_UNAVAIL;
2186 return RTE_ETH_RX_DESC_AVAIL;
2190 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2192 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2193 struct bnxt_tx_ring_info *txr;
2194 struct bnxt_cp_ring_info *cpr;
2195 struct bnxt_sw_tx_bd *tx_buf;
2196 struct tx_pkt_cmpl *txcmp;
2197 uint32_t cons, cp_cons;
2203 rc = is_bnxt_in_error(txq->bp);
2210 if (offset >= txq->nb_tx_desc)
2213 cons = RING_CMP(cpr->cp_ring_struct, offset);
2214 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2215 cp_cons = cpr->cp_raw_cons;
2217 if (cons > cp_cons) {
2218 if (CMPL_VALID(txcmp, cpr->valid))
2219 return RTE_ETH_TX_DESC_UNAVAIL;
2221 if (CMPL_VALID(txcmp, !cpr->valid))
2222 return RTE_ETH_TX_DESC_UNAVAIL;
2224 tx_buf = &txr->tx_buf_ring[cons];
2225 if (tx_buf->mbuf == NULL)
2226 return RTE_ETH_TX_DESC_DONE;
2228 return RTE_ETH_TX_DESC_FULL;
2231 static struct bnxt_filter_info *
2232 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2233 struct rte_eth_ethertype_filter *efilter,
2234 struct bnxt_vnic_info *vnic0,
2235 struct bnxt_vnic_info *vnic,
2238 struct bnxt_filter_info *mfilter = NULL;
2242 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2243 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2244 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2245 " ethertype filter.", efilter->ether_type);
2249 if (efilter->queue >= bp->rx_nr_rings) {
2250 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2255 vnic0 = &bp->vnic_info[0];
2256 vnic = &bp->vnic_info[efilter->queue];
2258 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2263 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2264 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2265 if ((!memcmp(efilter->mac_addr.addr_bytes,
2266 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2268 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2269 mfilter->ethertype == efilter->ether_type)) {
2275 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2276 if ((!memcmp(efilter->mac_addr.addr_bytes,
2277 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2278 mfilter->ethertype == efilter->ether_type &&
2280 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2294 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2295 enum rte_filter_op filter_op,
2298 struct bnxt *bp = dev->data->dev_private;
2299 struct rte_eth_ethertype_filter *efilter =
2300 (struct rte_eth_ethertype_filter *)arg;
2301 struct bnxt_filter_info *bfilter, *filter1;
2302 struct bnxt_vnic_info *vnic, *vnic0;
2305 if (filter_op == RTE_ETH_FILTER_NOP)
2309 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2314 vnic0 = &bp->vnic_info[0];
2315 vnic = &bp->vnic_info[efilter->queue];
2317 switch (filter_op) {
2318 case RTE_ETH_FILTER_ADD:
2319 bnxt_match_and_validate_ether_filter(bp, efilter,
2324 bfilter = bnxt_get_unused_filter(bp);
2325 if (bfilter == NULL) {
2327 "Not enough resources for a new filter.\n");
2330 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2331 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2332 RTE_ETHER_ADDR_LEN);
2333 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2334 RTE_ETHER_ADDR_LEN);
2335 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2336 bfilter->ethertype = efilter->ether_type;
2337 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2339 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2340 if (filter1 == NULL) {
2345 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2346 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2348 bfilter->dst_id = vnic->fw_vnic_id;
2350 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2352 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2355 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2358 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2360 case RTE_ETH_FILTER_DELETE:
2361 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2363 if (ret == -EEXIST) {
2364 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2366 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2368 bnxt_free_filter(bp, filter1);
2369 } else if (ret == 0) {
2370 PMD_DRV_LOG(ERR, "No matching filter found\n");
2374 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2380 bnxt_free_filter(bp, bfilter);
2386 parse_ntuple_filter(struct bnxt *bp,
2387 struct rte_eth_ntuple_filter *nfilter,
2388 struct bnxt_filter_info *bfilter)
2392 if (nfilter->queue >= bp->rx_nr_rings) {
2393 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2397 switch (nfilter->dst_port_mask) {
2399 bfilter->dst_port_mask = -1;
2400 bfilter->dst_port = nfilter->dst_port;
2401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2402 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2405 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2409 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2410 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2412 switch (nfilter->proto_mask) {
2414 if (nfilter->proto == 17) /* IPPROTO_UDP */
2415 bfilter->ip_protocol = 17;
2416 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2417 bfilter->ip_protocol = 6;
2420 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2423 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2427 switch (nfilter->dst_ip_mask) {
2429 bfilter->dst_ipaddr_mask[0] = -1;
2430 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2431 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2432 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2435 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2439 switch (nfilter->src_ip_mask) {
2441 bfilter->src_ipaddr_mask[0] = -1;
2442 bfilter->src_ipaddr[0] = nfilter->src_ip;
2443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2444 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2447 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2451 switch (nfilter->src_port_mask) {
2453 bfilter->src_port_mask = -1;
2454 bfilter->src_port = nfilter->src_port;
2455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2456 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2459 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2464 //nfilter->priority = (uint8_t)filter->priority;
2466 bfilter->enables = en;
2470 static struct bnxt_filter_info*
2471 bnxt_match_ntuple_filter(struct bnxt *bp,
2472 struct bnxt_filter_info *bfilter,
2473 struct bnxt_vnic_info **mvnic)
2475 struct bnxt_filter_info *mfilter = NULL;
2478 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2479 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2480 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2481 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2482 bfilter->src_ipaddr_mask[0] ==
2483 mfilter->src_ipaddr_mask[0] &&
2484 bfilter->src_port == mfilter->src_port &&
2485 bfilter->src_port_mask == mfilter->src_port_mask &&
2486 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2487 bfilter->dst_ipaddr_mask[0] ==
2488 mfilter->dst_ipaddr_mask[0] &&
2489 bfilter->dst_port == mfilter->dst_port &&
2490 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2491 bfilter->flags == mfilter->flags &&
2492 bfilter->enables == mfilter->enables) {
2503 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2504 struct rte_eth_ntuple_filter *nfilter,
2505 enum rte_filter_op filter_op)
2507 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2508 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2511 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2512 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2516 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2517 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2521 bfilter = bnxt_get_unused_filter(bp);
2522 if (bfilter == NULL) {
2524 "Not enough resources for a new filter.\n");
2527 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2531 vnic = &bp->vnic_info[nfilter->queue];
2532 vnic0 = &bp->vnic_info[0];
2533 filter1 = STAILQ_FIRST(&vnic0->filter);
2534 if (filter1 == NULL) {
2539 bfilter->dst_id = vnic->fw_vnic_id;
2540 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2542 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2543 bfilter->ethertype = 0x800;
2544 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2546 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2548 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2549 bfilter->dst_id == mfilter->dst_id) {
2550 PMD_DRV_LOG(ERR, "filter exists.\n");
2553 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2554 bfilter->dst_id != mfilter->dst_id) {
2555 mfilter->dst_id = vnic->fw_vnic_id;
2556 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2557 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2558 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2559 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2560 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2563 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2564 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2569 if (filter_op == RTE_ETH_FILTER_ADD) {
2570 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2571 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2574 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2576 if (mfilter == NULL) {
2577 /* This should not happen. But for Coverity! */
2581 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2583 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2584 bnxt_free_filter(bp, mfilter);
2585 mfilter->fw_l2_filter_id = -1;
2586 bnxt_free_filter(bp, bfilter);
2587 bfilter->fw_l2_filter_id = -1;
2592 bfilter->fw_l2_filter_id = -1;
2593 bnxt_free_filter(bp, bfilter);
2598 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2599 enum rte_filter_op filter_op,
2602 struct bnxt *bp = dev->data->dev_private;
2605 if (filter_op == RTE_ETH_FILTER_NOP)
2609 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2614 switch (filter_op) {
2615 case RTE_ETH_FILTER_ADD:
2616 ret = bnxt_cfg_ntuple_filter(bp,
2617 (struct rte_eth_ntuple_filter *)arg,
2620 case RTE_ETH_FILTER_DELETE:
2621 ret = bnxt_cfg_ntuple_filter(bp,
2622 (struct rte_eth_ntuple_filter *)arg,
2626 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2634 bnxt_parse_fdir_filter(struct bnxt *bp,
2635 struct rte_eth_fdir_filter *fdir,
2636 struct bnxt_filter_info *filter)
2638 enum rte_fdir_mode fdir_mode =
2639 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2640 struct bnxt_vnic_info *vnic0, *vnic;
2641 struct bnxt_filter_info *filter1;
2645 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2648 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2649 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2651 switch (fdir->input.flow_type) {
2652 case RTE_ETH_FLOW_IPV4:
2653 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2655 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2656 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2657 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2658 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2659 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2660 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2661 filter->ip_addr_type =
2662 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2663 filter->src_ipaddr_mask[0] = 0xffffffff;
2664 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2665 filter->dst_ipaddr_mask[0] = 0xffffffff;
2666 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2667 filter->ethertype = 0x800;
2668 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2670 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2671 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2672 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2673 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2674 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2675 filter->dst_port_mask = 0xffff;
2676 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2677 filter->src_port_mask = 0xffff;
2678 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2679 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2680 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2681 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2682 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2683 filter->ip_protocol = 6;
2684 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2685 filter->ip_addr_type =
2686 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2687 filter->src_ipaddr_mask[0] = 0xffffffff;
2688 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2689 filter->dst_ipaddr_mask[0] = 0xffffffff;
2690 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2691 filter->ethertype = 0x800;
2692 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2694 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2695 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2696 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2697 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2698 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2699 filter->dst_port_mask = 0xffff;
2700 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2701 filter->src_port_mask = 0xffff;
2702 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2703 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2704 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2705 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2706 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2707 filter->ip_protocol = 17;
2708 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2709 filter->ip_addr_type =
2710 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2711 filter->src_ipaddr_mask[0] = 0xffffffff;
2712 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2713 filter->dst_ipaddr_mask[0] = 0xffffffff;
2714 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2715 filter->ethertype = 0x800;
2716 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2718 case RTE_ETH_FLOW_IPV6:
2719 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2721 filter->ip_addr_type =
2722 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2723 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2724 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2725 rte_memcpy(filter->src_ipaddr,
2726 fdir->input.flow.ipv6_flow.src_ip, 16);
2727 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2728 rte_memcpy(filter->dst_ipaddr,
2729 fdir->input.flow.ipv6_flow.dst_ip, 16);
2730 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2731 memset(filter->dst_ipaddr_mask, 0xff, 16);
2732 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2733 memset(filter->src_ipaddr_mask, 0xff, 16);
2734 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2735 filter->ethertype = 0x86dd;
2736 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2738 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2739 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2740 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2741 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2742 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2743 filter->dst_port_mask = 0xffff;
2744 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2745 filter->src_port_mask = 0xffff;
2746 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2747 filter->ip_addr_type =
2748 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2749 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2750 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2751 rte_memcpy(filter->src_ipaddr,
2752 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2753 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2754 rte_memcpy(filter->dst_ipaddr,
2755 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2756 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2757 memset(filter->dst_ipaddr_mask, 0xff, 16);
2758 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2759 memset(filter->src_ipaddr_mask, 0xff, 16);
2760 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2761 filter->ethertype = 0x86dd;
2762 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2764 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2765 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2766 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2767 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2768 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2769 filter->dst_port_mask = 0xffff;
2770 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2771 filter->src_port_mask = 0xffff;
2772 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2773 filter->ip_addr_type =
2774 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2775 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2776 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2777 rte_memcpy(filter->src_ipaddr,
2778 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2780 rte_memcpy(filter->dst_ipaddr,
2781 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2782 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2783 memset(filter->dst_ipaddr_mask, 0xff, 16);
2784 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2785 memset(filter->src_ipaddr_mask, 0xff, 16);
2786 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2787 filter->ethertype = 0x86dd;
2788 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2790 case RTE_ETH_FLOW_L2_PAYLOAD:
2791 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2792 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2794 case RTE_ETH_FLOW_VXLAN:
2795 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2797 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2798 filter->tunnel_type =
2799 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2800 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2802 case RTE_ETH_FLOW_NVGRE:
2803 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2805 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2806 filter->tunnel_type =
2807 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2808 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2810 case RTE_ETH_FLOW_UNKNOWN:
2811 case RTE_ETH_FLOW_RAW:
2812 case RTE_ETH_FLOW_FRAG_IPV4:
2813 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2814 case RTE_ETH_FLOW_FRAG_IPV6:
2815 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2816 case RTE_ETH_FLOW_IPV6_EX:
2817 case RTE_ETH_FLOW_IPV6_TCP_EX:
2818 case RTE_ETH_FLOW_IPV6_UDP_EX:
2819 case RTE_ETH_FLOW_GENEVE:
2825 vnic0 = &bp->vnic_info[0];
2826 vnic = &bp->vnic_info[fdir->action.rx_queue];
2828 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2833 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2834 rte_memcpy(filter->dst_macaddr,
2835 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2836 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2839 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2840 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2841 filter1 = STAILQ_FIRST(&vnic0->filter);
2842 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2844 filter->dst_id = vnic->fw_vnic_id;
2845 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2846 if (filter->dst_macaddr[i] == 0x00)
2847 filter1 = STAILQ_FIRST(&vnic0->filter);
2849 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2852 if (filter1 == NULL)
2855 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2856 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2858 filter->enables = en;
2863 static struct bnxt_filter_info *
2864 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2865 struct bnxt_vnic_info **mvnic)
2867 struct bnxt_filter_info *mf = NULL;
2870 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2871 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2873 STAILQ_FOREACH(mf, &vnic->filter, next) {
2874 if (mf->filter_type == nf->filter_type &&
2875 mf->flags == nf->flags &&
2876 mf->src_port == nf->src_port &&
2877 mf->src_port_mask == nf->src_port_mask &&
2878 mf->dst_port == nf->dst_port &&
2879 mf->dst_port_mask == nf->dst_port_mask &&
2880 mf->ip_protocol == nf->ip_protocol &&
2881 mf->ip_addr_type == nf->ip_addr_type &&
2882 mf->ethertype == nf->ethertype &&
2883 mf->vni == nf->vni &&
2884 mf->tunnel_type == nf->tunnel_type &&
2885 mf->l2_ovlan == nf->l2_ovlan &&
2886 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2887 mf->l2_ivlan == nf->l2_ivlan &&
2888 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2889 !memcmp(mf->l2_addr, nf->l2_addr,
2890 RTE_ETHER_ADDR_LEN) &&
2891 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2892 RTE_ETHER_ADDR_LEN) &&
2893 !memcmp(mf->src_macaddr, nf->src_macaddr,
2894 RTE_ETHER_ADDR_LEN) &&
2895 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2896 RTE_ETHER_ADDR_LEN) &&
2897 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2898 sizeof(nf->src_ipaddr)) &&
2899 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2900 sizeof(nf->src_ipaddr_mask)) &&
2901 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2902 sizeof(nf->dst_ipaddr)) &&
2903 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2904 sizeof(nf->dst_ipaddr_mask))) {
2915 bnxt_fdir_filter(struct rte_eth_dev *dev,
2916 enum rte_filter_op filter_op,
2919 struct bnxt *bp = dev->data->dev_private;
2920 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2921 struct bnxt_filter_info *filter, *match;
2922 struct bnxt_vnic_info *vnic, *mvnic;
2925 if (filter_op == RTE_ETH_FILTER_NOP)
2928 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2931 switch (filter_op) {
2932 case RTE_ETH_FILTER_ADD:
2933 case RTE_ETH_FILTER_DELETE:
2935 filter = bnxt_get_unused_filter(bp);
2936 if (filter == NULL) {
2938 "Not enough resources for a new flow.\n");
2942 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2945 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2947 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2948 vnic = &bp->vnic_info[0];
2950 vnic = &bp->vnic_info[fdir->action.rx_queue];
2952 match = bnxt_match_fdir(bp, filter, &mvnic);
2953 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2954 if (match->dst_id == vnic->fw_vnic_id) {
2955 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2959 match->dst_id = vnic->fw_vnic_id;
2960 ret = bnxt_hwrm_set_ntuple_filter(bp,
2963 STAILQ_REMOVE(&mvnic->filter, match,
2964 bnxt_filter_info, next);
2965 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2967 "Filter with matching pattern exist\n");
2969 "Updated it to new destination q\n");
2973 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2974 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2979 if (filter_op == RTE_ETH_FILTER_ADD) {
2980 ret = bnxt_hwrm_set_ntuple_filter(bp,
2985 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2987 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2988 STAILQ_REMOVE(&vnic->filter, match,
2989 bnxt_filter_info, next);
2990 bnxt_free_filter(bp, match);
2991 filter->fw_l2_filter_id = -1;
2992 bnxt_free_filter(bp, filter);
2995 case RTE_ETH_FILTER_FLUSH:
2996 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2997 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2999 STAILQ_FOREACH(filter, &vnic->filter, next) {
3000 if (filter->filter_type ==
3001 HWRM_CFA_NTUPLE_FILTER) {
3003 bnxt_hwrm_clear_ntuple_filter(bp,
3005 STAILQ_REMOVE(&vnic->filter, filter,
3006 bnxt_filter_info, next);
3011 case RTE_ETH_FILTER_UPDATE:
3012 case RTE_ETH_FILTER_STATS:
3013 case RTE_ETH_FILTER_INFO:
3014 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3017 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3024 filter->fw_l2_filter_id = -1;
3025 bnxt_free_filter(bp, filter);
3030 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3031 enum rte_filter_type filter_type,
3032 enum rte_filter_op filter_op, void *arg)
3036 ret = is_bnxt_in_error(dev->data->dev_private);
3040 switch (filter_type) {
3041 case RTE_ETH_FILTER_TUNNEL:
3043 "filter type: %d: To be implemented\n", filter_type);
3045 case RTE_ETH_FILTER_FDIR:
3046 ret = bnxt_fdir_filter(dev, filter_op, arg);
3048 case RTE_ETH_FILTER_NTUPLE:
3049 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3051 case RTE_ETH_FILTER_ETHERTYPE:
3052 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3054 case RTE_ETH_FILTER_GENERIC:
3055 if (filter_op != RTE_ETH_FILTER_GET)
3057 *(const void **)arg = &bnxt_flow_ops;
3061 "Filter type (%d) not supported", filter_type);
3068 static const uint32_t *
3069 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3071 static const uint32_t ptypes[] = {
3072 RTE_PTYPE_L2_ETHER_VLAN,
3073 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3074 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3078 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3079 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3080 RTE_PTYPE_INNER_L4_ICMP,
3081 RTE_PTYPE_INNER_L4_TCP,
3082 RTE_PTYPE_INNER_L4_UDP,
3086 if (!dev->rx_pkt_burst)
3092 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3095 uint32_t reg_base = *reg_arr & 0xfffff000;
3099 for (i = 0; i < count; i++) {
3100 if ((reg_arr[i] & 0xfffff000) != reg_base)
3103 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3104 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3108 static int bnxt_map_ptp_regs(struct bnxt *bp)
3110 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3114 reg_arr = ptp->rx_regs;
3115 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3119 reg_arr = ptp->tx_regs;
3120 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3124 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3125 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3127 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3128 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3133 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3135 rte_write32(0, (uint8_t *)bp->bar0 +
3136 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3137 rte_write32(0, (uint8_t *)bp->bar0 +
3138 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3141 static uint64_t bnxt_cc_read(struct bnxt *bp)
3145 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3146 BNXT_GRCPF_REG_SYNC_TIME));
3147 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3148 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3152 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3154 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3157 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3159 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3162 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3163 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3164 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3165 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3166 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3172 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3174 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3175 struct bnxt_pf_info *pf = &bp->pf;
3182 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3183 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3184 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3187 port_id = pf->port_id;
3188 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3189 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3191 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3192 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3193 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3194 /* bnxt_clr_rx_ts(bp); TBD */
3198 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3199 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3200 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3201 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3207 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3210 struct bnxt *bp = dev->data->dev_private;
3211 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3216 ns = rte_timespec_to_ns(ts);
3217 /* Set the timecounters to a new value. */
3224 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3226 uint64_t ns, systime_cycles;
3227 struct bnxt *bp = dev->data->dev_private;
3228 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3233 systime_cycles = bnxt_cc_read(bp);
3234 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3235 *ts = rte_ns_to_timespec(ns);
3240 bnxt_timesync_enable(struct rte_eth_dev *dev)
3242 struct bnxt *bp = dev->data->dev_private;
3243 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3250 ptp->tx_tstamp_en = 1;
3251 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3253 if (!bnxt_hwrm_ptp_cfg(bp))
3254 bnxt_map_ptp_regs(bp);
3256 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3257 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3258 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3260 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3261 ptp->tc.cc_shift = shift;
3262 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3264 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3265 ptp->rx_tstamp_tc.cc_shift = shift;
3266 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3268 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3269 ptp->tx_tstamp_tc.cc_shift = shift;
3270 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3276 bnxt_timesync_disable(struct rte_eth_dev *dev)
3278 struct bnxt *bp = dev->data->dev_private;
3279 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3285 ptp->tx_tstamp_en = 0;
3288 bnxt_hwrm_ptp_cfg(bp);
3290 bnxt_unmap_ptp_regs(bp);
3296 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3297 struct timespec *timestamp,
3298 uint32_t flags __rte_unused)
3300 struct bnxt *bp = dev->data->dev_private;
3301 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3302 uint64_t rx_tstamp_cycles = 0;
3308 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3309 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3310 *timestamp = rte_ns_to_timespec(ns);
3315 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3316 struct timespec *timestamp)
3318 struct bnxt *bp = dev->data->dev_private;
3319 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3320 uint64_t tx_tstamp_cycles = 0;
3326 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3327 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3328 *timestamp = rte_ns_to_timespec(ns);
3334 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3336 struct bnxt *bp = dev->data->dev_private;
3337 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3342 ptp->tc.nsec += delta;
3348 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3350 struct bnxt *bp = dev->data->dev_private;
3352 uint32_t dir_entries;
3353 uint32_t entry_length;
3355 rc = is_bnxt_in_error(bp);
3359 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3360 bp->pdev->addr.domain, bp->pdev->addr.bus,
3361 bp->pdev->addr.devid, bp->pdev->addr.function);
3363 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3367 return dir_entries * entry_length;
3371 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3372 struct rte_dev_eeprom_info *in_eeprom)
3374 struct bnxt *bp = dev->data->dev_private;
3379 rc = is_bnxt_in_error(bp);
3383 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3384 "len = %d\n", bp->pdev->addr.domain,
3385 bp->pdev->addr.bus, bp->pdev->addr.devid,
3386 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3388 if (in_eeprom->offset == 0) /* special offset value to get directory */
3389 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3392 index = in_eeprom->offset >> 24;
3393 offset = in_eeprom->offset & 0xffffff;
3396 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3397 in_eeprom->length, in_eeprom->data);
3402 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3405 case BNX_DIR_TYPE_CHIMP_PATCH:
3406 case BNX_DIR_TYPE_BOOTCODE:
3407 case BNX_DIR_TYPE_BOOTCODE_2:
3408 case BNX_DIR_TYPE_APE_FW:
3409 case BNX_DIR_TYPE_APE_PATCH:
3410 case BNX_DIR_TYPE_KONG_FW:
3411 case BNX_DIR_TYPE_KONG_PATCH:
3412 case BNX_DIR_TYPE_BONO_FW:
3413 case BNX_DIR_TYPE_BONO_PATCH:
3421 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3424 case BNX_DIR_TYPE_AVS:
3425 case BNX_DIR_TYPE_EXP_ROM_MBA:
3426 case BNX_DIR_TYPE_PCIE:
3427 case BNX_DIR_TYPE_TSCF_UCODE:
3428 case BNX_DIR_TYPE_EXT_PHY:
3429 case BNX_DIR_TYPE_CCM:
3430 case BNX_DIR_TYPE_ISCSI_BOOT:
3431 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3432 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3440 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3442 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3443 bnxt_dir_type_is_other_exec_format(dir_type);
3447 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3448 struct rte_dev_eeprom_info *in_eeprom)
3450 struct bnxt *bp = dev->data->dev_private;
3451 uint8_t index, dir_op;
3452 uint16_t type, ext, ordinal, attr;
3455 rc = is_bnxt_in_error(bp);
3459 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3460 "len = %d\n", bp->pdev->addr.domain,
3461 bp->pdev->addr.bus, bp->pdev->addr.devid,
3462 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3465 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3469 type = in_eeprom->magic >> 16;
3471 if (type == 0xffff) { /* special value for directory operations */
3472 index = in_eeprom->magic & 0xff;
3473 dir_op = in_eeprom->magic >> 8;
3477 case 0x0e: /* erase */
3478 if (in_eeprom->offset != ~in_eeprom->magic)
3480 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3486 /* Create or re-write an NVM item: */
3487 if (bnxt_dir_type_is_executable(type) == true)
3489 ext = in_eeprom->magic & 0xffff;
3490 ordinal = in_eeprom->offset >> 16;
3491 attr = in_eeprom->offset & 0xffff;
3493 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3494 in_eeprom->data, in_eeprom->length);
3501 static const struct eth_dev_ops bnxt_dev_ops = {
3502 .dev_infos_get = bnxt_dev_info_get_op,
3503 .dev_close = bnxt_dev_close_op,
3504 .dev_configure = bnxt_dev_configure_op,
3505 .dev_start = bnxt_dev_start_op,
3506 .dev_stop = bnxt_dev_stop_op,
3507 .dev_set_link_up = bnxt_dev_set_link_up_op,
3508 .dev_set_link_down = bnxt_dev_set_link_down_op,
3509 .stats_get = bnxt_stats_get_op,
3510 .stats_reset = bnxt_stats_reset_op,
3511 .rx_queue_setup = bnxt_rx_queue_setup_op,
3512 .rx_queue_release = bnxt_rx_queue_release_op,
3513 .tx_queue_setup = bnxt_tx_queue_setup_op,
3514 .tx_queue_release = bnxt_tx_queue_release_op,
3515 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3516 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3517 .reta_update = bnxt_reta_update_op,
3518 .reta_query = bnxt_reta_query_op,
3519 .rss_hash_update = bnxt_rss_hash_update_op,
3520 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3521 .link_update = bnxt_link_update_op,
3522 .promiscuous_enable = bnxt_promiscuous_enable_op,
3523 .promiscuous_disable = bnxt_promiscuous_disable_op,
3524 .allmulticast_enable = bnxt_allmulticast_enable_op,
3525 .allmulticast_disable = bnxt_allmulticast_disable_op,
3526 .mac_addr_add = bnxt_mac_addr_add_op,
3527 .mac_addr_remove = bnxt_mac_addr_remove_op,
3528 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3529 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3530 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3531 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3532 .vlan_filter_set = bnxt_vlan_filter_set_op,
3533 .vlan_offload_set = bnxt_vlan_offload_set_op,
3534 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3535 .mtu_set = bnxt_mtu_set_op,
3536 .mac_addr_set = bnxt_set_default_mac_addr_op,
3537 .xstats_get = bnxt_dev_xstats_get_op,
3538 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3539 .xstats_reset = bnxt_dev_xstats_reset_op,
3540 .fw_version_get = bnxt_fw_version_get,
3541 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3542 .rxq_info_get = bnxt_rxq_info_get_op,
3543 .txq_info_get = bnxt_txq_info_get_op,
3544 .dev_led_on = bnxt_dev_led_on_op,
3545 .dev_led_off = bnxt_dev_led_off_op,
3546 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3547 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3548 .rx_queue_count = bnxt_rx_queue_count_op,
3549 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3550 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3551 .rx_queue_start = bnxt_rx_queue_start,
3552 .rx_queue_stop = bnxt_rx_queue_stop,
3553 .tx_queue_start = bnxt_tx_queue_start,
3554 .tx_queue_stop = bnxt_tx_queue_stop,
3555 .filter_ctrl = bnxt_filter_ctrl_op,
3556 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3557 .get_eeprom_length = bnxt_get_eeprom_length_op,
3558 .get_eeprom = bnxt_get_eeprom_op,
3559 .set_eeprom = bnxt_set_eeprom_op,
3560 .timesync_enable = bnxt_timesync_enable,
3561 .timesync_disable = bnxt_timesync_disable,
3562 .timesync_read_time = bnxt_timesync_read_time,
3563 .timesync_write_time = bnxt_timesync_write_time,
3564 .timesync_adjust_time = bnxt_timesync_adjust_time,
3565 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3566 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3569 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3573 /* Only pre-map the reset GRC registers using window 3 */
3574 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3575 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3577 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3582 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3584 struct bnxt_error_recovery_info *info = bp->recovery_info;
3585 uint32_t reg_base = 0xffffffff;
3588 /* Only pre-map the monitoring GRC registers using window 2 */
3589 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3590 uint32_t reg = info->status_regs[i];
3592 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3595 if (reg_base == 0xffffffff)
3596 reg_base = reg & 0xfffff000;
3597 if ((reg & 0xfffff000) != reg_base)
3600 /* Use mask 0xffc as the Lower 2 bits indicates
3601 * address space location
3603 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3607 if (reg_base == 0xffffffff)
3610 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3611 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3616 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3618 struct bnxt_error_recovery_info *info = bp->recovery_info;
3619 uint32_t delay = info->delay_after_reset[index];
3620 uint32_t val = info->reset_reg_val[index];
3621 uint32_t reg = info->reset_reg[index];
3622 uint32_t type, offset;
3624 type = BNXT_FW_STATUS_REG_TYPE(reg);
3625 offset = BNXT_FW_STATUS_REG_OFF(reg);
3628 case BNXT_FW_STATUS_REG_TYPE_CFG:
3629 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3631 case BNXT_FW_STATUS_REG_TYPE_GRC:
3632 offset = bnxt_map_reset_regs(bp, offset);
3633 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3635 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3636 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3639 /* wait on a specific interval of time until core reset is complete */
3641 rte_delay_ms(delay);
3644 static void bnxt_dev_cleanup(struct bnxt *bp)
3646 bnxt_set_hwrm_link_config(bp, false);
3647 bp->link_info.link_up = 0;
3648 if (bp->dev_stopped == 0)
3649 bnxt_dev_stop_op(bp->eth_dev);
3651 bnxt_uninit_resources(bp, true);
3654 static int bnxt_restore_filters(struct bnxt *bp)
3656 struct rte_eth_dev *dev = bp->eth_dev;
3659 if (dev->data->all_multicast)
3660 ret = bnxt_allmulticast_enable_op(dev);
3661 if (dev->data->promiscuous)
3662 ret = bnxt_promiscuous_enable_op(dev);
3664 /* TODO restore other filters as well */
3668 static void bnxt_dev_recover(void *arg)
3670 struct bnxt *bp = arg;
3671 int timeout = bp->fw_reset_max_msecs;
3674 /* Clear Error flag so that device re-init should happen */
3675 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3678 rc = bnxt_hwrm_ver_get(bp);
3681 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3682 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3683 } while (rc && timeout);
3686 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3690 rc = bnxt_init_resources(bp, true);
3693 "Failed to initialize resources after reset\n");
3696 /* clear reset flag as the device is initialized now */
3697 bp->flags &= ~BNXT_FLAG_FW_RESET;
3699 rc = bnxt_dev_start_op(bp->eth_dev);
3701 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3705 rc = bnxt_restore_filters(bp);
3709 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3712 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3713 bnxt_uninit_resources(bp, false);
3714 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3717 void bnxt_dev_reset_and_resume(void *arg)
3719 struct bnxt *bp = arg;
3722 bnxt_dev_cleanup(bp);
3724 bnxt_wait_for_device_shutdown(bp);
3726 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3727 bnxt_dev_recover, (void *)bp);
3729 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3732 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3734 struct bnxt_error_recovery_info *info = bp->recovery_info;
3735 uint32_t reg = info->status_regs[index];
3736 uint32_t type, offset, val = 0;
3738 type = BNXT_FW_STATUS_REG_TYPE(reg);
3739 offset = BNXT_FW_STATUS_REG_OFF(reg);
3742 case BNXT_FW_STATUS_REG_TYPE_CFG:
3743 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3745 case BNXT_FW_STATUS_REG_TYPE_GRC:
3746 offset = info->mapped_status_regs[index];
3748 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3749 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3757 static int bnxt_fw_reset_all(struct bnxt *bp)
3759 struct bnxt_error_recovery_info *info = bp->recovery_info;
3763 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3764 /* Reset through master function driver */
3765 for (i = 0; i < info->reg_array_cnt; i++)
3766 bnxt_write_fw_reset_reg(bp, i);
3767 /* Wait for time specified by FW after triggering reset */
3768 rte_delay_ms(info->master_func_wait_period_after_reset);
3769 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3770 /* Reset with the help of Kong processor */
3771 rc = bnxt_hwrm_fw_reset(bp);
3773 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3779 static void bnxt_fw_reset_cb(void *arg)
3781 struct bnxt *bp = arg;
3782 struct bnxt_error_recovery_info *info = bp->recovery_info;
3785 /* Only Master function can do FW reset */
3786 if (bnxt_is_master_func(bp) &&
3787 bnxt_is_recovery_enabled(bp)) {
3788 rc = bnxt_fw_reset_all(bp);
3790 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3795 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3796 * EXCEPTION_FATAL_ASYNC event to all the functions
3797 * (including MASTER FUNC). After receiving this Async, all the active
3798 * drivers should treat this case as FW initiated recovery
3800 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3801 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3802 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3804 /* To recover from error */
3805 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3810 /* Driver should poll FW heartbeat, reset_counter with the frequency
3811 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3812 * When the driver detects heartbeat stop or change in reset_counter,
3813 * it has to trigger a reset to recover from the error condition.
3814 * A “master PF” is the function who will have the privilege to
3815 * initiate the chimp reset. The master PF will be elected by the
3816 * firmware and will be notified through async message.
3818 static void bnxt_check_fw_health(void *arg)
3820 struct bnxt *bp = arg;
3821 struct bnxt_error_recovery_info *info = bp->recovery_info;
3822 uint32_t val = 0, wait_msec;
3824 if (!info || !bnxt_is_recovery_enabled(bp) ||
3825 is_bnxt_in_error(bp))
3828 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3829 if (val == info->last_heart_beat)
3832 info->last_heart_beat = val;
3834 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3835 if (val != info->last_reset_counter)
3838 info->last_reset_counter = val;
3840 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3841 bnxt_check_fw_health, (void *)bp);
3845 /* Stop DMA to/from device */
3846 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3847 bp->flags |= BNXT_FLAG_FW_RESET;
3849 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3851 if (bnxt_is_master_func(bp))
3852 wait_msec = info->master_func_wait_period;
3854 wait_msec = info->normal_func_wait_period;
3856 rte_eal_alarm_set(US_PER_MS * wait_msec,
3857 bnxt_fw_reset_cb, (void *)bp);
3860 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3862 uint32_t polling_freq;
3864 if (!bnxt_is_recovery_enabled(bp))
3867 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3870 polling_freq = bp->recovery_info->driver_polling_freq;
3872 rte_eal_alarm_set(US_PER_MS * polling_freq,
3873 bnxt_check_fw_health, (void *)bp);
3874 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3877 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3879 if (!bnxt_is_recovery_enabled(bp))
3882 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3883 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3886 static bool bnxt_vf_pciid(uint16_t id)
3888 if (id == BROADCOM_DEV_ID_57304_VF ||
3889 id == BROADCOM_DEV_ID_57406_VF ||
3890 id == BROADCOM_DEV_ID_5731X_VF ||
3891 id == BROADCOM_DEV_ID_5741X_VF ||
3892 id == BROADCOM_DEV_ID_57414_VF ||
3893 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3894 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3895 id == BROADCOM_DEV_ID_58802_VF ||
3896 id == BROADCOM_DEV_ID_57500_VF1 ||
3897 id == BROADCOM_DEV_ID_57500_VF2)
3902 bool bnxt_stratus_device(struct bnxt *bp)
3904 uint16_t id = bp->pdev->id.device_id;
3906 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3907 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3908 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3913 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3916 struct bnxt *bp = eth_dev->data->dev_private;
3918 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3919 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3920 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3921 if (!bp->bar0 || !bp->doorbell_base) {
3922 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3926 bp->eth_dev = eth_dev;
3932 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3933 struct bnxt_ctx_pg_info *ctx_pg,
3938 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3939 const struct rte_memzone *mz = NULL;
3940 char mz_name[RTE_MEMZONE_NAMESIZE];
3941 rte_iova_t mz_phys_addr;
3942 uint64_t valid_bits = 0;
3949 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3951 rmem->page_size = BNXT_PAGE_SIZE;
3952 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3953 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3954 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3956 valid_bits = PTU_PTE_VALID;
3958 if (rmem->nr_pages > 1) {
3959 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3960 "bnxt_ctx_pg_tbl%s_%x_%d",
3961 suffix, idx, bp->eth_dev->data->port_id);
3962 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3963 mz = rte_memzone_lookup(mz_name);
3965 mz = rte_memzone_reserve_aligned(mz_name,
3969 RTE_MEMZONE_SIZE_HINT_ONLY |
3970 RTE_MEMZONE_IOVA_CONTIG,
3976 memset(mz->addr, 0, mz->len);
3977 mz_phys_addr = mz->iova;
3978 if ((unsigned long)mz->addr == mz_phys_addr) {
3979 PMD_DRV_LOG(WARNING,
3980 "Memzone physical address same as virtual.\n");
3981 PMD_DRV_LOG(WARNING,
3982 "Using rte_mem_virt2iova()\n");
3983 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3984 if (mz_phys_addr == RTE_BAD_IOVA) {
3986 "unable to map addr to phys memory\n");
3990 rte_mem_lock_page(((char *)mz->addr));
3992 rmem->pg_tbl = mz->addr;
3993 rmem->pg_tbl_map = mz_phys_addr;
3994 rmem->pg_tbl_mz = mz;
3997 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3998 suffix, idx, bp->eth_dev->data->port_id);
3999 mz = rte_memzone_lookup(mz_name);
4001 mz = rte_memzone_reserve_aligned(mz_name,
4005 RTE_MEMZONE_SIZE_HINT_ONLY |
4006 RTE_MEMZONE_IOVA_CONTIG,
4012 memset(mz->addr, 0, mz->len);
4013 mz_phys_addr = mz->iova;
4014 if ((unsigned long)mz->addr == mz_phys_addr) {
4015 PMD_DRV_LOG(WARNING,
4016 "Memzone physical address same as virtual.\n");
4017 PMD_DRV_LOG(WARNING,
4018 "Using rte_mem_virt2iova()\n");
4019 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4020 rte_mem_lock_page(((char *)mz->addr) + sz);
4021 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4022 if (mz_phys_addr == RTE_BAD_IOVA) {
4024 "unable to map addr to phys memory\n");
4029 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4030 rte_mem_lock_page(((char *)mz->addr) + sz);
4031 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4032 rmem->dma_arr[i] = mz_phys_addr + sz;
4034 if (rmem->nr_pages > 1) {
4035 if (i == rmem->nr_pages - 2 &&
4036 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4037 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4038 else if (i == rmem->nr_pages - 1 &&
4039 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4040 valid_bits |= PTU_PTE_LAST;
4042 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4048 if (rmem->vmem_size)
4049 rmem->vmem = (void **)mz->addr;
4050 rmem->dma_arr[0] = mz_phys_addr;
4054 static void bnxt_free_ctx_mem(struct bnxt *bp)
4058 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4061 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4062 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4063 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4064 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4065 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4066 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4067 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4068 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4069 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4070 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4071 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4073 for (i = 0; i < BNXT_MAX_Q; i++) {
4074 if (bp->ctx->tqm_mem[i])
4075 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4082 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4084 #define min_t(type, x, y) ({ \
4085 type __min1 = (x); \
4086 type __min2 = (y); \
4087 __min1 < __min2 ? __min1 : __min2; })
4089 #define max_t(type, x, y) ({ \
4090 type __max1 = (x); \
4091 type __max2 = (y); \
4092 __max1 > __max2 ? __max1 : __max2; })
4094 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4096 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4098 struct bnxt_ctx_pg_info *ctx_pg;
4099 struct bnxt_ctx_mem_info *ctx;
4100 uint32_t mem_size, ena, entries;
4103 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4105 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4109 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4112 ctx_pg = &ctx->qp_mem;
4113 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4114 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4115 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4119 ctx_pg = &ctx->srq_mem;
4120 ctx_pg->entries = ctx->srq_max_l2_entries;
4121 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4122 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4126 ctx_pg = &ctx->cq_mem;
4127 ctx_pg->entries = ctx->cq_max_l2_entries;
4128 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4129 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4133 ctx_pg = &ctx->vnic_mem;
4134 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4135 ctx->vnic_max_ring_table_entries;
4136 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4137 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4141 ctx_pg = &ctx->stat_mem;
4142 ctx_pg->entries = ctx->stat_max_entries;
4143 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4144 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4148 entries = ctx->qp_max_l2_entries;
4149 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4150 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4151 ctx->tqm_max_entries_per_ring);
4152 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4153 ctx_pg = ctx->tqm_mem[i];
4154 /* use min tqm entries for now. */
4155 ctx_pg->entries = entries;
4156 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4157 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4160 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4163 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4164 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4167 "Failed to configure context mem: rc = %d\n", rc);
4169 ctx->flags |= BNXT_CTX_FLAG_INITED;
4174 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4176 struct rte_pci_device *pci_dev = bp->pdev;
4177 char mz_name[RTE_MEMZONE_NAMESIZE];
4178 const struct rte_memzone *mz = NULL;
4179 uint32_t total_alloc_len;
4180 rte_iova_t mz_phys_addr;
4182 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4185 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4186 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4187 pci_dev->addr.bus, pci_dev->addr.devid,
4188 pci_dev->addr.function, "rx_port_stats");
4189 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4190 mz = rte_memzone_lookup(mz_name);
4192 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4193 sizeof(struct rx_port_stats_ext) + 512);
4195 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4198 RTE_MEMZONE_SIZE_HINT_ONLY |
4199 RTE_MEMZONE_IOVA_CONTIG);
4203 memset(mz->addr, 0, mz->len);
4204 mz_phys_addr = mz->iova;
4205 if ((unsigned long)mz->addr == mz_phys_addr) {
4206 PMD_DRV_LOG(WARNING,
4207 "Memzone physical address same as virtual.\n");
4208 PMD_DRV_LOG(WARNING,
4209 "Using rte_mem_virt2iova()\n");
4210 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4211 if (mz_phys_addr == RTE_BAD_IOVA) {
4213 "Can't map address to physical memory\n");
4218 bp->rx_mem_zone = (const void *)mz;
4219 bp->hw_rx_port_stats = mz->addr;
4220 bp->hw_rx_port_stats_map = mz_phys_addr;
4222 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4223 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4224 pci_dev->addr.bus, pci_dev->addr.devid,
4225 pci_dev->addr.function, "tx_port_stats");
4226 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4227 mz = rte_memzone_lookup(mz_name);
4229 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4230 sizeof(struct tx_port_stats_ext) + 512);
4232 mz = rte_memzone_reserve(mz_name,
4236 RTE_MEMZONE_SIZE_HINT_ONLY |
4237 RTE_MEMZONE_IOVA_CONTIG);
4241 memset(mz->addr, 0, mz->len);
4242 mz_phys_addr = mz->iova;
4243 if ((unsigned long)mz->addr == mz_phys_addr) {
4244 PMD_DRV_LOG(WARNING,
4245 "Memzone physical address same as virtual\n");
4246 PMD_DRV_LOG(WARNING,
4247 "Using rte_mem_virt2iova()\n");
4248 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4249 if (mz_phys_addr == RTE_BAD_IOVA) {
4251 "Can't map address to physical memory\n");
4256 bp->tx_mem_zone = (const void *)mz;
4257 bp->hw_tx_port_stats = mz->addr;
4258 bp->hw_tx_port_stats_map = mz_phys_addr;
4259 bp->flags |= BNXT_FLAG_PORT_STATS;
4261 /* Display extended statistics if FW supports it */
4262 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4263 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4264 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4267 bp->hw_rx_port_stats_ext = (void *)
4268 ((uint8_t *)bp->hw_rx_port_stats +
4269 sizeof(struct rx_port_stats));
4270 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4271 sizeof(struct rx_port_stats);
4272 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4274 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4275 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4276 bp->hw_tx_port_stats_ext = (void *)
4277 ((uint8_t *)bp->hw_tx_port_stats +
4278 sizeof(struct tx_port_stats));
4279 bp->hw_tx_port_stats_ext_map =
4280 bp->hw_tx_port_stats_map +
4281 sizeof(struct tx_port_stats);
4282 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4288 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4290 struct bnxt *bp = eth_dev->data->dev_private;
4293 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4294 RTE_ETHER_ADDR_LEN *
4297 if (eth_dev->data->mac_addrs == NULL) {
4298 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4302 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4306 /* Generate a random MAC address, if none was assigned by PF */
4307 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4308 bnxt_eth_hw_addr_random(bp->mac_addr);
4310 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4311 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4312 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4314 rc = bnxt_hwrm_set_mac(bp);
4316 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4317 RTE_ETHER_ADDR_LEN);
4321 /* Copy the permanent MAC from the FUNC_QCAPS response */
4322 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4323 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4328 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4332 /* MAC is already configured in FW */
4333 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4336 /* Restore the old MAC configured */
4337 rc = bnxt_hwrm_set_mac(bp);
4339 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4344 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4349 #define ALLOW_FUNC(x) \
4351 uint32_t arg = (x); \
4352 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4353 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4356 /* Forward all requests if firmware is new enough */
4357 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4358 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4359 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4360 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4362 PMD_DRV_LOG(WARNING,
4363 "Firmware too old for VF mailbox functionality\n");
4364 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4368 * The following are used for driver cleanup. If we disallow these,
4369 * VF drivers can't clean up cleanly.
4371 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4372 ALLOW_FUNC(HWRM_VNIC_FREE);
4373 ALLOW_FUNC(HWRM_RING_FREE);
4374 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4375 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4376 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4377 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4378 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4379 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4382 static int bnxt_init_fw(struct bnxt *bp)
4387 rc = bnxt_hwrm_ver_get(bp);
4391 rc = bnxt_hwrm_func_reset(bp);
4395 rc = bnxt_hwrm_queue_qportcfg(bp);
4399 /* Get the MAX capabilities for this function */
4400 rc = bnxt_hwrm_func_qcaps(bp);
4404 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4408 /* Get the adapter error recovery support info */
4409 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4411 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4413 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4414 mtu != bp->eth_dev->data->mtu)
4415 bp->eth_dev->data->mtu = mtu;
4417 bnxt_hwrm_port_led_qcaps(bp);
4422 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4426 rc = bnxt_init_fw(bp);
4430 if (!reconfig_dev) {
4431 rc = bnxt_setup_mac_addr(bp->eth_dev);
4435 rc = bnxt_restore_dflt_mac(bp);
4440 bnxt_config_vf_req_fwd(bp);
4442 rc = bnxt_hwrm_func_driver_register(bp);
4444 PMD_DRV_LOG(ERR, "Failed to register driver");
4449 if (bp->pdev->max_vfs) {
4450 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4452 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4456 rc = bnxt_hwrm_allocate_pf_only(bp);
4459 "Failed to allocate PF resources");
4465 rc = bnxt_alloc_mem(bp, reconfig_dev);
4469 rc = bnxt_setup_int(bp);
4475 rc = bnxt_request_int(bp);
4483 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4485 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4486 static int version_printed;
4490 if (version_printed++ == 0)
4491 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4493 rte_eth_copy_pci_info(eth_dev, pci_dev);
4495 bp = eth_dev->data->dev_private;
4497 bp->dev_stopped = 1;
4499 eth_dev->dev_ops = &bnxt_dev_ops;
4500 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4501 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4504 * For secondary processes, we don't initialise any further
4505 * as primary has already done this work.
4507 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4510 if (bnxt_vf_pciid(pci_dev->id.device_id))
4511 bp->flags |= BNXT_FLAG_VF;
4513 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4514 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4515 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4516 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4517 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4518 bp->flags |= BNXT_FLAG_THOR_CHIP;
4520 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4521 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4522 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4523 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4524 bp->flags |= BNXT_FLAG_STINGRAY;
4526 rc = bnxt_init_board(eth_dev);
4529 "Failed to initialize board rc: %x\n", rc);
4533 rc = bnxt_alloc_hwrm_resources(bp);
4536 "Failed to allocate hwrm resource rc: %x\n", rc);
4539 rc = bnxt_init_resources(bp, false);
4543 rc = bnxt_alloc_stats_mem(bp);
4548 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4549 pci_dev->mem_resource[0].phys_addr,
4550 pci_dev->mem_resource[0].addr);
4555 bnxt_dev_uninit(eth_dev);
4560 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4564 bnxt_disable_int(bp);
4566 bnxt_free_mem(bp, reconfig_dev);
4567 bnxt_hwrm_func_buf_unrgtr(bp);
4568 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4569 bp->flags &= ~BNXT_FLAG_REGISTERED;
4570 bnxt_free_ctx_mem(bp);
4571 if (!reconfig_dev) {
4572 bnxt_free_hwrm_resources(bp);
4574 if (bp->recovery_info != NULL) {
4575 rte_free(bp->recovery_info);
4576 bp->recovery_info = NULL;
4584 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4586 struct bnxt *bp = eth_dev->data->dev_private;
4589 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4592 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4594 rc = bnxt_uninit_resources(bp, false);
4596 if (bp->grp_info != NULL) {
4597 rte_free(bp->grp_info);
4598 bp->grp_info = NULL;
4601 if (bp->tx_mem_zone) {
4602 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4603 bp->tx_mem_zone = NULL;
4606 if (bp->rx_mem_zone) {
4607 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4608 bp->rx_mem_zone = NULL;
4611 if (bp->dev_stopped == 0)
4612 bnxt_dev_close_op(eth_dev);
4614 rte_free(bp->pf.vf_info);
4615 eth_dev->dev_ops = NULL;
4616 eth_dev->rx_pkt_burst = NULL;
4617 eth_dev->tx_pkt_burst = NULL;
4622 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4623 struct rte_pci_device *pci_dev)
4625 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4629 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4631 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4632 return rte_eth_dev_pci_generic_remove(pci_dev,
4635 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4638 static struct rte_pci_driver bnxt_rte_pmd = {
4639 .id_table = bnxt_pci_id_map,
4640 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4641 .probe = bnxt_pci_probe,
4642 .remove = bnxt_pci_remove,
4646 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4648 if (strcmp(dev->device->driver->name, drv->driver.name))
4654 bool is_bnxt_supported(struct rte_eth_dev *dev)
4656 return is_device_supported(dev, &bnxt_rte_pmd);
4659 RTE_INIT(bnxt_init_log)
4661 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4662 if (bnxt_logtype_driver >= 0)
4663 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4666 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4667 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4668 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");