1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
132 static const char *const bnxt_dev_args[] = {
134 BNXT_DEVARG_FLOW_XSTAT,
139 * truflow == false to disable the feature
140 * truflow == true to enable the feature
142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
145 * flow_xstat == false to disable the feature
146 * flow_xstat == true to enable the feature
148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
157 static void bnxt_dev_recover(void *arg);
158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
160 int is_bnxt_in_error(struct bnxt *bp)
162 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
164 if (bp->flags & BNXT_FLAG_FW_RESET)
170 /***********************/
173 * High level utility functions
176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
178 if (!BNXT_CHIP_THOR(bp))
181 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
182 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
183 BNXT_RSS_ENTRIES_PER_CTX_THOR;
186 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
188 if (!BNXT_CHIP_THOR(bp))
189 return HW_HASH_INDEX_SIZE;
191 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
194 static void bnxt_free_leds_info(struct bnxt *bp)
200 static void bnxt_free_cos_queues(struct bnxt *bp)
202 rte_free(bp->rx_cos_queue);
203 rte_free(bp->tx_cos_queue);
206 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
208 bnxt_free_filter_mem(bp);
209 bnxt_free_vnic_attributes(bp);
210 bnxt_free_vnic_mem(bp);
212 /* tx/rx rings are configured as part of *_queue_setup callbacks.
213 * If the number of rings change across fw update,
214 * we don't have much choice except to warn the user.
218 bnxt_free_tx_rings(bp);
219 bnxt_free_rx_rings(bp);
221 bnxt_free_async_cp_ring(bp);
222 bnxt_free_rxtx_nq_ring(bp);
224 rte_free(bp->grp_info);
228 static int bnxt_alloc_leds_info(struct bnxt *bp)
230 bp->leds = rte_zmalloc("bnxt_leds",
231 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
233 if (bp->leds == NULL)
239 static int bnxt_alloc_cos_queues(struct bnxt *bp)
242 rte_zmalloc("bnxt_rx_cosq",
243 BNXT_COS_QUEUE_COUNT *
244 sizeof(struct bnxt_cos_queue_info),
246 if (bp->rx_cos_queue == NULL)
250 rte_zmalloc("bnxt_tx_cosq",
251 BNXT_COS_QUEUE_COUNT *
252 sizeof(struct bnxt_cos_queue_info),
254 if (bp->tx_cos_queue == NULL)
260 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
264 rc = bnxt_alloc_ring_grps(bp);
268 rc = bnxt_alloc_async_ring_struct(bp);
272 rc = bnxt_alloc_vnic_mem(bp);
276 rc = bnxt_alloc_vnic_attributes(bp);
280 rc = bnxt_alloc_filter_mem(bp);
284 rc = bnxt_alloc_async_cp_ring(bp);
288 rc = bnxt_alloc_rxtx_nq_ring(bp);
295 bnxt_free_mem(bp, reconfig);
299 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
301 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
302 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
303 uint64_t rx_offloads = dev_conf->rxmode.offloads;
304 struct bnxt_rx_queue *rxq;
308 rc = bnxt_vnic_grp_alloc(bp, vnic);
312 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
313 vnic_id, vnic, vnic->fw_grp_ids);
315 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
319 /* Alloc RSS context only if RSS mode is enabled */
320 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
321 int j, nr_ctxs = bnxt_rss_ctxts(bp);
324 for (j = 0; j < nr_ctxs; j++) {
325 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
331 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
335 vnic->num_lb_ctxts = nr_ctxs;
339 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
340 * setting is not available at this time, it will not be
341 * configured correctly in the CFA.
343 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
344 vnic->vlan_strip = true;
346 vnic->vlan_strip = false;
348 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
352 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
356 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
357 rxq = bp->eth_dev->data->rx_queues[j];
360 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
361 j, rxq->vnic, rxq->vnic->fw_grp_ids);
363 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
364 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
366 vnic->rx_queue_cnt++;
369 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
371 rc = bnxt_vnic_rss_configure(bp, vnic);
375 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
377 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
378 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
380 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
384 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
389 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
393 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
394 &bp->rx_fc_in_tbl.ctx_id);
399 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
400 " rx_fc_in_tbl.ctx_id = %d\n",
402 (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
403 bp->rx_fc_in_tbl.ctx_id);
405 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
406 &bp->rx_fc_out_tbl.ctx_id);
411 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
412 " rx_fc_out_tbl.ctx_id = %d\n",
413 bp->rx_fc_out_tbl.va,
414 (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
415 bp->rx_fc_out_tbl.ctx_id);
417 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
418 &bp->tx_fc_in_tbl.ctx_id);
423 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
424 " tx_fc_in_tbl.ctx_id = %d\n",
426 (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
427 bp->tx_fc_in_tbl.ctx_id);
429 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
430 &bp->tx_fc_out_tbl.ctx_id);
435 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
436 " tx_fc_out_tbl.ctx_id = %d\n",
437 bp->tx_fc_out_tbl.va,
438 (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
439 bp->tx_fc_out_tbl.ctx_id);
441 memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
442 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
443 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
444 bp->rx_fc_out_tbl.ctx_id,
450 memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
451 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
452 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
453 bp->tx_fc_out_tbl.ctx_id,
460 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
461 struct bnxt_ctx_mem_buf_info *ctx)
466 ctx->va = rte_zmalloc(type, size, 0);
469 rte_mem_lock_page(ctx->va);
471 ctx->dma = rte_mem_virt2iova(ctx->va);
472 if (ctx->dma == RTE_BAD_IOVA)
478 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
480 struct rte_pci_device *pdev = bp->pdev;
481 char type[RTE_MEMZONE_NAMESIZE];
487 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
488 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
489 /* 4 bytes for each counter-id */
490 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
494 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
495 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
496 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
497 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
501 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
502 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
503 /* 4 bytes for each counter-id */
504 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
508 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
509 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
510 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
511 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
515 rc = bnxt_register_fc_ctx_mem(bp);
520 static int bnxt_init_ctx_mem(struct bnxt *bp)
524 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
525 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
528 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
532 rc = bnxt_init_fc_ctx_mem(bp);
537 static int bnxt_init_chip(struct bnxt *bp)
539 struct rte_eth_link new;
540 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
541 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
542 uint32_t intr_vector = 0;
543 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
544 uint32_t vec = BNXT_MISC_VEC_ID;
548 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
549 bp->eth_dev->data->dev_conf.rxmode.offloads |=
550 DEV_RX_OFFLOAD_JUMBO_FRAME;
551 bp->flags |= BNXT_FLAG_JUMBO;
553 bp->eth_dev->data->dev_conf.rxmode.offloads &=
554 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
555 bp->flags &= ~BNXT_FLAG_JUMBO;
558 /* THOR does not support ring groups.
559 * But we will use the array to save RSS context IDs.
561 if (BNXT_CHIP_THOR(bp))
562 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
564 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
566 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
570 rc = bnxt_alloc_hwrm_rings(bp);
572 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
576 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
578 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
582 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
585 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
586 if (bp->rx_cos_queue[i].id != 0xff) {
587 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
591 "Num pools more than FW profile\n");
595 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
601 rc = bnxt_mq_rx_configure(bp);
603 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
607 /* VNIC configuration */
608 for (i = 0; i < bp->nr_vnics; i++) {
609 rc = bnxt_setup_one_vnic(bp, i);
614 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
617 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
621 /* check and configure queue intr-vector mapping */
622 if ((rte_intr_cap_multiple(intr_handle) ||
623 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
624 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
625 intr_vector = bp->eth_dev->data->nb_rx_queues;
626 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
627 if (intr_vector > bp->rx_cp_nr_rings) {
628 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
632 rc = rte_intr_efd_enable(intr_handle, intr_vector);
637 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
638 intr_handle->intr_vec =
639 rte_zmalloc("intr_vec",
640 bp->eth_dev->data->nb_rx_queues *
642 if (intr_handle->intr_vec == NULL) {
643 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
644 " intr_vec", bp->eth_dev->data->nb_rx_queues);
648 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
649 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
650 intr_handle->intr_vec, intr_handle->nb_efd,
651 intr_handle->max_intr);
652 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
654 intr_handle->intr_vec[queue_id] =
655 vec + BNXT_RX_VEC_START;
656 if (vec < base + intr_handle->nb_efd - 1)
661 /* enable uio/vfio intr/eventfd mapping */
662 rc = rte_intr_enable(intr_handle);
663 #ifndef RTE_EXEC_ENV_FREEBSD
664 /* In FreeBSD OS, nic_uio driver does not support interrupts */
669 rc = bnxt_get_hwrm_link_config(bp, &new);
671 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
675 if (!bp->link_info.link_up) {
676 rc = bnxt_set_hwrm_link_config(bp, true);
679 "HWRM link config failure rc: %x\n", rc);
683 bnxt_print_link_info(bp->eth_dev);
685 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
687 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
692 rte_free(intr_handle->intr_vec);
694 rte_intr_efd_disable(intr_handle);
696 /* Some of the error status returned by FW may not be from errno.h */
703 static int bnxt_shutdown_nic(struct bnxt *bp)
705 bnxt_free_all_hwrm_resources(bp);
706 bnxt_free_all_filters(bp);
707 bnxt_free_all_vnics(bp);
712 * Device configuration and status function
715 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
717 uint32_t link_speed = bp->link_info.support_speeds;
718 uint32_t speed_capa = 0;
720 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
721 speed_capa |= ETH_LINK_SPEED_100M;
722 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
723 speed_capa |= ETH_LINK_SPEED_100M_HD;
724 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
725 speed_capa |= ETH_LINK_SPEED_1G;
726 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
727 speed_capa |= ETH_LINK_SPEED_2_5G;
728 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
729 speed_capa |= ETH_LINK_SPEED_10G;
730 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
731 speed_capa |= ETH_LINK_SPEED_20G;
732 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
733 speed_capa |= ETH_LINK_SPEED_25G;
734 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
735 speed_capa |= ETH_LINK_SPEED_40G;
736 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
737 speed_capa |= ETH_LINK_SPEED_50G;
738 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
739 speed_capa |= ETH_LINK_SPEED_100G;
740 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
741 speed_capa |= ETH_LINK_SPEED_200G;
743 if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
744 speed_capa |= ETH_LINK_SPEED_FIXED;
746 speed_capa |= ETH_LINK_SPEED_AUTONEG;
751 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
752 struct rte_eth_dev_info *dev_info)
754 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
755 struct bnxt *bp = eth_dev->data->dev_private;
756 uint16_t max_vnics, i, j, vpool, vrxq;
757 unsigned int max_rx_rings;
760 rc = is_bnxt_in_error(bp);
765 dev_info->max_mac_addrs = bp->max_l2_ctx;
766 dev_info->max_hash_mac_addrs = 0;
768 /* PF/VF specifics */
770 dev_info->max_vfs = pdev->max_vfs;
772 max_rx_rings = BNXT_MAX_RINGS(bp);
773 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
774 dev_info->max_rx_queues = max_rx_rings;
775 dev_info->max_tx_queues = max_rx_rings;
776 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
777 dev_info->hash_key_size = 40;
778 max_vnics = bp->max_vnics;
781 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
782 dev_info->max_mtu = BNXT_MAX_MTU;
784 /* Fast path specifics */
785 dev_info->min_rx_bufsize = 1;
786 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
788 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
789 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
790 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
791 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
792 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
794 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
797 dev_info->default_rxconf = (struct rte_eth_rxconf) {
803 .rx_free_thresh = 32,
804 /* If no descriptors available, pkts are dropped by default */
808 dev_info->default_txconf = (struct rte_eth_txconf) {
814 .tx_free_thresh = 32,
817 eth_dev->data->dev_conf.intr_conf.lsc = 1;
819 eth_dev->data->dev_conf.intr_conf.rxq = 1;
820 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
821 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
822 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
823 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
828 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
829 * need further investigation.
833 vpool = 64; /* ETH_64_POOLS */
834 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
835 for (i = 0; i < 4; vpool >>= 1, i++) {
836 if (max_vnics > vpool) {
837 for (j = 0; j < 5; vrxq >>= 1, j++) {
838 if (dev_info->max_rx_queues > vrxq) {
844 /* Not enough resources to support VMDq */
848 /* Not enough resources to support VMDq */
852 dev_info->max_vmdq_pools = vpool;
853 dev_info->vmdq_queue_num = vrxq;
855 dev_info->vmdq_pool_base = 0;
856 dev_info->vmdq_queue_base = 0;
861 /* Configure the device based on the configuration provided */
862 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
864 struct bnxt *bp = eth_dev->data->dev_private;
865 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
868 bp->rx_queues = (void *)eth_dev->data->rx_queues;
869 bp->tx_queues = (void *)eth_dev->data->tx_queues;
870 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
871 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
873 rc = is_bnxt_in_error(bp);
877 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
878 rc = bnxt_hwrm_check_vf_rings(bp);
880 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
884 /* If a resource has already been allocated - in this case
885 * it is the async completion ring, free it. Reallocate it after
886 * resource reservation. This will ensure the resource counts
887 * are calculated correctly.
890 pthread_mutex_lock(&bp->def_cp_lock);
892 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
893 bnxt_disable_int(bp);
894 bnxt_free_cp_ring(bp, bp->async_cp_ring);
897 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
899 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
900 pthread_mutex_unlock(&bp->def_cp_lock);
904 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
905 rc = bnxt_alloc_async_cp_ring(bp);
907 pthread_mutex_unlock(&bp->def_cp_lock);
913 pthread_mutex_unlock(&bp->def_cp_lock);
915 /* legacy driver needs to get updated values */
916 rc = bnxt_hwrm_func_qcaps(bp);
918 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
923 /* Inherit new configurations */
924 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
925 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
926 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
927 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
928 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
932 if (BNXT_HAS_RING_GRPS(bp) &&
933 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
936 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
937 bp->max_vnics < eth_dev->data->nb_rx_queues)
940 bp->rx_cp_nr_rings = bp->rx_nr_rings;
941 bp->tx_cp_nr_rings = bp->tx_nr_rings;
943 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
944 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
945 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
947 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
949 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
950 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
952 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
958 "Insufficient resources to support requested config\n");
960 "Num Queues Requested: Tx %d, Rx %d\n",
961 eth_dev->data->nb_tx_queues,
962 eth_dev->data->nb_rx_queues);
964 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
965 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
966 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
970 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
972 struct rte_eth_link *link = ð_dev->data->dev_link;
974 if (link->link_status)
975 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
976 eth_dev->data->port_id,
977 (uint32_t)link->link_speed,
978 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
979 ("full-duplex") : ("half-duplex\n"));
981 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
982 eth_dev->data->port_id);
986 * Determine whether the current configuration requires support for scattered
987 * receive; return 1 if scattered receive is required and 0 if not.
989 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
994 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
997 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
998 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1000 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1001 RTE_PKTMBUF_HEADROOM);
1002 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1008 static eth_rx_burst_t
1009 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1011 struct bnxt *bp = eth_dev->data->dev_private;
1014 #ifndef RTE_LIBRTE_IEEE1588
1016 * Vector mode receive can be enabled only if scatter rx is not
1017 * in use and rx offloads are limited to VLAN stripping and
1020 if (!eth_dev->data->scattered_rx &&
1021 !(eth_dev->data->dev_conf.rxmode.offloads &
1022 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1023 DEV_RX_OFFLOAD_KEEP_CRC |
1024 DEV_RX_OFFLOAD_JUMBO_FRAME |
1025 DEV_RX_OFFLOAD_IPV4_CKSUM |
1026 DEV_RX_OFFLOAD_UDP_CKSUM |
1027 DEV_RX_OFFLOAD_TCP_CKSUM |
1028 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1029 DEV_RX_OFFLOAD_RSS_HASH |
1030 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1032 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1033 eth_dev->data->port_id);
1034 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1035 return bnxt_recv_pkts_vec;
1037 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1038 eth_dev->data->port_id);
1040 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1041 eth_dev->data->port_id,
1042 eth_dev->data->scattered_rx,
1043 eth_dev->data->dev_conf.rxmode.offloads);
1046 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1047 return bnxt_recv_pkts;
1050 static eth_tx_burst_t
1051 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1054 #ifndef RTE_LIBRTE_IEEE1588
1056 * Vector mode transmit can be enabled only if not using scatter rx
1059 if (!eth_dev->data->scattered_rx &&
1060 !eth_dev->data->dev_conf.txmode.offloads) {
1061 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1062 eth_dev->data->port_id);
1063 return bnxt_xmit_pkts_vec;
1065 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1066 eth_dev->data->port_id);
1068 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1069 eth_dev->data->port_id,
1070 eth_dev->data->scattered_rx,
1071 eth_dev->data->dev_conf.txmode.offloads);
1074 return bnxt_xmit_pkts;
1077 static int bnxt_handle_if_change_status(struct bnxt *bp)
1081 /* Since fw has undergone a reset and lost all contexts,
1082 * set fatal flag to not issue hwrm during cleanup
1084 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1085 bnxt_uninit_resources(bp, true);
1087 /* clear fatal flag so that re-init happens */
1088 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1089 rc = bnxt_init_resources(bp, true);
1091 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1096 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1098 struct bnxt *bp = eth_dev->data->dev_private;
1099 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1101 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1103 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1104 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1108 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1110 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1111 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1115 rc = bnxt_hwrm_if_change(bp, true);
1116 if (rc == 0 || rc != -EAGAIN)
1119 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1120 } while (retry_cnt--);
1125 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1126 rc = bnxt_handle_if_change_status(bp);
1131 bnxt_enable_int(bp);
1133 rc = bnxt_init_chip(bp);
1137 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1138 eth_dev->data->dev_started = 1;
1140 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1142 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1143 vlan_mask |= ETH_VLAN_FILTER_MASK;
1144 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1145 vlan_mask |= ETH_VLAN_STRIP_MASK;
1146 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1150 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1151 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1153 pthread_mutex_lock(&bp->def_cp_lock);
1154 bnxt_schedule_fw_health_check(bp);
1155 pthread_mutex_unlock(&bp->def_cp_lock);
1163 bnxt_shutdown_nic(bp);
1164 bnxt_free_tx_mbufs(bp);
1165 bnxt_free_rx_mbufs(bp);
1166 bnxt_hwrm_if_change(bp, false);
1167 eth_dev->data->dev_started = 0;
1171 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1173 struct bnxt *bp = eth_dev->data->dev_private;
1176 if (!bp->link_info.link_up)
1177 rc = bnxt_set_hwrm_link_config(bp, true);
1179 eth_dev->data->dev_link.link_status = 1;
1181 bnxt_print_link_info(eth_dev);
1185 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1187 struct bnxt *bp = eth_dev->data->dev_private;
1189 eth_dev->data->dev_link.link_status = 0;
1190 bnxt_set_hwrm_link_config(bp, false);
1191 bp->link_info.link_up = 0;
1196 /* Unload the driver, release resources */
1197 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1199 struct bnxt *bp = eth_dev->data->dev_private;
1200 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1201 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1204 bnxt_ulp_deinit(bp);
1206 eth_dev->data->dev_started = 0;
1207 /* Prevent crashes when queues are still in use */
1208 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1209 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1211 bnxt_disable_int(bp);
1213 /* disable uio/vfio intr/eventfd mapping */
1214 rte_intr_disable(intr_handle);
1216 bnxt_cancel_fw_health_check(bp);
1218 bnxt_dev_set_link_down_op(eth_dev);
1220 /* Wait for link to be reset and the async notification to process.
1221 * During reset recovery, there is no need to wait and
1222 * VF/NPAR functions do not have privilege to change PHY config.
1224 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1225 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1227 /* Clean queue intr-vector mapping */
1228 rte_intr_efd_disable(intr_handle);
1229 if (intr_handle->intr_vec != NULL) {
1230 rte_free(intr_handle->intr_vec);
1231 intr_handle->intr_vec = NULL;
1234 bnxt_hwrm_port_clr_stats(bp);
1235 bnxt_free_tx_mbufs(bp);
1236 bnxt_free_rx_mbufs(bp);
1237 /* Process any remaining notifications in default completion queue */
1238 bnxt_int_handler(eth_dev);
1239 bnxt_shutdown_nic(bp);
1240 bnxt_hwrm_if_change(bp, false);
1242 rte_free(bp->mark_table);
1243 bp->mark_table = NULL;
1245 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1246 bp->rx_cosq_cnt = 0;
1249 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1251 struct bnxt *bp = eth_dev->data->dev_private;
1253 /* cancel the recovery handler before remove dev */
1254 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1255 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1256 bnxt_cancel_fc_thread(bp);
1258 if (eth_dev->data->dev_started)
1259 bnxt_dev_stop_op(eth_dev);
1261 bnxt_uninit_resources(bp, false);
1263 bnxt_free_leds_info(bp);
1264 bnxt_free_cos_queues(bp);
1266 eth_dev->dev_ops = NULL;
1267 eth_dev->rx_pkt_burst = NULL;
1268 eth_dev->tx_pkt_burst = NULL;
1270 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1271 bp->tx_mem_zone = NULL;
1272 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1273 bp->rx_mem_zone = NULL;
1275 rte_free(bp->pf.vf_info);
1276 bp->pf.vf_info = NULL;
1278 rte_free(bp->grp_info);
1279 bp->grp_info = NULL;
1282 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1285 struct bnxt *bp = eth_dev->data->dev_private;
1286 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1287 struct bnxt_vnic_info *vnic;
1288 struct bnxt_filter_info *filter, *temp_filter;
1291 if (is_bnxt_in_error(bp))
1295 * Loop through all VNICs from the specified filter flow pools to
1296 * remove the corresponding MAC addr filter
1298 for (i = 0; i < bp->nr_vnics; i++) {
1299 if (!(pool_mask & (1ULL << i)))
1302 vnic = &bp->vnic_info[i];
1303 filter = STAILQ_FIRST(&vnic->filter);
1305 temp_filter = STAILQ_NEXT(filter, next);
1306 if (filter->mac_index == index) {
1307 STAILQ_REMOVE(&vnic->filter, filter,
1308 bnxt_filter_info, next);
1309 bnxt_hwrm_clear_l2_filter(bp, filter);
1310 bnxt_free_filter(bp, filter);
1312 filter = temp_filter;
1317 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1318 struct rte_ether_addr *mac_addr, uint32_t index,
1321 struct bnxt_filter_info *filter;
1324 /* Attach requested MAC address to the new l2_filter */
1325 STAILQ_FOREACH(filter, &vnic->filter, next) {
1326 if (filter->mac_index == index) {
1328 "MAC addr already existed for pool %d\n",
1334 filter = bnxt_alloc_filter(bp);
1336 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1340 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1341 * if the MAC that's been programmed now is a different one, then,
1342 * copy that addr to filter->l2_addr
1345 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1346 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1348 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1350 filter->mac_index = index;
1351 if (filter->mac_index == 0)
1352 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1354 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1356 bnxt_free_filter(bp, filter);
1362 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1363 struct rte_ether_addr *mac_addr,
1364 uint32_t index, uint32_t pool)
1366 struct bnxt *bp = eth_dev->data->dev_private;
1367 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1370 rc = is_bnxt_in_error(bp);
1374 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1375 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1380 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1384 /* Filter settings will get applied when port is started */
1385 if (!eth_dev->data->dev_started)
1388 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1393 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1394 bool exp_link_status)
1397 struct bnxt *bp = eth_dev->data->dev_private;
1398 struct rte_eth_link new;
1399 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1400 BNXT_LINK_DOWN_WAIT_CNT;
1402 rc = is_bnxt_in_error(bp);
1406 memset(&new, 0, sizeof(new));
1408 /* Retrieve link info from hardware */
1409 rc = bnxt_get_hwrm_link_config(bp, &new);
1411 new.link_speed = ETH_LINK_SPEED_100M;
1412 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1414 "Failed to retrieve link rc = 0x%x!\n", rc);
1418 if (!wait_to_complete || new.link_status == exp_link_status)
1421 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1425 /* Timed out or success */
1426 if (new.link_status != eth_dev->data->dev_link.link_status ||
1427 new.link_speed != eth_dev->data->dev_link.link_speed) {
1428 rte_eth_linkstatus_set(eth_dev, &new);
1430 _rte_eth_dev_callback_process(eth_dev,
1431 RTE_ETH_EVENT_INTR_LSC,
1434 bnxt_print_link_info(eth_dev);
1440 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1441 int wait_to_complete)
1443 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1446 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1448 struct bnxt *bp = eth_dev->data->dev_private;
1449 struct bnxt_vnic_info *vnic;
1453 rc = is_bnxt_in_error(bp);
1457 /* Filter settings will get applied when port is started */
1458 if (!eth_dev->data->dev_started)
1461 if (bp->vnic_info == NULL)
1464 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1466 old_flags = vnic->flags;
1467 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1468 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1470 vnic->flags = old_flags;
1475 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1477 struct bnxt *bp = eth_dev->data->dev_private;
1478 struct bnxt_vnic_info *vnic;
1482 rc = is_bnxt_in_error(bp);
1486 /* Filter settings will get applied when port is started */
1487 if (!eth_dev->data->dev_started)
1490 if (bp->vnic_info == NULL)
1493 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1495 old_flags = vnic->flags;
1496 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1497 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1499 vnic->flags = old_flags;
1504 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1506 struct bnxt *bp = eth_dev->data->dev_private;
1507 struct bnxt_vnic_info *vnic;
1511 rc = is_bnxt_in_error(bp);
1515 /* Filter settings will get applied when port is started */
1516 if (!eth_dev->data->dev_started)
1519 if (bp->vnic_info == NULL)
1522 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1524 old_flags = vnic->flags;
1525 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1526 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1528 vnic->flags = old_flags;
1533 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1535 struct bnxt *bp = eth_dev->data->dev_private;
1536 struct bnxt_vnic_info *vnic;
1540 rc = is_bnxt_in_error(bp);
1544 /* Filter settings will get applied when port is started */
1545 if (!eth_dev->data->dev_started)
1548 if (bp->vnic_info == NULL)
1551 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1553 old_flags = vnic->flags;
1554 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1555 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1557 vnic->flags = old_flags;
1562 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1563 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1565 if (qid >= bp->rx_nr_rings)
1568 return bp->eth_dev->data->rx_queues[qid];
1571 /* Return rxq corresponding to a given rss table ring/group ID. */
1572 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1574 struct bnxt_rx_queue *rxq;
1577 if (!BNXT_HAS_RING_GRPS(bp)) {
1578 for (i = 0; i < bp->rx_nr_rings; i++) {
1579 rxq = bp->eth_dev->data->rx_queues[i];
1580 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1584 for (i = 0; i < bp->rx_nr_rings; i++) {
1585 if (bp->grp_info[i].fw_grp_id == fwr)
1590 return INVALID_HW_RING_ID;
1593 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1594 struct rte_eth_rss_reta_entry64 *reta_conf,
1597 struct bnxt *bp = eth_dev->data->dev_private;
1598 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1599 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1600 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1604 rc = is_bnxt_in_error(bp);
1608 if (!vnic->rss_table)
1611 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1614 if (reta_size != tbl_size) {
1615 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1616 "(%d) must equal the size supported by the hardware "
1617 "(%d)\n", reta_size, tbl_size);
1621 for (i = 0; i < reta_size; i++) {
1622 struct bnxt_rx_queue *rxq;
1624 idx = i / RTE_RETA_GROUP_SIZE;
1625 sft = i % RTE_RETA_GROUP_SIZE;
1627 if (!(reta_conf[idx].mask & (1ULL << sft)))
1630 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1632 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1636 if (BNXT_CHIP_THOR(bp)) {
1637 vnic->rss_table[i * 2] =
1638 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1639 vnic->rss_table[i * 2 + 1] =
1640 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1642 vnic->rss_table[i] =
1643 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1647 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1651 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1652 struct rte_eth_rss_reta_entry64 *reta_conf,
1655 struct bnxt *bp = eth_dev->data->dev_private;
1656 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1657 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1658 uint16_t idx, sft, i;
1661 rc = is_bnxt_in_error(bp);
1665 /* Retrieve from the default VNIC */
1668 if (!vnic->rss_table)
1671 if (reta_size != tbl_size) {
1672 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1673 "(%d) must equal the size supported by the hardware "
1674 "(%d)\n", reta_size, tbl_size);
1678 for (idx = 0, i = 0; i < reta_size; i++) {
1679 idx = i / RTE_RETA_GROUP_SIZE;
1680 sft = i % RTE_RETA_GROUP_SIZE;
1682 if (reta_conf[idx].mask & (1ULL << sft)) {
1685 if (BNXT_CHIP_THOR(bp))
1686 qid = bnxt_rss_to_qid(bp,
1687 vnic->rss_table[i * 2]);
1689 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1691 if (qid == INVALID_HW_RING_ID) {
1692 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1695 reta_conf[idx].reta[sft] = qid;
1702 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1703 struct rte_eth_rss_conf *rss_conf)
1705 struct bnxt *bp = eth_dev->data->dev_private;
1706 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1707 struct bnxt_vnic_info *vnic;
1710 rc = is_bnxt_in_error(bp);
1715 * If RSS enablement were different than dev_configure,
1716 * then return -EINVAL
1718 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1719 if (!rss_conf->rss_hf)
1720 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1722 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1726 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1727 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1729 /* Update the default RSS VNIC(s) */
1730 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1731 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1734 * If hashkey is not specified, use the previously configured
1737 if (!rss_conf->rss_key)
1740 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1742 "Invalid hashkey length, should be 16 bytes\n");
1745 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1748 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1752 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1753 struct rte_eth_rss_conf *rss_conf)
1755 struct bnxt *bp = eth_dev->data->dev_private;
1756 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1758 uint32_t hash_types;
1760 rc = is_bnxt_in_error(bp);
1764 /* RSS configuration is the same for all VNICs */
1765 if (vnic && vnic->rss_hash_key) {
1766 if (rss_conf->rss_key) {
1767 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1768 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1769 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1772 hash_types = vnic->hash_type;
1773 rss_conf->rss_hf = 0;
1774 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1775 rss_conf->rss_hf |= ETH_RSS_IPV4;
1776 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1778 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1779 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1781 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1783 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1784 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1786 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1788 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1789 rss_conf->rss_hf |= ETH_RSS_IPV6;
1790 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1792 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1793 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1795 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1797 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1798 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1800 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1804 "Unknown RSS config from firmware (%08x), RSS disabled",
1809 rss_conf->rss_hf = 0;
1814 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1815 struct rte_eth_fc_conf *fc_conf)
1817 struct bnxt *bp = dev->data->dev_private;
1818 struct rte_eth_link link_info;
1821 rc = is_bnxt_in_error(bp);
1825 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1829 memset(fc_conf, 0, sizeof(*fc_conf));
1830 if (bp->link_info.auto_pause)
1831 fc_conf->autoneg = 1;
1832 switch (bp->link_info.pause) {
1834 fc_conf->mode = RTE_FC_NONE;
1836 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1837 fc_conf->mode = RTE_FC_TX_PAUSE;
1839 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1840 fc_conf->mode = RTE_FC_RX_PAUSE;
1842 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1843 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1844 fc_conf->mode = RTE_FC_FULL;
1850 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1851 struct rte_eth_fc_conf *fc_conf)
1853 struct bnxt *bp = dev->data->dev_private;
1856 rc = is_bnxt_in_error(bp);
1860 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1861 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1865 switch (fc_conf->mode) {
1867 bp->link_info.auto_pause = 0;
1868 bp->link_info.force_pause = 0;
1870 case RTE_FC_RX_PAUSE:
1871 if (fc_conf->autoneg) {
1872 bp->link_info.auto_pause =
1873 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1874 bp->link_info.force_pause = 0;
1876 bp->link_info.auto_pause = 0;
1877 bp->link_info.force_pause =
1878 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1881 case RTE_FC_TX_PAUSE:
1882 if (fc_conf->autoneg) {
1883 bp->link_info.auto_pause =
1884 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1885 bp->link_info.force_pause = 0;
1887 bp->link_info.auto_pause = 0;
1888 bp->link_info.force_pause =
1889 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1893 if (fc_conf->autoneg) {
1894 bp->link_info.auto_pause =
1895 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1896 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1897 bp->link_info.force_pause = 0;
1899 bp->link_info.auto_pause = 0;
1900 bp->link_info.force_pause =
1901 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1902 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1906 return bnxt_set_hwrm_link_config(bp, true);
1909 /* Add UDP tunneling port */
1911 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1912 struct rte_eth_udp_tunnel *udp_tunnel)
1914 struct bnxt *bp = eth_dev->data->dev_private;
1915 uint16_t tunnel_type = 0;
1918 rc = is_bnxt_in_error(bp);
1922 switch (udp_tunnel->prot_type) {
1923 case RTE_TUNNEL_TYPE_VXLAN:
1924 if (bp->vxlan_port_cnt) {
1925 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1926 udp_tunnel->udp_port);
1927 if (bp->vxlan_port != udp_tunnel->udp_port) {
1928 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1931 bp->vxlan_port_cnt++;
1935 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1936 bp->vxlan_port_cnt++;
1938 case RTE_TUNNEL_TYPE_GENEVE:
1939 if (bp->geneve_port_cnt) {
1940 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1941 udp_tunnel->udp_port);
1942 if (bp->geneve_port != udp_tunnel->udp_port) {
1943 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1946 bp->geneve_port_cnt++;
1950 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1951 bp->geneve_port_cnt++;
1954 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1957 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1963 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1964 struct rte_eth_udp_tunnel *udp_tunnel)
1966 struct bnxt *bp = eth_dev->data->dev_private;
1967 uint16_t tunnel_type = 0;
1971 rc = is_bnxt_in_error(bp);
1975 switch (udp_tunnel->prot_type) {
1976 case RTE_TUNNEL_TYPE_VXLAN:
1977 if (!bp->vxlan_port_cnt) {
1978 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1981 if (bp->vxlan_port != udp_tunnel->udp_port) {
1982 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1983 udp_tunnel->udp_port, bp->vxlan_port);
1986 if (--bp->vxlan_port_cnt)
1990 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1991 port = bp->vxlan_fw_dst_port_id;
1993 case RTE_TUNNEL_TYPE_GENEVE:
1994 if (!bp->geneve_port_cnt) {
1995 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1998 if (bp->geneve_port != udp_tunnel->udp_port) {
1999 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2000 udp_tunnel->udp_port, bp->geneve_port);
2003 if (--bp->geneve_port_cnt)
2007 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2008 port = bp->geneve_fw_dst_port_id;
2011 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2015 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2018 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2021 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2022 bp->geneve_port = 0;
2027 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2029 struct bnxt_filter_info *filter;
2030 struct bnxt_vnic_info *vnic;
2032 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2034 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2035 filter = STAILQ_FIRST(&vnic->filter);
2037 /* Search for this matching MAC+VLAN filter */
2038 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2039 /* Delete the filter */
2040 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2043 STAILQ_REMOVE(&vnic->filter, filter,
2044 bnxt_filter_info, next);
2045 bnxt_free_filter(bp, filter);
2047 "Deleted vlan filter for %d\n",
2051 filter = STAILQ_NEXT(filter, next);
2056 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2058 struct bnxt_filter_info *filter;
2059 struct bnxt_vnic_info *vnic;
2061 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2062 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2063 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2065 /* Implementation notes on the use of VNIC in this command:
2067 * By default, these filters belong to default vnic for the function.
2068 * Once these filters are set up, only destination VNIC can be modified.
2069 * If the destination VNIC is not specified in this command,
2070 * then the HWRM shall only create an l2 context id.
2073 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2074 filter = STAILQ_FIRST(&vnic->filter);
2075 /* Check if the VLAN has already been added */
2077 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2080 filter = STAILQ_NEXT(filter, next);
2083 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2084 * command to create MAC+VLAN filter with the right flags, enables set.
2086 filter = bnxt_alloc_filter(bp);
2089 "MAC/VLAN filter alloc failed\n");
2092 /* MAC + VLAN ID filter */
2093 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2094 * untagged packets are received
2096 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2097 * packets and only the programmed vlan's packets are received
2099 filter->l2_ivlan = vlan_id;
2100 filter->l2_ivlan_mask = 0x0FFF;
2101 filter->enables |= en;
2102 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2104 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2106 /* Free the newly allocated filter as we were
2107 * not able to create the filter in hardware.
2109 bnxt_free_filter(bp, filter);
2113 filter->mac_index = 0;
2114 /* Add this new filter to the list */
2116 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2118 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2121 "Added Vlan filter for %d\n", vlan_id);
2125 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2126 uint16_t vlan_id, int on)
2128 struct bnxt *bp = eth_dev->data->dev_private;
2131 rc = is_bnxt_in_error(bp);
2135 if (!eth_dev->data->dev_started) {
2136 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2140 /* These operations apply to ALL existing MAC/VLAN filters */
2142 return bnxt_add_vlan_filter(bp, vlan_id);
2144 return bnxt_del_vlan_filter(bp, vlan_id);
2147 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2148 struct bnxt_vnic_info *vnic)
2150 struct bnxt_filter_info *filter;
2153 filter = STAILQ_FIRST(&vnic->filter);
2155 if (filter->mac_index == 0 &&
2156 !memcmp(filter->l2_addr, bp->mac_addr,
2157 RTE_ETHER_ADDR_LEN)) {
2158 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2160 STAILQ_REMOVE(&vnic->filter, filter,
2161 bnxt_filter_info, next);
2162 bnxt_free_filter(bp, filter);
2166 filter = STAILQ_NEXT(filter, next);
2172 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2174 struct bnxt_vnic_info *vnic;
2178 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2179 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2180 /* Remove any VLAN filters programmed */
2181 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2182 bnxt_del_vlan_filter(bp, i);
2184 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2188 /* Default filter will allow packets that match the
2189 * dest mac. So, it has to be deleted, otherwise, we
2190 * will endup receiving vlan packets for which the
2191 * filter is not programmed, when hw-vlan-filter
2192 * configuration is ON
2194 bnxt_del_dflt_mac_filter(bp, vnic);
2195 /* This filter will allow only untagged packets */
2196 bnxt_add_vlan_filter(bp, 0);
2198 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2199 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2204 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2206 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2210 /* Destroy vnic filters and vnic */
2211 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2212 DEV_RX_OFFLOAD_VLAN_FILTER) {
2213 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2214 bnxt_del_vlan_filter(bp, i);
2216 bnxt_del_dflt_mac_filter(bp, vnic);
2218 rc = bnxt_hwrm_vnic_free(bp, vnic);
2222 rte_free(vnic->fw_grp_ids);
2223 vnic->fw_grp_ids = NULL;
2225 vnic->rx_queue_cnt = 0;
2231 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2233 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2236 /* Destroy, recreate and reconfigure the default vnic */
2237 rc = bnxt_free_one_vnic(bp, 0);
2241 /* default vnic 0 */
2242 rc = bnxt_setup_one_vnic(bp, 0);
2246 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2247 DEV_RX_OFFLOAD_VLAN_FILTER) {
2248 rc = bnxt_add_vlan_filter(bp, 0);
2251 rc = bnxt_restore_vlan_filters(bp);
2255 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2260 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2264 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2265 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2271 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2273 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2274 struct bnxt *bp = dev->data->dev_private;
2277 rc = is_bnxt_in_error(bp);
2281 /* Filter settings will get applied when port is started */
2282 if (!dev->data->dev_started)
2285 if (mask & ETH_VLAN_FILTER_MASK) {
2286 /* Enable or disable VLAN filtering */
2287 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2292 if (mask & ETH_VLAN_STRIP_MASK) {
2293 /* Enable or disable VLAN stripping */
2294 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2299 if (mask & ETH_VLAN_EXTEND_MASK) {
2300 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2301 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2303 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2310 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2313 struct bnxt *bp = dev->data->dev_private;
2314 int qinq = dev->data->dev_conf.rxmode.offloads &
2315 DEV_RX_OFFLOAD_VLAN_EXTEND;
2317 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2318 vlan_type != ETH_VLAN_TYPE_OUTER) {
2320 "Unsupported vlan type.");
2325 "QinQ not enabled. Needs to be ON as we can "
2326 "accelerate only outer vlan\n");
2330 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2332 case RTE_ETHER_TYPE_QINQ:
2334 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2336 case RTE_ETHER_TYPE_VLAN:
2338 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2342 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2346 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2350 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2353 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2356 bp->outer_tpid_bd |= tpid;
2357 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2358 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2360 "Can accelerate only outer vlan in QinQ\n");
2368 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2369 struct rte_ether_addr *addr)
2371 struct bnxt *bp = dev->data->dev_private;
2372 /* Default Filter is tied to VNIC 0 */
2373 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2376 rc = is_bnxt_in_error(bp);
2380 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2383 if (rte_is_zero_ether_addr(addr))
2386 /* Filter settings will get applied when port is started */
2387 if (!dev->data->dev_started)
2390 /* Check if the requested MAC is already added */
2391 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2394 /* Destroy filter and re-create it */
2395 bnxt_del_dflt_mac_filter(bp, vnic);
2397 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2398 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2399 /* This filter will allow only untagged packets */
2400 rc = bnxt_add_vlan_filter(bp, 0);
2402 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2405 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2410 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2411 struct rte_ether_addr *mc_addr_set,
2412 uint32_t nb_mc_addr)
2414 struct bnxt *bp = eth_dev->data->dev_private;
2415 char *mc_addr_list = (char *)mc_addr_set;
2416 struct bnxt_vnic_info *vnic;
2417 uint32_t off = 0, i = 0;
2420 rc = is_bnxt_in_error(bp);
2424 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2426 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2427 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2431 /* TODO Check for Duplicate mcast addresses */
2432 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2433 for (i = 0; i < nb_mc_addr; i++) {
2434 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2435 RTE_ETHER_ADDR_LEN);
2436 off += RTE_ETHER_ADDR_LEN;
2439 vnic->mc_addr_cnt = i;
2440 if (vnic->mc_addr_cnt)
2441 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2443 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2446 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2450 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2452 struct bnxt *bp = dev->data->dev_private;
2453 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2454 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2455 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2456 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2459 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2460 fw_major, fw_minor, fw_updt, fw_rsvd);
2462 ret += 1; /* add the size of '\0' */
2463 if (fw_size < (uint32_t)ret)
2470 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2471 struct rte_eth_rxq_info *qinfo)
2473 struct bnxt *bp = dev->data->dev_private;
2474 struct bnxt_rx_queue *rxq;
2476 if (is_bnxt_in_error(bp))
2479 rxq = dev->data->rx_queues[queue_id];
2481 qinfo->mp = rxq->mb_pool;
2482 qinfo->scattered_rx = dev->data->scattered_rx;
2483 qinfo->nb_desc = rxq->nb_rx_desc;
2485 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2486 qinfo->conf.rx_drop_en = 0;
2487 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2491 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2492 struct rte_eth_txq_info *qinfo)
2494 struct bnxt *bp = dev->data->dev_private;
2495 struct bnxt_tx_queue *txq;
2497 if (is_bnxt_in_error(bp))
2500 txq = dev->data->tx_queues[queue_id];
2502 qinfo->nb_desc = txq->nb_tx_desc;
2504 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2505 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2506 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2508 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2509 qinfo->conf.tx_rs_thresh = 0;
2510 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2513 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2515 struct bnxt *bp = eth_dev->data->dev_private;
2516 uint32_t new_pkt_size;
2520 rc = is_bnxt_in_error(bp);
2524 /* Exit if receive queues are not configured yet */
2525 if (!eth_dev->data->nb_rx_queues)
2528 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2529 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2533 * If vector-mode tx/rx is active, disallow any MTU change that would
2534 * require scattered receive support.
2536 if (eth_dev->data->dev_started &&
2537 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2538 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2540 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2542 "MTU change would require scattered rx support. ");
2543 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2548 if (new_mtu > RTE_ETHER_MTU) {
2549 bp->flags |= BNXT_FLAG_JUMBO;
2550 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2551 DEV_RX_OFFLOAD_JUMBO_FRAME;
2553 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2554 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2555 bp->flags &= ~BNXT_FLAG_JUMBO;
2558 /* Is there a change in mtu setting? */
2559 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2562 for (i = 0; i < bp->nr_vnics; i++) {
2563 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2566 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2567 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2571 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2572 size -= RTE_PKTMBUF_HEADROOM;
2574 if (size < new_mtu) {
2575 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2582 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2584 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2590 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2592 struct bnxt *bp = dev->data->dev_private;
2593 uint16_t vlan = bp->vlan;
2596 rc = is_bnxt_in_error(bp);
2600 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2602 "PVID cannot be modified for this function\n");
2605 bp->vlan = on ? pvid : 0;
2607 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2614 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2616 struct bnxt *bp = dev->data->dev_private;
2619 rc = is_bnxt_in_error(bp);
2623 return bnxt_hwrm_port_led_cfg(bp, true);
2627 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2629 struct bnxt *bp = dev->data->dev_private;
2632 rc = is_bnxt_in_error(bp);
2636 return bnxt_hwrm_port_led_cfg(bp, false);
2640 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2642 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2643 uint32_t desc = 0, raw_cons = 0, cons;
2644 struct bnxt_cp_ring_info *cpr;
2645 struct bnxt_rx_queue *rxq;
2646 struct rx_pkt_cmpl *rxcmp;
2649 rc = is_bnxt_in_error(bp);
2653 rxq = dev->data->rx_queues[rx_queue_id];
2655 raw_cons = cpr->cp_raw_cons;
2658 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2659 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2660 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2662 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2674 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2676 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2677 struct bnxt_rx_ring_info *rxr;
2678 struct bnxt_cp_ring_info *cpr;
2679 struct bnxt_sw_rx_bd *rx_buf;
2680 struct rx_pkt_cmpl *rxcmp;
2681 uint32_t cons, cp_cons;
2687 rc = is_bnxt_in_error(rxq->bp);
2694 if (offset >= rxq->nb_rx_desc)
2697 cons = RING_CMP(cpr->cp_ring_struct, offset);
2698 cp_cons = cpr->cp_raw_cons;
2699 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2701 if (cons > cp_cons) {
2702 if (CMPL_VALID(rxcmp, cpr->valid))
2703 return RTE_ETH_RX_DESC_DONE;
2705 if (CMPL_VALID(rxcmp, !cpr->valid))
2706 return RTE_ETH_RX_DESC_DONE;
2708 rx_buf = &rxr->rx_buf_ring[cons];
2709 if (rx_buf->mbuf == NULL)
2710 return RTE_ETH_RX_DESC_UNAVAIL;
2713 return RTE_ETH_RX_DESC_AVAIL;
2717 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2719 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2720 struct bnxt_tx_ring_info *txr;
2721 struct bnxt_cp_ring_info *cpr;
2722 struct bnxt_sw_tx_bd *tx_buf;
2723 struct tx_pkt_cmpl *txcmp;
2724 uint32_t cons, cp_cons;
2730 rc = is_bnxt_in_error(txq->bp);
2737 if (offset >= txq->nb_tx_desc)
2740 cons = RING_CMP(cpr->cp_ring_struct, offset);
2741 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2742 cp_cons = cpr->cp_raw_cons;
2744 if (cons > cp_cons) {
2745 if (CMPL_VALID(txcmp, cpr->valid))
2746 return RTE_ETH_TX_DESC_UNAVAIL;
2748 if (CMPL_VALID(txcmp, !cpr->valid))
2749 return RTE_ETH_TX_DESC_UNAVAIL;
2751 tx_buf = &txr->tx_buf_ring[cons];
2752 if (tx_buf->mbuf == NULL)
2753 return RTE_ETH_TX_DESC_DONE;
2755 return RTE_ETH_TX_DESC_FULL;
2758 static struct bnxt_filter_info *
2759 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2760 struct rte_eth_ethertype_filter *efilter,
2761 struct bnxt_vnic_info *vnic0,
2762 struct bnxt_vnic_info *vnic,
2765 struct bnxt_filter_info *mfilter = NULL;
2769 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2770 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2771 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2772 " ethertype filter.", efilter->ether_type);
2776 if (efilter->queue >= bp->rx_nr_rings) {
2777 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2782 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2783 vnic = &bp->vnic_info[efilter->queue];
2785 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2790 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2791 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2792 if ((!memcmp(efilter->mac_addr.addr_bytes,
2793 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2795 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2796 mfilter->ethertype == efilter->ether_type)) {
2802 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2803 if ((!memcmp(efilter->mac_addr.addr_bytes,
2804 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2805 mfilter->ethertype == efilter->ether_type &&
2807 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2821 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2822 enum rte_filter_op filter_op,
2825 struct bnxt *bp = dev->data->dev_private;
2826 struct rte_eth_ethertype_filter *efilter =
2827 (struct rte_eth_ethertype_filter *)arg;
2828 struct bnxt_filter_info *bfilter, *filter1;
2829 struct bnxt_vnic_info *vnic, *vnic0;
2832 if (filter_op == RTE_ETH_FILTER_NOP)
2836 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2841 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2842 vnic = &bp->vnic_info[efilter->queue];
2844 switch (filter_op) {
2845 case RTE_ETH_FILTER_ADD:
2846 bnxt_match_and_validate_ether_filter(bp, efilter,
2851 bfilter = bnxt_get_unused_filter(bp);
2852 if (bfilter == NULL) {
2854 "Not enough resources for a new filter.\n");
2857 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2858 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2859 RTE_ETHER_ADDR_LEN);
2860 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2861 RTE_ETHER_ADDR_LEN);
2862 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2863 bfilter->ethertype = efilter->ether_type;
2864 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2866 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2867 if (filter1 == NULL) {
2872 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2873 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2875 bfilter->dst_id = vnic->fw_vnic_id;
2877 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2879 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2882 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2885 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2887 case RTE_ETH_FILTER_DELETE:
2888 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2890 if (ret == -EEXIST) {
2891 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2893 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2895 bnxt_free_filter(bp, filter1);
2896 } else if (ret == 0) {
2897 PMD_DRV_LOG(ERR, "No matching filter found\n");
2901 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2907 bnxt_free_filter(bp, bfilter);
2913 parse_ntuple_filter(struct bnxt *bp,
2914 struct rte_eth_ntuple_filter *nfilter,
2915 struct bnxt_filter_info *bfilter)
2919 if (nfilter->queue >= bp->rx_nr_rings) {
2920 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2924 switch (nfilter->dst_port_mask) {
2926 bfilter->dst_port_mask = -1;
2927 bfilter->dst_port = nfilter->dst_port;
2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2929 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2932 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2936 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2937 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2939 switch (nfilter->proto_mask) {
2941 if (nfilter->proto == 17) /* IPPROTO_UDP */
2942 bfilter->ip_protocol = 17;
2943 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2944 bfilter->ip_protocol = 6;
2947 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2950 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2954 switch (nfilter->dst_ip_mask) {
2956 bfilter->dst_ipaddr_mask[0] = -1;
2957 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2959 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2962 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2966 switch (nfilter->src_ip_mask) {
2968 bfilter->src_ipaddr_mask[0] = -1;
2969 bfilter->src_ipaddr[0] = nfilter->src_ip;
2970 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2971 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2974 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2978 switch (nfilter->src_port_mask) {
2980 bfilter->src_port_mask = -1;
2981 bfilter->src_port = nfilter->src_port;
2982 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2983 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2986 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2990 bfilter->enables = en;
2994 static struct bnxt_filter_info*
2995 bnxt_match_ntuple_filter(struct bnxt *bp,
2996 struct bnxt_filter_info *bfilter,
2997 struct bnxt_vnic_info **mvnic)
2999 struct bnxt_filter_info *mfilter = NULL;
3002 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3003 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3004 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3005 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3006 bfilter->src_ipaddr_mask[0] ==
3007 mfilter->src_ipaddr_mask[0] &&
3008 bfilter->src_port == mfilter->src_port &&
3009 bfilter->src_port_mask == mfilter->src_port_mask &&
3010 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3011 bfilter->dst_ipaddr_mask[0] ==
3012 mfilter->dst_ipaddr_mask[0] &&
3013 bfilter->dst_port == mfilter->dst_port &&
3014 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3015 bfilter->flags == mfilter->flags &&
3016 bfilter->enables == mfilter->enables) {
3027 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3028 struct rte_eth_ntuple_filter *nfilter,
3029 enum rte_filter_op filter_op)
3031 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3032 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3035 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3036 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3040 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3041 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3045 bfilter = bnxt_get_unused_filter(bp);
3046 if (bfilter == NULL) {
3048 "Not enough resources for a new filter.\n");
3051 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3055 vnic = &bp->vnic_info[nfilter->queue];
3056 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3057 filter1 = STAILQ_FIRST(&vnic0->filter);
3058 if (filter1 == NULL) {
3063 bfilter->dst_id = vnic->fw_vnic_id;
3064 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3066 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3067 bfilter->ethertype = 0x800;
3068 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3070 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3072 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3073 bfilter->dst_id == mfilter->dst_id) {
3074 PMD_DRV_LOG(ERR, "filter exists.\n");
3077 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3078 bfilter->dst_id != mfilter->dst_id) {
3079 mfilter->dst_id = vnic->fw_vnic_id;
3080 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3081 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3082 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3083 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3084 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3087 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3088 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3093 if (filter_op == RTE_ETH_FILTER_ADD) {
3094 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3095 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3098 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3100 if (mfilter == NULL) {
3101 /* This should not happen. But for Coverity! */
3105 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3107 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3108 bnxt_free_filter(bp, mfilter);
3109 bnxt_free_filter(bp, bfilter);
3114 bnxt_free_filter(bp, bfilter);
3119 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3120 enum rte_filter_op filter_op,
3123 struct bnxt *bp = dev->data->dev_private;
3126 if (filter_op == RTE_ETH_FILTER_NOP)
3130 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3135 switch (filter_op) {
3136 case RTE_ETH_FILTER_ADD:
3137 ret = bnxt_cfg_ntuple_filter(bp,
3138 (struct rte_eth_ntuple_filter *)arg,
3141 case RTE_ETH_FILTER_DELETE:
3142 ret = bnxt_cfg_ntuple_filter(bp,
3143 (struct rte_eth_ntuple_filter *)arg,
3147 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3155 bnxt_parse_fdir_filter(struct bnxt *bp,
3156 struct rte_eth_fdir_filter *fdir,
3157 struct bnxt_filter_info *filter)
3159 enum rte_fdir_mode fdir_mode =
3160 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3161 struct bnxt_vnic_info *vnic0, *vnic;
3162 struct bnxt_filter_info *filter1;
3166 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3169 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3170 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3172 switch (fdir->input.flow_type) {
3173 case RTE_ETH_FLOW_IPV4:
3174 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3176 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3177 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3178 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3179 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3180 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3181 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3182 filter->ip_addr_type =
3183 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3184 filter->src_ipaddr_mask[0] = 0xffffffff;
3185 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3186 filter->dst_ipaddr_mask[0] = 0xffffffff;
3187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3188 filter->ethertype = 0x800;
3189 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3191 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3192 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3193 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3194 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3195 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3196 filter->dst_port_mask = 0xffff;
3197 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3198 filter->src_port_mask = 0xffff;
3199 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3200 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3202 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3203 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3204 filter->ip_protocol = 6;
3205 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3206 filter->ip_addr_type =
3207 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3208 filter->src_ipaddr_mask[0] = 0xffffffff;
3209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3210 filter->dst_ipaddr_mask[0] = 0xffffffff;
3211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3212 filter->ethertype = 0x800;
3213 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3215 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3216 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3217 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3218 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3219 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3220 filter->dst_port_mask = 0xffff;
3221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3222 filter->src_port_mask = 0xffff;
3223 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3224 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3225 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3226 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3227 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3228 filter->ip_protocol = 17;
3229 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3230 filter->ip_addr_type =
3231 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3232 filter->src_ipaddr_mask[0] = 0xffffffff;
3233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3234 filter->dst_ipaddr_mask[0] = 0xffffffff;
3235 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3236 filter->ethertype = 0x800;
3237 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3239 case RTE_ETH_FLOW_IPV6:
3240 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3242 filter->ip_addr_type =
3243 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3244 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3245 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3246 rte_memcpy(filter->src_ipaddr,
3247 fdir->input.flow.ipv6_flow.src_ip, 16);
3248 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3249 rte_memcpy(filter->dst_ipaddr,
3250 fdir->input.flow.ipv6_flow.dst_ip, 16);
3251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3252 memset(filter->dst_ipaddr_mask, 0xff, 16);
3253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3254 memset(filter->src_ipaddr_mask, 0xff, 16);
3255 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3256 filter->ethertype = 0x86dd;
3257 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3259 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3260 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3261 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3262 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3263 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3264 filter->dst_port_mask = 0xffff;
3265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3266 filter->src_port_mask = 0xffff;
3267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3268 filter->ip_addr_type =
3269 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3270 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3271 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3272 rte_memcpy(filter->src_ipaddr,
3273 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3274 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3275 rte_memcpy(filter->dst_ipaddr,
3276 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3278 memset(filter->dst_ipaddr_mask, 0xff, 16);
3279 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3280 memset(filter->src_ipaddr_mask, 0xff, 16);
3281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3282 filter->ethertype = 0x86dd;
3283 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3285 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3286 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3287 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3288 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3289 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3290 filter->dst_port_mask = 0xffff;
3291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3292 filter->src_port_mask = 0xffff;
3293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3294 filter->ip_addr_type =
3295 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3296 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3297 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3298 rte_memcpy(filter->src_ipaddr,
3299 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3300 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3301 rte_memcpy(filter->dst_ipaddr,
3302 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3304 memset(filter->dst_ipaddr_mask, 0xff, 16);
3305 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3306 memset(filter->src_ipaddr_mask, 0xff, 16);
3307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3308 filter->ethertype = 0x86dd;
3309 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3311 case RTE_ETH_FLOW_L2_PAYLOAD:
3312 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3313 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3315 case RTE_ETH_FLOW_VXLAN:
3316 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3318 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3319 filter->tunnel_type =
3320 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3321 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3323 case RTE_ETH_FLOW_NVGRE:
3324 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3326 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3327 filter->tunnel_type =
3328 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3329 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3331 case RTE_ETH_FLOW_UNKNOWN:
3332 case RTE_ETH_FLOW_RAW:
3333 case RTE_ETH_FLOW_FRAG_IPV4:
3334 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3335 case RTE_ETH_FLOW_FRAG_IPV6:
3336 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3337 case RTE_ETH_FLOW_IPV6_EX:
3338 case RTE_ETH_FLOW_IPV6_TCP_EX:
3339 case RTE_ETH_FLOW_IPV6_UDP_EX:
3340 case RTE_ETH_FLOW_GENEVE:
3346 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3347 vnic = &bp->vnic_info[fdir->action.rx_queue];
3349 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3353 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3354 rte_memcpy(filter->dst_macaddr,
3355 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3356 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3359 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3360 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3361 filter1 = STAILQ_FIRST(&vnic0->filter);
3362 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3364 filter->dst_id = vnic->fw_vnic_id;
3365 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3366 if (filter->dst_macaddr[i] == 0x00)
3367 filter1 = STAILQ_FIRST(&vnic0->filter);
3369 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3372 if (filter1 == NULL)
3375 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3376 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3378 filter->enables = en;
3383 static struct bnxt_filter_info *
3384 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3385 struct bnxt_vnic_info **mvnic)
3387 struct bnxt_filter_info *mf = NULL;
3390 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3391 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3393 STAILQ_FOREACH(mf, &vnic->filter, next) {
3394 if (mf->filter_type == nf->filter_type &&
3395 mf->flags == nf->flags &&
3396 mf->src_port == nf->src_port &&
3397 mf->src_port_mask == nf->src_port_mask &&
3398 mf->dst_port == nf->dst_port &&
3399 mf->dst_port_mask == nf->dst_port_mask &&
3400 mf->ip_protocol == nf->ip_protocol &&
3401 mf->ip_addr_type == nf->ip_addr_type &&
3402 mf->ethertype == nf->ethertype &&
3403 mf->vni == nf->vni &&
3404 mf->tunnel_type == nf->tunnel_type &&
3405 mf->l2_ovlan == nf->l2_ovlan &&
3406 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3407 mf->l2_ivlan == nf->l2_ivlan &&
3408 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3409 !memcmp(mf->l2_addr, nf->l2_addr,
3410 RTE_ETHER_ADDR_LEN) &&
3411 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3412 RTE_ETHER_ADDR_LEN) &&
3413 !memcmp(mf->src_macaddr, nf->src_macaddr,
3414 RTE_ETHER_ADDR_LEN) &&
3415 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3416 RTE_ETHER_ADDR_LEN) &&
3417 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3418 sizeof(nf->src_ipaddr)) &&
3419 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3420 sizeof(nf->src_ipaddr_mask)) &&
3421 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3422 sizeof(nf->dst_ipaddr)) &&
3423 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3424 sizeof(nf->dst_ipaddr_mask))) {
3435 bnxt_fdir_filter(struct rte_eth_dev *dev,
3436 enum rte_filter_op filter_op,
3439 struct bnxt *bp = dev->data->dev_private;
3440 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3441 struct bnxt_filter_info *filter, *match;
3442 struct bnxt_vnic_info *vnic, *mvnic;
3445 if (filter_op == RTE_ETH_FILTER_NOP)
3448 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3451 switch (filter_op) {
3452 case RTE_ETH_FILTER_ADD:
3453 case RTE_ETH_FILTER_DELETE:
3455 filter = bnxt_get_unused_filter(bp);
3456 if (filter == NULL) {
3458 "Not enough resources for a new flow.\n");
3462 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3465 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3467 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3468 vnic = &bp->vnic_info[0];
3470 vnic = &bp->vnic_info[fdir->action.rx_queue];
3472 match = bnxt_match_fdir(bp, filter, &mvnic);
3473 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3474 if (match->dst_id == vnic->fw_vnic_id) {
3475 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3479 match->dst_id = vnic->fw_vnic_id;
3480 ret = bnxt_hwrm_set_ntuple_filter(bp,
3483 STAILQ_REMOVE(&mvnic->filter, match,
3484 bnxt_filter_info, next);
3485 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3487 "Filter with matching pattern exist\n");
3489 "Updated it to new destination q\n");
3493 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3494 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3499 if (filter_op == RTE_ETH_FILTER_ADD) {
3500 ret = bnxt_hwrm_set_ntuple_filter(bp,
3505 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3507 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3508 STAILQ_REMOVE(&vnic->filter, match,
3509 bnxt_filter_info, next);
3510 bnxt_free_filter(bp, match);
3511 bnxt_free_filter(bp, filter);
3514 case RTE_ETH_FILTER_FLUSH:
3515 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3516 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3518 STAILQ_FOREACH(filter, &vnic->filter, next) {
3519 if (filter->filter_type ==
3520 HWRM_CFA_NTUPLE_FILTER) {
3522 bnxt_hwrm_clear_ntuple_filter(bp,
3524 STAILQ_REMOVE(&vnic->filter, filter,
3525 bnxt_filter_info, next);
3530 case RTE_ETH_FILTER_UPDATE:
3531 case RTE_ETH_FILTER_STATS:
3532 case RTE_ETH_FILTER_INFO:
3533 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3536 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3543 bnxt_free_filter(bp, filter);
3548 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3549 enum rte_filter_type filter_type,
3550 enum rte_filter_op filter_op, void *arg)
3552 struct bnxt *bp = dev->data->dev_private;
3555 ret = is_bnxt_in_error(dev->data->dev_private);
3559 switch (filter_type) {
3560 case RTE_ETH_FILTER_TUNNEL:
3562 "filter type: %d: To be implemented\n", filter_type);
3564 case RTE_ETH_FILTER_FDIR:
3565 ret = bnxt_fdir_filter(dev, filter_op, arg);
3567 case RTE_ETH_FILTER_NTUPLE:
3568 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3570 case RTE_ETH_FILTER_ETHERTYPE:
3571 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3573 case RTE_ETH_FILTER_GENERIC:
3574 if (filter_op != RTE_ETH_FILTER_GET)
3577 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3579 *(const void **)arg = &bnxt_flow_ops;
3583 "Filter type (%d) not supported", filter_type);
3590 static const uint32_t *
3591 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3593 static const uint32_t ptypes[] = {
3594 RTE_PTYPE_L2_ETHER_VLAN,
3595 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3596 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3600 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3601 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3602 RTE_PTYPE_INNER_L4_ICMP,
3603 RTE_PTYPE_INNER_L4_TCP,
3604 RTE_PTYPE_INNER_L4_UDP,
3608 if (!dev->rx_pkt_burst)
3614 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3617 uint32_t reg_base = *reg_arr & 0xfffff000;
3621 for (i = 0; i < count; i++) {
3622 if ((reg_arr[i] & 0xfffff000) != reg_base)
3625 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3626 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3630 static int bnxt_map_ptp_regs(struct bnxt *bp)
3632 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3636 reg_arr = ptp->rx_regs;
3637 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3641 reg_arr = ptp->tx_regs;
3642 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3646 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3647 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3649 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3650 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3655 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3657 rte_write32(0, (uint8_t *)bp->bar0 +
3658 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3659 rte_write32(0, (uint8_t *)bp->bar0 +
3660 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3663 static uint64_t bnxt_cc_read(struct bnxt *bp)
3667 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3668 BNXT_GRCPF_REG_SYNC_TIME));
3669 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3670 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3674 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3676 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3679 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3680 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3681 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3684 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3685 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3686 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3687 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3688 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3689 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3694 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3696 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3697 struct bnxt_pf_info *pf = &bp->pf;
3704 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3705 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3706 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3709 port_id = pf->port_id;
3710 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3711 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3713 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3714 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3715 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3716 /* bnxt_clr_rx_ts(bp); TBD */
3720 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3721 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3722 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3723 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3729 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3732 struct bnxt *bp = dev->data->dev_private;
3733 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3738 ns = rte_timespec_to_ns(ts);
3739 /* Set the timecounters to a new value. */
3746 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3748 struct bnxt *bp = dev->data->dev_private;
3749 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3750 uint64_t ns, systime_cycles = 0;
3756 if (BNXT_CHIP_THOR(bp))
3757 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3760 systime_cycles = bnxt_cc_read(bp);
3762 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3763 *ts = rte_ns_to_timespec(ns);
3768 bnxt_timesync_enable(struct rte_eth_dev *dev)
3770 struct bnxt *bp = dev->data->dev_private;
3771 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3779 ptp->tx_tstamp_en = 1;
3780 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3782 rc = bnxt_hwrm_ptp_cfg(bp);
3786 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3787 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3788 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3790 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3791 ptp->tc.cc_shift = shift;
3792 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3794 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3795 ptp->rx_tstamp_tc.cc_shift = shift;
3796 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3798 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3799 ptp->tx_tstamp_tc.cc_shift = shift;
3800 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3802 if (!BNXT_CHIP_THOR(bp))
3803 bnxt_map_ptp_regs(bp);
3809 bnxt_timesync_disable(struct rte_eth_dev *dev)
3811 struct bnxt *bp = dev->data->dev_private;
3812 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3818 ptp->tx_tstamp_en = 0;
3821 bnxt_hwrm_ptp_cfg(bp);
3823 if (!BNXT_CHIP_THOR(bp))
3824 bnxt_unmap_ptp_regs(bp);
3830 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3831 struct timespec *timestamp,
3832 uint32_t flags __rte_unused)
3834 struct bnxt *bp = dev->data->dev_private;
3835 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3836 uint64_t rx_tstamp_cycles = 0;
3842 if (BNXT_CHIP_THOR(bp))
3843 rx_tstamp_cycles = ptp->rx_timestamp;
3845 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3847 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3848 *timestamp = rte_ns_to_timespec(ns);
3853 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3854 struct timespec *timestamp)
3856 struct bnxt *bp = dev->data->dev_private;
3857 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3858 uint64_t tx_tstamp_cycles = 0;
3865 if (BNXT_CHIP_THOR(bp))
3866 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3869 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3871 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3872 *timestamp = rte_ns_to_timespec(ns);
3878 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3880 struct bnxt *bp = dev->data->dev_private;
3881 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3886 ptp->tc.nsec += delta;
3892 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3894 struct bnxt *bp = dev->data->dev_private;
3896 uint32_t dir_entries;
3897 uint32_t entry_length;
3899 rc = is_bnxt_in_error(bp);
3903 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3904 bp->pdev->addr.domain, bp->pdev->addr.bus,
3905 bp->pdev->addr.devid, bp->pdev->addr.function);
3907 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3911 return dir_entries * entry_length;
3915 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3916 struct rte_dev_eeprom_info *in_eeprom)
3918 struct bnxt *bp = dev->data->dev_private;
3923 rc = is_bnxt_in_error(bp);
3927 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3928 bp->pdev->addr.domain, bp->pdev->addr.bus,
3929 bp->pdev->addr.devid, bp->pdev->addr.function,
3930 in_eeprom->offset, in_eeprom->length);
3932 if (in_eeprom->offset == 0) /* special offset value to get directory */
3933 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3936 index = in_eeprom->offset >> 24;
3937 offset = in_eeprom->offset & 0xffffff;
3940 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3941 in_eeprom->length, in_eeprom->data);
3946 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3949 case BNX_DIR_TYPE_CHIMP_PATCH:
3950 case BNX_DIR_TYPE_BOOTCODE:
3951 case BNX_DIR_TYPE_BOOTCODE_2:
3952 case BNX_DIR_TYPE_APE_FW:
3953 case BNX_DIR_TYPE_APE_PATCH:
3954 case BNX_DIR_TYPE_KONG_FW:
3955 case BNX_DIR_TYPE_KONG_PATCH:
3956 case BNX_DIR_TYPE_BONO_FW:
3957 case BNX_DIR_TYPE_BONO_PATCH:
3965 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3968 case BNX_DIR_TYPE_AVS:
3969 case BNX_DIR_TYPE_EXP_ROM_MBA:
3970 case BNX_DIR_TYPE_PCIE:
3971 case BNX_DIR_TYPE_TSCF_UCODE:
3972 case BNX_DIR_TYPE_EXT_PHY:
3973 case BNX_DIR_TYPE_CCM:
3974 case BNX_DIR_TYPE_ISCSI_BOOT:
3975 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3976 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3984 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3986 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3987 bnxt_dir_type_is_other_exec_format(dir_type);
3991 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3992 struct rte_dev_eeprom_info *in_eeprom)
3994 struct bnxt *bp = dev->data->dev_private;
3995 uint8_t index, dir_op;
3996 uint16_t type, ext, ordinal, attr;
3999 rc = is_bnxt_in_error(bp);
4003 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4004 bp->pdev->addr.domain, bp->pdev->addr.bus,
4005 bp->pdev->addr.devid, bp->pdev->addr.function,
4006 in_eeprom->offset, in_eeprom->length);
4009 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4013 type = in_eeprom->magic >> 16;
4015 if (type == 0xffff) { /* special value for directory operations */
4016 index = in_eeprom->magic & 0xff;
4017 dir_op = in_eeprom->magic >> 8;
4021 case 0x0e: /* erase */
4022 if (in_eeprom->offset != ~in_eeprom->magic)
4024 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4030 /* Create or re-write an NVM item: */
4031 if (bnxt_dir_type_is_executable(type) == true)
4033 ext = in_eeprom->magic & 0xffff;
4034 ordinal = in_eeprom->offset >> 16;
4035 attr = in_eeprom->offset & 0xffff;
4037 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4038 in_eeprom->data, in_eeprom->length);
4045 static const struct eth_dev_ops bnxt_dev_ops = {
4046 .dev_infos_get = bnxt_dev_info_get_op,
4047 .dev_close = bnxt_dev_close_op,
4048 .dev_configure = bnxt_dev_configure_op,
4049 .dev_start = bnxt_dev_start_op,
4050 .dev_stop = bnxt_dev_stop_op,
4051 .dev_set_link_up = bnxt_dev_set_link_up_op,
4052 .dev_set_link_down = bnxt_dev_set_link_down_op,
4053 .stats_get = bnxt_stats_get_op,
4054 .stats_reset = bnxt_stats_reset_op,
4055 .rx_queue_setup = bnxt_rx_queue_setup_op,
4056 .rx_queue_release = bnxt_rx_queue_release_op,
4057 .tx_queue_setup = bnxt_tx_queue_setup_op,
4058 .tx_queue_release = bnxt_tx_queue_release_op,
4059 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4060 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4061 .reta_update = bnxt_reta_update_op,
4062 .reta_query = bnxt_reta_query_op,
4063 .rss_hash_update = bnxt_rss_hash_update_op,
4064 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4065 .link_update = bnxt_link_update_op,
4066 .promiscuous_enable = bnxt_promiscuous_enable_op,
4067 .promiscuous_disable = bnxt_promiscuous_disable_op,
4068 .allmulticast_enable = bnxt_allmulticast_enable_op,
4069 .allmulticast_disable = bnxt_allmulticast_disable_op,
4070 .mac_addr_add = bnxt_mac_addr_add_op,
4071 .mac_addr_remove = bnxt_mac_addr_remove_op,
4072 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4073 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4074 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4075 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4076 .vlan_filter_set = bnxt_vlan_filter_set_op,
4077 .vlan_offload_set = bnxt_vlan_offload_set_op,
4078 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4079 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4080 .mtu_set = bnxt_mtu_set_op,
4081 .mac_addr_set = bnxt_set_default_mac_addr_op,
4082 .xstats_get = bnxt_dev_xstats_get_op,
4083 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4084 .xstats_reset = bnxt_dev_xstats_reset_op,
4085 .fw_version_get = bnxt_fw_version_get,
4086 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4087 .rxq_info_get = bnxt_rxq_info_get_op,
4088 .txq_info_get = bnxt_txq_info_get_op,
4089 .dev_led_on = bnxt_dev_led_on_op,
4090 .dev_led_off = bnxt_dev_led_off_op,
4091 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4092 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4093 .rx_queue_count = bnxt_rx_queue_count_op,
4094 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4095 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4096 .rx_queue_start = bnxt_rx_queue_start,
4097 .rx_queue_stop = bnxt_rx_queue_stop,
4098 .tx_queue_start = bnxt_tx_queue_start,
4099 .tx_queue_stop = bnxt_tx_queue_stop,
4100 .filter_ctrl = bnxt_filter_ctrl_op,
4101 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4102 .get_eeprom_length = bnxt_get_eeprom_length_op,
4103 .get_eeprom = bnxt_get_eeprom_op,
4104 .set_eeprom = bnxt_set_eeprom_op,
4105 .timesync_enable = bnxt_timesync_enable,
4106 .timesync_disable = bnxt_timesync_disable,
4107 .timesync_read_time = bnxt_timesync_read_time,
4108 .timesync_write_time = bnxt_timesync_write_time,
4109 .timesync_adjust_time = bnxt_timesync_adjust_time,
4110 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4111 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4114 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4118 /* Only pre-map the reset GRC registers using window 3 */
4119 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4120 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4122 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4127 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4129 struct bnxt_error_recovery_info *info = bp->recovery_info;
4130 uint32_t reg_base = 0xffffffff;
4133 /* Only pre-map the monitoring GRC registers using window 2 */
4134 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4135 uint32_t reg = info->status_regs[i];
4137 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4140 if (reg_base == 0xffffffff)
4141 reg_base = reg & 0xfffff000;
4142 if ((reg & 0xfffff000) != reg_base)
4145 /* Use mask 0xffc as the Lower 2 bits indicates
4146 * address space location
4148 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4152 if (reg_base == 0xffffffff)
4155 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4156 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4161 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4163 struct bnxt_error_recovery_info *info = bp->recovery_info;
4164 uint32_t delay = info->delay_after_reset[index];
4165 uint32_t val = info->reset_reg_val[index];
4166 uint32_t reg = info->reset_reg[index];
4167 uint32_t type, offset;
4169 type = BNXT_FW_STATUS_REG_TYPE(reg);
4170 offset = BNXT_FW_STATUS_REG_OFF(reg);
4173 case BNXT_FW_STATUS_REG_TYPE_CFG:
4174 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4176 case BNXT_FW_STATUS_REG_TYPE_GRC:
4177 offset = bnxt_map_reset_regs(bp, offset);
4178 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4180 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4181 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4184 /* wait on a specific interval of time until core reset is complete */
4186 rte_delay_ms(delay);
4189 static void bnxt_dev_cleanup(struct bnxt *bp)
4191 bnxt_set_hwrm_link_config(bp, false);
4192 bp->link_info.link_up = 0;
4193 if (bp->eth_dev->data->dev_started)
4194 bnxt_dev_stop_op(bp->eth_dev);
4196 bnxt_uninit_resources(bp, true);
4199 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4201 struct rte_eth_dev *dev = bp->eth_dev;
4202 struct rte_vlan_filter_conf *vfc;
4206 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4207 vfc = &dev->data->vlan_filter_conf;
4208 vidx = vlan_id / 64;
4209 vbit = vlan_id % 64;
4211 /* Each bit corresponds to a VLAN id */
4212 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4213 rc = bnxt_add_vlan_filter(bp, vlan_id);
4222 static int bnxt_restore_mac_filters(struct bnxt *bp)
4224 struct rte_eth_dev *dev = bp->eth_dev;
4225 struct rte_eth_dev_info dev_info;
4226 struct rte_ether_addr *addr;
4232 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4235 rc = bnxt_dev_info_get_op(dev, &dev_info);
4239 /* replay MAC address configuration */
4240 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4241 addr = &dev->data->mac_addrs[i];
4243 /* skip zero address */
4244 if (rte_is_zero_ether_addr(addr))
4248 pool_mask = dev->data->mac_pool_sel[i];
4251 if (pool_mask & 1ULL) {
4252 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4258 } while (pool_mask);
4264 static int bnxt_restore_filters(struct bnxt *bp)
4266 struct rte_eth_dev *dev = bp->eth_dev;
4269 if (dev->data->all_multicast) {
4270 ret = bnxt_allmulticast_enable_op(dev);
4274 if (dev->data->promiscuous) {
4275 ret = bnxt_promiscuous_enable_op(dev);
4280 ret = bnxt_restore_mac_filters(bp);
4284 ret = bnxt_restore_vlan_filters(bp);
4285 /* TODO restore other filters as well */
4289 static void bnxt_dev_recover(void *arg)
4291 struct bnxt *bp = arg;
4292 int timeout = bp->fw_reset_max_msecs;
4295 /* Clear Error flag so that device re-init should happen */
4296 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4299 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4302 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4303 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4304 } while (rc && timeout);
4307 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4311 rc = bnxt_init_resources(bp, true);
4314 "Failed to initialize resources after reset\n");
4317 /* clear reset flag as the device is initialized now */
4318 bp->flags &= ~BNXT_FLAG_FW_RESET;
4320 rc = bnxt_dev_start_op(bp->eth_dev);
4322 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4326 rc = bnxt_restore_filters(bp);
4330 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4333 bnxt_dev_stop_op(bp->eth_dev);
4335 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4336 bnxt_uninit_resources(bp, false);
4337 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4340 void bnxt_dev_reset_and_resume(void *arg)
4342 struct bnxt *bp = arg;
4345 bnxt_dev_cleanup(bp);
4347 bnxt_wait_for_device_shutdown(bp);
4349 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4350 bnxt_dev_recover, (void *)bp);
4352 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4355 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4357 struct bnxt_error_recovery_info *info = bp->recovery_info;
4358 uint32_t reg = info->status_regs[index];
4359 uint32_t type, offset, val = 0;
4361 type = BNXT_FW_STATUS_REG_TYPE(reg);
4362 offset = BNXT_FW_STATUS_REG_OFF(reg);
4365 case BNXT_FW_STATUS_REG_TYPE_CFG:
4366 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4368 case BNXT_FW_STATUS_REG_TYPE_GRC:
4369 offset = info->mapped_status_regs[index];
4371 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4372 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4380 static int bnxt_fw_reset_all(struct bnxt *bp)
4382 struct bnxt_error_recovery_info *info = bp->recovery_info;
4386 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4387 /* Reset through master function driver */
4388 for (i = 0; i < info->reg_array_cnt; i++)
4389 bnxt_write_fw_reset_reg(bp, i);
4390 /* Wait for time specified by FW after triggering reset */
4391 rte_delay_ms(info->master_func_wait_period_after_reset);
4392 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4393 /* Reset with the help of Kong processor */
4394 rc = bnxt_hwrm_fw_reset(bp);
4396 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4402 static void bnxt_fw_reset_cb(void *arg)
4404 struct bnxt *bp = arg;
4405 struct bnxt_error_recovery_info *info = bp->recovery_info;
4408 /* Only Master function can do FW reset */
4409 if (bnxt_is_master_func(bp) &&
4410 bnxt_is_recovery_enabled(bp)) {
4411 rc = bnxt_fw_reset_all(bp);
4413 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4418 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4419 * EXCEPTION_FATAL_ASYNC event to all the functions
4420 * (including MASTER FUNC). After receiving this Async, all the active
4421 * drivers should treat this case as FW initiated recovery
4423 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4424 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4425 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4427 /* To recover from error */
4428 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4433 /* Driver should poll FW heartbeat, reset_counter with the frequency
4434 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4435 * When the driver detects heartbeat stop or change in reset_counter,
4436 * it has to trigger a reset to recover from the error condition.
4437 * A “master PF” is the function who will have the privilege to
4438 * initiate the chimp reset. The master PF will be elected by the
4439 * firmware and will be notified through async message.
4441 static void bnxt_check_fw_health(void *arg)
4443 struct bnxt *bp = arg;
4444 struct bnxt_error_recovery_info *info = bp->recovery_info;
4445 uint32_t val = 0, wait_msec;
4447 if (!info || !bnxt_is_recovery_enabled(bp) ||
4448 is_bnxt_in_error(bp))
4451 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4452 if (val == info->last_heart_beat)
4455 info->last_heart_beat = val;
4457 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4458 if (val != info->last_reset_counter)
4461 info->last_reset_counter = val;
4463 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4464 bnxt_check_fw_health, (void *)bp);
4468 /* Stop DMA to/from device */
4469 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4470 bp->flags |= BNXT_FLAG_FW_RESET;
4472 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4474 if (bnxt_is_master_func(bp))
4475 wait_msec = info->master_func_wait_period;
4477 wait_msec = info->normal_func_wait_period;
4479 rte_eal_alarm_set(US_PER_MS * wait_msec,
4480 bnxt_fw_reset_cb, (void *)bp);
4483 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4485 uint32_t polling_freq;
4487 if (!bnxt_is_recovery_enabled(bp))
4490 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4493 polling_freq = bp->recovery_info->driver_polling_freq;
4495 rte_eal_alarm_set(US_PER_MS * polling_freq,
4496 bnxt_check_fw_health, (void *)bp);
4497 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4500 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4502 if (!bnxt_is_recovery_enabled(bp))
4505 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4506 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4509 static bool bnxt_vf_pciid(uint16_t device_id)
4511 switch (device_id) {
4512 case BROADCOM_DEV_ID_57304_VF:
4513 case BROADCOM_DEV_ID_57406_VF:
4514 case BROADCOM_DEV_ID_5731X_VF:
4515 case BROADCOM_DEV_ID_5741X_VF:
4516 case BROADCOM_DEV_ID_57414_VF:
4517 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4518 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4519 case BROADCOM_DEV_ID_58802_VF:
4520 case BROADCOM_DEV_ID_57500_VF1:
4521 case BROADCOM_DEV_ID_57500_VF2:
4529 static bool bnxt_thor_device(uint16_t device_id)
4531 switch (device_id) {
4532 case BROADCOM_DEV_ID_57508:
4533 case BROADCOM_DEV_ID_57504:
4534 case BROADCOM_DEV_ID_57502:
4535 case BROADCOM_DEV_ID_57508_MF1:
4536 case BROADCOM_DEV_ID_57504_MF1:
4537 case BROADCOM_DEV_ID_57502_MF1:
4538 case BROADCOM_DEV_ID_57508_MF2:
4539 case BROADCOM_DEV_ID_57504_MF2:
4540 case BROADCOM_DEV_ID_57502_MF2:
4541 case BROADCOM_DEV_ID_57500_VF1:
4542 case BROADCOM_DEV_ID_57500_VF2:
4550 bool bnxt_stratus_device(struct bnxt *bp)
4552 uint16_t device_id = bp->pdev->id.device_id;
4554 switch (device_id) {
4555 case BROADCOM_DEV_ID_STRATUS_NIC:
4556 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4557 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4565 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4567 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4568 struct bnxt *bp = eth_dev->data->dev_private;
4570 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4571 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4572 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4573 if (!bp->bar0 || !bp->doorbell_base) {
4574 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4578 bp->eth_dev = eth_dev;
4584 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4585 struct bnxt_ctx_pg_info *ctx_pg,
4590 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4591 const struct rte_memzone *mz = NULL;
4592 char mz_name[RTE_MEMZONE_NAMESIZE];
4593 rte_iova_t mz_phys_addr;
4594 uint64_t valid_bits = 0;
4601 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4603 rmem->page_size = BNXT_PAGE_SIZE;
4604 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4605 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4606 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4608 valid_bits = PTU_PTE_VALID;
4610 if (rmem->nr_pages > 1) {
4611 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4612 "bnxt_ctx_pg_tbl%s_%x_%d",
4613 suffix, idx, bp->eth_dev->data->port_id);
4614 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4615 mz = rte_memzone_lookup(mz_name);
4617 mz = rte_memzone_reserve_aligned(mz_name,
4621 RTE_MEMZONE_SIZE_HINT_ONLY |
4622 RTE_MEMZONE_IOVA_CONTIG,
4628 memset(mz->addr, 0, mz->len);
4629 mz_phys_addr = mz->iova;
4631 rmem->pg_tbl = mz->addr;
4632 rmem->pg_tbl_map = mz_phys_addr;
4633 rmem->pg_tbl_mz = mz;
4636 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4637 suffix, idx, bp->eth_dev->data->port_id);
4638 mz = rte_memzone_lookup(mz_name);
4640 mz = rte_memzone_reserve_aligned(mz_name,
4644 RTE_MEMZONE_SIZE_HINT_ONLY |
4645 RTE_MEMZONE_IOVA_CONTIG,
4651 memset(mz->addr, 0, mz->len);
4652 mz_phys_addr = mz->iova;
4654 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4655 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4656 rmem->dma_arr[i] = mz_phys_addr + sz;
4658 if (rmem->nr_pages > 1) {
4659 if (i == rmem->nr_pages - 2 &&
4660 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4661 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4662 else if (i == rmem->nr_pages - 1 &&
4663 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4664 valid_bits |= PTU_PTE_LAST;
4666 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4672 if (rmem->vmem_size)
4673 rmem->vmem = (void **)mz->addr;
4674 rmem->dma_arr[0] = mz_phys_addr;
4678 static void bnxt_free_ctx_mem(struct bnxt *bp)
4682 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4685 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4686 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4687 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4688 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4689 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4690 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4691 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4692 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4693 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4694 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4695 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4697 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4698 if (bp->ctx->tqm_mem[i])
4699 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4706 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4708 #define min_t(type, x, y) ({ \
4709 type __min1 = (x); \
4710 type __min2 = (y); \
4711 __min1 < __min2 ? __min1 : __min2; })
4713 #define max_t(type, x, y) ({ \
4714 type __max1 = (x); \
4715 type __max2 = (y); \
4716 __max1 > __max2 ? __max1 : __max2; })
4718 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4720 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4722 struct bnxt_ctx_pg_info *ctx_pg;
4723 struct bnxt_ctx_mem_info *ctx;
4724 uint32_t mem_size, ena, entries;
4725 uint32_t entries_sp, min;
4728 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4730 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4734 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4737 ctx_pg = &ctx->qp_mem;
4738 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4739 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4740 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4744 ctx_pg = &ctx->srq_mem;
4745 ctx_pg->entries = ctx->srq_max_l2_entries;
4746 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4747 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4751 ctx_pg = &ctx->cq_mem;
4752 ctx_pg->entries = ctx->cq_max_l2_entries;
4753 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4754 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4758 ctx_pg = &ctx->vnic_mem;
4759 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4760 ctx->vnic_max_ring_table_entries;
4761 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4762 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4766 ctx_pg = &ctx->stat_mem;
4767 ctx_pg->entries = ctx->stat_max_entries;
4768 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4769 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4773 min = ctx->tqm_min_entries_per_ring;
4775 entries_sp = ctx->qp_max_l2_entries +
4776 ctx->vnic_max_vnic_entries +
4777 2 * ctx->qp_min_qp1_entries + min;
4778 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4780 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4781 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4782 entries = clamp_t(uint32_t, entries, min,
4783 ctx->tqm_max_entries_per_ring);
4784 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4785 ctx_pg = ctx->tqm_mem[i];
4786 ctx_pg->entries = i ? entries : entries_sp;
4787 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4788 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4791 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4794 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4795 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4798 "Failed to configure context mem: rc = %d\n", rc);
4800 ctx->flags |= BNXT_CTX_FLAG_INITED;
4805 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4807 struct rte_pci_device *pci_dev = bp->pdev;
4808 char mz_name[RTE_MEMZONE_NAMESIZE];
4809 const struct rte_memzone *mz = NULL;
4810 uint32_t total_alloc_len;
4811 rte_iova_t mz_phys_addr;
4813 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4816 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4817 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4818 pci_dev->addr.bus, pci_dev->addr.devid,
4819 pci_dev->addr.function, "rx_port_stats");
4820 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4821 mz = rte_memzone_lookup(mz_name);
4823 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4824 sizeof(struct rx_port_stats_ext) + 512);
4826 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4829 RTE_MEMZONE_SIZE_HINT_ONLY |
4830 RTE_MEMZONE_IOVA_CONTIG);
4834 memset(mz->addr, 0, mz->len);
4835 mz_phys_addr = mz->iova;
4837 bp->rx_mem_zone = (const void *)mz;
4838 bp->hw_rx_port_stats = mz->addr;
4839 bp->hw_rx_port_stats_map = mz_phys_addr;
4841 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4842 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4843 pci_dev->addr.bus, pci_dev->addr.devid,
4844 pci_dev->addr.function, "tx_port_stats");
4845 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4846 mz = rte_memzone_lookup(mz_name);
4848 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4849 sizeof(struct tx_port_stats_ext) + 512);
4851 mz = rte_memzone_reserve(mz_name,
4855 RTE_MEMZONE_SIZE_HINT_ONLY |
4856 RTE_MEMZONE_IOVA_CONTIG);
4860 memset(mz->addr, 0, mz->len);
4861 mz_phys_addr = mz->iova;
4863 bp->tx_mem_zone = (const void *)mz;
4864 bp->hw_tx_port_stats = mz->addr;
4865 bp->hw_tx_port_stats_map = mz_phys_addr;
4866 bp->flags |= BNXT_FLAG_PORT_STATS;
4868 /* Display extended statistics if FW supports it */
4869 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4870 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4871 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4874 bp->hw_rx_port_stats_ext = (void *)
4875 ((uint8_t *)bp->hw_rx_port_stats +
4876 sizeof(struct rx_port_stats));
4877 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4878 sizeof(struct rx_port_stats);
4879 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4881 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4882 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4883 bp->hw_tx_port_stats_ext = (void *)
4884 ((uint8_t *)bp->hw_tx_port_stats +
4885 sizeof(struct tx_port_stats));
4886 bp->hw_tx_port_stats_ext_map =
4887 bp->hw_tx_port_stats_map +
4888 sizeof(struct tx_port_stats);
4889 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4895 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4897 struct bnxt *bp = eth_dev->data->dev_private;
4900 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4901 RTE_ETHER_ADDR_LEN *
4904 if (eth_dev->data->mac_addrs == NULL) {
4905 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4909 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4913 /* Generate a random MAC address, if none was assigned by PF */
4914 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4915 bnxt_eth_hw_addr_random(bp->mac_addr);
4917 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4918 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4919 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4921 rc = bnxt_hwrm_set_mac(bp);
4923 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4924 RTE_ETHER_ADDR_LEN);
4928 /* Copy the permanent MAC from the FUNC_QCAPS response */
4929 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4930 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4935 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4939 /* MAC is already configured in FW */
4940 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4943 /* Restore the old MAC configured */
4944 rc = bnxt_hwrm_set_mac(bp);
4946 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4951 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4956 #define ALLOW_FUNC(x) \
4958 uint32_t arg = (x); \
4959 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4960 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4963 /* Forward all requests if firmware is new enough */
4964 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4965 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4966 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4967 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4969 PMD_DRV_LOG(WARNING,
4970 "Firmware too old for VF mailbox functionality\n");
4971 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4975 * The following are used for driver cleanup. If we disallow these,
4976 * VF drivers can't clean up cleanly.
4978 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4979 ALLOW_FUNC(HWRM_VNIC_FREE);
4980 ALLOW_FUNC(HWRM_RING_FREE);
4981 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4982 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4983 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4984 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4985 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4986 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4990 bnxt_get_svif(uint16_t port_id, bool func_svif)
4992 struct rte_eth_dev *eth_dev;
4995 eth_dev = &rte_eth_devices[port_id];
4996 bp = eth_dev->data->dev_private;
4998 return func_svif ? bp->func_svif : bp->port_svif;
5002 bnxt_get_vnic_id(uint16_t port)
5004 struct rte_eth_dev *eth_dev;
5005 struct bnxt_vnic_info *vnic;
5008 eth_dev = &rte_eth_devices[port];
5009 bp = eth_dev->data->dev_private;
5011 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5013 return vnic->fw_vnic_id;
5017 bnxt_get_fw_func_id(uint16_t port)
5019 struct rte_eth_dev *eth_dev;
5022 eth_dev = &rte_eth_devices[port];
5023 bp = eth_dev->data->dev_private;
5028 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5030 struct bnxt_error_recovery_info *info = bp->recovery_info;
5033 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5034 memset(info, 0, sizeof(*info));
5038 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5041 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5044 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5046 bp->recovery_info = info;
5049 static void bnxt_check_fw_status(struct bnxt *bp)
5053 if (!(bp->recovery_info &&
5054 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5057 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5058 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5059 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5063 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5065 struct bnxt_error_recovery_info *info = bp->recovery_info;
5066 uint32_t status_loc;
5069 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5070 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5071 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5072 BNXT_GRCP_WINDOW_2_BASE +
5073 offsetof(struct hcomm_status,
5075 /* If the signature is absent, then FW does not support this feature */
5076 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5077 HCOMM_STATUS_SIGNATURE_VAL)
5081 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5085 bp->recovery_info = info;
5087 memset(info, 0, sizeof(*info));
5090 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5091 BNXT_GRCP_WINDOW_2_BASE +
5092 offsetof(struct hcomm_status,
5095 /* Only pre-map the FW health status GRC register */
5096 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5099 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5100 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5101 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5103 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5104 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5106 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5111 static int bnxt_init_fw(struct bnxt *bp)
5118 rc = bnxt_map_hcomm_fw_status_reg(bp);
5122 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5124 bnxt_check_fw_status(bp);
5128 rc = bnxt_hwrm_func_reset(bp);
5132 rc = bnxt_hwrm_vnic_qcaps(bp);
5136 rc = bnxt_hwrm_queue_qportcfg(bp);
5140 /* Get the MAX capabilities for this function.
5141 * This function also allocates context memory for TQM rings and
5142 * informs the firmware about this allocated backing store memory.
5144 rc = bnxt_hwrm_func_qcaps(bp);
5148 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5152 bnxt_hwrm_port_mac_qcfg(bp);
5154 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5158 bnxt_alloc_error_recovery_info(bp);
5159 /* Get the adapter error recovery support info */
5160 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5162 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5164 bnxt_hwrm_port_led_qcaps(bp);
5170 bnxt_init_locks(struct bnxt *bp)
5174 err = pthread_mutex_init(&bp->flow_lock, NULL);
5176 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5180 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5182 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5186 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5190 rc = bnxt_init_fw(bp);
5194 if (!reconfig_dev) {
5195 rc = bnxt_setup_mac_addr(bp->eth_dev);
5199 rc = bnxt_restore_dflt_mac(bp);
5204 bnxt_config_vf_req_fwd(bp);
5206 rc = bnxt_hwrm_func_driver_register(bp);
5208 PMD_DRV_LOG(ERR, "Failed to register driver");
5213 if (bp->pdev->max_vfs) {
5214 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5216 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5220 rc = bnxt_hwrm_allocate_pf_only(bp);
5223 "Failed to allocate PF resources");
5229 rc = bnxt_alloc_mem(bp, reconfig_dev);
5233 rc = bnxt_setup_int(bp);
5237 rc = bnxt_request_int(bp);
5241 rc = bnxt_init_ctx_mem(bp);
5243 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5247 rc = bnxt_init_locks(bp);
5255 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5256 const char *value, void *opaque_arg)
5258 struct bnxt *bp = opaque_arg;
5259 unsigned long truflow;
5262 if (!value || !opaque_arg) {
5264 "Invalid parameter passed to truflow devargs.\n");
5268 truflow = strtoul(value, &end, 10);
5269 if (end == NULL || *end != '\0' ||
5270 (truflow == ULONG_MAX && errno == ERANGE)) {
5272 "Invalid parameter passed to truflow devargs.\n");
5276 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5278 "Invalid value passed to truflow devargs.\n");
5282 bp->truflow = truflow;
5284 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5290 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5291 const char *value, void *opaque_arg)
5293 struct bnxt *bp = opaque_arg;
5294 unsigned long flow_xstat;
5297 if (!value || !opaque_arg) {
5299 "Invalid parameter passed to flow_xstat devarg.\n");
5303 flow_xstat = strtoul(value, &end, 10);
5304 if (end == NULL || *end != '\0' ||
5305 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5307 "Invalid parameter passed to flow_xstat devarg.\n");
5311 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5313 "Invalid value passed to flow_xstat devarg.\n");
5317 bp->flow_xstat = flow_xstat;
5319 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5325 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5327 struct rte_kvargs *kvlist;
5329 if (devargs == NULL)
5332 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5337 * Handler for "truflow" devarg.
5338 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5340 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5341 bnxt_parse_devarg_truflow, bp);
5344 * Handler for "flow_xstat" devarg.
5345 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5347 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5348 bnxt_parse_devarg_flow_xstat, bp);
5350 rte_kvargs_free(kvlist);
5354 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5356 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5357 static int version_printed;
5361 if (version_printed++ == 0)
5362 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5364 eth_dev->dev_ops = &bnxt_dev_ops;
5365 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5366 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5369 * For secondary processes, we don't initialise any further
5370 * as primary has already done this work.
5372 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5375 rte_eth_copy_pci_info(eth_dev, pci_dev);
5377 bp = eth_dev->data->dev_private;
5379 /* Parse dev arguments passed on when starting the DPDK application. */
5380 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5382 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5384 if (bnxt_vf_pciid(pci_dev->id.device_id))
5385 bp->flags |= BNXT_FLAG_VF;
5387 if (bnxt_thor_device(pci_dev->id.device_id))
5388 bp->flags |= BNXT_FLAG_THOR_CHIP;
5390 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5391 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5392 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5393 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5394 bp->flags |= BNXT_FLAG_STINGRAY;
5396 rc = bnxt_init_board(eth_dev);
5399 "Failed to initialize board rc: %x\n", rc);
5403 rc = bnxt_alloc_hwrm_resources(bp);
5406 "Failed to allocate hwrm resource rc: %x\n", rc);
5409 rc = bnxt_alloc_leds_info(bp);
5413 rc = bnxt_alloc_cos_queues(bp);
5417 rc = bnxt_init_resources(bp, false);
5421 rc = bnxt_alloc_stats_mem(bp);
5425 /* Pass the information to the rte_eth_dev_close() that it should also
5426 * release the private port resources.
5428 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5431 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5432 pci_dev->mem_resource[0].phys_addr,
5433 pci_dev->mem_resource[0].addr);
5438 bnxt_dev_uninit(eth_dev);
5443 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5452 ctx->dma = RTE_BAD_IOVA;
5453 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5456 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5458 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5459 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5460 bp->rx_fc_out_tbl.ctx_id,
5464 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5465 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5466 bp->tx_fc_out_tbl.ctx_id,
5470 if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5471 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5472 bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5474 if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5475 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5476 bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5478 if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5479 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5480 bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5482 if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5483 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5484 bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5487 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5489 bnxt_unregister_fc_ctx_mem(bp);
5491 bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5492 bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5493 bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5494 bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5497 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5499 bnxt_uninit_fc_ctx_mem(bp);
5503 bnxt_free_error_recovery_info(struct bnxt *bp)
5505 rte_free(bp->recovery_info);
5506 bp->recovery_info = NULL;
5507 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5511 bnxt_uninit_locks(struct bnxt *bp)
5513 pthread_mutex_destroy(&bp->flow_lock);
5514 pthread_mutex_destroy(&bp->def_cp_lock);
5518 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5523 bnxt_free_mem(bp, reconfig_dev);
5524 bnxt_hwrm_func_buf_unrgtr(bp);
5525 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5526 bp->flags &= ~BNXT_FLAG_REGISTERED;
5527 bnxt_free_ctx_mem(bp);
5528 if (!reconfig_dev) {
5529 bnxt_free_hwrm_resources(bp);
5530 bnxt_free_error_recovery_info(bp);
5533 bnxt_uninit_ctx_mem(bp);
5535 bnxt_uninit_locks(bp);
5536 rte_free(bp->ptp_cfg);
5542 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5544 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5547 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5549 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5550 bnxt_dev_close_op(eth_dev);
5555 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5556 struct rte_pci_device *pci_dev)
5558 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5562 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5564 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5565 return rte_eth_dev_pci_generic_remove(pci_dev,
5568 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5571 static struct rte_pci_driver bnxt_rte_pmd = {
5572 .id_table = bnxt_pci_id_map,
5573 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5574 .probe = bnxt_pci_probe,
5575 .remove = bnxt_pci_remove,
5579 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5581 if (strcmp(dev->device->driver->name, drv->driver.name))
5587 bool is_bnxt_supported(struct rte_eth_dev *dev)
5589 return is_device_supported(dev, &bnxt_rte_pmd);
5592 RTE_INIT(bnxt_init_log)
5594 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5595 if (bnxt_logtype_driver >= 0)
5596 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5599 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5600 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5601 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");