1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
6 #ifndef _BNXT_FILTER_H_
7 #define _BNXT_FILTER_H_
13 #define BNXT_FLOW_L2_VALID_FLAG BIT(0)
14 #define BNXT_FLOW_L2_SRC_VALID_FLAG BIT(1)
15 #define BNXT_FLOW_L2_INNER_SRC_VALID_FLAG BIT(2)
16 #define BNXT_FLOW_L2_DST_VALID_FLAG BIT(3)
17 #define BNXT_FLOW_L2_INNER_DST_VALID_FLAG BIT(4)
18 #define BNXT_FLOW_L2_DROP_FLAG BIT(5)
19 #define BNXT_FLOW_PARSE_INNER_FLAG BIT(6)
21 struct bnxt_filter_info {
22 STAILQ_ENTRY(bnxt_filter_info) next;
23 uint64_t fw_l2_filter_id;
24 struct bnxt_filter_info *matching_l2_fltr_ptr;
25 uint64_t fw_em_filter_id;
26 uint64_t fw_ntuple_filter_id;
27 #define INVALID_MAC_INDEX ((uint16_t)-1)
29 #define HWRM_CFA_L2_FILTER 0
30 #define HWRM_CFA_EM_FILTER 1
31 #define HWRM_CFA_NTUPLE_FILTER 2
32 #define HWRM_CFA_TUNNEL_REDIRECT_FILTER 3
36 /* Filter Characteristics */
40 uint8_t l2_addr[RTE_ETHER_ADDR_LEN];
41 uint8_t l2_addr_mask[RTE_ETHER_ADDR_LEN];
44 uint16_t l2_ovlan_mask;
46 uint16_t l2_ivlan_mask;
47 uint8_t t_l2_addr[RTE_ETHER_ADDR_LEN];
48 uint8_t t_l2_addr_mask[RTE_ETHER_ADDR_LEN];
50 uint16_t t_l2_ovlan_mask;
52 uint16_t t_l2_ivlan_mask;
54 uint16_t mirror_vnic_id;
57 uint64_t l2_filter_id_hint;
60 uint8_t src_macaddr[6];
61 uint8_t dst_macaddr[6];
62 uint32_t dst_ipaddr[4];
63 uint32_t dst_ipaddr_mask[4];
64 uint32_t src_ipaddr[4];
65 uint32_t src_ipaddr_mask[4];
67 uint16_t dst_port_mask;
69 uint16_t src_port_mask;
71 uint16_t ip_addr_type;
77 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
78 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
79 void bnxt_init_filters(struct bnxt *bp);
80 void bnxt_free_all_filters(struct bnxt *bp);
81 void bnxt_free_filter_mem(struct bnxt *bp);
82 int bnxt_alloc_filter_mem(struct bnxt *bp);
83 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
84 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
85 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
86 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
88 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR \
89 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
90 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR \
91 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
92 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR \
93 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
94 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR \
95 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
96 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE \
97 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
98 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE \
99 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
100 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID \
101 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
102 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR \
103 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
104 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK \
105 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
106 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR \
107 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
108 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK \
109 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
110 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT \
111 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
112 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK \
113 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
114 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT \
115 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
116 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK \
117 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
118 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO \
119 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
120 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR \
121 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
122 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR \
123 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
124 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
125 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
126 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
127 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
128 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
129 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
130 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
131 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
132 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
133 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
134 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN \
135 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
136 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE \
137 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
138 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE \
139 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE
140 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK \
141 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
142 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
143 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
144 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
145 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
146 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
147 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
148 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
149 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
150 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
151 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
152 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID \
153 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
154 #define L2_FILTER_ALLOC_INPUT_EN_T_NUM_VLANS \
155 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS
156 #define L2_FILTER_ALLOC_INPUT_EN_NUM_VLANS \
157 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS