4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <rte_byteorder.h>
37 #include <rte_common.h>
38 #include <rte_cycles.h>
39 #include <rte_malloc.h>
40 #include <rte_memzone.h>
41 #include <rte_version.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
49 #include "bnxt_ring.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
57 #define HWRM_CMD_TIMEOUT 10000
59 struct bnxt_plcmodes_cfg {
61 uint16_t jumbo_thresh;
63 uint16_t hds_threshold;
66 static int page_getenum(size_t size)
82 RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
83 return sizeof(void *) * 8 - 1;
86 static int page_roundup(size_t size)
88 return 1 << page_getenum(size);
92 * HWRM Functions (sent to HWRM)
93 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
94 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
95 * command was failed by the ChiMP.
98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
102 struct input *req = msg;
103 struct output *resp = bp->hwrm_cmd_resp_addr;
104 uint32_t *data = msg;
107 uint16_t max_req_len = bp->max_req_len;
108 struct hwrm_short_input short_input = { 0 };
110 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
111 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
113 memset(short_cmd_req, 0, bp->max_req_len);
114 memcpy(short_cmd_req, req, msg_len);
116 short_input.req_type = rte_cpu_to_le_16(req->req_type);
117 short_input.signature = rte_cpu_to_le_16(
118 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
119 short_input.size = rte_cpu_to_le_16(msg_len);
120 short_input.req_addr =
121 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
123 data = (uint32_t *)&short_input;
124 msg_len = sizeof(short_input);
126 /* Sync memory write before updating doorbell */
129 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
132 /* Write request msg to hwrm channel */
133 for (i = 0; i < msg_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + i;
135 rte_write32(*data, bar);
139 /* Zero the rest of the request space */
140 for (; i < max_req_len; i += 4) {
141 bar = (uint8_t *)bp->bar0 + i;
145 /* Ring channel doorbell */
146 bar = (uint8_t *)bp->bar0 + 0x100;
149 /* Poll for the valid bit */
150 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
151 /* Sanity check on the resp->resp_len */
153 if (resp->resp_len && resp->resp_len <=
155 /* Last byte of resp contains the valid key */
156 valid = (uint8_t *)resp + resp->resp_len - 1;
157 if (*valid == HWRM_RESP_VALID_KEY)
163 if (i >= HWRM_CMD_TIMEOUT) {
164 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
175 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
176 * spinlock, and does initial processing.
178 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
179 * releases the spinlock only if it returns. If the regular int return codes
180 * are not used by the function, HWRM_CHECK_RESULT() should not be used
181 * directly, rather it should be copied and modified to suit the function.
183 * HWRM_UNLOCK() must be called after all response processing is completed.
185 #define HWRM_PREP(req, type) do { \
186 rte_spinlock_lock(&bp->hwrm_lock); \
187 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
188 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
189 req.cmpl_ring = rte_cpu_to_le_16(-1); \
190 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
191 req.target_id = rte_cpu_to_le_16(0xffff); \
192 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
195 #define HWRM_CHECK_RESULT() do {\
197 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
199 rte_spinlock_unlock(&bp->hwrm_lock); \
202 if (resp->error_code) { \
203 rc = rte_le_to_cpu_16(resp->error_code); \
204 if (resp->resp_len >= 16) { \
205 struct hwrm_err_output *tmp_hwrm_err_op = \
208 "%s error %d:%d:%08x:%04x\n", \
210 rc, tmp_hwrm_err_op->cmd_err, \
212 tmp_hwrm_err_op->opaque_0), \
214 tmp_hwrm_err_op->opaque_1)); \
218 "%s error %d\n", __func__, rc); \
220 rte_spinlock_unlock(&bp->hwrm_lock); \
225 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
230 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
231 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
233 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
234 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
246 struct bnxt_vnic_info *vnic,
248 struct bnxt_vlan_table_entry *vlan_table)
251 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
252 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
255 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
256 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
258 /* FIXME add multicast flag, when multicast adding options is supported
261 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
262 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
263 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
264 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
265 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
266 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
267 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
268 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
269 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
270 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
271 if (vnic->mc_addr_cnt) {
272 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
273 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
274 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
277 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
278 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
279 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
280 rte_mem_virt2iova(vlan_table));
281 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
283 req.mask = rte_cpu_to_le_32(mask);
285 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
295 struct bnxt_vlan_antispoof_table_entry *vlan_table)
298 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
299 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
300 bp->hwrm_cmd_resp_addr;
303 * Older HWRM versions did not support this command, and the set_rx_mask
304 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
305 * removed from set_rx_mask call, and this command was added.
307 * This command is also present from 1.7.8.11 and higher,
310 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
311 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
312 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
317 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
318 req.fid = rte_cpu_to_le_16(fid);
320 req.vlan_tag_mask_tbl_addr =
321 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
322 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
333 struct bnxt_filter_info *filter)
336 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
337 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
339 if (filter->fw_l2_filter_id == UINT64_MAX)
342 HWRM_PREP(req, CFA_L2_FILTER_FREE);
344 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
351 filter->fw_l2_filter_id = -1;
356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
358 struct bnxt_filter_info *filter)
361 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
362 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
363 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
364 const struct rte_eth_vmdq_rx_conf *conf =
365 &dev_conf->rx_adv_conf.vmdq_rx_conf;
366 uint32_t enables = 0;
367 uint16_t j = dst_id - 1;
369 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
370 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
371 conf->pool_map[j].pools & (1UL << j)) {
373 "Add vlan %u to vmdq pool %u\n",
374 conf->pool_map[j].vlan_id, j);
376 filter->l2_ivlan = conf->pool_map[j].vlan_id;
378 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
379 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
382 if (filter->fw_l2_filter_id != UINT64_MAX)
383 bnxt_hwrm_clear_l2_filter(bp, filter);
385 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
387 req.flags = rte_cpu_to_le_32(filter->flags);
389 enables = filter->enables |
390 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
391 req.dst_id = rte_cpu_to_le_16(dst_id);
394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
395 memcpy(req.l2_addr, filter->l2_addr,
398 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
399 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
402 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
403 req.l2_ovlan = filter->l2_ovlan;
405 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
406 req.l2_ovlan = filter->l2_ivlan;
408 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
409 req.l2_ovlan_mask = filter->l2_ovlan_mask;
411 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
412 req.l2_ovlan_mask = filter->l2_ivlan_mask;
413 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
414 req.src_id = rte_cpu_to_le_32(filter->src_id);
415 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
416 req.src_type = filter->src_type;
418 req.enables = rte_cpu_to_le_32(enables);
420 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
424 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
430 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
432 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
433 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
440 HWRM_PREP(req, PORT_MAC_CFG);
443 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
445 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
446 if (ptp->tx_tstamp_en)
447 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
449 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
450 req.flags = rte_cpu_to_le_32(flags);
452 rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
453 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
455 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
461 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
464 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
465 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
466 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
468 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
472 HWRM_PREP(req, PORT_MAC_PTP_QCFG);
474 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
476 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
480 if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
483 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
487 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
488 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
489 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
490 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
491 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
492 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
493 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
494 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
495 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
496 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
497 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
498 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
499 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
500 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
501 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
502 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
503 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
504 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
512 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
515 struct hwrm_func_qcaps_input req = {.req_type = 0 };
516 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
517 uint16_t new_max_vfs;
521 HWRM_PREP(req, FUNC_QCAPS);
523 req.fid = rte_cpu_to_le_16(0xffff);
525 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
529 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
530 flags = rte_le_to_cpu_32(resp->flags);
532 bp->pf.port_id = resp->port_id;
533 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
534 new_max_vfs = bp->pdev->max_vfs;
535 if (new_max_vfs != bp->pf.max_vfs) {
537 rte_free(bp->pf.vf_info);
538 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
539 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
540 bp->pf.max_vfs = new_max_vfs;
541 for (i = 0; i < new_max_vfs; i++) {
542 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
543 bp->pf.vf_info[i].vlan_table =
544 rte_zmalloc("VF VLAN table",
547 if (bp->pf.vf_info[i].vlan_table == NULL)
549 "Fail to alloc VLAN table for VF %d\n",
553 bp->pf.vf_info[i].vlan_table);
554 bp->pf.vf_info[i].vlan_as_table =
555 rte_zmalloc("VF VLAN AS table",
558 if (bp->pf.vf_info[i].vlan_as_table == NULL)
560 "Alloc VLAN AS table for VF %d fail\n",
564 bp->pf.vf_info[i].vlan_as_table);
565 STAILQ_INIT(&bp->pf.vf_info[i].filter);
570 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
571 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
572 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
573 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
574 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
575 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
576 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
577 /* TODO: For now, do not support VMDq/RFS on VFs. */
582 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
586 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
588 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
589 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
590 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
591 RTE_LOG(INFO, PMD, "PTP SUPPORTED");
593 bnxt_hwrm_ptp_qcfg(bp);
602 int bnxt_hwrm_func_reset(struct bnxt *bp)
605 struct hwrm_func_reset_input req = {.req_type = 0 };
606 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
608 HWRM_PREP(req, FUNC_RESET);
610 req.enables = rte_cpu_to_le_32(0);
612 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
620 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
623 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
624 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
626 if (bp->flags & BNXT_FLAG_REGISTERED)
629 HWRM_PREP(req, FUNC_DRV_RGTR);
630 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
631 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
632 req.ver_maj = RTE_VER_YEAR;
633 req.ver_min = RTE_VER_MONTH;
634 req.ver_upd = RTE_VER_MINOR;
637 req.enables |= rte_cpu_to_le_32(
638 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
639 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
640 RTE_MIN(sizeof(req.vf_req_fwd),
641 sizeof(bp->pf.vf_req_fwd)));
644 req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1); /* TODO: Use MACRO */
645 //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
647 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
652 bp->flags |= BNXT_FLAG_REGISTERED;
657 int bnxt_hwrm_ver_get(struct bnxt *bp)
660 struct hwrm_ver_get_input req = {.req_type = 0 };
661 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
664 uint16_t max_resp_len;
665 char type[RTE_MEMZONE_NAMESIZE];
666 uint32_t dev_caps_cfg;
668 bp->max_req_len = HWRM_MAX_REQ_LEN;
669 HWRM_PREP(req, VER_GET);
671 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
672 req.hwrm_intf_min = HWRM_VERSION_MINOR;
673 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
679 RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
680 resp->hwrm_intf_maj, resp->hwrm_intf_min,
682 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
683 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
684 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
685 RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
686 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
688 my_version = HWRM_VERSION_MAJOR << 16;
689 my_version |= HWRM_VERSION_MINOR << 8;
690 my_version |= HWRM_VERSION_UPDATE;
692 fw_version = resp->hwrm_intf_maj << 16;
693 fw_version |= resp->hwrm_intf_min << 8;
694 fw_version |= resp->hwrm_intf_upd;
696 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
697 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
702 if (my_version != fw_version) {
703 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
704 if (my_version < fw_version) {
706 "Firmware API version is newer than driver.\n");
708 "The driver may be missing features.\n");
711 "Firmware API version is older than driver.\n");
713 "Not all driver features may be functional.\n");
717 if (bp->max_req_len > resp->max_req_win_len) {
718 RTE_LOG(ERR, PMD, "Unsupported request length\n");
721 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
722 max_resp_len = resp->max_resp_len;
723 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
725 if (bp->max_resp_len != max_resp_len) {
726 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
727 bp->pdev->addr.domain, bp->pdev->addr.bus,
728 bp->pdev->addr.devid, bp->pdev->addr.function);
730 rte_free(bp->hwrm_cmd_resp_addr);
732 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
733 if (bp->hwrm_cmd_resp_addr == NULL) {
737 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
738 bp->hwrm_cmd_resp_dma_addr =
739 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
740 if (bp->hwrm_cmd_resp_dma_addr == 0) {
742 "Unable to map response buffer to physical memory.\n");
746 bp->max_resp_len = max_resp_len;
750 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
752 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
753 RTE_LOG(DEBUG, PMD, "Short command supported\n");
755 rte_free(bp->hwrm_short_cmd_req_addr);
757 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
759 if (bp->hwrm_short_cmd_req_addr == NULL) {
763 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
764 bp->hwrm_short_cmd_req_dma_addr =
765 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
766 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
767 rte_free(bp->hwrm_short_cmd_req_addr);
769 "Unable to map buffer to physical memory.\n");
774 bp->flags |= BNXT_FLAG_SHORT_CMD;
782 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
785 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
786 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
788 if (!(bp->flags & BNXT_FLAG_REGISTERED))
791 HWRM_PREP(req, FUNC_DRV_UNRGTR);
794 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
799 bp->flags &= ~BNXT_FLAG_REGISTERED;
804 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
807 struct hwrm_port_phy_cfg_input req = {0};
808 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
809 uint32_t enables = 0;
811 HWRM_PREP(req, PORT_PHY_CFG);
814 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
815 if (bp->link_info.auto_mode && conf->link_speed) {
816 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
817 RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
820 req.flags = rte_cpu_to_le_32(conf->phy_flags);
821 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
822 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
824 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
825 * any auto mode, even "none".
827 if (!conf->link_speed) {
828 /* No speeds specified. Enable AutoNeg - all speeds */
830 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
832 /* AutoNeg - Advertise speeds specified. */
833 if (conf->auto_link_speed_mask) {
835 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
836 req.auto_link_speed_mask =
837 conf->auto_link_speed_mask;
839 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
842 req.auto_duplex = conf->duplex;
843 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
844 req.auto_pause = conf->auto_pause;
845 req.force_pause = conf->force_pause;
846 /* Set force_pause if there is no auto or if there is a force */
847 if (req.auto_pause && !req.force_pause)
848 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
850 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
852 req.enables = rte_cpu_to_le_32(enables);
855 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
856 RTE_LOG(INFO, PMD, "Force Link Down\n");
859 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
867 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
868 struct bnxt_link_info *link_info)
871 struct hwrm_port_phy_qcfg_input req = {0};
872 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
874 HWRM_PREP(req, PORT_PHY_QCFG);
876 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
880 link_info->phy_link_status = resp->link;
882 (link_info->phy_link_status ==
883 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
884 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
885 link_info->duplex = resp->duplex_cfg;
886 link_info->pause = resp->pause;
887 link_info->auto_pause = resp->auto_pause;
888 link_info->force_pause = resp->force_pause;
889 link_info->auto_mode = resp->auto_mode;
890 link_info->phy_type = resp->phy_type;
891 link_info->media_type = resp->media_type;
893 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
894 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
895 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
896 link_info->phy_ver[0] = resp->phy_maj;
897 link_info->phy_ver[1] = resp->phy_min;
898 link_info->phy_ver[2] = resp->phy_bld;
905 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
908 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
909 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
911 HWRM_PREP(req, QUEUE_QPORTCFG);
913 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
917 #define GET_QUEUE_INFO(x) \
918 bp->cos_queue[x].id = resp->queue_id##x; \
919 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
935 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
936 struct bnxt_ring *ring,
937 uint32_t ring_type, uint32_t map_index,
938 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
941 uint32_t enables = 0;
942 struct hwrm_ring_alloc_input req = {.req_type = 0 };
943 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
945 HWRM_PREP(req, RING_ALLOC);
947 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
948 req.fbo = rte_cpu_to_le_32(0);
949 /* Association of ring index with doorbell index */
950 req.logical_id = rte_cpu_to_le_16(map_index);
951 req.length = rte_cpu_to_le_32(ring->ring_size);
954 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
955 req.queue_id = bp->cos_queue[0].id;
957 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
958 req.ring_type = ring_type;
959 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
960 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
961 if (stats_ctx_id != INVALID_STATS_CTX_ID)
963 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
965 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
966 req.ring_type = ring_type;
968 * TODO: Some HWRM versions crash with
969 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
971 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
974 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
979 req.enables = rte_cpu_to_le_32(enables);
981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
983 if (rc || resp->error_code) {
984 if (rc == 0 && resp->error_code)
985 rc = rte_le_to_cpu_16(resp->error_code);
987 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
989 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
992 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
994 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
997 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
999 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1003 RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
1009 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1014 int bnxt_hwrm_ring_free(struct bnxt *bp,
1015 struct bnxt_ring *ring, uint32_t ring_type)
1018 struct hwrm_ring_free_input req = {.req_type = 0 };
1019 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1021 HWRM_PREP(req, RING_FREE);
1023 req.ring_type = ring_type;
1024 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1026 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1028 if (rc || resp->error_code) {
1029 if (rc == 0 && resp->error_code)
1030 rc = rte_le_to_cpu_16(resp->error_code);
1033 switch (ring_type) {
1034 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1035 RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
1038 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1039 RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
1042 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1043 RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
1047 RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
1055 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1058 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1059 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1061 HWRM_PREP(req, RING_GRP_ALLOC);
1063 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1064 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1065 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1066 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1068 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1070 HWRM_CHECK_RESULT();
1072 bp->grp_info[idx].fw_grp_id =
1073 rte_le_to_cpu_16(resp->ring_group_id);
1080 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1083 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1084 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1086 HWRM_PREP(req, RING_GRP_FREE);
1088 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1090 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1092 HWRM_CHECK_RESULT();
1095 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1099 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1102 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1103 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1105 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1108 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1110 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1114 HWRM_CHECK_RESULT();
1120 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1121 unsigned int idx __rte_unused)
1124 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1125 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1127 HWRM_PREP(req, STAT_CTX_ALLOC);
1129 req.update_period_ms = rte_cpu_to_le_32(0);
1131 req.stats_dma_addr =
1132 rte_cpu_to_le_64(cpr->hw_stats_map);
1134 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1136 HWRM_CHECK_RESULT();
1138 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1145 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1146 unsigned int idx __rte_unused)
1149 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1150 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1152 HWRM_PREP(req, STAT_CTX_FREE);
1154 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1156 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1158 HWRM_CHECK_RESULT();
1164 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1167 struct hwrm_vnic_alloc_input req = { 0 };
1168 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1170 /* map ring groups to this vnic */
1171 RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1172 vnic->start_grp_id, vnic->end_grp_id);
1173 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1174 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1175 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1176 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1177 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1178 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1179 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1180 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1181 HWRM_PREP(req, VNIC_ALLOC);
1183 if (vnic->func_default)
1184 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1185 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1187 HWRM_CHECK_RESULT();
1189 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1191 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1195 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1196 struct bnxt_vnic_info *vnic,
1197 struct bnxt_plcmodes_cfg *pmode)
1200 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1201 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1203 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1205 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1207 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1209 HWRM_CHECK_RESULT();
1211 pmode->flags = rte_le_to_cpu_32(resp->flags);
1212 /* dflt_vnic bit doesn't exist in the _cfg command */
1213 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1214 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1215 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1216 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1223 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1224 struct bnxt_vnic_info *vnic,
1225 struct bnxt_plcmodes_cfg *pmode)
1228 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1229 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1231 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1233 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1234 req.flags = rte_cpu_to_le_32(pmode->flags);
1235 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1236 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1237 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1238 req.enables = rte_cpu_to_le_32(
1239 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1240 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1241 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1244 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1246 HWRM_CHECK_RESULT();
1252 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1255 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1256 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1257 uint32_t ctx_enable_flag = 0;
1258 struct bnxt_plcmodes_cfg pmodes;
1260 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1261 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1265 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1269 HWRM_PREP(req, VNIC_CFG);
1271 /* Only RSS support for now TBD: COS & LB */
1273 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1274 if (vnic->lb_rule != 0xffff)
1275 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1276 if (vnic->cos_rule != 0xffff)
1277 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1278 if (vnic->rss_rule != 0xffff) {
1279 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1280 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1282 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1283 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1284 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1285 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1286 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1287 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1288 req.mru = rte_cpu_to_le_16(vnic->mru);
1289 if (vnic->func_default)
1291 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1292 if (vnic->vlan_strip)
1294 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1297 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1298 if (vnic->roce_dual)
1299 req.flags |= rte_cpu_to_le_32(
1300 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1301 if (vnic->roce_only)
1302 req.flags |= rte_cpu_to_le_32(
1303 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1304 if (vnic->rss_dflt_cr)
1305 req.flags |= rte_cpu_to_le_32(
1306 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1308 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1310 HWRM_CHECK_RESULT();
1313 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1318 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1322 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1323 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1325 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1326 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1329 HWRM_PREP(req, VNIC_QCFG);
1332 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1333 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1334 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1336 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1338 HWRM_CHECK_RESULT();
1340 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1341 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1342 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1343 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1344 vnic->mru = rte_le_to_cpu_16(resp->mru);
1345 vnic->func_default = rte_le_to_cpu_32(
1346 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1347 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1348 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1349 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1350 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1351 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1352 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1353 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1354 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1355 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1356 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1363 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1366 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1367 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1368 bp->hwrm_cmd_resp_addr;
1370 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1372 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1374 HWRM_CHECK_RESULT();
1376 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1378 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1383 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1386 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1387 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1388 bp->hwrm_cmd_resp_addr;
1390 if (vnic->rss_rule == 0xffff) {
1391 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1394 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1396 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1398 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1400 HWRM_CHECK_RESULT();
1403 vnic->rss_rule = INVALID_HW_RING_ID;
1408 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1411 struct hwrm_vnic_free_input req = {.req_type = 0 };
1412 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1414 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1415 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1419 HWRM_PREP(req, VNIC_FREE);
1421 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1423 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1425 HWRM_CHECK_RESULT();
1428 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1432 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1433 struct bnxt_vnic_info *vnic)
1436 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1437 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1439 HWRM_PREP(req, VNIC_RSS_CFG);
1441 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1443 req.ring_grp_tbl_addr =
1444 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1445 req.hash_key_tbl_addr =
1446 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1447 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1451 HWRM_CHECK_RESULT();
1457 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1458 struct bnxt_vnic_info *vnic)
1461 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1462 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1465 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1467 req.flags = rte_cpu_to_le_32(
1468 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1470 req.enables = rte_cpu_to_le_32(
1471 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1473 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1474 size -= RTE_PKTMBUF_HEADROOM;
1476 req.jumbo_thresh = rte_cpu_to_le_16(size);
1477 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1479 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1481 HWRM_CHECK_RESULT();
1487 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1488 struct bnxt_vnic_info *vnic, bool enable)
1491 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1492 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1494 HWRM_PREP(req, VNIC_TPA_CFG);
1497 req.enables = rte_cpu_to_le_32(
1498 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1499 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1500 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1501 req.flags = rte_cpu_to_le_32(
1502 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1503 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1504 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1505 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1506 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1507 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1508 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1509 req.max_agg_segs = rte_cpu_to_le_16(5);
1511 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1512 req.min_agg_len = rte_cpu_to_le_32(512);
1515 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1517 HWRM_CHECK_RESULT();
1523 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1525 struct hwrm_func_cfg_input req = {0};
1526 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1529 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1530 req.enables = rte_cpu_to_le_32(
1531 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1532 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1533 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1535 HWRM_PREP(req, FUNC_CFG);
1537 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1538 HWRM_CHECK_RESULT();
1541 bp->pf.vf_info[vf].random_mac = false;
1546 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1550 struct hwrm_func_qstats_input req = {.req_type = 0};
1551 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1553 HWRM_PREP(req, FUNC_QSTATS);
1555 req.fid = rte_cpu_to_le_16(fid);
1557 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1559 HWRM_CHECK_RESULT();
1562 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1569 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1570 struct rte_eth_stats *stats)
1573 struct hwrm_func_qstats_input req = {.req_type = 0};
1574 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1576 HWRM_PREP(req, FUNC_QSTATS);
1578 req.fid = rte_cpu_to_le_16(fid);
1580 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1582 HWRM_CHECK_RESULT();
1584 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1585 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1586 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1587 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1588 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1589 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1591 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1592 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1593 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1594 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1595 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1596 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1598 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1599 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1601 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1608 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1611 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1612 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1614 HWRM_PREP(req, FUNC_CLR_STATS);
1616 req.fid = rte_cpu_to_le_16(fid);
1618 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1620 HWRM_CHECK_RESULT();
1627 * HWRM utility functions
1630 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1635 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1636 struct bnxt_tx_queue *txq;
1637 struct bnxt_rx_queue *rxq;
1638 struct bnxt_cp_ring_info *cpr;
1640 if (i >= bp->rx_cp_nr_rings) {
1641 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1644 rxq = bp->rx_queues[i];
1648 rc = bnxt_hwrm_stat_clear(bp, cpr);
1655 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1659 struct bnxt_cp_ring_info *cpr;
1661 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1663 if (i >= bp->rx_cp_nr_rings) {
1664 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1666 cpr = bp->rx_queues[i]->cp_ring;
1667 bp->grp_info[i].fw_stats_ctx = -1;
1669 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1670 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1671 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1679 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1684 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1685 struct bnxt_tx_queue *txq;
1686 struct bnxt_rx_queue *rxq;
1687 struct bnxt_cp_ring_info *cpr;
1689 if (i >= bp->rx_cp_nr_rings) {
1690 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1693 rxq = bp->rx_queues[i];
1697 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1705 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1710 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1712 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1715 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1723 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1724 unsigned int idx __rte_unused)
1726 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1728 bnxt_hwrm_ring_free(bp, cp_ring,
1729 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1730 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1731 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1732 sizeof(*cpr->cp_desc_ring));
1733 cpr->cp_raw_cons = 0;
1736 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1741 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1742 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1743 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1744 struct bnxt_ring *ring = txr->tx_ring_struct;
1745 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1746 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1748 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1749 bnxt_hwrm_ring_free(bp, ring,
1750 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1751 ring->fw_ring_id = INVALID_HW_RING_ID;
1752 memset(txr->tx_desc_ring, 0,
1753 txr->tx_ring_struct->ring_size *
1754 sizeof(*txr->tx_desc_ring));
1755 memset(txr->tx_buf_ring, 0,
1756 txr->tx_ring_struct->ring_size *
1757 sizeof(*txr->tx_buf_ring));
1761 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1762 bnxt_free_cp_ring(bp, cpr, idx);
1763 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1767 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1768 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1769 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1770 struct bnxt_ring *ring = rxr->rx_ring_struct;
1771 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1772 unsigned int idx = i + 1;
1774 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1775 bnxt_hwrm_ring_free(bp, ring,
1776 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1777 ring->fw_ring_id = INVALID_HW_RING_ID;
1778 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1779 memset(rxr->rx_desc_ring, 0,
1780 rxr->rx_ring_struct->ring_size *
1781 sizeof(*rxr->rx_desc_ring));
1782 memset(rxr->rx_buf_ring, 0,
1783 rxr->rx_ring_struct->ring_size *
1784 sizeof(*rxr->rx_buf_ring));
1786 memset(rxr->ag_buf_ring, 0,
1787 rxr->ag_ring_struct->ring_size *
1788 sizeof(*rxr->ag_buf_ring));
1791 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1792 bnxt_free_cp_ring(bp, cpr, idx);
1793 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1794 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1798 /* Default completion ring */
1800 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1802 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1803 bnxt_free_cp_ring(bp, cpr, 0);
1804 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1811 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1816 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1817 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1824 void bnxt_free_hwrm_resources(struct bnxt *bp)
1826 /* Release memzone */
1827 rte_free(bp->hwrm_cmd_resp_addr);
1828 rte_free(bp->hwrm_short_cmd_req_addr);
1829 bp->hwrm_cmd_resp_addr = NULL;
1830 bp->hwrm_short_cmd_req_addr = NULL;
1831 bp->hwrm_cmd_resp_dma_addr = 0;
1832 bp->hwrm_short_cmd_req_dma_addr = 0;
1835 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1837 struct rte_pci_device *pdev = bp->pdev;
1838 char type[RTE_MEMZONE_NAMESIZE];
1840 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1841 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1842 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1843 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1844 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1845 if (bp->hwrm_cmd_resp_addr == NULL)
1847 bp->hwrm_cmd_resp_dma_addr =
1848 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1849 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1851 "unable to map response address to physical memory\n");
1854 rte_spinlock_init(&bp->hwrm_lock);
1859 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1861 struct bnxt_filter_info *filter;
1864 STAILQ_FOREACH(filter, &vnic->filter, next) {
1865 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1866 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1867 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1868 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1870 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1878 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1880 struct bnxt_filter_info *filter;
1881 struct rte_flow *flow;
1884 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1885 filter = flow->filter;
1886 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1887 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1888 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1889 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1890 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1892 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1894 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1902 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1904 struct bnxt_filter_info *filter;
1907 STAILQ_FOREACH(filter, &vnic->filter, next) {
1908 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1909 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1911 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1912 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1915 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1923 void bnxt_free_tunnel_ports(struct bnxt *bp)
1925 if (bp->vxlan_port_cnt)
1926 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1927 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1929 if (bp->geneve_port_cnt)
1930 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1931 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1932 bp->geneve_port = 0;
1935 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1939 if (bp->vnic_info == NULL)
1943 * Cleanup VNICs in reverse order, to make sure the L2 filter
1944 * from vnic0 is last to be cleaned up.
1946 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1947 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1949 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1951 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1953 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1955 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1957 bnxt_hwrm_vnic_free(bp, vnic);
1959 /* Ring resources */
1960 bnxt_free_all_hwrm_rings(bp);
1961 bnxt_free_all_hwrm_ring_grps(bp);
1962 bnxt_free_all_hwrm_stat_ctxs(bp);
1963 bnxt_free_tunnel_ports(bp);
1966 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1968 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1970 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1971 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1973 switch (conf_link_speed) {
1974 case ETH_LINK_SPEED_10M_HD:
1975 case ETH_LINK_SPEED_100M_HD:
1976 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1978 return hw_link_duplex;
1981 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1983 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1986 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1988 uint16_t eth_link_speed = 0;
1990 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1991 return ETH_LINK_SPEED_AUTONEG;
1993 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1994 case ETH_LINK_SPEED_100M:
1995 case ETH_LINK_SPEED_100M_HD:
1997 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1999 case ETH_LINK_SPEED_1G:
2001 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2003 case ETH_LINK_SPEED_2_5G:
2005 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2007 case ETH_LINK_SPEED_10G:
2009 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2011 case ETH_LINK_SPEED_20G:
2013 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2015 case ETH_LINK_SPEED_25G:
2017 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2019 case ETH_LINK_SPEED_40G:
2021 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2023 case ETH_LINK_SPEED_50G:
2025 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2029 "Unsupported link speed %d; default to AUTO\n",
2033 return eth_link_speed;
2036 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2037 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2038 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2039 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
2041 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2045 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2048 if (link_speed & ETH_LINK_SPEED_FIXED) {
2049 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2051 if (one_speed & (one_speed - 1)) {
2053 "Invalid advertised speeds (%u) for port %u\n",
2054 link_speed, port_id);
2057 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2059 "Unsupported advertised speed (%u) for port %u\n",
2060 link_speed, port_id);
2064 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2066 "Unsupported advertised speeds (%u) for port %u\n",
2067 link_speed, port_id);
2075 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2079 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2080 if (bp->link_info.support_speeds)
2081 return bp->link_info.support_speeds;
2082 link_speed = BNXT_SUPPORTED_SPEEDS;
2085 if (link_speed & ETH_LINK_SPEED_100M)
2086 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2087 if (link_speed & ETH_LINK_SPEED_100M_HD)
2088 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2089 if (link_speed & ETH_LINK_SPEED_1G)
2090 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2091 if (link_speed & ETH_LINK_SPEED_2_5G)
2092 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2093 if (link_speed & ETH_LINK_SPEED_10G)
2094 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2095 if (link_speed & ETH_LINK_SPEED_20G)
2096 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2097 if (link_speed & ETH_LINK_SPEED_25G)
2098 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2099 if (link_speed & ETH_LINK_SPEED_40G)
2100 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2101 if (link_speed & ETH_LINK_SPEED_50G)
2102 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2106 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2108 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2110 switch (hw_link_speed) {
2111 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2112 eth_link_speed = ETH_SPEED_NUM_100M;
2114 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2115 eth_link_speed = ETH_SPEED_NUM_1G;
2117 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2118 eth_link_speed = ETH_SPEED_NUM_2_5G;
2120 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2121 eth_link_speed = ETH_SPEED_NUM_10G;
2123 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2124 eth_link_speed = ETH_SPEED_NUM_20G;
2126 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2127 eth_link_speed = ETH_SPEED_NUM_25G;
2129 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2130 eth_link_speed = ETH_SPEED_NUM_40G;
2132 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2133 eth_link_speed = ETH_SPEED_NUM_50G;
2135 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2137 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2141 return eth_link_speed;
2144 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2146 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2148 switch (hw_link_duplex) {
2149 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2150 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2151 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2153 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2154 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2157 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2161 return eth_link_duplex;
2164 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2167 struct bnxt_link_info *link_info = &bp->link_info;
2169 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2172 "Get link config failed with rc %d\n", rc);
2175 if (link_info->link_speed)
2177 bnxt_parse_hw_link_speed(link_info->link_speed);
2179 link->link_speed = ETH_SPEED_NUM_NONE;
2180 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2181 link->link_status = link_info->link_up;
2182 link->link_autoneg = link_info->auto_mode ==
2183 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2184 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2189 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2192 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2193 struct bnxt_link_info link_req;
2194 uint16_t speed, autoneg;
2196 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2199 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2200 bp->eth_dev->data->port_id);
2204 memset(&link_req, 0, sizeof(link_req));
2205 link_req.link_up = link_up;
2209 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2210 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2211 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2213 link_req.phy_flags |=
2214 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2215 link_req.auto_link_speed_mask =
2216 bnxt_parse_eth_link_speed_mask(bp,
2217 dev_conf->link_speeds);
2219 if (bp->link_info.phy_type ==
2220 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2221 bp->link_info.phy_type ==
2222 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2223 bp->link_info.media_type ==
2224 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2225 RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
2229 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2230 link_req.link_speed = speed;
2232 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2233 link_req.auto_pause = bp->link_info.auto_pause;
2234 link_req.force_pause = bp->link_info.force_pause;
2237 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2240 "Set link config failed with rc %d\n", rc);
2248 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2250 struct hwrm_func_qcfg_input req = {0};
2251 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2255 HWRM_PREP(req, FUNC_QCFG);
2256 req.fid = rte_cpu_to_le_16(0xffff);
2258 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2260 HWRM_CHECK_RESULT();
2262 /* Hard Coded.. 0xfff VLAN ID mask */
2263 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2264 flags = rte_le_to_cpu_16(resp->flags);
2265 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2266 bp->flags |= BNXT_FLAG_MULTI_HOST;
2268 switch (resp->port_partition_type) {
2269 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2270 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2271 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2272 bp->port_partition_type = resp->port_partition_type;
2275 bp->port_partition_type = 0;
2284 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2285 struct hwrm_func_qcaps_output *qcaps)
2287 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2288 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2289 sizeof(qcaps->mac_address));
2290 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2291 qcaps->max_rx_rings = fcfg->num_rx_rings;
2292 qcaps->max_tx_rings = fcfg->num_tx_rings;
2293 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2294 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2296 qcaps->first_vf_id = 0;
2297 qcaps->max_vnics = fcfg->num_vnics;
2298 qcaps->max_decap_records = 0;
2299 qcaps->max_encap_records = 0;
2300 qcaps->max_tx_wm_flows = 0;
2301 qcaps->max_tx_em_flows = 0;
2302 qcaps->max_rx_wm_flows = 0;
2303 qcaps->max_rx_em_flows = 0;
2304 qcaps->max_flow_id = 0;
2305 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2306 qcaps->max_sp_tx_rings = 0;
2307 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2310 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2312 struct hwrm_func_cfg_input req = {0};
2313 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2316 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2317 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2318 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2319 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2320 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2321 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2322 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2323 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2324 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2325 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2326 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2327 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2328 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2329 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2330 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2331 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2332 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2333 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2334 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2335 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2336 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2337 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2338 req.fid = rte_cpu_to_le_16(0xffff);
2340 HWRM_PREP(req, FUNC_CFG);
2342 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2344 HWRM_CHECK_RESULT();
2350 static void populate_vf_func_cfg_req(struct bnxt *bp,
2351 struct hwrm_func_cfg_input *req,
2354 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2355 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2356 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2357 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2358 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2359 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2360 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2361 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2362 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2363 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2365 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2366 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2367 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2368 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2369 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2371 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2372 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2374 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2375 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2376 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2377 /* TODO: For now, do not support VMDq/RFS on VFs. */
2378 req->num_vnics = rte_cpu_to_le_16(1);
2379 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2383 static void add_random_mac_if_needed(struct bnxt *bp,
2384 struct hwrm_func_cfg_input *cfg_req,
2387 struct ether_addr mac;
2389 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2392 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2394 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2395 eth_random_addr(cfg_req->dflt_mac_addr);
2396 bp->pf.vf_info[vf].random_mac = true;
2398 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2402 static void reserve_resources_from_vf(struct bnxt *bp,
2403 struct hwrm_func_cfg_input *cfg_req,
2406 struct hwrm_func_qcaps_input req = {0};
2407 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2410 /* Get the actual allocated values now */
2411 HWRM_PREP(req, FUNC_QCAPS);
2412 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2413 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2416 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2417 copy_func_cfg_to_qcaps(cfg_req, resp);
2418 } else if (resp->error_code) {
2419 rc = rte_le_to_cpu_16(resp->error_code);
2420 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2421 copy_func_cfg_to_qcaps(cfg_req, resp);
2424 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2425 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2426 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2427 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2428 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2429 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2431 * TODO: While not supporting VMDq with VFs, max_vnics is always
2432 * forced to 1 in this case
2434 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2435 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2440 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2442 struct hwrm_func_qcfg_input req = {0};
2443 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2446 /* Check for zero MAC address */
2447 HWRM_PREP(req, FUNC_QCFG);
2448 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2451 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2453 } else if (resp->error_code) {
2454 rc = rte_le_to_cpu_16(resp->error_code);
2455 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2458 rc = rte_le_to_cpu_16(resp->vlan);
2465 static int update_pf_resource_max(struct bnxt *bp)
2467 struct hwrm_func_qcfg_input req = {0};
2468 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2471 /* And copy the allocated numbers into the pf struct */
2472 HWRM_PREP(req, FUNC_QCFG);
2473 req.fid = rte_cpu_to_le_16(0xffff);
2474 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2475 HWRM_CHECK_RESULT();
2477 /* Only TX ring value reflects actual allocation? TODO */
2478 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2479 bp->pf.evb_mode = resp->evb_mode;
2486 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2491 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2495 rc = bnxt_hwrm_func_qcaps(bp);
2499 bp->pf.func_cfg_flags &=
2500 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2501 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2502 bp->pf.func_cfg_flags |=
2503 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2504 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2508 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2510 struct hwrm_func_cfg_input req = {0};
2511 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2518 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2522 rc = bnxt_hwrm_func_qcaps(bp);
2527 bp->pf.active_vfs = num_vfs;
2530 * First, configure the PF to only use one TX ring. This ensures that
2531 * there are enough rings for all VFs.
2533 * If we don't do this, when we call func_alloc() later, we will lock
2534 * extra rings to the PF that won't be available during func_cfg() of
2537 * This has been fixed with firmware versions above 20.6.54
2539 bp->pf.func_cfg_flags &=
2540 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2541 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2542 bp->pf.func_cfg_flags |=
2543 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2544 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2549 * Now, create and register a buffer to hold forwarded VF requests
2551 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2552 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2553 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2554 if (bp->pf.vf_req_buf == NULL) {
2558 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2559 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2560 for (i = 0; i < num_vfs; i++)
2561 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2562 (i * HWRM_MAX_REQ_LEN);
2564 rc = bnxt_hwrm_func_buf_rgtr(bp);
2568 populate_vf_func_cfg_req(bp, &req, num_vfs);
2570 bp->pf.active_vfs = 0;
2571 for (i = 0; i < num_vfs; i++) {
2572 add_random_mac_if_needed(bp, &req, i);
2574 HWRM_PREP(req, FUNC_CFG);
2575 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2576 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2577 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2579 /* Clear enable flag for next pass */
2580 req.enables &= ~rte_cpu_to_le_32(
2581 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2583 if (rc || resp->error_code) {
2585 "Failed to initizlie VF %d\n", i);
2587 "Not all VFs available. (%d, %d)\n",
2588 rc, resp->error_code);
2595 reserve_resources_from_vf(bp, &req, i);
2596 bp->pf.active_vfs++;
2597 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2601 * Now configure the PF to use "the rest" of the resources
2602 * We're using STD_TX_RING_MODE here though which will limit the TX
2603 * rings. This will allow QoS to function properly. Not setting this
2604 * will cause PF rings to break bandwidth settings.
2606 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2610 rc = update_pf_resource_max(bp);
2617 bnxt_hwrm_func_buf_unrgtr(bp);
2621 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2623 struct hwrm_func_cfg_input req = {0};
2624 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2627 HWRM_PREP(req, FUNC_CFG);
2629 req.fid = rte_cpu_to_le_16(0xffff);
2630 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2631 req.evb_mode = bp->pf.evb_mode;
2633 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2634 HWRM_CHECK_RESULT();
2640 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2641 uint8_t tunnel_type)
2643 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2644 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2647 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2648 req.tunnel_type = tunnel_type;
2649 req.tunnel_dst_port_val = port;
2650 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2651 HWRM_CHECK_RESULT();
2653 switch (tunnel_type) {
2654 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2655 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2656 bp->vxlan_port = port;
2658 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2659 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2660 bp->geneve_port = port;
2671 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2672 uint8_t tunnel_type)
2674 struct hwrm_tunnel_dst_port_free_input req = {0};
2675 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2678 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2680 req.tunnel_type = tunnel_type;
2681 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2682 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2684 HWRM_CHECK_RESULT();
2690 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2693 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2694 struct hwrm_func_cfg_input req = {0};
2697 HWRM_PREP(req, FUNC_CFG);
2699 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2700 req.flags = rte_cpu_to_le_32(flags);
2701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2703 HWRM_CHECK_RESULT();
2709 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2711 uint32_t *flag = flagp;
2713 vnic->flags = *flag;
2716 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2718 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2721 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2724 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2725 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2727 HWRM_PREP(req, FUNC_BUF_RGTR);
2729 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2730 req.req_buf_page_size = rte_cpu_to_le_16(
2731 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2732 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2733 req.req_buf_page_addr[0] =
2734 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2735 if (req.req_buf_page_addr[0] == 0) {
2737 "unable to map buffer address to physical memory\n");
2741 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2743 HWRM_CHECK_RESULT();
2749 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2752 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2753 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2755 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2757 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2759 HWRM_CHECK_RESULT();
2765 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2767 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2768 struct hwrm_func_cfg_input req = {0};
2771 HWRM_PREP(req, FUNC_CFG);
2773 req.fid = rte_cpu_to_le_16(0xffff);
2774 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2775 req.enables = rte_cpu_to_le_32(
2776 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2777 req.async_event_cr = rte_cpu_to_le_16(
2778 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2779 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2781 HWRM_CHECK_RESULT();
2787 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2789 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2790 struct hwrm_func_vf_cfg_input req = {0};
2793 HWRM_PREP(req, FUNC_VF_CFG);
2795 req.enables = rte_cpu_to_le_32(
2796 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2797 req.async_event_cr = rte_cpu_to_le_16(
2798 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2799 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2801 HWRM_CHECK_RESULT();
2807 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2809 struct hwrm_func_cfg_input req = {0};
2810 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2811 uint16_t dflt_vlan, fid;
2812 uint32_t func_cfg_flags;
2815 HWRM_PREP(req, FUNC_CFG);
2818 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2819 fid = bp->pf.vf_info[vf].fid;
2820 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2822 fid = rte_cpu_to_le_16(0xffff);
2823 func_cfg_flags = bp->pf.func_cfg_flags;
2824 dflt_vlan = bp->vlan;
2827 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2828 req.fid = rte_cpu_to_le_16(fid);
2829 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2830 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2832 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2834 HWRM_CHECK_RESULT();
2840 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2841 uint16_t max_bw, uint16_t enables)
2843 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2844 struct hwrm_func_cfg_input req = {0};
2847 HWRM_PREP(req, FUNC_CFG);
2849 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2850 req.enables |= rte_cpu_to_le_32(enables);
2851 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2852 req.max_bw = rte_cpu_to_le_32(max_bw);
2853 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2855 HWRM_CHECK_RESULT();
2861 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2863 struct hwrm_func_cfg_input req = {0};
2864 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2867 HWRM_PREP(req, FUNC_CFG);
2869 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2870 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2871 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2872 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2874 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2876 HWRM_CHECK_RESULT();
2882 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2883 void *encaped, size_t ec_size)
2886 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2887 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2889 if (ec_size > sizeof(req.encap_request))
2892 HWRM_PREP(req, REJECT_FWD_RESP);
2894 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2895 memcpy(req.encap_request, encaped, ec_size);
2897 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2899 HWRM_CHECK_RESULT();
2905 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2906 struct ether_addr *mac)
2908 struct hwrm_func_qcfg_input req = {0};
2909 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2912 HWRM_PREP(req, FUNC_QCFG);
2914 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2915 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2917 HWRM_CHECK_RESULT();
2919 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2926 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2927 void *encaped, size_t ec_size)
2930 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2931 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2933 if (ec_size > sizeof(req.encap_request))
2936 HWRM_PREP(req, EXEC_FWD_RESP);
2938 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2939 memcpy(req.encap_request, encaped, ec_size);
2941 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2943 HWRM_CHECK_RESULT();
2949 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2950 struct rte_eth_stats *stats, uint8_t rx)
2953 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2954 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2956 HWRM_PREP(req, STAT_CTX_QUERY);
2958 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2962 HWRM_CHECK_RESULT();
2965 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2966 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2967 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2968 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2969 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2970 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2971 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2972 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2974 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2975 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2976 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2977 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2978 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2979 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2980 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2989 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2991 struct hwrm_port_qstats_input req = {0};
2992 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2993 struct bnxt_pf_info *pf = &bp->pf;
2996 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2999 HWRM_PREP(req, PORT_QSTATS);
3001 req.port_id = rte_cpu_to_le_16(pf->port_id);
3002 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3003 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3004 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3006 HWRM_CHECK_RESULT();
3012 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3014 struct hwrm_port_clr_stats_input req = {0};
3015 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3016 struct bnxt_pf_info *pf = &bp->pf;
3019 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3022 HWRM_PREP(req, PORT_CLR_STATS);
3024 req.port_id = rte_cpu_to_le_16(pf->port_id);
3025 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3027 HWRM_CHECK_RESULT();
3033 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3035 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3036 struct hwrm_port_led_qcaps_input req = {0};
3042 HWRM_PREP(req, PORT_LED_QCAPS);
3043 req.port_id = bp->pf.port_id;
3044 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3046 HWRM_CHECK_RESULT();
3048 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3051 bp->num_leds = resp->num_leds;
3052 memcpy(bp->leds, &resp->led0_id,
3053 sizeof(bp->leds[0]) * bp->num_leds);
3054 for (i = 0; i < bp->num_leds; i++) {
3055 struct bnxt_led_info *led = &bp->leds[i];
3057 uint16_t caps = led->led_state_caps;
3059 if (!led->led_group_id ||
3060 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3072 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3074 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3075 struct hwrm_port_led_cfg_input req = {0};
3076 struct bnxt_led_cfg *led_cfg;
3077 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3078 uint16_t duration = 0;
3081 if (!bp->num_leds || BNXT_VF(bp))
3084 HWRM_PREP(req, PORT_LED_CFG);
3087 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3088 duration = rte_cpu_to_le_16(500);
3090 req.port_id = bp->pf.port_id;
3091 req.num_leds = bp->num_leds;
3092 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3093 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3094 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3095 led_cfg->led_id = bp->leds[i].led_id;
3096 led_cfg->led_state = led_state;
3097 led_cfg->led_blink_on = duration;
3098 led_cfg->led_blink_off = duration;
3099 led_cfg->led_group_id = bp->leds[i].led_group_id;
3102 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3104 HWRM_CHECK_RESULT();
3110 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3114 struct hwrm_nvm_get_dir_info_input req = {0};
3115 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3117 HWRM_PREP(req, NVM_GET_DIR_INFO);
3119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3121 HWRM_CHECK_RESULT();
3125 *entries = rte_le_to_cpu_32(resp->entries);
3126 *length = rte_le_to_cpu_32(resp->entry_length);
3131 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3134 uint32_t dir_entries;
3135 uint32_t entry_length;
3138 rte_iova_t dma_handle;
3139 struct hwrm_nvm_get_dir_entries_input req = {0};
3140 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3142 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3146 *data++ = dir_entries;
3147 *data++ = entry_length;
3149 memset(data, 0xff, len);
3151 buflen = dir_entries * entry_length;
3152 buf = rte_malloc("nvm_dir", buflen, 0);
3153 rte_mem_lock_page(buf);
3156 dma_handle = rte_mem_virt2iova(buf);
3157 if (dma_handle == 0) {
3159 "unable to map response address to physical memory\n");
3162 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3163 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3164 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3166 HWRM_CHECK_RESULT();
3170 memcpy(data, buf, len > buflen ? buflen : len);
3177 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3178 uint32_t offset, uint32_t length,
3183 rte_iova_t dma_handle;
3184 struct hwrm_nvm_read_input req = {0};
3185 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3187 buf = rte_malloc("nvm_item", length, 0);
3188 rte_mem_lock_page(buf);
3192 dma_handle = rte_mem_virt2iova(buf);
3193 if (dma_handle == 0) {
3195 "unable to map response address to physical memory\n");
3198 HWRM_PREP(req, NVM_READ);
3199 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3200 req.dir_idx = rte_cpu_to_le_16(index);
3201 req.offset = rte_cpu_to_le_32(offset);
3202 req.len = rte_cpu_to_le_32(length);
3203 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3204 HWRM_CHECK_RESULT();
3207 memcpy(data, buf, length);
3213 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3216 struct hwrm_nvm_erase_dir_entry_input req = {0};
3217 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3219 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3220 req.dir_idx = rte_cpu_to_le_16(index);
3221 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3222 HWRM_CHECK_RESULT();
3229 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3230 uint16_t dir_ordinal, uint16_t dir_ext,
3231 uint16_t dir_attr, const uint8_t *data,
3235 struct hwrm_nvm_write_input req = {0};
3236 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3237 rte_iova_t dma_handle;
3240 HWRM_PREP(req, NVM_WRITE);
3242 req.dir_type = rte_cpu_to_le_16(dir_type);
3243 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3244 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3245 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3246 req.dir_data_length = rte_cpu_to_le_32(data_len);
3248 buf = rte_malloc("nvm_write", data_len, 0);
3249 rte_mem_lock_page(buf);
3253 dma_handle = rte_mem_virt2iova(buf);
3254 if (dma_handle == 0) {
3256 "unable to map response address to physical memory\n");
3259 memcpy(buf, data, data_len);
3260 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3262 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3264 HWRM_CHECK_RESULT();
3272 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3274 uint32_t *count = cbdata;
3276 *count = *count + 1;
3279 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3280 struct bnxt_vnic_info *vnic __rte_unused)
3285 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3289 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3290 &count, bnxt_vnic_count_hwrm_stub);
3295 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3298 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3299 struct hwrm_func_vf_vnic_ids_query_output *resp =
3300 bp->hwrm_cmd_resp_addr;
3303 /* First query all VNIC ids */
3304 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3306 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3307 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3308 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3310 if (req.vnic_id_tbl_addr == 0) {
3313 "unable to map VNIC ID table address to physical memory\n");
3316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3319 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3321 } else if (resp->error_code) {
3322 rc = rte_le_to_cpu_16(resp->error_code);
3324 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3327 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3335 * This function queries the VNIC IDs for a specified VF. It then calls
3336 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3337 * Then it calls the hwrm_cb function to program this new vnic configuration.
3339 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3340 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3341 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3343 struct bnxt_vnic_info vnic;
3345 int i, num_vnic_ids;
3350 /* First query all VNIC ids */
3351 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3352 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3353 RTE_CACHE_LINE_SIZE);
3354 if (vnic_ids == NULL) {
3358 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3359 rte_mem_lock_page(((char *)vnic_ids) + sz);
3361 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3363 if (num_vnic_ids < 0)
3364 return num_vnic_ids;
3366 /* Retrieve VNIC, update bd_stall then update */
3368 for (i = 0; i < num_vnic_ids; i++) {
3369 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3370 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3371 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3374 if (vnic.mru <= 4) /* Indicates unallocated */
3377 vnic_cb(&vnic, cbdata);
3379 rc = hwrm_cb(bp, &vnic);
3389 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3392 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3393 struct hwrm_func_cfg_input req = {0};
3396 HWRM_PREP(req, FUNC_CFG);
3398 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3399 req.enables |= rte_cpu_to_le_32(
3400 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3401 req.vlan_antispoof_mode = on ?
3402 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3403 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3404 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3406 HWRM_CHECK_RESULT();
3412 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3414 struct bnxt_vnic_info vnic;
3417 int num_vnic_ids, i;
3421 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3422 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3423 RTE_CACHE_LINE_SIZE);
3424 if (vnic_ids == NULL) {
3429 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3430 rte_mem_lock_page(((char *)vnic_ids) + sz);
3432 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3438 * Loop through to find the default VNIC ID.
3439 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3440 * by sending the hwrm_func_qcfg command to the firmware.
3442 for (i = 0; i < num_vnic_ids; i++) {
3443 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3444 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3445 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3446 bp->pf.first_vf_id + vf);
3449 if (vnic.func_default) {
3451 return vnic.fw_vnic_id;
3454 /* Could not find a default VNIC. */
3455 RTE_LOG(ERR, PMD, "No default VNIC\n");
3461 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3463 struct bnxt_filter_info *filter)
3466 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3467 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3468 uint32_t enables = 0;
3470 if (filter->fw_em_filter_id != UINT64_MAX)
3471 bnxt_hwrm_clear_em_filter(bp, filter);
3473 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3475 req.flags = rte_cpu_to_le_32(filter->flags);
3477 enables = filter->enables |
3478 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3479 req.dst_id = rte_cpu_to_le_16(dst_id);
3481 if (filter->ip_addr_type) {
3482 req.ip_addr_type = filter->ip_addr_type;
3483 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3486 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3487 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3489 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3490 memcpy(req.src_macaddr, filter->src_macaddr,
3493 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3494 memcpy(req.dst_macaddr, filter->dst_macaddr,
3497 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3498 req.ovlan_vid = filter->l2_ovlan;
3500 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3501 req.ivlan_vid = filter->l2_ivlan;
3503 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3504 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3506 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3507 req.ip_protocol = filter->ip_protocol;
3509 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3510 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3512 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3513 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3515 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3516 req.src_port = rte_cpu_to_be_16(filter->src_port);
3518 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3519 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3521 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3522 req.mirror_vnic_id = filter->mirror_vnic_id;
3524 req.enables = rte_cpu_to_le_32(enables);
3526 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3528 HWRM_CHECK_RESULT();
3530 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3536 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3539 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3540 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3542 if (filter->fw_em_filter_id == UINT64_MAX)
3545 RTE_LOG(ERR, PMD, "Clear EM filter\n");
3546 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3548 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3550 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3552 HWRM_CHECK_RESULT();
3555 filter->fw_em_filter_id = -1;
3556 filter->fw_l2_filter_id = -1;
3561 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3563 struct bnxt_filter_info *filter)
3566 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3567 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3568 bp->hwrm_cmd_resp_addr;
3569 uint32_t enables = 0;
3571 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3572 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3574 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3576 req.flags = rte_cpu_to_le_32(filter->flags);
3578 enables = filter->enables |
3579 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3580 req.dst_id = rte_cpu_to_le_16(dst_id);
3583 if (filter->ip_addr_type) {
3584 req.ip_addr_type = filter->ip_addr_type;
3586 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3589 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3590 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3592 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3593 memcpy(req.src_macaddr, filter->src_macaddr,
3596 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3597 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3600 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3601 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3603 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3604 req.ip_protocol = filter->ip_protocol;
3606 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3607 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3609 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3610 req.src_ipaddr_mask[0] =
3611 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3613 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3614 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3616 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3617 req.dst_ipaddr_mask[0] =
3618 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3620 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3621 req.src_port = rte_cpu_to_le_16(filter->src_port);
3623 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3624 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3626 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3627 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3629 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3630 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3632 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3633 req.mirror_vnic_id = filter->mirror_vnic_id;
3635 req.enables = rte_cpu_to_le_32(enables);
3637 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3639 HWRM_CHECK_RESULT();
3641 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3647 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3648 struct bnxt_filter_info *filter)
3651 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3652 struct hwrm_cfa_ntuple_filter_free_output *resp =
3653 bp->hwrm_cmd_resp_addr;
3655 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3658 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3660 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3662 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3664 HWRM_CHECK_RESULT();
3667 filter->fw_ntuple_filter_id = -1;
3668 filter->fw_l2_filter_id = -1;