1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
31 struct bnxt_plcmodes_cfg {
33 uint16_t jumbo_thresh;
35 uint16_t hds_threshold;
38 static int page_getenum(size_t size)
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
58 static int page_roundup(size_t size)
60 return 1 << page_getenum(size);
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
67 if (rmem->nr_pages > 1) {
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
103 timeout = bp->hwrm_cmd_timeout;
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
184 * HWRM_UNLOCK() must be called after all response processing is completed.
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
201 #define HWRM_CHECK_RESULT_SILENT() do {\
203 rte_spinlock_unlock(&bp->hwrm_lock); \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
213 #define HWRM_CHECK_RESULT() do {\
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
240 tmp_hwrm_err_op->opaque_0), \
242 tmp_hwrm_err_op->opaque_1)); \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
279 mailbox = BNXT_USE_KONG(bp);
281 HWRM_PREP(req, msg_type, mailbox);
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
288 memcpy(resp_msg, resp, resp_len);
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
299 uint32_t *tf_response_code,
303 uint32_t response_len)
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
310 if (msg_len > sizeof(req.tf_req))
314 mailbox = BNXT_USE_KONG(bp);
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
335 if (response_len != 0) {
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
369 struct bnxt_vlan_table_entry *vlan_table)
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
404 req.mask = rte_cpu_to_le_32(mask);
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
428 * This command is also present from 1.7.8.11 and higher,
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
462 if (filter->fw_l2_filter_id == UINT64_MAX)
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
471 if (l2_filter->l2_ref_cnt == 0)
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
477 if (l2_filter->l2_ref_cnt > 0)
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
504 struct bnxt_filter_info *filter)
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
533 req.flags = rte_cpu_to_le_32(filter->flags);
535 enables = filter->enables |
536 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
537 req.dst_id = rte_cpu_to_le_16(dst_id);
540 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
541 memcpy(req.l2_addr, filter->l2_addr,
544 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
545 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
548 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
549 req.l2_ovlan = filter->l2_ovlan;
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
552 req.l2_ivlan = filter->l2_ivlan;
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
555 req.l2_ovlan_mask = filter->l2_ovlan_mask;
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
558 req.l2_ivlan_mask = filter->l2_ivlan_mask;
559 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
560 req.src_id = rte_cpu_to_le_32(filter->src_id);
561 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
562 req.src_type = filter->src_type;
563 if (filter->pri_hint) {
564 req.pri_hint = filter->pri_hint;
565 req.l2_filter_id_hint =
566 rte_cpu_to_le_64(filter->l2_filter_id_hint);
569 req.enables = rte_cpu_to_le_32(enables);
571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
575 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
576 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
579 filter->l2_ref_cnt++;
584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
586 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
587 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
594 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
597 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
600 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
601 if (ptp->tx_tstamp_en)
602 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
605 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
606 req.flags = rte_cpu_to_le_32(flags);
607 req.enables = rte_cpu_to_le_32
608 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
609 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
620 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
621 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
622 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
627 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
629 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
635 if (!BNXT_CHIP_THOR(bp) &&
636 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
639 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
640 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
642 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
646 if (!BNXT_CHIP_THOR(bp)) {
647 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
648 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
649 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
650 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
651 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
652 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
653 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
654 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
655 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
656 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
657 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
658 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
659 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
660 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
661 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
662 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
663 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
664 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
676 struct hwrm_func_qcaps_input req = {.req_type = 0 };
677 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
678 uint16_t new_max_vfs;
682 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
684 req.fid = rte_cpu_to_le_16(0xffff);
686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
690 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
691 flags = rte_le_to_cpu_32(resp->flags);
693 bp->pf->port_id = resp->port_id;
694 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
695 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
696 new_max_vfs = bp->pdev->max_vfs;
697 if (new_max_vfs != bp->pf->max_vfs) {
699 rte_free(bp->pf->vf_info);
700 bp->pf->vf_info = rte_malloc("bnxt_vf_info",
701 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
702 bp->pf->max_vfs = new_max_vfs;
703 for (i = 0; i < new_max_vfs; i++) {
704 bp->pf->vf_info[i].fid =
705 bp->pf->first_vf_id + i;
706 bp->pf->vf_info[i].vlan_table =
707 rte_zmalloc("VF VLAN table",
710 if (bp->pf->vf_info[i].vlan_table == NULL)
712 "Fail to alloc VLAN table for VF %d\n",
716 bp->pf->vf_info[i].vlan_table);
717 bp->pf->vf_info[i].vlan_as_table =
718 rte_zmalloc("VF VLAN AS table",
721 if (bp->pf->vf_info[i].vlan_as_table == NULL)
723 "Alloc VLAN AS table for VF %d fail\n",
727 bp->pf->vf_info[i].vlan_as_table);
728 STAILQ_INIT(&bp->pf->vf_info[i].filter);
733 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
734 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
735 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
736 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
738 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
740 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
741 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
742 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
743 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
744 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
745 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
746 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
747 if (!BNXT_CHIP_THOR(bp))
748 bp->max_l2_ctx += bp->max_rx_em_flows;
749 /* TODO: For now, do not support VMDq/RFS on VFs. */
754 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
758 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
759 bp->max_l2_ctx, bp->max_vnics);
760 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
762 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
763 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
764 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
765 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
767 bnxt_hwrm_ptp_qcfg(bp);
771 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
772 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
774 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
775 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
776 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
779 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
780 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
782 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
783 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
794 rc = __bnxt_hwrm_func_qcaps(bp);
795 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
796 rc = bnxt_alloc_ctx_mem(bp);
800 rc = bnxt_hwrm_func_resc_qcaps(bp);
802 bp->flags |= BNXT_FLAG_NEW_RM;
806 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
807 * But the error can be ignored. Return success.
813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
817 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
818 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
820 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
822 req.target_id = rte_cpu_to_le_16(0xffff);
824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
828 if (rte_le_to_cpu_32(resp->flags) &
829 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
830 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
831 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
834 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
841 int bnxt_hwrm_func_reset(struct bnxt *bp)
844 struct hwrm_func_reset_input req = {.req_type = 0 };
845 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
847 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
849 req.enables = rte_cpu_to_le_32(0);
851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
863 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
864 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
866 if (bp->flags & BNXT_FLAG_REGISTERED)
869 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
870 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
871 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
872 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
874 /* PFs and trusted VFs should indicate the support of the
875 * Master capability on non Stingray platform
877 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
878 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
880 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
881 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
882 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
883 req.ver_maj = RTE_VER_YEAR;
884 req.ver_min = RTE_VER_MONTH;
885 req.ver_upd = RTE_VER_MINOR;
888 req.enables |= rte_cpu_to_le_32(
889 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
890 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
891 RTE_MIN(sizeof(req.vf_req_fwd),
892 sizeof(bp->pf->vf_req_fwd)));
895 * PF can sniff HWRM API issued by VF. This can be set up by
896 * linux driver and inherited by the DPDK PF driver. Clear
897 * this HWRM sniffer list in FW because DPDK PF driver does
900 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
903 req.flags = rte_cpu_to_le_32(flags);
905 req.async_event_fwd[0] |=
906 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
907 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
908 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
909 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
910 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
911 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
912 req.async_event_fwd[0] |=
913 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
914 req.async_event_fwd[1] |=
915 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
916 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
918 req.async_event_fwd[1] |=
919 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
925 flags = rte_le_to_cpu_32(resp->flags);
926 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
927 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
931 bp->flags |= BNXT_FLAG_REGISTERED;
936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
938 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
941 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
949 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
950 struct hwrm_func_vf_cfg_input req = {0};
952 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
954 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
955 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
956 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
957 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
958 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
960 if (BNXT_HAS_RING_GRPS(bp)) {
961 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
962 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
965 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
966 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
967 AGG_RING_MULTIPLIER);
968 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
969 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
971 BNXT_NUM_ASYNC_CPR(bp));
972 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
973 if (bp->vf_resv_strategy ==
974 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
975 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
976 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
977 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
978 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
979 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
980 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
981 } else if (bp->vf_resv_strategy ==
982 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
983 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
984 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
988 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
989 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
990 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
991 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
992 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
993 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
995 if (test && BNXT_HAS_RING_GRPS(bp))
996 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
998 req.flags = rte_cpu_to_le_32(flags);
999 req.enables |= rte_cpu_to_le_32(enables);
1001 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1004 HWRM_CHECK_RESULT_SILENT();
1006 HWRM_CHECK_RESULT();
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1015 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016 struct hwrm_func_resource_qcaps_input req = {0};
1018 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019 req.fid = rte_cpu_to_le_16(0xffff);
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1023 HWRM_CHECK_RESULT_SILENT();
1026 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031 /* func_resource_qcaps does not return max_rx_em_flows.
1032 * So use the value provided by func_qcaps.
1034 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035 if (!BNXT_CHIP_THOR(bp))
1036 bp->max_l2_ctx += bp->max_rx_em_flows;
1037 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1040 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042 if (bp->vf_resv_strategy >
1043 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044 bp->vf_resv_strategy =
1045 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1054 struct hwrm_ver_get_input req = {.req_type = 0 };
1055 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056 uint32_t fw_version;
1057 uint16_t max_resp_len;
1058 char type[RTE_MEMZONE_NAMESIZE];
1059 uint32_t dev_caps_cfg;
1061 bp->max_req_len = HWRM_MAX_REQ_LEN;
1062 bp->hwrm_cmd_timeout = timeout;
1063 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1065 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1071 if (bp->flags & BNXT_FLAG_FW_RESET)
1072 HWRM_CHECK_RESULT_SILENT();
1074 HWRM_CHECK_RESULT();
1076 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081 (resp->hwrm_fw_min_8b << 16) |
1082 (resp->hwrm_fw_bld_8b << 8) |
1083 resp->hwrm_fw_rsvd_8b;
1084 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1087 fw_version = resp->hwrm_intf_maj_8b << 16;
1088 fw_version |= resp->hwrm_intf_min_8b << 8;
1089 fw_version |= resp->hwrm_intf_upd_8b;
1090 bp->hwrm_spec_code = fw_version;
1092 /* def_req_timeout value is in milliseconds */
1093 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094 /* convert timeout to usec */
1095 bp->hwrm_cmd_timeout *= 1000;
1096 if (!bp->hwrm_cmd_timeout)
1097 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1099 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1105 if (bp->max_req_len > resp->max_req_win_len) {
1106 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1109 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1114 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1117 if (bp->max_resp_len != max_resp_len) {
1118 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119 bp->pdev->addr.domain, bp->pdev->addr.bus,
1120 bp->pdev->addr.devid, bp->pdev->addr.function);
1122 rte_free(bp->hwrm_cmd_resp_addr);
1124 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125 if (bp->hwrm_cmd_resp_addr == NULL) {
1129 bp->hwrm_cmd_resp_dma_addr =
1130 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1133 "Unable to map response buffer to physical memory.\n");
1137 bp->max_resp_len = max_resp_len;
1141 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1143 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145 bp->flags |= BNXT_FLAG_SHORT_CMD;
1148 if (((dev_caps_cfg &
1149 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1151 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154 bp->pdev->addr.domain, bp->pdev->addr.bus,
1155 bp->pdev->addr.devid, bp->pdev->addr.function);
1157 rte_free(bp->hwrm_short_cmd_req_addr);
1159 bp->hwrm_short_cmd_req_addr =
1160 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161 if (bp->hwrm_short_cmd_req_addr == NULL) {
1165 bp->hwrm_short_cmd_req_dma_addr =
1166 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168 rte_free(bp->hwrm_short_cmd_req_addr);
1170 "Unable to map buffer to physical memory.\n");
1176 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1184 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1190 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1204 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1207 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1210 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1215 HWRM_CHECK_RESULT();
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1224 struct hwrm_port_phy_cfg_input req = {0};
1225 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226 uint32_t enables = 0;
1228 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1230 if (conf->link_up) {
1231 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232 if (bp->link_info->auto_mode && conf->link_speed) {
1233 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1237 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1241 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242 * any auto mode, even "none".
1244 if (!conf->link_speed) {
1245 /* No speeds specified. Enable AutoNeg - all speeds */
1247 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1249 /* AutoNeg - Advertise speeds specified. */
1250 if (conf->auto_link_speed_mask &&
1251 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1253 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254 req.auto_link_speed_mask =
1255 conf->auto_link_speed_mask;
1257 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1260 req.auto_duplex = conf->duplex;
1261 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262 req.auto_pause = conf->auto_pause;
1263 req.force_pause = conf->force_pause;
1264 /* Set force_pause if there is no auto or if there is a force */
1265 if (req.auto_pause && !req.force_pause)
1266 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1268 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1270 req.enables = rte_cpu_to_le_32(enables);
1273 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274 PMD_DRV_LOG(INFO, "Force Link Down\n");
1277 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1279 HWRM_CHECK_RESULT();
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286 struct bnxt_link_info *link_info)
1289 struct hwrm_port_phy_qcfg_input req = {0};
1290 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1292 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1296 HWRM_CHECK_RESULT();
1298 link_info->phy_link_status = resp->link;
1299 link_info->link_up =
1300 (link_info->phy_link_status ==
1301 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303 link_info->duplex = resp->duplex_cfg;
1304 link_info->pause = resp->pause;
1305 link_info->auto_pause = resp->auto_pause;
1306 link_info->force_pause = resp->force_pause;
1307 link_info->auto_mode = resp->auto_mode;
1308 link_info->phy_type = resp->phy_type;
1309 link_info->media_type = resp->media_type;
1311 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315 link_info->phy_ver[0] = resp->phy_maj;
1316 link_info->phy_ver[1] = resp->phy_min;
1317 link_info->phy_ver[2] = resp->phy_bld;
1321 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326 link_info->auto_link_speed_mask);
1327 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328 link_info->force_link_speed);
1333 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1337 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1338 if (bp->tx_cos_queue[i].profile ==
1339 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1340 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1347 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1351 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1352 if (bp->tx_cos_queue[i].profile !=
1353 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1354 bp->tx_cos_queue[i].id !=
1355 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1356 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1362 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1365 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1366 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1367 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1371 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1373 req.flags = rte_cpu_to_le_32(dir);
1374 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1375 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1376 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1378 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1381 HWRM_CHECK_RESULT();
1383 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1384 GET_TX_QUEUE_INFO(0);
1385 GET_TX_QUEUE_INFO(1);
1386 GET_TX_QUEUE_INFO(2);
1387 GET_TX_QUEUE_INFO(3);
1388 GET_TX_QUEUE_INFO(4);
1389 GET_TX_QUEUE_INFO(5);
1390 GET_TX_QUEUE_INFO(6);
1391 GET_TX_QUEUE_INFO(7);
1393 GET_RX_QUEUE_INFO(0);
1394 GET_RX_QUEUE_INFO(1);
1395 GET_RX_QUEUE_INFO(2);
1396 GET_RX_QUEUE_INFO(3);
1397 GET_RX_QUEUE_INFO(4);
1398 GET_RX_QUEUE_INFO(5);
1399 GET_RX_QUEUE_INFO(6);
1400 GET_RX_QUEUE_INFO(7);
1405 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1408 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1409 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1413 /* iterate and find the COSq profile to use for Tx */
1414 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1415 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1416 if (bp->tx_cos_queue[i].id != 0xff)
1417 bp->tx_cosq_id[j++] =
1418 bp->tx_cos_queue[i].id;
1421 /* When CoS classification is disabled, for normal NIC
1422 * operations, ideally we should look to use LOSSY.
1423 * If not found, fallback to the first valid profile
1425 if (!bnxt_find_lossy_profile(bp))
1426 bnxt_find_first_valid_profile(bp);
1431 bp->max_tc = resp->max_configurable_queues;
1432 bp->max_lltc = resp->max_configurable_lossless_queues;
1433 if (bp->max_tc > BNXT_MAX_QUEUE)
1434 bp->max_tc = BNXT_MAX_QUEUE;
1435 bp->max_q = bp->max_tc;
1437 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1438 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1446 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1447 struct bnxt_ring *ring,
1448 uint32_t ring_type, uint32_t map_index,
1449 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1450 uint16_t tx_cosq_id)
1453 uint32_t enables = 0;
1454 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1455 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1456 struct rte_mempool *mb_pool;
1457 uint16_t rx_buf_size;
1459 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1461 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1462 req.fbo = rte_cpu_to_le_32(0);
1463 /* Association of ring index with doorbell index */
1464 req.logical_id = rte_cpu_to_le_16(map_index);
1465 req.length = rte_cpu_to_le_32(ring->ring_size);
1467 switch (ring_type) {
1468 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1469 req.ring_type = ring_type;
1470 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1471 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1472 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1473 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1475 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1477 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1478 req.ring_type = ring_type;
1479 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1480 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1481 if (BNXT_CHIP_THOR(bp)) {
1482 mb_pool = bp->rx_queues[0]->mb_pool;
1483 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1484 RTE_PKTMBUF_HEADROOM;
1485 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1486 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1488 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1490 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1492 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1494 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1495 req.ring_type = ring_type;
1496 if (BNXT_HAS_NQ(bp)) {
1497 /* Association of cp ring with nq */
1498 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1500 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1502 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1504 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1505 req.ring_type = ring_type;
1506 req.page_size = BNXT_PAGE_SHFT;
1507 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1509 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1510 req.ring_type = ring_type;
1511 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1513 mb_pool = bp->rx_queues[0]->mb_pool;
1514 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1515 RTE_PKTMBUF_HEADROOM;
1516 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1517 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1519 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1520 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1521 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1522 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1525 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1530 req.enables = rte_cpu_to_le_32(enables);
1532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1534 if (rc || resp->error_code) {
1535 if (rc == 0 && resp->error_code)
1536 rc = rte_le_to_cpu_16(resp->error_code);
1537 switch (ring_type) {
1538 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1540 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1543 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1545 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1548 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1550 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1554 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1556 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1559 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1561 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1565 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1571 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1576 int bnxt_hwrm_ring_free(struct bnxt *bp,
1577 struct bnxt_ring *ring, uint32_t ring_type)
1580 struct hwrm_ring_free_input req = {.req_type = 0 };
1581 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1583 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1585 req.ring_type = ring_type;
1586 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1590 if (rc || resp->error_code) {
1591 if (rc == 0 && resp->error_code)
1592 rc = rte_le_to_cpu_16(resp->error_code);
1595 switch (ring_type) {
1596 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1597 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1600 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1601 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1604 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1605 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1608 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1610 "hwrm_ring_free nq failed. rc:%d\n", rc);
1612 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1614 "hwrm_ring_free agg failed. rc:%d\n", rc);
1617 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1625 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1628 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1629 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1631 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1633 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1634 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1635 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1636 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1638 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1640 HWRM_CHECK_RESULT();
1642 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1649 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1652 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1653 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1655 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1657 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1661 HWRM_CHECK_RESULT();
1664 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1668 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1671 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1672 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1674 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1677 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1679 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1683 HWRM_CHECK_RESULT();
1689 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1690 unsigned int idx __rte_unused)
1693 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1694 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1696 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1698 req.update_period_ms = rte_cpu_to_le_32(0);
1700 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1704 HWRM_CHECK_RESULT();
1706 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1713 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1714 unsigned int idx __rte_unused)
1717 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1718 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1720 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1722 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1726 HWRM_CHECK_RESULT();
1732 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1735 struct hwrm_vnic_alloc_input req = { 0 };
1736 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1738 if (!BNXT_HAS_RING_GRPS(bp))
1739 goto skip_ring_grps;
1741 /* map ring groups to this vnic */
1742 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1743 vnic->start_grp_id, vnic->end_grp_id);
1744 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1745 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1747 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1748 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1749 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1750 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1753 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1754 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1756 if (vnic->func_default)
1758 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1761 HWRM_CHECK_RESULT();
1763 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1765 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1769 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1770 struct bnxt_vnic_info *vnic,
1771 struct bnxt_plcmodes_cfg *pmode)
1774 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1777 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1779 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1783 HWRM_CHECK_RESULT();
1785 pmode->flags = rte_le_to_cpu_32(resp->flags);
1786 /* dflt_vnic bit doesn't exist in the _cfg command */
1787 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1788 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1789 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1790 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1797 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1798 struct bnxt_vnic_info *vnic,
1799 struct bnxt_plcmodes_cfg *pmode)
1802 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1803 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1805 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1806 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1810 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1812 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1813 req.flags = rte_cpu_to_le_32(pmode->flags);
1814 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1815 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1816 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1817 req.enables = rte_cpu_to_le_32(
1818 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1819 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1820 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1823 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1825 HWRM_CHECK_RESULT();
1831 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1834 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1835 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1836 struct bnxt_plcmodes_cfg pmodes = { 0 };
1837 uint32_t ctx_enable_flag = 0;
1838 uint32_t enables = 0;
1840 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1841 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1845 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1849 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1851 if (BNXT_CHIP_THOR(bp)) {
1852 int dflt_rxq = vnic->start_grp_id;
1853 struct bnxt_rx_ring_info *rxr;
1854 struct bnxt_cp_ring_info *cpr;
1855 struct bnxt_rx_queue *rxq;
1859 * The first active receive ring is used as the VNIC
1860 * default receive ring. If there are no active receive
1861 * rings (all corresponding receive queues are stopped),
1862 * the first receive ring is used.
1864 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1865 rxq = bp->eth_dev->data->rx_queues[i];
1866 if (rxq->rx_started) {
1872 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1876 req.default_rx_ring_id =
1877 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1878 req.default_cmpl_ring_id =
1879 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1880 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1881 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1885 /* Only RSS support for now TBD: COS & LB */
1886 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1887 if (vnic->lb_rule != 0xffff)
1888 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1889 if (vnic->cos_rule != 0xffff)
1890 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1891 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1892 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1893 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1895 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1896 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1897 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1900 enables |= ctx_enable_flag;
1901 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1902 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1903 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1904 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1907 req.enables = rte_cpu_to_le_32(enables);
1908 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1909 req.mru = rte_cpu_to_le_16(vnic->mru);
1910 /* Configure default VNIC only once. */
1911 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1913 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1914 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1916 if (vnic->vlan_strip)
1918 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1921 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1922 if (vnic->roce_dual)
1923 req.flags |= rte_cpu_to_le_32(
1924 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1925 if (vnic->roce_only)
1926 req.flags |= rte_cpu_to_le_32(
1927 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1928 if (vnic->rss_dflt_cr)
1929 req.flags |= rte_cpu_to_le_32(
1930 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1934 HWRM_CHECK_RESULT();
1937 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1942 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1946 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1947 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1949 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1950 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1953 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1956 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1957 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1958 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1962 HWRM_CHECK_RESULT();
1964 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1965 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1966 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1967 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1968 vnic->mru = rte_le_to_cpu_16(resp->mru);
1969 vnic->func_default = rte_le_to_cpu_32(
1970 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1971 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1972 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1973 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1974 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1975 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1976 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1977 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1978 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1979 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1980 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1987 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1988 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1992 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1993 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1994 bp->hwrm_cmd_resp_addr;
1996 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999 HWRM_CHECK_RESULT();
2001 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2002 if (!BNXT_HAS_RING_GRPS(bp))
2003 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2004 else if (ctx_idx == 0)
2005 vnic->rss_rule = ctx_id;
2013 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2014 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2017 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2018 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2019 bp->hwrm_cmd_resp_addr;
2021 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2022 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2025 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2027 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2031 HWRM_CHECK_RESULT();
2037 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2041 if (BNXT_CHIP_THOR(bp)) {
2044 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2045 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2047 vnic->fw_grp_ids[j]);
2048 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2050 vnic->num_lb_ctxts = 0;
2052 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2053 vnic->rss_rule = INVALID_HW_RING_ID;
2059 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2062 struct hwrm_vnic_free_input req = {.req_type = 0 };
2063 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2065 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2066 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2070 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2072 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2076 HWRM_CHECK_RESULT();
2079 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2080 /* Configure default VNIC again if necessary. */
2081 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2082 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2088 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2092 int nr_ctxs = vnic->num_lb_ctxts;
2093 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2094 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2096 for (i = 0; i < nr_ctxs; i++) {
2097 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2099 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2100 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2101 req.hash_mode_flags = vnic->hash_mode;
2103 req.hash_key_tbl_addr =
2104 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2106 req.ring_grp_tbl_addr =
2107 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2108 i * HW_HASH_INDEX_SIZE);
2109 req.ring_table_pair_index = i;
2110 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2115 HWRM_CHECK_RESULT();
2122 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2123 struct bnxt_vnic_info *vnic)
2126 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2127 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2129 if (!vnic->rss_table)
2132 if (BNXT_CHIP_THOR(bp))
2133 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2135 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2137 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2138 req.hash_mode_flags = vnic->hash_mode;
2140 req.ring_grp_tbl_addr =
2141 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2142 req.hash_key_tbl_addr =
2143 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2144 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2145 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2147 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2149 HWRM_CHECK_RESULT();
2155 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2156 struct bnxt_vnic_info *vnic)
2159 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2160 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2163 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2164 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2168 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2170 req.flags = rte_cpu_to_le_32(
2171 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2173 req.enables = rte_cpu_to_le_32(
2174 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2176 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2177 size -= RTE_PKTMBUF_HEADROOM;
2178 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2180 req.jumbo_thresh = rte_cpu_to_le_16(size);
2181 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2185 HWRM_CHECK_RESULT();
2191 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2192 struct bnxt_vnic_info *vnic, bool enable)
2195 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2196 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2198 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2200 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2204 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2205 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2209 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2212 req.enables = rte_cpu_to_le_32(
2213 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2214 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2215 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2216 req.flags = rte_cpu_to_le_32(
2217 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2218 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2219 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2220 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2221 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2222 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2223 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2224 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2225 req.min_agg_len = rte_cpu_to_le_32(512);
2227 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2231 HWRM_CHECK_RESULT();
2237 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2239 struct hwrm_func_cfg_input req = {0};
2240 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2243 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2244 req.enables = rte_cpu_to_le_32(
2245 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2246 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2247 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2249 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2251 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252 HWRM_CHECK_RESULT();
2255 bp->pf->vf_info[vf].random_mac = false;
2260 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2264 struct hwrm_func_qstats_input req = {.req_type = 0};
2265 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2267 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2269 req.fid = rte_cpu_to_le_16(fid);
2271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2273 HWRM_CHECK_RESULT();
2276 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2283 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2284 struct rte_eth_stats *stats,
2285 struct hwrm_func_qstats_output *func_qstats)
2288 struct hwrm_func_qstats_input req = {.req_type = 0};
2289 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2291 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2293 req.fid = rte_cpu_to_le_16(fid);
2295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2297 HWRM_CHECK_RESULT();
2299 memcpy(func_qstats, resp,
2300 sizeof(struct hwrm_func_qstats_output));
2305 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2306 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2307 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2308 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2309 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2310 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2312 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2313 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2314 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2315 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2316 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2317 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2319 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2320 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2321 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2329 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2332 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2333 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2335 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2337 req.fid = rte_cpu_to_le_16(fid);
2339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2341 HWRM_CHECK_RESULT();
2347 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2352 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2353 struct bnxt_tx_queue *txq;
2354 struct bnxt_rx_queue *rxq;
2355 struct bnxt_cp_ring_info *cpr;
2357 if (i >= bp->rx_cp_nr_rings) {
2358 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2361 rxq = bp->rx_queues[i];
2365 rc = bnxt_hwrm_stat_clear(bp, cpr);
2373 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2377 struct bnxt_cp_ring_info *cpr;
2379 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2381 if (i >= bp->rx_cp_nr_rings) {
2382 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2384 cpr = bp->rx_queues[i]->cp_ring;
2385 if (BNXT_HAS_RING_GRPS(bp))
2386 bp->grp_info[i].fw_stats_ctx = -1;
2388 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2389 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2390 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2398 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2403 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2404 struct bnxt_tx_queue *txq;
2405 struct bnxt_rx_queue *rxq;
2406 struct bnxt_cp_ring_info *cpr;
2408 if (i >= bp->rx_cp_nr_rings) {
2409 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2412 rxq = bp->rx_queues[i];
2416 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2425 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2430 if (!BNXT_HAS_RING_GRPS(bp))
2433 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2435 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2438 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2446 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2448 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2450 bnxt_hwrm_ring_free(bp, cp_ring,
2451 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2452 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2453 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2454 sizeof(*cpr->cp_desc_ring));
2455 cpr->cp_raw_cons = 0;
2459 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2461 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2463 bnxt_hwrm_ring_free(bp, cp_ring,
2464 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2465 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2466 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2467 sizeof(*cpr->cp_desc_ring));
2468 cpr->cp_raw_cons = 0;
2472 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2474 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2475 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2476 struct bnxt_ring *ring = rxr->rx_ring_struct;
2477 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2479 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2480 bnxt_hwrm_ring_free(bp, ring,
2481 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2482 ring->fw_ring_id = INVALID_HW_RING_ID;
2483 if (BNXT_HAS_RING_GRPS(bp))
2484 bp->grp_info[queue_index].rx_fw_ring_id =
2487 ring = rxr->ag_ring_struct;
2488 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2489 bnxt_hwrm_ring_free(bp, ring,
2490 BNXT_CHIP_THOR(bp) ?
2491 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2492 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2493 if (BNXT_HAS_RING_GRPS(bp))
2494 bp->grp_info[queue_index].ag_fw_ring_id =
2497 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2498 bnxt_free_cp_ring(bp, cpr);
2500 if (BNXT_HAS_RING_GRPS(bp))
2501 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2505 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2509 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2510 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2511 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2512 struct bnxt_ring *ring = txr->tx_ring_struct;
2513 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2515 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2516 bnxt_hwrm_ring_free(bp, ring,
2517 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2518 ring->fw_ring_id = INVALID_HW_RING_ID;
2519 memset(txr->tx_desc_ring, 0,
2520 txr->tx_ring_struct->ring_size *
2521 sizeof(*txr->tx_desc_ring));
2522 memset(txr->tx_buf_ring, 0,
2523 txr->tx_ring_struct->ring_size *
2524 sizeof(*txr->tx_buf_ring));
2528 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2529 bnxt_free_cp_ring(bp, cpr);
2530 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2534 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2535 bnxt_free_hwrm_rx_ring(bp, i);
2540 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2545 if (!BNXT_HAS_RING_GRPS(bp))
2548 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2549 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2557 * HWRM utility functions
2560 void bnxt_free_hwrm_resources(struct bnxt *bp)
2562 /* Release memzone */
2563 rte_free(bp->hwrm_cmd_resp_addr);
2564 rte_free(bp->hwrm_short_cmd_req_addr);
2565 bp->hwrm_cmd_resp_addr = NULL;
2566 bp->hwrm_short_cmd_req_addr = NULL;
2567 bp->hwrm_cmd_resp_dma_addr = 0;
2568 bp->hwrm_short_cmd_req_dma_addr = 0;
2571 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2573 struct rte_pci_device *pdev = bp->pdev;
2574 char type[RTE_MEMZONE_NAMESIZE];
2576 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2578 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2579 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2580 if (bp->hwrm_cmd_resp_addr == NULL)
2582 bp->hwrm_cmd_resp_dma_addr =
2583 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2584 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2586 "unable to map response address to physical memory\n");
2589 rte_spinlock_init(&bp->hwrm_lock);
2595 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2597 struct bnxt_filter_info *filter;
2600 STAILQ_FOREACH(filter, &vnic->filter, next) {
2601 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2602 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2603 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2604 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2605 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2606 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2607 bnxt_free_filter(bp, filter);
2613 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2615 struct bnxt_filter_info *filter;
2616 struct rte_flow *flow;
2619 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2620 flow = STAILQ_FIRST(&vnic->flow_list);
2621 filter = flow->filter;
2622 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2623 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2624 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2625 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2626 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2629 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2635 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2637 struct bnxt_filter_info *filter;
2640 STAILQ_FOREACH(filter, &vnic->filter, next) {
2641 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2642 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2644 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2645 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2648 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2657 bnxt_free_tunnel_ports(struct bnxt *bp)
2659 if (bp->vxlan_port_cnt)
2660 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2661 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2663 if (bp->geneve_port_cnt)
2664 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2665 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2666 bp->geneve_port = 0;
2669 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2673 if (bp->vnic_info == NULL)
2677 * Cleanup VNICs in reverse order, to make sure the L2 filter
2678 * from vnic0 is last to be cleaned up.
2680 for (i = bp->max_vnics - 1; i >= 0; i--) {
2681 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2683 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2686 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2688 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2690 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2692 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2694 bnxt_hwrm_vnic_free(bp, vnic);
2696 rte_free(vnic->fw_grp_ids);
2698 /* Ring resources */
2699 bnxt_free_all_hwrm_rings(bp);
2700 bnxt_free_all_hwrm_ring_grps(bp);
2701 bnxt_free_all_hwrm_stat_ctxs(bp);
2702 bnxt_free_tunnel_ports(bp);
2705 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2707 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2709 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2710 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2712 switch (conf_link_speed) {
2713 case ETH_LINK_SPEED_10M_HD:
2714 case ETH_LINK_SPEED_100M_HD:
2716 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2718 return hw_link_duplex;
2721 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2723 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2726 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2728 uint16_t eth_link_speed = 0;
2730 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2731 return ETH_LINK_SPEED_AUTONEG;
2733 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2734 case ETH_LINK_SPEED_100M:
2735 case ETH_LINK_SPEED_100M_HD:
2738 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2740 case ETH_LINK_SPEED_1G:
2742 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2744 case ETH_LINK_SPEED_2_5G:
2746 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2748 case ETH_LINK_SPEED_10G:
2750 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2752 case ETH_LINK_SPEED_20G:
2754 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2756 case ETH_LINK_SPEED_25G:
2758 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2760 case ETH_LINK_SPEED_40G:
2762 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2764 case ETH_LINK_SPEED_50G:
2766 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2768 case ETH_LINK_SPEED_100G:
2770 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2772 case ETH_LINK_SPEED_200G:
2774 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2778 "Unsupported link speed %d; default to AUTO\n",
2782 return eth_link_speed;
2785 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2786 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2787 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2788 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2789 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2791 static int bnxt_validate_link_speed(struct bnxt *bp)
2793 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
2794 uint16_t port_id = bp->eth_dev->data->port_id;
2795 uint32_t link_speed_capa;
2798 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2801 link_speed_capa = bnxt_get_speed_capabilities(bp);
2803 if (link_speed & ETH_LINK_SPEED_FIXED) {
2804 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2806 if (one_speed & (one_speed - 1)) {
2808 "Invalid advertised speeds (%u) for port %u\n",
2809 link_speed, port_id);
2812 if ((one_speed & link_speed_capa) != one_speed) {
2814 "Unsupported advertised speed (%u) for port %u\n",
2815 link_speed, port_id);
2819 if (!(link_speed & link_speed_capa)) {
2821 "Unsupported advertised speeds (%u) for port %u\n",
2822 link_speed, port_id);
2830 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2834 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2835 if (bp->link_info->support_speeds)
2836 return bp->link_info->support_speeds;
2837 link_speed = BNXT_SUPPORTED_SPEEDS;
2840 if (link_speed & ETH_LINK_SPEED_100M)
2841 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2842 if (link_speed & ETH_LINK_SPEED_100M_HD)
2843 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2844 if (link_speed & ETH_LINK_SPEED_1G)
2845 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2846 if (link_speed & ETH_LINK_SPEED_2_5G)
2847 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2848 if (link_speed & ETH_LINK_SPEED_10G)
2849 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2850 if (link_speed & ETH_LINK_SPEED_20G)
2851 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2852 if (link_speed & ETH_LINK_SPEED_25G)
2853 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2854 if (link_speed & ETH_LINK_SPEED_40G)
2855 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2856 if (link_speed & ETH_LINK_SPEED_50G)
2857 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2858 if (link_speed & ETH_LINK_SPEED_100G)
2859 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2860 if (link_speed & ETH_LINK_SPEED_200G)
2861 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2865 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2867 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2869 switch (hw_link_speed) {
2870 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2871 eth_link_speed = ETH_SPEED_NUM_100M;
2873 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2874 eth_link_speed = ETH_SPEED_NUM_1G;
2876 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2877 eth_link_speed = ETH_SPEED_NUM_2_5G;
2879 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2880 eth_link_speed = ETH_SPEED_NUM_10G;
2882 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2883 eth_link_speed = ETH_SPEED_NUM_20G;
2885 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2886 eth_link_speed = ETH_SPEED_NUM_25G;
2888 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2889 eth_link_speed = ETH_SPEED_NUM_40G;
2891 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2892 eth_link_speed = ETH_SPEED_NUM_50G;
2894 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2895 eth_link_speed = ETH_SPEED_NUM_100G;
2897 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2898 eth_link_speed = ETH_SPEED_NUM_200G;
2900 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2902 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2906 return eth_link_speed;
2909 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2911 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2913 switch (hw_link_duplex) {
2914 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2915 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2917 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2919 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2920 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2923 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2927 return eth_link_duplex;
2930 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2933 struct bnxt_link_info *link_info = bp->link_info;
2935 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2938 "Get link config failed with rc %d\n", rc);
2941 if (link_info->link_speed)
2943 bnxt_parse_hw_link_speed(link_info->link_speed);
2945 link->link_speed = ETH_SPEED_NUM_NONE;
2946 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2947 link->link_status = link_info->link_up;
2948 link->link_autoneg = link_info->auto_mode ==
2949 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2950 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2955 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2958 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2959 struct bnxt_link_info link_req;
2960 uint16_t speed, autoneg;
2962 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2965 rc = bnxt_validate_link_speed(bp);
2969 memset(&link_req, 0, sizeof(link_req));
2970 link_req.link_up = link_up;
2974 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2975 if (BNXT_CHIP_THOR(bp) &&
2976 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2977 /* 40G is not supported as part of media auto detect.
2978 * The speed should be forced and autoneg disabled
2979 * to configure 40G speed.
2981 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2985 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2986 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2987 /* Autoneg can be done only when the FW allows.
2988 * When user configures fixed speed of 40G and later changes to
2989 * any other speed, auto_link_speed/force_link_speed is still set
2990 * to 40G until link comes up at new speed.
2993 !(!BNXT_CHIP_THOR(bp) &&
2994 (bp->link_info->auto_link_speed ||
2995 bp->link_info->force_link_speed))) {
2996 link_req.phy_flags |=
2997 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2998 link_req.auto_link_speed_mask =
2999 bnxt_parse_eth_link_speed_mask(bp,
3000 dev_conf->link_speeds);
3002 if (bp->link_info->phy_type ==
3003 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3004 bp->link_info->phy_type ==
3005 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3006 bp->link_info->media_type ==
3007 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3008 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3012 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3013 /* If user wants a particular speed try that first. */
3015 link_req.link_speed = speed;
3016 else if (bp->link_info->force_link_speed)
3017 link_req.link_speed = bp->link_info->force_link_speed;
3019 link_req.link_speed = bp->link_info->auto_link_speed;
3021 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3022 link_req.auto_pause = bp->link_info->auto_pause;
3023 link_req.force_pause = bp->link_info->force_pause;
3026 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3029 "Set link config failed with rc %d\n", rc);
3037 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3039 struct hwrm_func_qcfg_input req = {0};
3040 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3043 bp->func_svif = BNXT_SVIF_INVALID;
3046 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3047 req.fid = rte_cpu_to_le_16(0xffff);
3049 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3051 HWRM_CHECK_RESULT();
3053 /* Hard Coded.. 0xfff VLAN ID mask */
3054 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3056 svif_info = rte_le_to_cpu_16(resp->svif_info);
3057 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3058 bp->func_svif = svif_info &
3059 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3061 flags = rte_le_to_cpu_16(resp->flags);
3062 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3063 bp->flags |= BNXT_FLAG_MULTI_HOST;
3066 !BNXT_VF_IS_TRUSTED(bp) &&
3067 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3068 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3069 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3070 } else if (BNXT_VF(bp) &&
3071 BNXT_VF_IS_TRUSTED(bp) &&
3072 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3073 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3074 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3078 *mtu = rte_le_to_cpu_16(resp->mtu);
3080 switch (resp->port_partition_type) {
3081 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3082 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3083 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3085 bp->flags |= BNXT_FLAG_NPAR_PF;
3088 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3097 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3099 struct hwrm_func_qcfg_input req = {0};
3100 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3103 if (!BNXT_VF_IS_TRUSTED(bp))
3109 bp->parent->fid = BNXT_PF_FID_INVALID;
3111 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3113 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3115 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3117 HWRM_CHECK_RESULT();
3119 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3120 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3121 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3122 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3124 /* FIXME: Temporary workaround - remove when firmware issue is fixed. */
3125 if (bp->parent->vnic == 0) {
3126 PMD_DRV_LOG(ERR, "Error: parent VNIC unavailable.\n");
3127 /* Use hard-coded values appropriate for current Wh+ fw. */
3128 if (bp->parent->fid == 2)
3129 bp->parent->vnic = 0x100;
3131 bp->parent->vnic = 1;
3139 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3140 uint16_t *vnic_id, uint16_t *svif)
3142 struct hwrm_func_qcfg_input req = {0};
3143 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3147 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3148 req.fid = rte_cpu_to_le_16(fid);
3150 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3152 HWRM_CHECK_RESULT();
3155 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3157 svif_info = rte_le_to_cpu_16(resp->svif_info);
3158 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3159 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3166 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3168 struct hwrm_port_mac_qcfg_input req = {0};
3169 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3170 uint16_t port_svif_info;
3173 bp->port_svif = BNXT_SVIF_INVALID;
3178 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3180 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3182 HWRM_CHECK_RESULT();
3184 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3185 if (port_svif_info &
3186 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3187 bp->port_svif = port_svif_info &
3188 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3195 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3196 struct hwrm_func_qcaps_output *qcaps)
3198 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3199 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3200 sizeof(qcaps->mac_address));
3201 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3202 qcaps->max_rx_rings = fcfg->num_rx_rings;
3203 qcaps->max_tx_rings = fcfg->num_tx_rings;
3204 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3205 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3207 qcaps->first_vf_id = 0;
3208 qcaps->max_vnics = fcfg->num_vnics;
3209 qcaps->max_decap_records = 0;
3210 qcaps->max_encap_records = 0;
3211 qcaps->max_tx_wm_flows = 0;
3212 qcaps->max_tx_em_flows = 0;
3213 qcaps->max_rx_wm_flows = 0;
3214 qcaps->max_rx_em_flows = 0;
3215 qcaps->max_flow_id = 0;
3216 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3217 qcaps->max_sp_tx_rings = 0;
3218 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3221 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3223 struct hwrm_func_cfg_input req = {0};
3224 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3228 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3229 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3230 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3231 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3232 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3233 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3234 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3235 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3236 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3238 if (BNXT_HAS_RING_GRPS(bp)) {
3239 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3240 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3241 } else if (BNXT_HAS_NQ(bp)) {
3242 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3243 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3246 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3247 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3248 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3249 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3250 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3251 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3252 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3253 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3254 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3255 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3256 req.fid = rte_cpu_to_le_16(0xffff);
3257 req.enables = rte_cpu_to_le_32(enables);
3259 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3261 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3263 HWRM_CHECK_RESULT();
3269 static void populate_vf_func_cfg_req(struct bnxt *bp,
3270 struct hwrm_func_cfg_input *req,
3273 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3274 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3275 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3276 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3277 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3278 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3279 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3280 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3281 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3282 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3284 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3285 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3287 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3288 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3290 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3291 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3293 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3294 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3295 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3296 /* TODO: For now, do not support VMDq/RFS on VFs. */
3297 req->num_vnics = rte_cpu_to_le_16(1);
3298 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3302 static void add_random_mac_if_needed(struct bnxt *bp,
3303 struct hwrm_func_cfg_input *cfg_req,
3306 struct rte_ether_addr mac;
3308 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3311 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3313 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3314 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3315 bp->pf->vf_info[vf].random_mac = true;
3317 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3318 RTE_ETHER_ADDR_LEN);
3322 static int reserve_resources_from_vf(struct bnxt *bp,
3323 struct hwrm_func_cfg_input *cfg_req,
3326 struct hwrm_func_qcaps_input req = {0};
3327 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3330 /* Get the actual allocated values now */
3331 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3332 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3333 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3336 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3337 copy_func_cfg_to_qcaps(cfg_req, resp);
3338 } else if (resp->error_code) {
3339 rc = rte_le_to_cpu_16(resp->error_code);
3340 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3341 copy_func_cfg_to_qcaps(cfg_req, resp);
3344 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3345 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3346 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3347 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3348 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3349 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3351 * TODO: While not supporting VMDq with VFs, max_vnics is always
3352 * forced to 1 in this case
3354 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3355 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3362 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3364 struct hwrm_func_qcfg_input req = {0};
3365 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3368 /* Check for zero MAC address */
3369 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3370 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3371 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3372 HWRM_CHECK_RESULT();
3373 rc = rte_le_to_cpu_16(resp->vlan);
3380 static int update_pf_resource_max(struct bnxt *bp)
3382 struct hwrm_func_qcfg_input req = {0};
3383 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3386 /* And copy the allocated numbers into the pf struct */
3387 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3388 req.fid = rte_cpu_to_le_16(0xffff);
3389 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3390 HWRM_CHECK_RESULT();
3392 /* Only TX ring value reflects actual allocation? TODO */
3393 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3394 bp->pf->evb_mode = resp->evb_mode;
3401 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3406 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3410 rc = bnxt_hwrm_func_qcaps(bp);
3414 bp->pf->func_cfg_flags &=
3415 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3416 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3417 bp->pf->func_cfg_flags |=
3418 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3419 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3420 rc = __bnxt_hwrm_func_qcaps(bp);
3424 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3426 struct hwrm_func_cfg_input req = {0};
3427 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3434 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3438 rc = bnxt_hwrm_func_qcaps(bp);
3443 bp->pf->active_vfs = num_vfs;
3446 * First, configure the PF to only use one TX ring. This ensures that
3447 * there are enough rings for all VFs.
3449 * If we don't do this, when we call func_alloc() later, we will lock
3450 * extra rings to the PF that won't be available during func_cfg() of
3453 * This has been fixed with firmware versions above 20.6.54
3455 bp->pf->func_cfg_flags &=
3456 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3457 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3458 bp->pf->func_cfg_flags |=
3459 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3460 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3465 * Now, create and register a buffer to hold forwarded VF requests
3467 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3468 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3469 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3470 if (bp->pf->vf_req_buf == NULL) {
3474 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3475 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3476 for (i = 0; i < num_vfs; i++)
3477 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3478 (i * HWRM_MAX_REQ_LEN);
3480 rc = bnxt_hwrm_func_buf_rgtr(bp);
3484 populate_vf_func_cfg_req(bp, &req, num_vfs);
3486 bp->pf->active_vfs = 0;
3487 for (i = 0; i < num_vfs; i++) {
3488 add_random_mac_if_needed(bp, &req, i);
3490 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3491 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3492 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3493 rc = bnxt_hwrm_send_message(bp,
3498 /* Clear enable flag for next pass */
3499 req.enables &= ~rte_cpu_to_le_32(
3500 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3502 if (rc || resp->error_code) {
3504 "Failed to initizlie VF %d\n", i);
3506 "Not all VFs available. (%d, %d)\n",
3507 rc, resp->error_code);
3514 reserve_resources_from_vf(bp, &req, i);
3515 bp->pf->active_vfs++;
3516 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3520 * Now configure the PF to use "the rest" of the resources
3521 * We're using STD_TX_RING_MODE here though which will limit the TX
3522 * rings. This will allow QoS to function properly. Not setting this
3523 * will cause PF rings to break bandwidth settings.
3525 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3529 rc = update_pf_resource_max(bp);
3536 bnxt_hwrm_func_buf_unrgtr(bp);
3540 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3542 struct hwrm_func_cfg_input req = {0};
3543 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3546 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3548 req.fid = rte_cpu_to_le_16(0xffff);
3549 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3550 req.evb_mode = bp->pf->evb_mode;
3552 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3553 HWRM_CHECK_RESULT();
3559 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3560 uint8_t tunnel_type)
3562 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3563 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3566 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3567 req.tunnel_type = tunnel_type;
3568 req.tunnel_dst_port_val = port;
3569 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3570 HWRM_CHECK_RESULT();
3572 switch (tunnel_type) {
3573 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3574 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3575 bp->vxlan_port = port;
3577 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3578 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3579 bp->geneve_port = port;
3590 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3591 uint8_t tunnel_type)
3593 struct hwrm_tunnel_dst_port_free_input req = {0};
3594 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3597 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3599 req.tunnel_type = tunnel_type;
3600 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3601 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3603 HWRM_CHECK_RESULT();
3609 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3612 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3613 struct hwrm_func_cfg_input req = {0};
3616 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3618 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3619 req.flags = rte_cpu_to_le_32(flags);
3620 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3622 HWRM_CHECK_RESULT();
3628 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3630 uint32_t *flag = flagp;
3632 vnic->flags = *flag;
3635 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3637 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3640 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3643 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3644 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3646 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3648 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3649 req.req_buf_page_size = rte_cpu_to_le_16(
3650 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3651 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3652 req.req_buf_page_addr0 =
3653 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3654 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3656 "unable to map buffer address to physical memory\n");
3660 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3662 HWRM_CHECK_RESULT();
3668 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3671 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3672 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3674 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3677 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3679 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3681 HWRM_CHECK_RESULT();
3687 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3689 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3690 struct hwrm_func_cfg_input req = {0};
3693 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3695 req.fid = rte_cpu_to_le_16(0xffff);
3696 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3697 req.enables = rte_cpu_to_le_32(
3698 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3699 req.async_event_cr = rte_cpu_to_le_16(
3700 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3701 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3703 HWRM_CHECK_RESULT();
3709 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3711 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3712 struct hwrm_func_vf_cfg_input req = {0};
3715 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3717 req.enables = rte_cpu_to_le_32(
3718 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3719 req.async_event_cr = rte_cpu_to_le_16(
3720 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3721 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3723 HWRM_CHECK_RESULT();
3729 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3731 struct hwrm_func_cfg_input req = {0};
3732 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3733 uint16_t dflt_vlan, fid;
3734 uint32_t func_cfg_flags;
3737 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3740 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3741 fid = bp->pf->vf_info[vf].fid;
3742 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3744 fid = rte_cpu_to_le_16(0xffff);
3745 func_cfg_flags = bp->pf->func_cfg_flags;
3746 dflt_vlan = bp->vlan;
3749 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3750 req.fid = rte_cpu_to_le_16(fid);
3751 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3752 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3754 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3756 HWRM_CHECK_RESULT();
3762 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3763 uint16_t max_bw, uint16_t enables)
3765 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3766 struct hwrm_func_cfg_input req = {0};
3769 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3771 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3772 req.enables |= rte_cpu_to_le_32(enables);
3773 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3774 req.max_bw = rte_cpu_to_le_32(max_bw);
3775 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3777 HWRM_CHECK_RESULT();
3783 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3785 struct hwrm_func_cfg_input req = {0};
3786 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3789 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3791 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3792 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3793 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3794 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3796 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3798 HWRM_CHECK_RESULT();
3804 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3809 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3811 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3816 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3817 void *encaped, size_t ec_size)
3820 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3821 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3823 if (ec_size > sizeof(req.encap_request))
3826 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3828 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3829 memcpy(req.encap_request, encaped, ec_size);
3831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3833 HWRM_CHECK_RESULT();
3839 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3840 struct rte_ether_addr *mac)
3842 struct hwrm_func_qcfg_input req = {0};
3843 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3846 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3848 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3849 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3851 HWRM_CHECK_RESULT();
3853 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3860 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3861 void *encaped, size_t ec_size)
3864 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3865 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3867 if (ec_size > sizeof(req.encap_request))
3870 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3872 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3873 memcpy(req.encap_request, encaped, ec_size);
3875 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3877 HWRM_CHECK_RESULT();
3883 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3884 struct rte_eth_stats *stats, uint8_t rx)
3887 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3888 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3890 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3892 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3894 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3896 HWRM_CHECK_RESULT();
3899 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3900 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3901 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3902 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3903 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3904 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3905 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3906 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3908 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3909 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3910 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3911 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3912 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3913 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3921 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3923 struct hwrm_port_qstats_input req = {0};
3924 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3925 struct bnxt_pf_info *pf = bp->pf;
3928 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3930 req.port_id = rte_cpu_to_le_16(pf->port_id);
3931 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3932 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3933 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3935 HWRM_CHECK_RESULT();
3941 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3943 struct hwrm_port_clr_stats_input req = {0};
3944 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3945 struct bnxt_pf_info *pf = bp->pf;
3948 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3949 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3950 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3953 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3955 req.port_id = rte_cpu_to_le_16(pf->port_id);
3956 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3958 HWRM_CHECK_RESULT();
3964 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3966 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3967 struct hwrm_port_led_qcaps_input req = {0};
3973 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3974 req.port_id = bp->pf->port_id;
3975 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3977 HWRM_CHECK_RESULT();
3979 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3982 bp->leds->num_leds = resp->num_leds;
3983 memcpy(bp->leds, &resp->led0_id,
3984 sizeof(bp->leds[0]) * bp->leds->num_leds);
3985 for (i = 0; i < bp->leds->num_leds; i++) {
3986 struct bnxt_led_info *led = &bp->leds[i];
3988 uint16_t caps = led->led_state_caps;
3990 if (!led->led_group_id ||
3991 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3992 bp->leds->num_leds = 0;
4003 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4005 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4006 struct hwrm_port_led_cfg_input req = {0};
4007 struct bnxt_led_cfg *led_cfg;
4008 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4009 uint16_t duration = 0;
4012 if (!bp->leds->num_leds || BNXT_VF(bp))
4015 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4018 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4019 duration = rte_cpu_to_le_16(500);
4021 req.port_id = bp->pf->port_id;
4022 req.num_leds = bp->leds->num_leds;
4023 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4024 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4025 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4026 led_cfg->led_id = bp->leds[i].led_id;
4027 led_cfg->led_state = led_state;
4028 led_cfg->led_blink_on = duration;
4029 led_cfg->led_blink_off = duration;
4030 led_cfg->led_group_id = bp->leds[i].led_group_id;
4033 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4035 HWRM_CHECK_RESULT();
4041 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4045 struct hwrm_nvm_get_dir_info_input req = {0};
4046 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4048 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4050 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4052 HWRM_CHECK_RESULT();
4054 *entries = rte_le_to_cpu_32(resp->entries);
4055 *length = rte_le_to_cpu_32(resp->entry_length);
4061 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4064 uint32_t dir_entries;
4065 uint32_t entry_length;
4068 rte_iova_t dma_handle;
4069 struct hwrm_nvm_get_dir_entries_input req = {0};
4070 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4072 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4076 *data++ = dir_entries;
4077 *data++ = entry_length;
4079 memset(data, 0xff, len);
4081 buflen = dir_entries * entry_length;
4082 buf = rte_malloc("nvm_dir", buflen, 0);
4085 dma_handle = rte_malloc_virt2iova(buf);
4086 if (dma_handle == RTE_BAD_IOVA) {
4088 "unable to map response address to physical memory\n");
4091 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4092 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4093 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4096 memcpy(data, buf, len > buflen ? buflen : len);
4099 HWRM_CHECK_RESULT();
4105 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4106 uint32_t offset, uint32_t length,
4111 rte_iova_t dma_handle;
4112 struct hwrm_nvm_read_input req = {0};
4113 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4115 buf = rte_malloc("nvm_item", length, 0);
4119 dma_handle = rte_malloc_virt2iova(buf);
4120 if (dma_handle == RTE_BAD_IOVA) {
4122 "unable to map response address to physical memory\n");
4125 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4126 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4127 req.dir_idx = rte_cpu_to_le_16(index);
4128 req.offset = rte_cpu_to_le_32(offset);
4129 req.len = rte_cpu_to_le_32(length);
4130 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4132 memcpy(data, buf, length);
4135 HWRM_CHECK_RESULT();
4141 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4144 struct hwrm_nvm_erase_dir_entry_input req = {0};
4145 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4147 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4148 req.dir_idx = rte_cpu_to_le_16(index);
4149 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4150 HWRM_CHECK_RESULT();
4157 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4158 uint16_t dir_ordinal, uint16_t dir_ext,
4159 uint16_t dir_attr, const uint8_t *data,
4163 struct hwrm_nvm_write_input req = {0};
4164 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4165 rte_iova_t dma_handle;
4168 buf = rte_malloc("nvm_write", data_len, 0);
4172 dma_handle = rte_malloc_virt2iova(buf);
4173 if (dma_handle == RTE_BAD_IOVA) {
4175 "unable to map response address to physical memory\n");
4178 memcpy(buf, data, data_len);
4180 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4182 req.dir_type = rte_cpu_to_le_16(dir_type);
4183 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4184 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4185 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4186 req.dir_data_length = rte_cpu_to_le_32(data_len);
4187 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4189 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4192 HWRM_CHECK_RESULT();
4199 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4201 uint32_t *count = cbdata;
4203 *count = *count + 1;
4206 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4207 struct bnxt_vnic_info *vnic __rte_unused)
4212 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4216 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4217 &count, bnxt_vnic_count_hwrm_stub);
4222 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4225 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4226 struct hwrm_func_vf_vnic_ids_query_output *resp =
4227 bp->hwrm_cmd_resp_addr;
4230 /* First query all VNIC ids */
4231 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4233 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4234 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4235 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4237 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4240 "unable to map VNIC ID table address to physical memory\n");
4243 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4244 HWRM_CHECK_RESULT();
4245 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4253 * This function queries the VNIC IDs for a specified VF. It then calls
4254 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4255 * Then it calls the hwrm_cb function to program this new vnic configuration.
4257 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4258 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4259 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4261 struct bnxt_vnic_info vnic;
4263 int i, num_vnic_ids;
4268 /* First query all VNIC ids */
4269 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4270 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4271 RTE_CACHE_LINE_SIZE);
4272 if (vnic_ids == NULL)
4275 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4276 rte_mem_lock_page(((char *)vnic_ids) + sz);
4278 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4280 if (num_vnic_ids < 0)
4281 return num_vnic_ids;
4283 /* Retrieve VNIC, update bd_stall then update */
4285 for (i = 0; i < num_vnic_ids; i++) {
4286 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4287 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4288 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4291 if (vnic.mru <= 4) /* Indicates unallocated */
4294 vnic_cb(&vnic, cbdata);
4296 rc = hwrm_cb(bp, &vnic);
4306 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4309 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4310 struct hwrm_func_cfg_input req = {0};
4313 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4315 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4316 req.enables |= rte_cpu_to_le_32(
4317 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4318 req.vlan_antispoof_mode = on ?
4319 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4320 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4321 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4323 HWRM_CHECK_RESULT();
4329 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4331 struct bnxt_vnic_info vnic;
4334 int num_vnic_ids, i;
4338 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4339 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4340 RTE_CACHE_LINE_SIZE);
4341 if (vnic_ids == NULL)
4344 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4345 rte_mem_lock_page(((char *)vnic_ids) + sz);
4347 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4353 * Loop through to find the default VNIC ID.
4354 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4355 * by sending the hwrm_func_qcfg command to the firmware.
4357 for (i = 0; i < num_vnic_ids; i++) {
4358 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4359 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4360 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4361 bp->pf->first_vf_id + vf);
4364 if (vnic.func_default) {
4366 return vnic.fw_vnic_id;
4369 /* Could not find a default VNIC. */
4370 PMD_DRV_LOG(ERR, "No default VNIC\n");
4376 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4378 struct bnxt_filter_info *filter)
4381 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4382 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4383 uint32_t enables = 0;
4385 if (filter->fw_em_filter_id != UINT64_MAX)
4386 bnxt_hwrm_clear_em_filter(bp, filter);
4388 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4390 req.flags = rte_cpu_to_le_32(filter->flags);
4392 enables = filter->enables |
4393 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4394 req.dst_id = rte_cpu_to_le_16(dst_id);
4396 if (filter->ip_addr_type) {
4397 req.ip_addr_type = filter->ip_addr_type;
4398 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4401 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4402 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4404 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4405 memcpy(req.src_macaddr, filter->src_macaddr,
4406 RTE_ETHER_ADDR_LEN);
4408 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4409 memcpy(req.dst_macaddr, filter->dst_macaddr,
4410 RTE_ETHER_ADDR_LEN);
4412 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4413 req.ovlan_vid = filter->l2_ovlan;
4415 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4416 req.ivlan_vid = filter->l2_ivlan;
4418 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4419 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4421 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4422 req.ip_protocol = filter->ip_protocol;
4424 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4425 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4427 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4428 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4430 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4431 req.src_port = rte_cpu_to_be_16(filter->src_port);
4433 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4434 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4436 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4437 req.mirror_vnic_id = filter->mirror_vnic_id;
4439 req.enables = rte_cpu_to_le_32(enables);
4441 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4443 HWRM_CHECK_RESULT();
4445 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4451 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4454 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4455 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4457 if (filter->fw_em_filter_id == UINT64_MAX)
4460 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4462 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4464 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4466 HWRM_CHECK_RESULT();
4469 filter->fw_em_filter_id = UINT64_MAX;
4470 filter->fw_l2_filter_id = UINT64_MAX;
4475 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4477 struct bnxt_filter_info *filter)
4480 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4481 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4482 bp->hwrm_cmd_resp_addr;
4483 uint32_t enables = 0;
4485 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4486 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4488 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4490 req.flags = rte_cpu_to_le_32(filter->flags);
4492 enables = filter->enables |
4493 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4494 req.dst_id = rte_cpu_to_le_16(dst_id);
4496 if (filter->ip_addr_type) {
4497 req.ip_addr_type = filter->ip_addr_type;
4499 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4502 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4503 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4505 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4506 memcpy(req.src_macaddr, filter->src_macaddr,
4507 RTE_ETHER_ADDR_LEN);
4509 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4510 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4512 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4513 req.ip_protocol = filter->ip_protocol;
4515 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4516 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4518 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4519 req.src_ipaddr_mask[0] =
4520 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4522 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4523 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4525 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4526 req.dst_ipaddr_mask[0] =
4527 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4529 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4530 req.src_port = rte_cpu_to_le_16(filter->src_port);
4532 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4533 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4535 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4536 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4538 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4539 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4541 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4542 req.mirror_vnic_id = filter->mirror_vnic_id;
4544 req.enables = rte_cpu_to_le_32(enables);
4546 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4548 HWRM_CHECK_RESULT();
4550 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4551 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4557 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4558 struct bnxt_filter_info *filter)
4561 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4562 struct hwrm_cfa_ntuple_filter_free_output *resp =
4563 bp->hwrm_cmd_resp_addr;
4565 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4568 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4570 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4574 HWRM_CHECK_RESULT();
4577 filter->fw_ntuple_filter_id = UINT64_MAX;
4583 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4585 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4586 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4587 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4588 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4589 uint16_t *ring_tbl = vnic->rss_table;
4590 int nr_ctxs = vnic->num_lb_ctxts;
4591 int max_rings = bp->rx_nr_rings;
4595 for (i = 0, k = 0; i < nr_ctxs; i++) {
4596 struct bnxt_rx_ring_info *rxr;
4597 struct bnxt_cp_ring_info *cpr;
4599 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4601 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4602 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4603 req.hash_mode_flags = vnic->hash_mode;
4605 req.ring_grp_tbl_addr =
4606 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4607 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4608 2 * sizeof(*ring_tbl));
4609 req.hash_key_tbl_addr =
4610 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4612 req.ring_table_pair_index = i;
4613 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4615 for (j = 0; j < 64; j++) {
4618 /* Find next active ring. */
4619 for (cnt = 0; cnt < max_rings; cnt++) {
4620 if (rx_queue_state[k] !=
4621 RTE_ETH_QUEUE_STATE_STOPPED)
4623 if (++k == max_rings)
4627 /* Return if no rings are active. */
4628 if (cnt == max_rings) {
4633 /* Add rx/cp ring pair to RSS table. */
4634 rxr = rxqs[k]->rx_ring;
4635 cpr = rxqs[k]->cp_ring;
4637 ring_id = rxr->rx_ring_struct->fw_ring_id;
4638 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4639 ring_id = cpr->cp_ring_struct->fw_ring_id;
4640 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4642 if (++k == max_rings)
4645 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4648 HWRM_CHECK_RESULT();
4655 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4657 unsigned int rss_idx, fw_idx, i;
4659 if (!(vnic->rss_table && vnic->hash_type))
4662 if (BNXT_CHIP_THOR(bp))
4663 return bnxt_vnic_rss_configure_thor(bp, vnic);
4665 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4668 if (vnic->rss_table && vnic->hash_type) {
4670 * Fill the RSS hash & redirection table with
4671 * ring group ids for all VNICs
4673 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4674 rss_idx++, fw_idx++) {
4675 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4676 fw_idx %= bp->rx_cp_nr_rings;
4677 if (vnic->fw_grp_ids[fw_idx] !=
4682 if (i == bp->rx_cp_nr_rings)
4684 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4686 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4692 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4693 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4697 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4699 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4700 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4702 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4703 req->num_cmpl_dma_aggr_during_int =
4704 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4706 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4708 /* min timer set to 1/2 of interrupt timer */
4709 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4711 /* buf timer set to 1/4 of interrupt timer */
4712 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4714 req->cmpl_aggr_dma_tmr_during_int =
4715 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4717 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4718 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4719 req->flags = rte_cpu_to_le_16(flags);
4722 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4723 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4725 struct hwrm_ring_aggint_qcaps_input req = {0};
4726 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4731 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4732 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4733 HWRM_CHECK_RESULT();
4735 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4736 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4738 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4739 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4740 agg_req->flags = rte_cpu_to_le_16(flags);
4742 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4743 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4744 agg_req->enables = rte_cpu_to_le_32(enables);
4750 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4751 struct bnxt_coal *coal, uint16_t ring_id)
4753 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4754 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4755 bp->hwrm_cmd_resp_addr;
4758 /* Set ring coalesce parameters only for 100G NICs */
4759 if (BNXT_CHIP_THOR(bp)) {
4760 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4762 } else if (bnxt_stratus_device(bp)) {
4763 bnxt_hwrm_set_coal_params(coal, &req);
4769 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4771 req.ring_id = rte_cpu_to_le_16(ring_id);
4772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4773 HWRM_CHECK_RESULT();
4778 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4779 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4781 struct hwrm_func_backing_store_qcaps_input req = {0};
4782 struct hwrm_func_backing_store_qcaps_output *resp =
4783 bp->hwrm_cmd_resp_addr;
4784 struct bnxt_ctx_pg_info *ctx_pg;
4785 struct bnxt_ctx_mem_info *ctx;
4786 int total_alloc_len;
4787 int rc, i, tqm_rings;
4789 if (!BNXT_CHIP_THOR(bp) ||
4790 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4795 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4796 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4797 HWRM_CHECK_RESULT_SILENT();
4799 total_alloc_len = sizeof(*ctx);
4800 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4801 RTE_CACHE_LINE_SIZE);
4807 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4808 ctx->qp_min_qp1_entries =
4809 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4810 ctx->qp_max_l2_entries =
4811 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4812 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4813 ctx->srq_max_l2_entries =
4814 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4815 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4816 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4817 ctx->cq_max_l2_entries =
4818 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4819 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4820 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4821 ctx->vnic_max_vnic_entries =
4822 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4823 ctx->vnic_max_ring_table_entries =
4824 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4825 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4826 ctx->stat_max_entries =
4827 rte_le_to_cpu_32(resp->stat_max_entries);
4828 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4829 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4830 ctx->tqm_min_entries_per_ring =
4831 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4832 ctx->tqm_max_entries_per_ring =
4833 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4834 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4835 if (!ctx->tqm_entries_multiple)
4836 ctx->tqm_entries_multiple = 1;
4837 ctx->mrav_max_entries =
4838 rte_le_to_cpu_32(resp->mrav_max_entries);
4839 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4840 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4841 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4842 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4844 if (!ctx->tqm_fp_rings_count)
4845 ctx->tqm_fp_rings_count = bp->max_q;
4847 tqm_rings = ctx->tqm_fp_rings_count + 1;
4849 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4850 sizeof(*ctx_pg) * tqm_rings,
4851 RTE_CACHE_LINE_SIZE);
4856 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4857 ctx->tqm_mem[i] = ctx_pg;
4865 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4867 struct hwrm_func_backing_store_cfg_input req = {0};
4868 struct hwrm_func_backing_store_cfg_output *resp =
4869 bp->hwrm_cmd_resp_addr;
4870 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4871 struct bnxt_ctx_pg_info *ctx_pg;
4872 uint32_t *num_entries;
4881 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4882 req.enables = rte_cpu_to_le_32(enables);
4884 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4885 ctx_pg = &ctx->qp_mem;
4886 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4887 req.qp_num_qp1_entries =
4888 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4889 req.qp_num_l2_entries =
4890 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4891 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4892 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4893 &req.qpc_pg_size_qpc_lvl,
4897 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4898 ctx_pg = &ctx->srq_mem;
4899 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4900 req.srq_num_l2_entries =
4901 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4902 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4903 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4904 &req.srq_pg_size_srq_lvl,
4908 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4909 ctx_pg = &ctx->cq_mem;
4910 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4911 req.cq_num_l2_entries =
4912 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4913 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4914 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4915 &req.cq_pg_size_cq_lvl,
4919 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4920 ctx_pg = &ctx->vnic_mem;
4921 req.vnic_num_vnic_entries =
4922 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4923 req.vnic_num_ring_table_entries =
4924 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4925 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4926 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4927 &req.vnic_pg_size_vnic_lvl,
4928 &req.vnic_page_dir);
4931 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4932 ctx_pg = &ctx->stat_mem;
4933 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4934 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4935 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4936 &req.stat_pg_size_stat_lvl,
4937 &req.stat_page_dir);
4940 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4941 num_entries = &req.tqm_sp_num_entries;
4942 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4943 pg_dir = &req.tqm_sp_page_dir;
4944 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4945 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4946 if (!(enables & ena))
4949 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4951 ctx_pg = ctx->tqm_mem[i];
4952 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4953 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4956 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4957 HWRM_CHECK_RESULT();
4963 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4965 struct hwrm_port_qstats_ext_input req = {0};
4966 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4967 struct bnxt_pf_info *pf = bp->pf;
4970 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4971 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4974 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4976 req.port_id = rte_cpu_to_le_16(pf->port_id);
4977 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4978 req.tx_stat_host_addr =
4979 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4981 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4983 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4984 req.rx_stat_host_addr =
4985 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4987 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4989 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4992 bp->fw_rx_port_stats_ext_size = 0;
4993 bp->fw_tx_port_stats_ext_size = 0;
4995 bp->fw_rx_port_stats_ext_size =
4996 rte_le_to_cpu_16(resp->rx_stat_size);
4997 bp->fw_tx_port_stats_ext_size =
4998 rte_le_to_cpu_16(resp->tx_stat_size);
5001 HWRM_CHECK_RESULT();
5008 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5010 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5011 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5012 bp->hwrm_cmd_resp_addr;
5015 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5016 req.tunnel_type = type;
5017 req.dest_fid = bp->fw_fid;
5018 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5019 HWRM_CHECK_RESULT();
5027 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5029 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5030 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5031 bp->hwrm_cmd_resp_addr;
5034 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5035 req.tunnel_type = type;
5036 req.dest_fid = bp->fw_fid;
5037 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5038 HWRM_CHECK_RESULT();
5045 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5047 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5048 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5049 bp->hwrm_cmd_resp_addr;
5052 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5053 req.src_fid = bp->fw_fid;
5054 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5055 HWRM_CHECK_RESULT();
5058 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5065 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5068 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5069 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5070 bp->hwrm_cmd_resp_addr;
5073 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5074 req.src_fid = bp->fw_fid;
5075 req.tunnel_type = tun_type;
5076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5077 HWRM_CHECK_RESULT();
5080 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5082 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5089 int bnxt_hwrm_set_mac(struct bnxt *bp)
5091 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5092 struct hwrm_func_vf_cfg_input req = {0};
5098 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5101 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5102 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5104 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5106 HWRM_CHECK_RESULT();
5113 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5115 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5116 struct hwrm_func_drv_if_change_input req = {0};
5120 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5123 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5124 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5125 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5127 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5130 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5134 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5136 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5138 HWRM_CHECK_RESULT();
5139 flags = rte_le_to_cpu_32(resp->flags);
5145 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5146 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5147 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5153 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5155 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5156 struct bnxt_error_recovery_info *info = bp->recovery_info;
5157 struct hwrm_error_recovery_qcfg_input req = {0};
5162 /* Older FW does not have error recovery support */
5163 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5166 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5168 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5170 HWRM_CHECK_RESULT();
5172 flags = rte_le_to_cpu_32(resp->flags);
5173 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5174 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5175 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5176 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5178 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5179 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5184 /* FW returned values are in units of 100msec */
5185 info->driver_polling_freq =
5186 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5187 info->master_func_wait_period =
5188 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5189 info->normal_func_wait_period =
5190 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5191 info->master_func_wait_period_after_reset =
5192 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5193 info->max_bailout_time_after_reset =
5194 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5195 info->status_regs[BNXT_FW_STATUS_REG] =
5196 rte_le_to_cpu_32(resp->fw_health_status_reg);
5197 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5198 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5199 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5200 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5201 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5202 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5203 info->reg_array_cnt =
5204 rte_le_to_cpu_32(resp->reg_array_cnt);
5206 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5211 for (i = 0; i < info->reg_array_cnt; i++) {
5212 info->reset_reg[i] =
5213 rte_le_to_cpu_32(resp->reset_reg[i]);
5214 info->reset_reg_val[i] =
5215 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5216 info->delay_after_reset[i] =
5217 resp->delay_after_reset[i];
5222 /* Map the FW status registers */
5224 rc = bnxt_map_fw_health_status_regs(bp);
5227 rte_free(bp->recovery_info);
5228 bp->recovery_info = NULL;
5233 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5235 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5236 struct hwrm_fw_reset_input req = {0};
5242 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5244 req.embedded_proc_type =
5245 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5246 req.selfrst_status =
5247 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5248 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5250 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5253 HWRM_CHECK_RESULT();
5259 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5261 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5262 struct hwrm_port_ts_query_input req = {0};
5263 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5270 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5273 case BNXT_PTP_FLAGS_PATH_TX:
5274 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5276 case BNXT_PTP_FLAGS_PATH_RX:
5277 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5279 case BNXT_PTP_FLAGS_CURRENT_TIME:
5280 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5284 req.flags = rte_cpu_to_le_32(flags);
5285 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5287 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5289 HWRM_CHECK_RESULT();
5292 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5294 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5301 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5303 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5304 bp->hwrm_cmd_resp_addr;
5305 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5309 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5312 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5314 "Not a PF or trusted VF. Command not supported\n");
5318 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5319 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5321 HWRM_CHECK_RESULT();
5322 flags = rte_le_to_cpu_32(resp->flags);
5325 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5326 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5327 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5333 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5337 struct hwrm_cfa_counter_qcaps_input req = {0};
5338 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5340 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5342 "Not a PF or trusted VF. Command not supported\n");
5346 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5347 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5348 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5350 HWRM_CHECK_RESULT();
5352 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5358 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5361 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5362 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5364 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5366 "Not a PF or trusted VF. Command not supported\n");
5370 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5372 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5373 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5374 req.page_dir = rte_cpu_to_le_64(dma_addr);
5376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5378 HWRM_CHECK_RESULT();
5380 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5381 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5388 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5391 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5392 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5394 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5396 "Not a PF or trusted VF. Command not supported\n");
5400 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5402 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5404 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5406 HWRM_CHECK_RESULT();
5412 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5413 uint16_t cntr, uint16_t ctx_id,
5414 uint32_t num_entries, bool enable)
5416 struct hwrm_cfa_counter_cfg_input req = {0};
5417 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5421 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5423 "Not a PF or trusted VF. Command not supported\n");
5427 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5429 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5430 req.counter_type = rte_cpu_to_le_16(cntr);
5431 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5432 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5433 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5434 if (dir == BNXT_DIR_RX)
5435 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5436 else if (dir == BNXT_DIR_TX)
5437 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5438 req.flags = rte_cpu_to_le_16(flags);
5439 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5440 req.num_entries = rte_cpu_to_le_32(num_entries);
5442 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5443 HWRM_CHECK_RESULT();
5449 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5450 enum bnxt_flow_dir dir,
5452 uint16_t num_entries)
5454 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5455 struct hwrm_cfa_counter_qstats_input req = {0};
5456 uint16_t flow_ctx_id = 0;
5460 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5462 "Not a PF or trusted VF. Command not supported\n");
5466 if (dir == BNXT_DIR_RX) {
5467 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5468 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5469 } else if (dir == BNXT_DIR_TX) {
5470 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5471 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5474 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5475 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5476 req.counter_type = rte_cpu_to_le_16(cntr);
5477 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5478 req.num_entries = rte_cpu_to_le_16(num_entries);
5479 req.flags = rte_cpu_to_le_16(flags);
5480 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5482 HWRM_CHECK_RESULT();