1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
29 #define HWRM_CMD_TIMEOUT 10000
30 #define HWRM_VERSION_1_9_1 0x10901
32 struct bnxt_plcmodes_cfg {
34 uint16_t jumbo_thresh;
36 uint16_t hds_threshold;
39 static int page_getenum(size_t size)
55 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
56 return sizeof(void *) * 8 - 1;
59 static int page_roundup(size_t size)
61 return 1 << page_getenum(size);
65 * HWRM Functions (sent to HWRM)
66 * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
67 * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
68 * command was failed by the ChiMP.
71 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
75 struct input *req = msg;
76 struct output *resp = bp->hwrm_cmd_resp_addr;
80 uint16_t max_req_len = bp->max_req_len;
81 struct hwrm_short_input short_input = { 0 };
83 if (bp->flags & BNXT_FLAG_SHORT_CMD) {
84 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
86 memset(short_cmd_req, 0, bp->max_req_len);
87 memcpy(short_cmd_req, req, msg_len);
89 short_input.req_type = rte_cpu_to_le_16(req->req_type);
90 short_input.signature = rte_cpu_to_le_16(
91 HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
92 short_input.size = rte_cpu_to_le_16(msg_len);
93 short_input.req_addr =
94 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
96 data = (uint32_t *)&short_input;
97 msg_len = sizeof(short_input);
99 /* Sync memory write before updating doorbell */
102 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
105 /* Write request msg to hwrm channel */
106 for (i = 0; i < msg_len; i += 4) {
107 bar = (uint8_t *)bp->bar0 + i;
108 rte_write32(*data, bar);
112 /* Zero the rest of the request space */
113 for (; i < max_req_len; i += 4) {
114 bar = (uint8_t *)bp->bar0 + i;
118 /* Ring channel doorbell */
119 bar = (uint8_t *)bp->bar0 + 0x100;
122 /* Poll for the valid bit */
123 for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
124 /* Sanity check on the resp->resp_len */
126 if (resp->resp_len && resp->resp_len <=
128 /* Last byte of resp contains the valid key */
129 valid = (uint8_t *)resp + resp->resp_len - 1;
130 if (*valid == HWRM_RESP_VALID_KEY)
136 if (i >= HWRM_CMD_TIMEOUT) {
137 PMD_DRV_LOG(ERR, "Error sending msg 0x%04x\n",
148 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
149 * spinlock, and does initial processing.
151 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
152 * releases the spinlock only if it returns. If the regular int return codes
153 * are not used by the function, HWRM_CHECK_RESULT() should not be used
154 * directly, rather it should be copied and modified to suit the function.
156 * HWRM_UNLOCK() must be called after all response processing is completed.
158 #define HWRM_PREP(req, type) do { \
159 rte_spinlock_lock(&bp->hwrm_lock); \
160 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
161 req.req_type = rte_cpu_to_le_16(HWRM_##type); \
162 req.cmpl_ring = rte_cpu_to_le_16(-1); \
163 req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
164 req.target_id = rte_cpu_to_le_16(0xffff); \
165 req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
168 #define HWRM_CHECK_RESULT() do {\
170 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
171 rte_spinlock_unlock(&bp->hwrm_lock); \
174 if (resp->error_code) { \
175 rc = rte_le_to_cpu_16(resp->error_code); \
176 if (resp->resp_len >= 16) { \
177 struct hwrm_err_output *tmp_hwrm_err_op = \
180 "error %d:%d:%08x:%04x\n", \
181 rc, tmp_hwrm_err_op->cmd_err, \
183 tmp_hwrm_err_op->opaque_0), \
185 tmp_hwrm_err_op->opaque_1)); \
187 PMD_DRV_LOG(ERR, "error %d\n", rc); \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
194 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
196 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
199 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
200 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
202 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
203 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
206 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
214 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
215 struct bnxt_vnic_info *vnic,
217 struct bnxt_vlan_table_entry *vlan_table)
220 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
221 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
224 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
227 HWRM_PREP(req, CFA_L2_SET_RX_MASK);
228 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
230 /* FIXME add multicast flag, when multicast adding options is supported
233 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
234 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
235 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
236 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
237 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
238 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
239 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
240 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
241 if (vnic->flags & BNXT_VNIC_INFO_MCAST)
242 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
243 if (vnic->mc_addr_cnt) {
244 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
245 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
246 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
249 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
250 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
251 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
252 rte_mem_virt2iova(vlan_table));
253 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
255 req.mask = rte_cpu_to_le_32(mask);
257 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
265 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
267 struct bnxt_vlan_antispoof_table_entry *vlan_table)
270 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
271 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
272 bp->hwrm_cmd_resp_addr;
275 * Older HWRM versions did not support this command, and the set_rx_mask
276 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
277 * removed from set_rx_mask call, and this command was added.
279 * This command is also present from 1.7.8.11 and higher,
282 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
283 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
284 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
289 HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
290 req.fid = rte_cpu_to_le_16(fid);
292 req.vlan_tag_mask_tbl_addr =
293 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
294 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
304 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
305 struct bnxt_filter_info *filter)
308 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
309 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
311 if (filter->fw_l2_filter_id == UINT64_MAX)
314 HWRM_PREP(req, CFA_L2_FILTER_FREE);
316 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
323 filter->fw_l2_filter_id = UINT64_MAX;
328 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
330 struct bnxt_filter_info *filter)
333 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
334 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
335 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
336 const struct rte_eth_vmdq_rx_conf *conf =
337 &dev_conf->rx_adv_conf.vmdq_rx_conf;
338 uint32_t enables = 0;
339 uint16_t j = dst_id - 1;
341 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
342 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
343 conf->pool_map[j].pools & (1UL << j)) {
345 "Add vlan %u to vmdq pool %u\n",
346 conf->pool_map[j].vlan_id, j);
348 filter->l2_ivlan = conf->pool_map[j].vlan_id;
350 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
351 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
354 if (filter->fw_l2_filter_id != UINT64_MAX)
355 bnxt_hwrm_clear_l2_filter(bp, filter);
357 HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
359 req.flags = rte_cpu_to_le_32(filter->flags);
361 enables = filter->enables |
362 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
363 req.dst_id = rte_cpu_to_le_16(dst_id);
366 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
367 memcpy(req.l2_addr, filter->l2_addr,
370 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
371 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
374 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
375 req.l2_ovlan = filter->l2_ovlan;
377 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
378 req.l2_ovlan = filter->l2_ivlan;
380 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
381 req.l2_ovlan_mask = filter->l2_ovlan_mask;
383 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
384 req.l2_ovlan_mask = filter->l2_ivlan_mask;
385 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
386 req.src_id = rte_cpu_to_le_32(filter->src_id);
387 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
388 req.src_type = filter->src_type;
390 req.enables = rte_cpu_to_le_32(enables);
392 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
396 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
402 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
404 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
405 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
412 HWRM_PREP(req, PORT_MAC_CFG);
415 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
417 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
418 if (ptp->tx_tstamp_en)
419 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
421 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
422 req.flags = rte_cpu_to_le_32(flags);
424 rte_cpu_to_le_32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
425 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
427 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
433 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
436 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
437 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
438 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
440 /* if (bp->hwrm_spec_code < 0x10801 || ptp) TBD */
444 HWRM_PREP(req, PORT_MAC_PTP_QCFG);
446 req.port_id = rte_cpu_to_le_16(bp->pf.port_id);
448 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
452 if (!(resp->flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS))
455 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
459 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
460 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
461 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
462 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
463 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
464 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
465 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
466 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
467 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
468 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
469 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
470 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
471 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
472 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
473 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
474 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
475 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
476 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
484 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
487 struct hwrm_func_qcaps_input req = {.req_type = 0 };
488 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
489 uint16_t new_max_vfs;
493 HWRM_PREP(req, FUNC_QCAPS);
495 req.fid = rte_cpu_to_le_16(0xffff);
497 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
501 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
502 flags = rte_le_to_cpu_32(resp->flags);
504 bp->pf.port_id = resp->port_id;
505 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
506 new_max_vfs = bp->pdev->max_vfs;
507 if (new_max_vfs != bp->pf.max_vfs) {
509 rte_free(bp->pf.vf_info);
510 bp->pf.vf_info = rte_malloc("bnxt_vf_info",
511 sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
512 bp->pf.max_vfs = new_max_vfs;
513 for (i = 0; i < new_max_vfs; i++) {
514 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
515 bp->pf.vf_info[i].vlan_table =
516 rte_zmalloc("VF VLAN table",
519 if (bp->pf.vf_info[i].vlan_table == NULL)
521 "Fail to alloc VLAN table for VF %d\n",
525 bp->pf.vf_info[i].vlan_table);
526 bp->pf.vf_info[i].vlan_as_table =
527 rte_zmalloc("VF VLAN AS table",
530 if (bp->pf.vf_info[i].vlan_as_table == NULL)
532 "Alloc VLAN AS table for VF %d fail\n",
536 bp->pf.vf_info[i].vlan_as_table);
537 STAILQ_INIT(&bp->pf.vf_info[i].filter);
542 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
543 memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
544 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
545 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
546 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
547 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
548 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
549 /* TODO: For now, do not support VMDq/RFS on VFs. */
554 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
558 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
560 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
561 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
562 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
563 PMD_DRV_LOG(INFO, "PTP SUPPORTED\n");
565 bnxt_hwrm_ptp_qcfg(bp);
574 int bnxt_hwrm_func_reset(struct bnxt *bp)
577 struct hwrm_func_reset_input req = {.req_type = 0 };
578 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
580 HWRM_PREP(req, FUNC_RESET);
582 req.enables = rte_cpu_to_le_32(0);
584 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
592 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
595 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
596 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
598 if (bp->flags & BNXT_FLAG_REGISTERED)
601 HWRM_PREP(req, FUNC_DRV_RGTR);
602 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
603 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
604 req.ver_maj = RTE_VER_YEAR;
605 req.ver_min = RTE_VER_MONTH;
606 req.ver_upd = RTE_VER_MINOR;
609 req.enables |= rte_cpu_to_le_32(
610 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
611 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
612 RTE_MIN(sizeof(req.vf_req_fwd),
613 sizeof(bp->pf.vf_req_fwd)));
616 req.async_event_fwd[0] |=
617 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
618 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
619 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE);
620 req.async_event_fwd[1] |=
621 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
622 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
624 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
629 bp->flags |= BNXT_FLAG_REGISTERED;
634 int bnxt_hwrm_ver_get(struct bnxt *bp)
637 struct hwrm_ver_get_input req = {.req_type = 0 };
638 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
641 uint16_t max_resp_len;
642 char type[RTE_MEMZONE_NAMESIZE];
643 uint32_t dev_caps_cfg;
645 bp->max_req_len = HWRM_MAX_REQ_LEN;
646 HWRM_PREP(req, VER_GET);
648 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
649 req.hwrm_intf_min = HWRM_VERSION_MINOR;
650 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
652 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
656 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
657 resp->hwrm_intf_maj, resp->hwrm_intf_min,
659 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
660 bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
661 (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
662 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
663 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
665 my_version = HWRM_VERSION_MAJOR << 16;
666 my_version |= HWRM_VERSION_MINOR << 8;
667 my_version |= HWRM_VERSION_UPDATE;
669 fw_version = resp->hwrm_intf_maj << 16;
670 fw_version |= resp->hwrm_intf_min << 8;
671 fw_version |= resp->hwrm_intf_upd;
672 bp->hwrm_spec_code = fw_version;
674 if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
675 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
680 if (my_version != fw_version) {
681 PMD_DRV_LOG(INFO, "BNXT Driver/HWRM API mismatch.\n");
682 if (my_version < fw_version) {
684 "Firmware API version is newer than driver.\n");
686 "The driver may be missing features.\n");
689 "Firmware API version is older than driver.\n");
691 "Not all driver features may be functional.\n");
695 if (bp->max_req_len > resp->max_req_win_len) {
696 PMD_DRV_LOG(ERR, "Unsupported request length\n");
699 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
700 max_resp_len = resp->max_resp_len;
701 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
703 if (bp->max_resp_len != max_resp_len) {
704 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
705 bp->pdev->addr.domain, bp->pdev->addr.bus,
706 bp->pdev->addr.devid, bp->pdev->addr.function);
708 rte_free(bp->hwrm_cmd_resp_addr);
710 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
711 if (bp->hwrm_cmd_resp_addr == NULL) {
715 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
716 bp->hwrm_cmd_resp_dma_addr =
717 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
718 if (bp->hwrm_cmd_resp_dma_addr == 0) {
720 "Unable to map response buffer to physical memory.\n");
724 bp->max_resp_len = max_resp_len;
728 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
730 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
731 PMD_DRV_LOG(DEBUG, "Short command supported\n");
733 rte_free(bp->hwrm_short_cmd_req_addr);
735 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
737 if (bp->hwrm_short_cmd_req_addr == NULL) {
741 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
742 bp->hwrm_short_cmd_req_dma_addr =
743 rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
744 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
745 rte_free(bp->hwrm_short_cmd_req_addr);
747 "Unable to map buffer to physical memory.\n");
752 bp->flags |= BNXT_FLAG_SHORT_CMD;
760 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
763 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
764 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
766 if (!(bp->flags & BNXT_FLAG_REGISTERED))
769 HWRM_PREP(req, FUNC_DRV_UNRGTR);
772 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
777 bp->flags &= ~BNXT_FLAG_REGISTERED;
782 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
785 struct hwrm_port_phy_cfg_input req = {0};
786 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
787 uint32_t enables = 0;
789 HWRM_PREP(req, PORT_PHY_CFG);
792 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
793 if (bp->link_info.auto_mode && conf->link_speed) {
794 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
795 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
798 req.flags = rte_cpu_to_le_32(conf->phy_flags);
799 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
800 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
802 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
803 * any auto mode, even "none".
805 if (!conf->link_speed) {
806 /* No speeds specified. Enable AutoNeg - all speeds */
808 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
810 /* AutoNeg - Advertise speeds specified. */
811 if (conf->auto_link_speed_mask &&
812 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
814 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
815 req.auto_link_speed_mask =
816 conf->auto_link_speed_mask;
818 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
821 req.auto_duplex = conf->duplex;
822 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
823 req.auto_pause = conf->auto_pause;
824 req.force_pause = conf->force_pause;
825 /* Set force_pause if there is no auto or if there is a force */
826 if (req.auto_pause && !req.force_pause)
827 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
829 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
831 req.enables = rte_cpu_to_le_32(enables);
834 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
835 PMD_DRV_LOG(INFO, "Force Link Down\n");
838 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
846 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
847 struct bnxt_link_info *link_info)
850 struct hwrm_port_phy_qcfg_input req = {0};
851 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
853 HWRM_PREP(req, PORT_PHY_QCFG);
855 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
859 link_info->phy_link_status = resp->link;
861 (link_info->phy_link_status ==
862 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
863 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
864 link_info->duplex = resp->duplex_cfg;
865 link_info->pause = resp->pause;
866 link_info->auto_pause = resp->auto_pause;
867 link_info->force_pause = resp->force_pause;
868 link_info->auto_mode = resp->auto_mode;
869 link_info->phy_type = resp->phy_type;
870 link_info->media_type = resp->media_type;
872 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
873 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
874 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
875 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
876 link_info->phy_ver[0] = resp->phy_maj;
877 link_info->phy_ver[1] = resp->phy_min;
878 link_info->phy_ver[2] = resp->phy_bld;
882 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
883 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
884 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
885 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
886 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
887 link_info->auto_link_speed_mask);
888 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
889 link_info->force_link_speed);
894 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
897 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
898 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
901 HWRM_PREP(req, QUEUE_QPORTCFG);
903 req.flags = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
904 /* HWRM Version >= 1.9.1 */
905 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1)
907 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
912 #define GET_QUEUE_INFO(x) \
913 bp->cos_queue[x].id = resp->queue_id##x; \
914 bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
927 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
928 bp->tx_cosq_id = bp->cos_queue[0].id;
930 /* iterate and find the COSq profile to use for Tx */
931 for (i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
932 if (bp->cos_queue[i].profile ==
933 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
934 bp->tx_cosq_id = bp->cos_queue[i].id;
939 PMD_DRV_LOG(DEBUG, "Tx Cos Queue to use: %d\n", bp->tx_cosq_id);
944 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
945 struct bnxt_ring *ring,
946 uint32_t ring_type, uint32_t map_index,
947 uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
950 uint32_t enables = 0;
951 struct hwrm_ring_alloc_input req = {.req_type = 0 };
952 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
954 HWRM_PREP(req, RING_ALLOC);
956 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
957 req.fbo = rte_cpu_to_le_32(0);
958 /* Association of ring index with doorbell index */
959 req.logical_id = rte_cpu_to_le_16(map_index);
960 req.length = rte_cpu_to_le_32(ring->ring_size);
963 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
964 req.queue_id = rte_cpu_to_le_16(bp->tx_cosq_id);
966 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
967 req.ring_type = ring_type;
968 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
969 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
970 if (stats_ctx_id != INVALID_STATS_CTX_ID)
972 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
974 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
975 req.ring_type = ring_type;
977 * TODO: Some HWRM versions crash with
978 * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
980 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
983 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
988 req.enables = rte_cpu_to_le_32(enables);
990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
992 if (rc || resp->error_code) {
993 if (rc == 0 && resp->error_code)
994 rc = rte_le_to_cpu_16(resp->error_code);
996 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
998 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1001 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1003 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1006 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1008 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1012 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1018 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1023 int bnxt_hwrm_ring_free(struct bnxt *bp,
1024 struct bnxt_ring *ring, uint32_t ring_type)
1027 struct hwrm_ring_free_input req = {.req_type = 0 };
1028 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1030 HWRM_PREP(req, RING_FREE);
1032 req.ring_type = ring_type;
1033 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1035 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1037 if (rc || resp->error_code) {
1038 if (rc == 0 && resp->error_code)
1039 rc = rte_le_to_cpu_16(resp->error_code);
1042 switch (ring_type) {
1043 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1044 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1047 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1048 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1051 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1052 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1056 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1064 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1067 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1068 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1070 HWRM_PREP(req, RING_GRP_ALLOC);
1072 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1073 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1074 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1075 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1077 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1079 HWRM_CHECK_RESULT();
1081 bp->grp_info[idx].fw_grp_id =
1082 rte_le_to_cpu_16(resp->ring_group_id);
1089 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1092 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1093 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1095 HWRM_PREP(req, RING_GRP_FREE);
1097 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1101 HWRM_CHECK_RESULT();
1104 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1108 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1111 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1112 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1114 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1117 HWRM_PREP(req, STAT_CTX_CLR_STATS);
1119 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1121 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1123 HWRM_CHECK_RESULT();
1129 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1130 unsigned int idx __rte_unused)
1133 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1134 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1136 HWRM_PREP(req, STAT_CTX_ALLOC);
1138 req.update_period_ms = rte_cpu_to_le_32(0);
1140 req.stats_dma_addr =
1141 rte_cpu_to_le_64(cpr->hw_stats_map);
1143 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1145 HWRM_CHECK_RESULT();
1147 cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1154 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1155 unsigned int idx __rte_unused)
1158 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1159 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1161 HWRM_PREP(req, STAT_CTX_FREE);
1163 req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1165 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1167 HWRM_CHECK_RESULT();
1173 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1176 struct hwrm_vnic_alloc_input req = { 0 };
1177 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1179 /* map ring groups to this vnic */
1180 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1181 vnic->start_grp_id, vnic->end_grp_id);
1182 for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1183 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1184 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1185 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1186 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1187 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1188 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1189 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1190 HWRM_PREP(req, VNIC_ALLOC);
1192 if (vnic->func_default)
1194 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1195 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1197 HWRM_CHECK_RESULT();
1199 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1201 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1205 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1206 struct bnxt_vnic_info *vnic,
1207 struct bnxt_plcmodes_cfg *pmode)
1210 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1211 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1213 HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1215 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1217 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1219 HWRM_CHECK_RESULT();
1221 pmode->flags = rte_le_to_cpu_32(resp->flags);
1222 /* dflt_vnic bit doesn't exist in the _cfg command */
1223 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1224 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1225 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1226 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1233 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1234 struct bnxt_vnic_info *vnic,
1235 struct bnxt_plcmodes_cfg *pmode)
1238 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1239 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1241 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1243 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1244 req.flags = rte_cpu_to_le_32(pmode->flags);
1245 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1246 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1247 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1248 req.enables = rte_cpu_to_le_32(
1249 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1250 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1251 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1254 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1256 HWRM_CHECK_RESULT();
1262 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1265 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1266 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1267 uint32_t ctx_enable_flag = 0;
1268 struct bnxt_plcmodes_cfg pmodes;
1270 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1271 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1275 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1279 HWRM_PREP(req, VNIC_CFG);
1281 /* Only RSS support for now TBD: COS & LB */
1283 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1284 if (vnic->lb_rule != 0xffff)
1285 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1286 if (vnic->cos_rule != 0xffff)
1287 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1288 if (vnic->rss_rule != 0xffff) {
1289 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1290 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1292 req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1293 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1294 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1295 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1296 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1297 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1298 req.mru = rte_cpu_to_le_16(vnic->mru);
1299 if (vnic->func_default)
1301 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1302 if (vnic->vlan_strip)
1304 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1307 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1308 if (vnic->roce_dual)
1309 req.flags |= rte_cpu_to_le_32(
1310 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1311 if (vnic->roce_only)
1312 req.flags |= rte_cpu_to_le_32(
1313 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1314 if (vnic->rss_dflt_cr)
1315 req.flags |= rte_cpu_to_le_32(
1316 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1318 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1320 HWRM_CHECK_RESULT();
1323 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1328 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1332 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1333 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1335 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1336 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1339 HWRM_PREP(req, VNIC_QCFG);
1342 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1343 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1344 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1348 HWRM_CHECK_RESULT();
1350 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1351 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1352 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1353 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1354 vnic->mru = rte_le_to_cpu_16(resp->mru);
1355 vnic->func_default = rte_le_to_cpu_32(
1356 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1357 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1358 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1359 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1360 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1361 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1362 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1363 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1364 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1365 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1366 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1373 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1376 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1377 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1378 bp->hwrm_cmd_resp_addr;
1380 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1382 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1384 HWRM_CHECK_RESULT();
1386 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1388 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1393 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1396 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1397 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1398 bp->hwrm_cmd_resp_addr;
1400 if (vnic->rss_rule == 0xffff) {
1401 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
1404 HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1406 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1408 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1410 HWRM_CHECK_RESULT();
1413 vnic->rss_rule = INVALID_HW_RING_ID;
1418 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1421 struct hwrm_vnic_free_input req = {.req_type = 0 };
1422 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1424 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1425 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1429 HWRM_PREP(req, VNIC_FREE);
1431 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1433 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1435 HWRM_CHECK_RESULT();
1438 vnic->fw_vnic_id = INVALID_HW_RING_ID;
1442 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1443 struct bnxt_vnic_info *vnic)
1446 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1447 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1449 HWRM_PREP(req, VNIC_RSS_CFG);
1451 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1453 req.ring_grp_tbl_addr =
1454 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1455 req.hash_key_tbl_addr =
1456 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1457 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1459 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1461 HWRM_CHECK_RESULT();
1467 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1468 struct bnxt_vnic_info *vnic)
1471 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1472 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1475 HWRM_PREP(req, VNIC_PLCMODES_CFG);
1477 req.flags = rte_cpu_to_le_32(
1478 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1480 req.enables = rte_cpu_to_le_32(
1481 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1483 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1484 size -= RTE_PKTMBUF_HEADROOM;
1486 req.jumbo_thresh = rte_cpu_to_le_16(size);
1487 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1489 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1491 HWRM_CHECK_RESULT();
1497 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1498 struct bnxt_vnic_info *vnic, bool enable)
1501 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1502 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1504 HWRM_PREP(req, VNIC_TPA_CFG);
1507 req.enables = rte_cpu_to_le_32(
1508 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1509 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1510 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1511 req.flags = rte_cpu_to_le_32(
1512 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1513 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1514 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1515 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1516 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1517 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1518 req.max_agg_segs = rte_cpu_to_le_16(5);
1520 rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1521 req.min_agg_len = rte_cpu_to_le_32(512);
1523 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1525 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1527 HWRM_CHECK_RESULT();
1533 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1535 struct hwrm_func_cfg_input req = {0};
1536 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1539 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1540 req.enables = rte_cpu_to_le_32(
1541 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1542 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1543 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1545 HWRM_PREP(req, FUNC_CFG);
1547 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1548 HWRM_CHECK_RESULT();
1551 bp->pf.vf_info[vf].random_mac = false;
1556 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1560 struct hwrm_func_qstats_input req = {.req_type = 0};
1561 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1563 HWRM_PREP(req, FUNC_QSTATS);
1565 req.fid = rte_cpu_to_le_16(fid);
1567 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1569 HWRM_CHECK_RESULT();
1572 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1579 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1580 struct rte_eth_stats *stats)
1583 struct hwrm_func_qstats_input req = {.req_type = 0};
1584 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1586 HWRM_PREP(req, FUNC_QSTATS);
1588 req.fid = rte_cpu_to_le_16(fid);
1590 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1592 HWRM_CHECK_RESULT();
1594 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1595 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1596 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1597 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1598 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1599 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1601 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1602 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1603 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1604 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1605 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1606 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1608 stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1609 stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1611 stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1618 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1621 struct hwrm_func_clr_stats_input req = {.req_type = 0};
1622 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1624 HWRM_PREP(req, FUNC_CLR_STATS);
1626 req.fid = rte_cpu_to_le_16(fid);
1628 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1630 HWRM_CHECK_RESULT();
1637 * HWRM utility functions
1640 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1645 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1646 struct bnxt_tx_queue *txq;
1647 struct bnxt_rx_queue *rxq;
1648 struct bnxt_cp_ring_info *cpr;
1650 if (i >= bp->rx_cp_nr_rings) {
1651 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1654 rxq = bp->rx_queues[i];
1658 rc = bnxt_hwrm_stat_clear(bp, cpr);
1665 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1669 struct bnxt_cp_ring_info *cpr;
1671 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1673 if (i >= bp->rx_cp_nr_rings) {
1674 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1676 cpr = bp->rx_queues[i]->cp_ring;
1677 bp->grp_info[i].fw_stats_ctx = -1;
1679 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1680 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1681 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1689 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1694 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1695 struct bnxt_tx_queue *txq;
1696 struct bnxt_rx_queue *rxq;
1697 struct bnxt_cp_ring_info *cpr;
1699 if (i >= bp->rx_cp_nr_rings) {
1700 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1703 rxq = bp->rx_queues[i];
1707 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1715 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1720 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1722 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1725 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1733 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1734 unsigned int idx __rte_unused)
1736 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1738 bnxt_hwrm_ring_free(bp, cp_ring,
1739 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1740 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1741 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1742 sizeof(*cpr->cp_desc_ring));
1743 cpr->cp_raw_cons = 0;
1746 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1751 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1752 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1753 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1754 struct bnxt_ring *ring = txr->tx_ring_struct;
1755 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1756 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1758 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1759 bnxt_hwrm_ring_free(bp, ring,
1760 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1761 ring->fw_ring_id = INVALID_HW_RING_ID;
1762 memset(txr->tx_desc_ring, 0,
1763 txr->tx_ring_struct->ring_size *
1764 sizeof(*txr->tx_desc_ring));
1765 memset(txr->tx_buf_ring, 0,
1766 txr->tx_ring_struct->ring_size *
1767 sizeof(*txr->tx_buf_ring));
1771 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1772 bnxt_free_cp_ring(bp, cpr, idx);
1773 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1777 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1778 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1779 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1780 struct bnxt_ring *ring = rxr->rx_ring_struct;
1781 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1782 unsigned int idx = i + 1;
1784 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1785 bnxt_hwrm_ring_free(bp, ring,
1786 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1787 ring->fw_ring_id = INVALID_HW_RING_ID;
1788 bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1789 memset(rxr->rx_desc_ring, 0,
1790 rxr->rx_ring_struct->ring_size *
1791 sizeof(*rxr->rx_desc_ring));
1792 memset(rxr->rx_buf_ring, 0,
1793 rxr->rx_ring_struct->ring_size *
1794 sizeof(*rxr->rx_buf_ring));
1797 ring = rxr->ag_ring_struct;
1798 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1799 bnxt_hwrm_ring_free(bp, ring,
1800 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1801 ring->fw_ring_id = INVALID_HW_RING_ID;
1802 memset(rxr->ag_buf_ring, 0,
1803 rxr->ag_ring_struct->ring_size *
1804 sizeof(*rxr->ag_buf_ring));
1806 bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1808 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1809 bnxt_free_cp_ring(bp, cpr, idx);
1810 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1811 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1815 /* Default completion ring */
1817 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1819 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1820 bnxt_free_cp_ring(bp, cpr, 0);
1821 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1828 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1833 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1834 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1841 void bnxt_free_hwrm_resources(struct bnxt *bp)
1843 /* Release memzone */
1844 rte_free(bp->hwrm_cmd_resp_addr);
1845 rte_free(bp->hwrm_short_cmd_req_addr);
1846 bp->hwrm_cmd_resp_addr = NULL;
1847 bp->hwrm_short_cmd_req_addr = NULL;
1848 bp->hwrm_cmd_resp_dma_addr = 0;
1849 bp->hwrm_short_cmd_req_dma_addr = 0;
1852 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1854 struct rte_pci_device *pdev = bp->pdev;
1855 char type[RTE_MEMZONE_NAMESIZE];
1857 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1858 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1859 bp->max_resp_len = HWRM_MAX_RESP_LEN;
1860 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1861 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1862 if (bp->hwrm_cmd_resp_addr == NULL)
1864 bp->hwrm_cmd_resp_dma_addr =
1865 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1866 if (bp->hwrm_cmd_resp_dma_addr == 0) {
1868 "unable to map response address to physical memory\n");
1871 rte_spinlock_init(&bp->hwrm_lock);
1876 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1878 struct bnxt_filter_info *filter;
1881 STAILQ_FOREACH(filter, &vnic->filter, next) {
1882 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1883 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1884 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1885 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1887 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1895 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1897 struct bnxt_filter_info *filter;
1898 struct rte_flow *flow;
1901 STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1902 filter = flow->filter;
1903 PMD_DRV_LOG(ERR, "filter type %d\n", filter->filter_type);
1904 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1905 rc = bnxt_hwrm_clear_em_filter(bp, filter);
1906 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1907 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1909 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1911 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1919 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1921 struct bnxt_filter_info *filter;
1924 STAILQ_FOREACH(filter, &vnic->filter, next) {
1925 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1926 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1928 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1929 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1932 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1940 void bnxt_free_tunnel_ports(struct bnxt *bp)
1942 if (bp->vxlan_port_cnt)
1943 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1944 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1946 if (bp->geneve_port_cnt)
1947 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1948 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1949 bp->geneve_port = 0;
1952 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1956 if (bp->vnic_info == NULL)
1960 * Cleanup VNICs in reverse order, to make sure the L2 filter
1961 * from vnic0 is last to be cleaned up.
1963 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1964 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1966 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1968 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1970 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1972 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1974 bnxt_hwrm_vnic_free(bp, vnic);
1976 /* Ring resources */
1977 bnxt_free_all_hwrm_rings(bp);
1978 bnxt_free_all_hwrm_ring_grps(bp);
1979 bnxt_free_all_hwrm_stat_ctxs(bp);
1980 bnxt_free_tunnel_ports(bp);
1983 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1985 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1987 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1988 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1990 switch (conf_link_speed) {
1991 case ETH_LINK_SPEED_10M_HD:
1992 case ETH_LINK_SPEED_100M_HD:
1993 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1995 return hw_link_duplex;
1998 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2000 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2003 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2005 uint16_t eth_link_speed = 0;
2007 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2008 return ETH_LINK_SPEED_AUTONEG;
2010 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2011 case ETH_LINK_SPEED_100M:
2012 case ETH_LINK_SPEED_100M_HD:
2014 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2016 case ETH_LINK_SPEED_1G:
2018 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2020 case ETH_LINK_SPEED_2_5G:
2022 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2024 case ETH_LINK_SPEED_10G:
2026 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2028 case ETH_LINK_SPEED_20G:
2030 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2032 case ETH_LINK_SPEED_25G:
2034 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2036 case ETH_LINK_SPEED_40G:
2038 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2040 case ETH_LINK_SPEED_50G:
2042 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2044 case ETH_LINK_SPEED_100G:
2046 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2050 "Unsupported link speed %d; default to AUTO\n",
2054 return eth_link_speed;
2057 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2058 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2059 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2060 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G)
2062 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2066 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2069 if (link_speed & ETH_LINK_SPEED_FIXED) {
2070 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2072 if (one_speed & (one_speed - 1)) {
2074 "Invalid advertised speeds (%u) for port %u\n",
2075 link_speed, port_id);
2078 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2080 "Unsupported advertised speed (%u) for port %u\n",
2081 link_speed, port_id);
2085 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2087 "Unsupported advertised speeds (%u) for port %u\n",
2088 link_speed, port_id);
2096 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2100 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2101 if (bp->link_info.support_speeds)
2102 return bp->link_info.support_speeds;
2103 link_speed = BNXT_SUPPORTED_SPEEDS;
2106 if (link_speed & ETH_LINK_SPEED_100M)
2107 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2108 if (link_speed & ETH_LINK_SPEED_100M_HD)
2109 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2110 if (link_speed & ETH_LINK_SPEED_1G)
2111 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2112 if (link_speed & ETH_LINK_SPEED_2_5G)
2113 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2114 if (link_speed & ETH_LINK_SPEED_10G)
2115 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2116 if (link_speed & ETH_LINK_SPEED_20G)
2117 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2118 if (link_speed & ETH_LINK_SPEED_25G)
2119 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2120 if (link_speed & ETH_LINK_SPEED_40G)
2121 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2122 if (link_speed & ETH_LINK_SPEED_50G)
2123 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2124 if (link_speed & ETH_LINK_SPEED_100G)
2125 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2129 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2131 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2133 switch (hw_link_speed) {
2134 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2135 eth_link_speed = ETH_SPEED_NUM_100M;
2137 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2138 eth_link_speed = ETH_SPEED_NUM_1G;
2140 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2141 eth_link_speed = ETH_SPEED_NUM_2_5G;
2143 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2144 eth_link_speed = ETH_SPEED_NUM_10G;
2146 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2147 eth_link_speed = ETH_SPEED_NUM_20G;
2149 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2150 eth_link_speed = ETH_SPEED_NUM_25G;
2152 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2153 eth_link_speed = ETH_SPEED_NUM_40G;
2155 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2156 eth_link_speed = ETH_SPEED_NUM_50G;
2158 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2159 eth_link_speed = ETH_SPEED_NUM_100G;
2161 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2163 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2167 return eth_link_speed;
2170 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2172 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2174 switch (hw_link_duplex) {
2175 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2176 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2177 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2179 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2180 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2183 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2187 return eth_link_duplex;
2190 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2193 struct bnxt_link_info *link_info = &bp->link_info;
2195 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2198 "Get link config failed with rc %d\n", rc);
2201 if (link_info->link_speed)
2203 bnxt_parse_hw_link_speed(link_info->link_speed);
2205 link->link_speed = ETH_SPEED_NUM_NONE;
2206 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2207 link->link_status = link_info->link_up;
2208 link->link_autoneg = link_info->auto_mode ==
2209 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2210 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2215 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2218 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2219 struct bnxt_link_info link_req;
2220 uint16_t speed, autoneg;
2222 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2225 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2226 bp->eth_dev->data->port_id);
2230 memset(&link_req, 0, sizeof(link_req));
2231 link_req.link_up = link_up;
2235 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2236 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2237 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2238 /* Autoneg can be done only when the FW allows */
2239 if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2240 bp->link_info.force_link_speed)) {
2241 link_req.phy_flags |=
2242 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2243 link_req.auto_link_speed_mask =
2244 bnxt_parse_eth_link_speed_mask(bp,
2245 dev_conf->link_speeds);
2247 if (bp->link_info.phy_type ==
2248 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2249 bp->link_info.phy_type ==
2250 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2251 bp->link_info.media_type ==
2252 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2253 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
2257 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2258 /* If user wants a particular speed try that first. */
2260 link_req.link_speed = speed;
2261 else if (bp->link_info.force_link_speed)
2262 link_req.link_speed = bp->link_info.force_link_speed;
2264 link_req.link_speed = bp->link_info.auto_link_speed;
2266 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2267 link_req.auto_pause = bp->link_info.auto_pause;
2268 link_req.force_pause = bp->link_info.force_pause;
2271 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2274 "Set link config failed with rc %d\n", rc);
2282 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2284 struct hwrm_func_qcfg_input req = {0};
2285 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2289 HWRM_PREP(req, FUNC_QCFG);
2290 req.fid = rte_cpu_to_le_16(0xffff);
2292 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2294 HWRM_CHECK_RESULT();
2296 /* Hard Coded.. 0xfff VLAN ID mask */
2297 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2298 flags = rte_le_to_cpu_16(resp->flags);
2299 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
2300 bp->flags |= BNXT_FLAG_MULTI_HOST;
2302 switch (resp->port_partition_type) {
2303 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2304 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2305 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2306 bp->port_partition_type = resp->port_partition_type;
2309 bp->port_partition_type = 0;
2318 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2319 struct hwrm_func_qcaps_output *qcaps)
2321 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2322 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2323 sizeof(qcaps->mac_address));
2324 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2325 qcaps->max_rx_rings = fcfg->num_rx_rings;
2326 qcaps->max_tx_rings = fcfg->num_tx_rings;
2327 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2328 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2330 qcaps->first_vf_id = 0;
2331 qcaps->max_vnics = fcfg->num_vnics;
2332 qcaps->max_decap_records = 0;
2333 qcaps->max_encap_records = 0;
2334 qcaps->max_tx_wm_flows = 0;
2335 qcaps->max_tx_em_flows = 0;
2336 qcaps->max_rx_wm_flows = 0;
2337 qcaps->max_rx_em_flows = 0;
2338 qcaps->max_flow_id = 0;
2339 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2340 qcaps->max_sp_tx_rings = 0;
2341 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2344 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2346 struct hwrm_func_cfg_input req = {0};
2347 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2350 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2351 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2352 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2353 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2354 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2355 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2356 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2357 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2358 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2359 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2360 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2361 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2362 req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2363 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2364 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2365 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2366 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2367 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2368 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2369 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2370 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2371 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2372 req.fid = rte_cpu_to_le_16(0xffff);
2374 HWRM_PREP(req, FUNC_CFG);
2376 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2378 HWRM_CHECK_RESULT();
2384 static void populate_vf_func_cfg_req(struct bnxt *bp,
2385 struct hwrm_func_cfg_input *req,
2388 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2389 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2390 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2391 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2392 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2393 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2394 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2395 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2396 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2397 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2399 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2400 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2401 req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2402 ETHER_CRC_LEN + VLAN_TAG_SIZE);
2403 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2405 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2406 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2408 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2409 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2410 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2411 /* TODO: For now, do not support VMDq/RFS on VFs. */
2412 req->num_vnics = rte_cpu_to_le_16(1);
2413 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2417 static void add_random_mac_if_needed(struct bnxt *bp,
2418 struct hwrm_func_cfg_input *cfg_req,
2421 struct ether_addr mac;
2423 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2426 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2428 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2429 eth_random_addr(cfg_req->dflt_mac_addr);
2430 bp->pf.vf_info[vf].random_mac = true;
2432 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2436 static void reserve_resources_from_vf(struct bnxt *bp,
2437 struct hwrm_func_cfg_input *cfg_req,
2440 struct hwrm_func_qcaps_input req = {0};
2441 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2444 /* Get the actual allocated values now */
2445 HWRM_PREP(req, FUNC_QCAPS);
2446 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2447 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2450 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
2451 copy_func_cfg_to_qcaps(cfg_req, resp);
2452 } else if (resp->error_code) {
2453 rc = rte_le_to_cpu_16(resp->error_code);
2454 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
2455 copy_func_cfg_to_qcaps(cfg_req, resp);
2458 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2459 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2460 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2461 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2462 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2463 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2465 * TODO: While not supporting VMDq with VFs, max_vnics is always
2466 * forced to 1 in this case
2468 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2469 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2474 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2476 struct hwrm_func_qcfg_input req = {0};
2477 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2480 /* Check for zero MAC address */
2481 HWRM_PREP(req, FUNC_QCFG);
2482 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2483 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2485 PMD_DRV_LOG(ERR, "hwrm_func_qcfg failed rc:%d\n", rc);
2487 } else if (resp->error_code) {
2488 rc = rte_le_to_cpu_16(resp->error_code);
2489 PMD_DRV_LOG(ERR, "hwrm_func_qcfg error %d\n", rc);
2492 rc = rte_le_to_cpu_16(resp->vlan);
2499 static int update_pf_resource_max(struct bnxt *bp)
2501 struct hwrm_func_qcfg_input req = {0};
2502 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2505 /* And copy the allocated numbers into the pf struct */
2506 HWRM_PREP(req, FUNC_QCFG);
2507 req.fid = rte_cpu_to_le_16(0xffff);
2508 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2509 HWRM_CHECK_RESULT();
2511 /* Only TX ring value reflects actual allocation? TODO */
2512 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2513 bp->pf.evb_mode = resp->evb_mode;
2520 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2525 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2529 rc = bnxt_hwrm_func_qcaps(bp);
2533 bp->pf.func_cfg_flags &=
2534 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2535 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2536 bp->pf.func_cfg_flags |=
2537 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2538 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2542 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2544 struct hwrm_func_cfg_input req = {0};
2545 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2552 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
2556 rc = bnxt_hwrm_func_qcaps(bp);
2561 bp->pf.active_vfs = num_vfs;
2564 * First, configure the PF to only use one TX ring. This ensures that
2565 * there are enough rings for all VFs.
2567 * If we don't do this, when we call func_alloc() later, we will lock
2568 * extra rings to the PF that won't be available during func_cfg() of
2571 * This has been fixed with firmware versions above 20.6.54
2573 bp->pf.func_cfg_flags &=
2574 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2575 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2576 bp->pf.func_cfg_flags |=
2577 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2578 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2583 * Now, create and register a buffer to hold forwarded VF requests
2585 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2586 bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2587 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2588 if (bp->pf.vf_req_buf == NULL) {
2592 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2593 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2594 for (i = 0; i < num_vfs; i++)
2595 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2596 (i * HWRM_MAX_REQ_LEN);
2598 rc = bnxt_hwrm_func_buf_rgtr(bp);
2602 populate_vf_func_cfg_req(bp, &req, num_vfs);
2604 bp->pf.active_vfs = 0;
2605 for (i = 0; i < num_vfs; i++) {
2606 add_random_mac_if_needed(bp, &req, i);
2608 HWRM_PREP(req, FUNC_CFG);
2609 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2610 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2613 /* Clear enable flag for next pass */
2614 req.enables &= ~rte_cpu_to_le_32(
2615 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2617 if (rc || resp->error_code) {
2619 "Failed to initizlie VF %d\n", i);
2621 "Not all VFs available. (%d, %d)\n",
2622 rc, resp->error_code);
2629 reserve_resources_from_vf(bp, &req, i);
2630 bp->pf.active_vfs++;
2631 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2635 * Now configure the PF to use "the rest" of the resources
2636 * We're using STD_TX_RING_MODE here though which will limit the TX
2637 * rings. This will allow QoS to function properly. Not setting this
2638 * will cause PF rings to break bandwidth settings.
2640 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2644 rc = update_pf_resource_max(bp);
2651 bnxt_hwrm_func_buf_unrgtr(bp);
2655 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2657 struct hwrm_func_cfg_input req = {0};
2658 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2661 HWRM_PREP(req, FUNC_CFG);
2663 req.fid = rte_cpu_to_le_16(0xffff);
2664 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2665 req.evb_mode = bp->pf.evb_mode;
2667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2668 HWRM_CHECK_RESULT();
2674 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2675 uint8_t tunnel_type)
2677 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2678 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2681 HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2682 req.tunnel_type = tunnel_type;
2683 req.tunnel_dst_port_val = port;
2684 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2685 HWRM_CHECK_RESULT();
2687 switch (tunnel_type) {
2688 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2689 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2690 bp->vxlan_port = port;
2692 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2693 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2694 bp->geneve_port = port;
2705 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2706 uint8_t tunnel_type)
2708 struct hwrm_tunnel_dst_port_free_input req = {0};
2709 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2712 HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2714 req.tunnel_type = tunnel_type;
2715 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2716 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2718 HWRM_CHECK_RESULT();
2724 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2727 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2728 struct hwrm_func_cfg_input req = {0};
2731 HWRM_PREP(req, FUNC_CFG);
2733 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2734 req.flags = rte_cpu_to_le_32(flags);
2735 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2737 HWRM_CHECK_RESULT();
2743 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2745 uint32_t *flag = flagp;
2747 vnic->flags = *flag;
2750 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2752 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2755 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2758 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2759 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2761 HWRM_PREP(req, FUNC_BUF_RGTR);
2763 req.req_buf_num_pages = rte_cpu_to_le_16(1);
2764 req.req_buf_page_size = rte_cpu_to_le_16(
2765 page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2766 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2767 req.req_buf_page_addr[0] =
2768 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2769 if (req.req_buf_page_addr[0] == 0) {
2771 "unable to map buffer address to physical memory\n");
2775 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2777 HWRM_CHECK_RESULT();
2783 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2786 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2787 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2789 HWRM_PREP(req, FUNC_BUF_UNRGTR);
2791 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2793 HWRM_CHECK_RESULT();
2799 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2801 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2802 struct hwrm_func_cfg_input req = {0};
2805 HWRM_PREP(req, FUNC_CFG);
2807 req.fid = rte_cpu_to_le_16(0xffff);
2808 req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2809 req.enables = rte_cpu_to_le_32(
2810 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2811 req.async_event_cr = rte_cpu_to_le_16(
2812 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2813 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2815 HWRM_CHECK_RESULT();
2821 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2823 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2824 struct hwrm_func_vf_cfg_input req = {0};
2827 HWRM_PREP(req, FUNC_VF_CFG);
2829 req.enables = rte_cpu_to_le_32(
2830 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2831 req.async_event_cr = rte_cpu_to_le_16(
2832 bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2833 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2835 HWRM_CHECK_RESULT();
2841 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2843 struct hwrm_func_cfg_input req = {0};
2844 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2845 uint16_t dflt_vlan, fid;
2846 uint32_t func_cfg_flags;
2849 HWRM_PREP(req, FUNC_CFG);
2852 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2853 fid = bp->pf.vf_info[vf].fid;
2854 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2856 fid = rte_cpu_to_le_16(0xffff);
2857 func_cfg_flags = bp->pf.func_cfg_flags;
2858 dflt_vlan = bp->vlan;
2861 req.flags = rte_cpu_to_le_32(func_cfg_flags);
2862 req.fid = rte_cpu_to_le_16(fid);
2863 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2864 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2866 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2868 HWRM_CHECK_RESULT();
2874 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2875 uint16_t max_bw, uint16_t enables)
2877 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2878 struct hwrm_func_cfg_input req = {0};
2881 HWRM_PREP(req, FUNC_CFG);
2883 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2884 req.enables |= rte_cpu_to_le_32(enables);
2885 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2886 req.max_bw = rte_cpu_to_le_32(max_bw);
2887 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2889 HWRM_CHECK_RESULT();
2895 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2897 struct hwrm_func_cfg_input req = {0};
2898 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2901 HWRM_PREP(req, FUNC_CFG);
2903 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2904 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2905 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2906 req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2908 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2910 HWRM_CHECK_RESULT();
2916 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2917 void *encaped, size_t ec_size)
2920 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2921 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2923 if (ec_size > sizeof(req.encap_request))
2926 HWRM_PREP(req, REJECT_FWD_RESP);
2928 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2929 memcpy(req.encap_request, encaped, ec_size);
2931 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2933 HWRM_CHECK_RESULT();
2939 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2940 struct ether_addr *mac)
2942 struct hwrm_func_qcfg_input req = {0};
2943 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2946 HWRM_PREP(req, FUNC_QCFG);
2948 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2949 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2951 HWRM_CHECK_RESULT();
2953 memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2960 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2961 void *encaped, size_t ec_size)
2964 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2965 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2967 if (ec_size > sizeof(req.encap_request))
2970 HWRM_PREP(req, EXEC_FWD_RESP);
2972 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2973 memcpy(req.encap_request, encaped, ec_size);
2975 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2977 HWRM_CHECK_RESULT();
2983 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2984 struct rte_eth_stats *stats, uint8_t rx)
2987 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2988 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2990 HWRM_PREP(req, STAT_CTX_QUERY);
2992 req.stat_ctx_id = rte_cpu_to_le_32(cid);
2994 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2996 HWRM_CHECK_RESULT();
2999 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3000 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3001 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3002 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3003 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3004 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3005 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3006 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3008 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3009 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3010 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3011 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3012 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3013 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3014 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
3023 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3025 struct hwrm_port_qstats_input req = {0};
3026 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3027 struct bnxt_pf_info *pf = &bp->pf;
3030 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3033 HWRM_PREP(req, PORT_QSTATS);
3035 req.port_id = rte_cpu_to_le_16(pf->port_id);
3036 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3037 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3040 HWRM_CHECK_RESULT();
3046 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3048 struct hwrm_port_clr_stats_input req = {0};
3049 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3050 struct bnxt_pf_info *pf = &bp->pf;
3053 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3056 HWRM_PREP(req, PORT_CLR_STATS);
3058 req.port_id = rte_cpu_to_le_16(pf->port_id);
3059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3061 HWRM_CHECK_RESULT();
3067 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3069 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3070 struct hwrm_port_led_qcaps_input req = {0};
3076 HWRM_PREP(req, PORT_LED_QCAPS);
3077 req.port_id = bp->pf.port_id;
3078 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3080 HWRM_CHECK_RESULT();
3082 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3085 bp->num_leds = resp->num_leds;
3086 memcpy(bp->leds, &resp->led0_id,
3087 sizeof(bp->leds[0]) * bp->num_leds);
3088 for (i = 0; i < bp->num_leds; i++) {
3089 struct bnxt_led_info *led = &bp->leds[i];
3091 uint16_t caps = led->led_state_caps;
3093 if (!led->led_group_id ||
3094 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3106 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3108 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3109 struct hwrm_port_led_cfg_input req = {0};
3110 struct bnxt_led_cfg *led_cfg;
3111 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3112 uint16_t duration = 0;
3115 if (!bp->num_leds || BNXT_VF(bp))
3118 HWRM_PREP(req, PORT_LED_CFG);
3121 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3122 duration = rte_cpu_to_le_16(500);
3124 req.port_id = bp->pf.port_id;
3125 req.num_leds = bp->num_leds;
3126 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3127 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3128 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3129 led_cfg->led_id = bp->leds[i].led_id;
3130 led_cfg->led_state = led_state;
3131 led_cfg->led_blink_on = duration;
3132 led_cfg->led_blink_off = duration;
3133 led_cfg->led_group_id = bp->leds[i].led_group_id;
3136 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3138 HWRM_CHECK_RESULT();
3144 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3148 struct hwrm_nvm_get_dir_info_input req = {0};
3149 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3151 HWRM_PREP(req, NVM_GET_DIR_INFO);
3153 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3155 HWRM_CHECK_RESULT();
3159 *entries = rte_le_to_cpu_32(resp->entries);
3160 *length = rte_le_to_cpu_32(resp->entry_length);
3165 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3168 uint32_t dir_entries;
3169 uint32_t entry_length;
3172 rte_iova_t dma_handle;
3173 struct hwrm_nvm_get_dir_entries_input req = {0};
3174 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3176 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3180 *data++ = dir_entries;
3181 *data++ = entry_length;
3183 memset(data, 0xff, len);
3185 buflen = dir_entries * entry_length;
3186 buf = rte_malloc("nvm_dir", buflen, 0);
3187 rte_mem_lock_page(buf);
3190 dma_handle = rte_mem_virt2iova(buf);
3191 if (dma_handle == 0) {
3193 "unable to map response address to physical memory\n");
3196 HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3197 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3198 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3200 HWRM_CHECK_RESULT();
3204 memcpy(data, buf, len > buflen ? buflen : len);
3211 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3212 uint32_t offset, uint32_t length,
3217 rte_iova_t dma_handle;
3218 struct hwrm_nvm_read_input req = {0};
3219 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3221 buf = rte_malloc("nvm_item", length, 0);
3222 rte_mem_lock_page(buf);
3226 dma_handle = rte_mem_virt2iova(buf);
3227 if (dma_handle == 0) {
3229 "unable to map response address to physical memory\n");
3232 HWRM_PREP(req, NVM_READ);
3233 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3234 req.dir_idx = rte_cpu_to_le_16(index);
3235 req.offset = rte_cpu_to_le_32(offset);
3236 req.len = rte_cpu_to_le_32(length);
3237 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3238 HWRM_CHECK_RESULT();
3241 memcpy(data, buf, length);
3247 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3250 struct hwrm_nvm_erase_dir_entry_input req = {0};
3251 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3253 HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3254 req.dir_idx = rte_cpu_to_le_16(index);
3255 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3256 HWRM_CHECK_RESULT();
3263 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3264 uint16_t dir_ordinal, uint16_t dir_ext,
3265 uint16_t dir_attr, const uint8_t *data,
3269 struct hwrm_nvm_write_input req = {0};
3270 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3271 rte_iova_t dma_handle;
3274 HWRM_PREP(req, NVM_WRITE);
3276 req.dir_type = rte_cpu_to_le_16(dir_type);
3277 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3278 req.dir_ext = rte_cpu_to_le_16(dir_ext);
3279 req.dir_attr = rte_cpu_to_le_16(dir_attr);
3280 req.dir_data_length = rte_cpu_to_le_32(data_len);
3282 buf = rte_malloc("nvm_write", data_len, 0);
3283 rte_mem_lock_page(buf);
3287 dma_handle = rte_mem_virt2iova(buf);
3288 if (dma_handle == 0) {
3290 "unable to map response address to physical memory\n");
3293 memcpy(buf, data, data_len);
3294 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3296 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3298 HWRM_CHECK_RESULT();
3306 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3308 uint32_t *count = cbdata;
3310 *count = *count + 1;
3313 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3314 struct bnxt_vnic_info *vnic __rte_unused)
3319 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3323 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3324 &count, bnxt_vnic_count_hwrm_stub);
3329 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3332 struct hwrm_func_vf_vnic_ids_query_input req = {0};
3333 struct hwrm_func_vf_vnic_ids_query_output *resp =
3334 bp->hwrm_cmd_resp_addr;
3337 /* First query all VNIC ids */
3338 HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3340 req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3341 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3342 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3344 if (req.vnic_id_tbl_addr == 0) {
3347 "unable to map VNIC ID table address to physical memory\n");
3350 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3353 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3355 } else if (resp->error_code) {
3356 rc = rte_le_to_cpu_16(resp->error_code);
3358 PMD_DRV_LOG(ERR, "hwrm_func_vf_vnic_query error %d\n", rc);
3361 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3369 * This function queries the VNIC IDs for a specified VF. It then calls
3370 * the vnic_cb to update the necessary field in vnic_info with cbdata.
3371 * Then it calls the hwrm_cb function to program this new vnic configuration.
3373 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3374 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3375 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3377 struct bnxt_vnic_info vnic;
3379 int i, num_vnic_ids;
3384 /* First query all VNIC ids */
3385 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3386 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3387 RTE_CACHE_LINE_SIZE);
3388 if (vnic_ids == NULL) {
3392 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3393 rte_mem_lock_page(((char *)vnic_ids) + sz);
3395 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3397 if (num_vnic_ids < 0)
3398 return num_vnic_ids;
3400 /* Retrieve VNIC, update bd_stall then update */
3402 for (i = 0; i < num_vnic_ids; i++) {
3403 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3404 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3405 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3408 if (vnic.mru <= 4) /* Indicates unallocated */
3411 vnic_cb(&vnic, cbdata);
3413 rc = hwrm_cb(bp, &vnic);
3423 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3426 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3427 struct hwrm_func_cfg_input req = {0};
3430 HWRM_PREP(req, FUNC_CFG);
3432 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3433 req.enables |= rte_cpu_to_le_32(
3434 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3435 req.vlan_antispoof_mode = on ?
3436 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3437 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3438 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3440 HWRM_CHECK_RESULT();
3446 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3448 struct bnxt_vnic_info vnic;
3451 int num_vnic_ids, i;
3455 vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3456 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3457 RTE_CACHE_LINE_SIZE);
3458 if (vnic_ids == NULL) {
3463 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3464 rte_mem_lock_page(((char *)vnic_ids) + sz);
3466 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3472 * Loop through to find the default VNIC ID.
3473 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3474 * by sending the hwrm_func_qcfg command to the firmware.
3476 for (i = 0; i < num_vnic_ids; i++) {
3477 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3478 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3479 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3480 bp->pf.first_vf_id + vf);
3483 if (vnic.func_default) {
3485 return vnic.fw_vnic_id;
3488 /* Could not find a default VNIC. */
3489 PMD_DRV_LOG(ERR, "No default VNIC\n");
3495 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3497 struct bnxt_filter_info *filter)
3500 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3501 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3502 uint32_t enables = 0;
3504 if (filter->fw_em_filter_id != UINT64_MAX)
3505 bnxt_hwrm_clear_em_filter(bp, filter);
3507 HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3509 req.flags = rte_cpu_to_le_32(filter->flags);
3511 enables = filter->enables |
3512 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3513 req.dst_id = rte_cpu_to_le_16(dst_id);
3515 if (filter->ip_addr_type) {
3516 req.ip_addr_type = filter->ip_addr_type;
3517 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3520 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3521 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3523 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3524 memcpy(req.src_macaddr, filter->src_macaddr,
3527 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3528 memcpy(req.dst_macaddr, filter->dst_macaddr,
3531 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3532 req.ovlan_vid = filter->l2_ovlan;
3534 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3535 req.ivlan_vid = filter->l2_ivlan;
3537 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3538 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3540 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3541 req.ip_protocol = filter->ip_protocol;
3543 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3544 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3546 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3547 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3549 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3550 req.src_port = rte_cpu_to_be_16(filter->src_port);
3552 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3553 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3555 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3556 req.mirror_vnic_id = filter->mirror_vnic_id;
3558 req.enables = rte_cpu_to_le_32(enables);
3560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3562 HWRM_CHECK_RESULT();
3564 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3570 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3573 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3574 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3576 if (filter->fw_em_filter_id == UINT64_MAX)
3579 PMD_DRV_LOG(ERR, "Clear EM filter\n");
3580 HWRM_PREP(req, CFA_EM_FLOW_FREE);
3582 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3584 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3586 HWRM_CHECK_RESULT();
3589 filter->fw_em_filter_id = UINT64_MAX;
3590 filter->fw_l2_filter_id = UINT64_MAX;
3595 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3597 struct bnxt_filter_info *filter)
3600 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3601 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3602 bp->hwrm_cmd_resp_addr;
3603 uint32_t enables = 0;
3605 if (filter->fw_ntuple_filter_id != UINT64_MAX)
3606 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3608 HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3610 req.flags = rte_cpu_to_le_32(filter->flags);
3612 enables = filter->enables |
3613 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3614 req.dst_id = rte_cpu_to_le_16(dst_id);
3617 if (filter->ip_addr_type) {
3618 req.ip_addr_type = filter->ip_addr_type;
3620 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3623 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3624 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3626 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3627 memcpy(req.src_macaddr, filter->src_macaddr,
3630 //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3631 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3634 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3635 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3637 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3638 req.ip_protocol = filter->ip_protocol;
3640 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3641 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3643 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3644 req.src_ipaddr_mask[0] =
3645 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3647 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3648 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3650 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3651 req.dst_ipaddr_mask[0] =
3652 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3654 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3655 req.src_port = rte_cpu_to_le_16(filter->src_port);
3657 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3658 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3660 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3661 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3663 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3664 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3666 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3667 req.mirror_vnic_id = filter->mirror_vnic_id;
3669 req.enables = rte_cpu_to_le_32(enables);
3671 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3673 HWRM_CHECK_RESULT();
3675 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3681 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3682 struct bnxt_filter_info *filter)
3685 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3686 struct hwrm_cfa_ntuple_filter_free_output *resp =
3687 bp->hwrm_cmd_resp_addr;
3689 if (filter->fw_ntuple_filter_id == UINT64_MAX)
3692 HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3694 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3696 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3698 HWRM_CHECK_RESULT();
3701 filter->fw_ntuple_filter_id = UINT64_MAX;
3702 filter->fw_l2_filter_id = UINT64_MAX;
3707 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3709 unsigned int rss_idx, fw_idx, i;
3711 if (vnic->rss_table && vnic->hash_type) {
3713 * Fill the RSS hash & redirection table with
3714 * ring group ids for all VNICs
3716 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
3717 rss_idx++, fw_idx++) {
3718 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
3719 fw_idx %= bp->rx_cp_nr_rings;
3720 if (vnic->fw_grp_ids[fw_idx] !=
3725 if (i == bp->rx_cp_nr_rings)
3727 vnic->rss_table[rss_idx] =
3728 vnic->fw_grp_ids[fw_idx];
3730 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);