1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
42 } __attribute__((packed));
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
55 } __attribute__((packed));
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The SRT EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 #define TLV_TYPE_LAST \
92 TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY
95 /* tlv (size:64b/8B) */
98 * The command discriminator is used to differentiate between various
99 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
100 * command messages as well as newer TLV encapsulated HWRM commands.
102 * For TLV encapsulated messages this field must be 0x8000.
108 * Indicates the presence of additional TLV encapsulated data
111 #define TLV_FLAGS_MORE UINT32_C(0x1)
112 /* Last TLV in a sequence of TLVs. */
113 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
114 /* More TLVs follow this TLV. */
115 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
117 * When an HWRM receiver detects a TLV type that it does not
118 * support with the TLV required flag set, the receiver must
119 * reject the HWRM message with an error code indicating an
120 * unsupported TLV type.
122 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
124 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
126 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
127 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
129 * This field defines the TLV type value which is divided into
130 * two ranges to differentiate between global and local TLV types.
131 * Global TLV types must be unique across all defined TLV types.
132 * Local TLV types are valid only for extensions to a given
133 * HWRM message and may be repeated across different HWRM message
134 * types. There is a direct correlation of each HWRM message type
135 * to a single global TLV type value.
137 * Global TLV range: `0 - (63k-1)`
139 * Local TLV range: `63k - (64k-1)`
143 * Length of the message data encapsulated by this TLV in bytes.
144 * This length does not include the size of the TLV header itself
145 * and it must be an integer multiple of 8B.
148 } __attribute__((packed));
151 /* input (size:128b/16B) */
154 * This value indicates what type of request this is. The format
155 * for the rest of the command is determined by this field.
159 * This value indicates the what completion ring the request will
160 * be optionally completed on. If the value is -1, then no
161 * CR completion will be generated. Any other value must be a
162 * valid CR ring_id value for this function.
165 /* This value indicates the command sequence number. */
168 * Target ID of this command.
170 * 0x0 - 0xFFF8 - Used for function ids
171 * 0xFFF8 - 0xFFFE - Reserved for internal processors
176 * This is the host address where the response will be written
177 * when the request is complete. This area must be 16B aligned
178 * and must be cleared to zero before the request is made.
181 } __attribute__((packed));
184 /* output (size:64b/8B) */
187 * Pass/Fail or error type
189 * Note: receiver to verify the in parameters, and fail the call
190 * with an error when appropriate
193 /* This field returns the type of original request. */
195 /* This field provides original sequence number of the command. */
198 * This field is the length of the response in bytes. The
199 * last byte of the response is a valid flag that will read
200 * as '1' when the command has been completely written to
204 } __attribute__((packed));
206 /* Short Command Structure */
207 /* hwrm_short_input (size:128b/16B) */
208 struct hwrm_short_input {
210 * This field indicates the type of request in the request buffer.
211 * The format for the rest of the command (request) is determined
216 * This field indicates a signature that is used to identify short
217 * form of the command listed here. This field shall be set to
221 /* Signature indicating this is a short form of HWRM command */
222 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
223 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
224 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
225 /* The target ID of the command */
227 /* Default target_id (0x0) to maintain compatibility with old driver */
228 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
229 /* Reserved for user-space HWRM interface */
230 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
231 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
232 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
233 /* This value indicates the length of the request. */
236 * This is the host address where the request was written.
237 * This area must be 16B aligned.
240 } __attribute__((packed));
244 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
245 * # So only structure definition is provided here.
247 /* cmd_nums (size:64b/8B) */
250 * This version of the specification defines the commands listed in
251 * the table below. The following are general implementation
252 * requirements for these commands:
254 * # All commands listed below that are marked neither
255 * reserved nor experimental shall be implemented by the HWRM.
256 * # A HWRM client compliant to this specification should not use
257 * commands outside of the list below.
258 * # A HWRM client compliant to this specification should not use
259 * command numbers marked reserved below.
260 * # A command marked experimental below may not be implemented
262 * # A command marked experimental may change in the
263 * future version of the HWRM specification.
264 * # A command not listed below may be implemented by the HWRM.
265 * The behavior of commands that are not listed below is outside
266 * the scope of this specification.
269 #define HWRM_VER_GET UINT32_C(0x0)
270 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
271 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
272 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
273 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
274 /* Reserved for future use. */
275 #define HWRM_RESERVED1 UINT32_C(0x10)
276 #define HWRM_FUNC_RESET UINT32_C(0x11)
277 #define HWRM_FUNC_GETFID UINT32_C(0x12)
278 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
279 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
280 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
281 #define HWRM_FUNC_QCFG UINT32_C(0x16)
282 #define HWRM_FUNC_CFG UINT32_C(0x17)
283 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
284 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
285 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
286 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
287 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
288 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
289 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
290 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
291 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
292 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
294 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
295 #define HWRM_PORT_QSTATS UINT32_C(0x23)
296 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
298 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
300 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
301 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
302 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
304 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
305 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
306 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
307 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
308 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
309 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
310 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
311 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
312 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
313 #define HWRM_QUEUE_CFG UINT32_C(0x32)
314 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
315 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
316 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
317 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
318 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
319 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
320 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
321 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
323 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 #define HWRM_RING_ALLOC UINT32_C(0x50)
341 #define HWRM_RING_FREE UINT32_C(0x51)
342 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
343 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
344 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
345 #define HWRM_RING_RESET UINT32_C(0x5e)
346 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
347 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
348 /* Reserved for future use. */
349 #define HWRM_RESERVED5 UINT32_C(0x64)
350 /* Reserved for future use. */
351 #define HWRM_RESERVED6 UINT32_C(0x65)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
353 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
354 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
355 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
356 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
357 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
358 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
359 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
360 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
362 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
364 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
365 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
366 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
367 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
369 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
371 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
373 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
374 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
375 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
376 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
377 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
378 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
379 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
380 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
381 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
382 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
383 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
384 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
385 #define HWRM_FW_RESET UINT32_C(0xc0)
386 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
387 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
388 #define HWRM_FW_SYNC UINT32_C(0xc3)
389 #define HWRM_FW_STATE_BUFFER_QCAPS UINT32_C(0xc4)
390 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
391 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
392 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
394 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
396 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
398 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
400 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
402 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
403 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
404 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
405 #define HWRM_FWD_RESP UINT32_C(0xd2)
406 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
407 #define HWRM_OEM_CMD UINT32_C(0xd4)
408 /* Tells the fw to run PRBS test on a given port and lane. */
409 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
410 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
411 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
412 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
413 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
414 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
416 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
418 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
420 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
422 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
424 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
426 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
428 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
430 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
432 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
434 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
436 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
438 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
440 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
442 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
444 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
446 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
448 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
450 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
452 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
453 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
454 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
455 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
457 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
459 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
461 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
463 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
464 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
465 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
467 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
469 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
471 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
473 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
475 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
477 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
479 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
481 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
483 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
485 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
487 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
489 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
491 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
493 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
495 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
497 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
499 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
501 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
503 #define HWRM_CFA_TFLIB UINT32_C(0x125)
504 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
505 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
506 /* Engine CKV - Add a new CKEK used to encrypt keys. */
507 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
508 /* Engine CKV - Delete a previously added CKEK. */
509 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
510 /* Engine CKV - Add a new key to the key vault. */
511 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
512 /* Engine CKV - Delete a key from the key vault. */
513 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
514 /* Engine CKV - Delete all keys from the key vault. */
515 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
516 /* Engine CKV - Get random data. */
517 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
518 /* Engine CKV - Generate and encrypt a new AES key. */
519 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
520 /* Engine CKV - Configure a label index with a label value. */
521 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
522 /* Engine CKV - Query a label */
523 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
524 /* Engine - Query the available queue groups configuration. */
525 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
526 /* Engine - Query the queue groups assigned to a function. */
527 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
528 /* Engine - Query the available queue group meter profile configuration. */
529 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
530 /* Engine - Query the configuration of a queue group meter profile. */
531 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
532 /* Engine - Allocate a queue group meter profile. */
533 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
534 /* Engine - Free a queue group meter profile. */
535 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
536 /* Engine - Query the meters assigned to a queue group. */
537 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
538 /* Engine - Bind a queue group meter profile to a queue group. */
539 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
540 /* Engine - Unbind a queue group meter profile from a queue group. */
541 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
542 /* Engine - Bind a queue group to a function. */
543 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
544 /* Engine - Query the scheduling group configuration. */
545 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
546 /* Engine - Query the queue groups assigned to a scheduling group. */
547 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
548 /* Engine - Query the configuration of a scheduling group's meter profiles. */
549 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
550 /* Engine - Configure a scheduling group's meter profiles. */
551 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
552 /* Engine - Bind a queue group to a scheduling group. */
553 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
554 /* Engine - Unbind a queue group from its scheduling group. */
555 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
556 /* Engine - Query the Engine configuration. */
557 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
558 /* Engine - Configure the statistics accumulator for an Engine. */
559 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
560 /* Engine - Clear the statistics accumulator for an Engine. */
561 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
562 /* Engine - Query the statistics accumulator for an Engine. */
563 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
564 /* Engine - Allocate an Engine RQ. */
565 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
566 /* Engine - Free an Engine RQ. */
567 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
568 /* Engine - Allocate an Engine CQ. */
569 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
570 /* Engine - Free an Engine CQ. */
571 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
572 /* Engine - Allocate an NQ. */
573 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
574 /* Engine - Free an NQ. */
575 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
576 /* Engine - Set the on-die RQE credit update location. */
577 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
578 /* Engine - Query the engine function configuration. */
579 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
581 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
583 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
585 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
587 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
589 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
590 /* Configures the BW of any VF */
591 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
592 /* Queries the BW of any VF */
593 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
594 /* Queries pf ids belong to specified host(s) */
595 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
597 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
599 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
601 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
603 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
605 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
607 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
608 /* Returns the current value of a free running counter from the device. */
609 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
611 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
613 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
615 * Tells the fw to run the DMA read from the host and DMA write
618 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
620 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
622 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
624 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
626 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
627 #define HWRM_DBG_DUMP UINT32_C(0xff14)
629 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
631 #define HWRM_DBG_CFG UINT32_C(0xff16)
633 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
635 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
637 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
639 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
641 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
643 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
645 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
647 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
649 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
650 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
651 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
652 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
653 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
654 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
655 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
656 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
657 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
658 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
659 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
660 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
661 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
662 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
663 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
664 #define HWRM_NVM_READ UINT32_C(0xfffd)
665 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
666 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
667 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
668 uint16_t unused_0[3];
669 } __attribute__((packed));
672 /* ret_codes (size:64b/8B) */
675 /* Request was successfully executed by the HWRM. */
676 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
677 /* The HWRM failed to execute the request. */
678 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
680 * The request contains invalid argument(s) or input
683 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
685 * The requester is not allowed to access the requested
686 * resource. This error code shall be provided in a
687 * response to a request to query or modify an existing
688 * resource that is not accessible by the requester.
690 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
692 * The HWRM is unable to allocate the requested resource.
693 * This code only applies to requests for HWRM resource
696 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
698 * Invalid combination of flags is specified in the
701 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
703 * Invalid combination of enables fields is specified in
706 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
708 * Request contains a required TLV that is not supported by
709 * the installed version of firmware.
711 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
713 * No firmware buffer available to accept the request. Driver
714 * should retry the request.
716 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
718 * This error code is only reported by firmware when some
719 * sub-option of a supported HWRM command is unsupported.
721 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
723 * This error code is only reported by firmware when the specific
724 * request is not able to process when the HOT reset in progress.
726 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
728 * This error code is only reported by firmware when the registered
729 * driver instances are not capable of hot reset.
731 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
733 * This error code is only reported by the firmware when during
734 * flow allocation when a requeest for a flow counter fails because
735 * the number of flow counters are exhausted.
737 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
739 * This error code is only reported by firmware when the registered
740 * driver instances requested to offloaded a flow but was unable to because
741 * the requested key's hash collides with the installed keys.
743 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
745 * This error code is only reported by firmware when the registered
746 * driver instances requested to offloaded a flow but was unable to because
747 * the same key has already been installed.
749 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
751 * Generic HWRM execution error that represents an
754 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
756 * This value indicates that the HWRM response is in TLV format and
757 * should be interpreted as one or more TLVs starting with the
758 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
759 * by itself, just an indicatation that the response should be parsed
760 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
762 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
764 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
765 /* Unsupported or invalid command */
766 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
767 #define HWRM_ERR_CODE_LAST \
768 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
769 uint16_t unused_0[3];
770 } __attribute__((packed));
773 /* hwrm_err_output (size:128b/16B) */
774 struct hwrm_err_output {
776 * Pass/Fail or error type
778 * Note: receiver to verify the in parameters, and fail the call
779 * with an error when appropriate
782 /* This field returns the type of original request. */
784 /* This field provides original sequence number of the command. */
787 * This field is the length of the response in bytes. The
788 * last byte of the response is a valid flag that will read
789 * as '1' when the command has been completely written to
793 /* debug info for this error response. */
795 /* debug info for this error response. */
798 * In the case of an error response, command specific error
799 * code is returned in this field.
803 * This field is used in Output records to indicate that the output
804 * is completely written to RAM. This field should be read as '1'
805 * to indicate that the output has been completely written.
806 * When writing a command completion or response to an internal processor,
807 * the order of writes has to be such that this field is written last.
810 } __attribute__((packed));
812 * Following is the signature for HWRM message field that indicates not
813 * applicable (All F's). Need to cast it the size of the field if needed.
815 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
816 /* hwrm_func_buf_rgtr */
817 #define HWRM_MAX_REQ_LEN 128
818 /* hwrm_cfa_flow_info */
819 #define HWRM_MAX_RESP_LEN 704
820 /* 7 bit indirection table index. */
821 #define HW_HASH_INDEX_SIZE 0x80
822 #define HW_HASH_KEY_SIZE 40
823 /* valid key for HWRM response */
824 #define HWRM_RESP_VALID_KEY 1
825 /* Reserved for BONO processor */
826 #define HWRM_TARGET_ID_BONO 0xFFF8
827 /* Reserved for KONG processor */
828 #define HWRM_TARGET_ID_KONG 0xFFF9
829 /* Reserved for APE processor */
830 #define HWRM_TARGET_ID_APE 0xFFFA
832 * This value will be used by tools for User-space HWRM Interface.
833 * When tool execute any HWRM command with this target_id, firmware
834 * will copy the response and/or data payload via register space instead
837 #define HWRM_TARGET_ID_TOOLS 0xFFFD
838 #define HWRM_VERSION_MAJOR 1
839 #define HWRM_VERSION_MINOR 10
840 #define HWRM_VERSION_UPDATE 0
841 /* non-zero means beta version */
842 #define HWRM_VERSION_RSVD 91
843 #define HWRM_VERSION_STR "1.10.0.91"
850 /* hwrm_ver_get_input (size:192b/24B) */
851 struct hwrm_ver_get_input {
852 /* The HWRM command request type. */
855 * The completion ring to send the completion event on. This should
856 * be the NQ ID returned from the `nq_alloc` HWRM command.
860 * The sequence ID is used by the driver for tracking multiple
861 * commands. This ID is treated as opaque data by the firmware and
862 * the value is returned in the `hwrm_resp_hdr` upon completion.
866 * The target ID of the command:
867 * * 0x0-0xFFF8 - The function ID
868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
869 * * 0xFFFD - Reserved for user-space HWRM interface
874 * A physical address pointer pointing to a host buffer that the
875 * command's response data will be written. This can be either a host
876 * physical address (HPA) or a guest physical address (GPA) and must
877 * point to a physically contiguous block of memory.
881 * This field represents the major version of HWRM interface
882 * specification supported by the driver HWRM implementation.
883 * The interface major version is intended to change only when
884 * non backward compatible changes are made to the HWRM
885 * interface specification.
887 uint8_t hwrm_intf_maj;
889 * This field represents the minor version of HWRM interface
890 * specification supported by the driver HWRM implementation.
891 * A change in interface minor version is used to reflect
892 * significant backward compatible modification to HWRM
893 * interface specification.
894 * This can be due to addition or removal of functionality.
895 * HWRM interface specifications with the same major version
896 * but different minor versions are compatible.
898 uint8_t hwrm_intf_min;
900 * This field represents the update version of HWRM interface
901 * specification supported by the driver HWRM implementation.
902 * The interface update version is used to reflect minor
903 * changes or bug fixes to a released HWRM interface
906 uint8_t hwrm_intf_upd;
908 } __attribute__((packed));
910 /* hwrm_ver_get_output (size:1408b/176B) */
911 struct hwrm_ver_get_output {
912 /* The specific error status for the command. */
914 /* The HWRM command request type. */
916 /* The sequence ID from the original command. */
918 /* The length of the response data in number of bytes. */
921 * This field represents the major version of HWRM interface
922 * specification supported by the HWRM implementation.
923 * The interface major version is intended to change only when
924 * non backward compatible changes are made to the HWRM
925 * interface specification.
926 * A HWRM implementation that is compliant with this
927 * specification shall provide value of 1 in this field.
929 uint8_t hwrm_intf_maj_8b;
931 * This field represents the minor version of HWRM interface
932 * specification supported by the HWRM implementation.
933 * A change in interface minor version is used to reflect
934 * significant backward compatible modification to HWRM
935 * interface specification.
936 * This can be due to addition or removal of functionality.
937 * HWRM interface specifications with the same major version
938 * but different minor versions are compatible.
939 * A HWRM implementation that is compliant with this
940 * specification shall provide value of 2 in this field.
942 uint8_t hwrm_intf_min_8b;
944 * This field represents the update version of HWRM interface
945 * specification supported by the HWRM implementation.
946 * The interface update version is used to reflect minor
947 * changes or bug fixes to a released HWRM interface
949 * A HWRM implementation that is compliant with this
950 * specification shall provide value of 2 in this field.
952 uint8_t hwrm_intf_upd_8b;
953 uint8_t hwrm_intf_rsvd_8b;
955 * This field represents the major version of HWRM firmware.
956 * A change in firmware major version represents a major
959 uint8_t hwrm_fw_maj_8b;
961 * This field represents the minor version of HWRM firmware.
962 * A change in firmware minor version represents significant
963 * firmware functionality changes.
965 uint8_t hwrm_fw_min_8b;
967 * This field represents the build version of HWRM firmware.
968 * A change in firmware build version represents bug fixes
969 * to a released firmware.
971 uint8_t hwrm_fw_bld_8b;
973 * This field is a reserved field. This field can be used to
974 * represent firmware branches or customer specific releases
975 * tied to a specific (major,minor,update) version of the
978 uint8_t hwrm_fw_rsvd_8b;
980 * This field represents the major version of mgmt firmware.
981 * A change in major version represents a major release.
983 uint8_t mgmt_fw_maj_8b;
985 * This field represents the minor version of mgmt firmware.
986 * A change in minor version represents significant
987 * functionality changes.
989 uint8_t mgmt_fw_min_8b;
991 * This field represents the build version of mgmt firmware.
992 * A change in update version represents bug fixes.
994 uint8_t mgmt_fw_bld_8b;
996 * This field is a reserved field. This field can be used to
997 * represent firmware branches or customer specific releases
998 * tied to a specific (major,minor,update) version
1000 uint8_t mgmt_fw_rsvd_8b;
1002 * This field represents the major version of network
1004 * A change in major version represents a major release.
1006 uint8_t netctrl_fw_maj_8b;
1008 * This field represents the minor version of network
1010 * A change in minor version represents significant
1011 * functionality changes.
1013 uint8_t netctrl_fw_min_8b;
1015 * This field represents the build version of network
1017 * A change in update version represents bug fixes.
1019 uint8_t netctrl_fw_bld_8b;
1021 * This field is a reserved field. This field can be used to
1022 * represent firmware branches or customer specific releases
1023 * tied to a specific (major,minor,update) version
1025 uint8_t netctrl_fw_rsvd_8b;
1027 * This field is used to indicate device's capabilities and
1030 uint32_t dev_caps_cfg;
1032 * If set to 1, then secure firmware update behavior
1034 * If set to 0, then secure firmware update behavior is
1037 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1040 * If set to 1, then firmware based DCBX agent is supported.
1041 * If set to 0, then firmware based DCBX agent capability
1042 * is not supported on this device.
1044 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1047 * If set to 1, then HWRM short command format is supported.
1048 * If set to 0, then HWRM short command format is not supported.
1050 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1053 * If set to 1, then HWRM short command format is required.
1054 * If set to 0, then HWRM short command format is not required.
1056 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1059 * If set to 1, then the KONG host mailbox channel is supported.
1060 * If set to 0, then the KONG host mailbox channel is not supported.
1061 * By default, this flag should be 0 for older version of core firmware.
1063 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1066 * If set to 1, then the 64bit flow handle is supported in addition to the
1067 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1068 * supported. By default, this flag should be 0 for older version of core firmware.
1070 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1073 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1074 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1075 * If set to 0, then filter types not supported.
1076 * By default, this flag should be 0 for older version of core firmware.
1078 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1081 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1082 * If set to 0, firmware can't supported virtio vSwitch offload model.
1083 * By default, this flag should be 0 for older version of core firmware.
1085 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1088 * If set to 1, firmware is capable to support trusted VF.
1089 * If set to 0, firmware is not capable to support trusted VF.
1090 * By default, this flag should be 0 for older version of core firmware.
1092 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1095 * If set to 1, firmware is capable to support flow aging.
1096 * If set to 0, firmware is not capable to support flow aging.
1097 * By default, this flag should be 0 for older version of core firmware.
1099 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1102 * If set to 1, firmware is capable to support advanced flow counters like,
1103 * Meter drop counters and EEM counters.
1104 * If set to 0, firmware is not capable to support advanced flow counters.
1105 * By default, this flag should be 0 for older version of core firmware.
1107 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1110 * If set to 1, the firmware is able to support the use of the CFA
1111 * Extended Exact Match(EEM) feature.
1112 * If set to 0, firmware is not capable to support the use of the
1114 * By default, this flag should be 0 for older version of core firmware.
1116 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1119 * If set to 1, the firmware is able to support advance CFA flow management
1120 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1121 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1123 * By default, this flag should be 0 for older version of core firmware.
1125 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1128 * If set to 1, the firmware is able to support TFLIB features.
1129 * If set to 0, then the firmware doesn’t support TFLIB features.
1130 * By default, this flag should be 0 for older version of core firmware.
1132 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1135 * This field represents the major version of RoCE firmware.
1136 * A change in major version represents a major release.
1138 uint8_t roce_fw_maj_8b;
1140 * This field represents the minor version of RoCE firmware.
1141 * A change in minor version represents significant
1142 * functionality changes.
1144 uint8_t roce_fw_min_8b;
1146 * This field represents the build version of RoCE firmware.
1147 * A change in update version represents bug fixes.
1149 uint8_t roce_fw_bld_8b;
1151 * This field is a reserved field. This field can be used to
1152 * represent firmware branches or customer specific releases
1153 * tied to a specific (major,minor,update) version
1155 uint8_t roce_fw_rsvd_8b;
1157 * This field represents the name of HWRM FW (ASCII chars
1158 * with NULL at the end).
1160 char hwrm_fw_name[16];
1162 * This field represents the name of mgmt FW (ASCII chars
1163 * with NULL at the end).
1165 char mgmt_fw_name[16];
1167 * This field represents the name of network control
1168 * firmware (ASCII chars with NULL at the end).
1170 char netctrl_fw_name[16];
1171 /* This field represents the active board package name. */
1172 char active_pkg_name[16];
1174 * This field represents the name of RoCE FW (ASCII chars
1175 * with NULL at the end).
1177 char roce_fw_name[16];
1178 /* This field returns the chip number. */
1180 /* This field returns the revision of chip. */
1182 /* This field returns the chip metal number. */
1184 /* This field returns the bond id of the chip. */
1185 uint8_t chip_bond_id;
1186 /* This value indicates the type of platform used for chip implementation. */
1187 uint8_t chip_platform_type;
1189 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1190 /* FPGA platform of the chip. */
1191 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1192 /* Palladium platform of the chip. */
1193 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1194 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1195 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1197 * This field returns the maximum value of request window that
1198 * is supported by the HWRM. The request window is mapped
1199 * into device address space using MMIO.
1201 uint16_t max_req_win_len;
1203 * This field returns the maximum value of response buffer in
1206 uint16_t max_resp_len;
1208 * This field returns the default request timeout value in
1211 uint16_t def_req_timeout;
1213 * This field will indicate if any subsystems is not fully
1218 * If set to 1, it will indicate to host drivers that firmware is
1219 * not ready to start full blown HWRM commands. Host drivers should
1220 * re-try HWRM_VER_GET with some timeout period. The timeout period
1221 * can be selected up to 5 seconds.
1222 * For Example, PCIe hot-plug:
1223 * Hot plug timing is system dependent. It generally takes up to
1224 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1225 * If set to 0, device is ready to accept all HWRM commands.
1227 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1229 * If set to 1, external version present.
1230 * If set to 0, external version not present.
1232 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1233 uint8_t unused_0[2];
1235 * For backward compatibility this field must be set to 1.
1236 * Older drivers might look for this field to be 1 before
1237 * processing the message.
1241 * This field represents the major version of HWRM interface
1242 * specification supported by the HWRM implementation.
1243 * The interface major version is intended to change only when
1244 * non backward compatible changes are made to the HWRM
1245 * interface specification. A HWRM implementation that is
1246 * compliant with this specification shall provide value of 1
1249 uint16_t hwrm_intf_major;
1251 * This field represents the minor version of HWRM interface
1252 * specification supported by the HWRM implementation.
1253 * A change in interface minor version is used to reflect
1254 * significant backward compatible modification to HWRM
1255 * interface specification. This can be due to addition or
1256 * removal of functionality. HWRM interface specifications
1257 * with the same major version but different minor versions are
1258 * compatible. A HWRM implementation that is compliant with
1259 * this specification shall provide value of 2 in this field.
1261 uint16_t hwrm_intf_minor;
1263 * This field represents the update version of HWRM interface
1264 * specification supported by the HWRM implementation. The
1265 * interface update version is used to reflect minor changes or
1266 * bug fixes to a released HWRM interface specification.
1267 * A HWRM implementation that is compliant with this
1268 * specification shall provide value of 2 in this field.
1270 uint16_t hwrm_intf_build;
1272 * This field represents the patch version of HWRM interface
1273 * specification supported by the HWRM implementation.
1275 uint16_t hwrm_intf_patch;
1277 * This field represents the major version of HWRM firmware.
1278 * A change in firmware major version represents a major
1281 uint16_t hwrm_fw_major;
1283 * This field represents the minor version of HWRM firmware.
1284 * A change in firmware minor version represents significant
1285 * firmware functionality changes.
1287 uint16_t hwrm_fw_minor;
1289 * This field represents the build version of HWRM firmware.
1290 * A change in firmware build version represents bug fixes to
1291 * a released firmware.
1293 uint16_t hwrm_fw_build;
1295 * This field is a reserved field.
1296 * This field can be used to represent firmware branches or customer
1297 * specific releases tied to a specific (major,minor,update) version
1298 * of the HWRM firmware.
1300 uint16_t hwrm_fw_patch;
1302 * This field represents the major version of mgmt firmware.
1303 * A change in major version represents a major release.
1305 uint16_t mgmt_fw_major;
1307 * This field represents the minor version of HWRM firmware.
1308 * A change in firmware minor version represents significant
1309 * firmware functionality changes.
1311 uint16_t mgmt_fw_minor;
1313 * This field represents the build version of mgmt firmware.
1314 * A change in update version represents bug fixes.
1316 uint16_t mgmt_fw_build;
1318 * This field is a reserved field. This field can be used to
1319 * represent firmware branches or customer specific releases
1320 * tied to a specific (major,minor,update) version.
1322 uint16_t mgmt_fw_patch;
1324 * This field represents the major version of network control
1325 * firmware. A change in major version represents
1328 uint16_t netctrl_fw_major;
1330 * This field represents the minor version of network control
1331 * firmware. A change in minor version represents significant
1332 * functionality changes.
1334 uint16_t netctrl_fw_minor;
1336 * This field represents the build version of network control
1337 * firmware. A change in update version represents bug fixes.
1339 uint16_t netctrl_fw_build;
1341 * This field is a reserved field. This field can be used to
1342 * represent firmware branches or customer specific releases
1343 * tied to a specific (major,minor,update) version
1345 uint16_t netctrl_fw_patch;
1347 * This field represents the major version of RoCE firmware.
1348 * A change in major version represents a major release.
1350 uint16_t roce_fw_major;
1352 * This field represents the minor version of RoCE firmware.
1353 * A change in minor version represents significant
1354 * functionality changes.
1356 uint16_t roce_fw_minor;
1358 * This field represents the build version of RoCE firmware.
1359 * A change in update version represents bug fixes.
1361 uint16_t roce_fw_build;
1363 * This field is a reserved field. This field can be used to
1364 * represent firmware branches or customer specific releases
1365 * tied to a specific (major,minor,update) version
1367 uint16_t roce_fw_patch;
1369 * This field returns the maximum extended request length acceptable
1370 * by the device which allows requests greater than mailbox size when
1371 * used with the short cmd request format.
1373 uint16_t max_ext_req_len;
1374 uint8_t unused_1[5];
1376 * This field is used in Output records to indicate that the output
1377 * is completely written to RAM. This field should be read as '1'
1378 * to indicate that the output has been completely written.
1379 * When writing a command completion or response to an internal processor,
1380 * the order of writes has to be such that this field is written last.
1383 } __attribute__((packed));
1385 /* bd_base (size:64b/8B) */
1388 /* This value identifies the type of buffer descriptor. */
1389 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1390 #define BD_BASE_TYPE_SFT 0
1392 * Indicates that this BD is 16B long and is used for
1393 * normal L2 packet transmission.
1395 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1397 * Indicates that this BD is 1BB long and is an empty
1398 * TX BD. Not valid for use by the driver.
1400 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1402 * Indicates that this BD is 16B long and is an RX Producer
1403 * (ie. empty) buffer descriptor.
1405 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1407 * Indicates that this BD is 16B long and is an RX
1408 * Producer Buffer BD.
1410 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1412 * Indicates that this BD is 16B long and is an
1413 * RX Producer Assembly Buffer Descriptor.
1415 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1417 * Indicates that this BD is 32B long and is used for
1418 * normal L2 packet transmission.
1420 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1422 * Indicates that this BD is 32B long and is used for
1423 * L2 packet transmission for small packets that require
1426 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1427 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1428 uint8_t unused_1[7];
1429 } __attribute__((packed));
1431 /* tx_bd_short (size:128b/16B) */
1432 struct tx_bd_short {
1434 * All bits in this field must be valid on the first BD of a packet.
1435 * Only the packet_end bit must be valid for the remaining BDs
1438 uint16_t flags_type;
1439 /* This value identifies the type of buffer descriptor. */
1440 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1441 #define TX_BD_SHORT_TYPE_SFT 0
1443 * Indicates that this BD is 16B long and is used for
1444 * normal L2 packet transmission.
1446 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1447 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1449 * All bits in this field must be valid on the first BD of a packet.
1450 * Only the packet_end bit must be valid for the remaining BDs
1453 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1454 #define TX_BD_SHORT_FLAGS_SFT 6
1456 * If set to 1, the packet ends with the data in the buffer
1457 * pointed to by this descriptor. This flag must be
1458 * valid on every BD.
1460 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1462 * If set to 1, the device will not generate a completion for
1463 * this transmit packet unless there is an error in it's
1466 * is set to 0, then the packet will be completed normally.
1468 * This bit must be valid only on the first BD of a packet.
1470 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1472 * This value indicates how many 16B BD locations are consumed
1473 * in the ring by this packet.
1474 * A value of 1 indicates that this BD is the only BD (and that
1475 * the it is a short BD). A value
1476 * of 3 indicates either 3 short BDs or 1 long BD and one short
1477 * BD in the packet. A value of 0 indicates
1478 * that there are 32 BD locations in the packet (the maximum).
1480 * This field is valid only on the first BD of a packet.
1482 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1483 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1485 * This value is a hint for the length of the entire packet.
1486 * It is used by the chip to optimize internal processing.
1488 * The packet will be dropped if the hint is too short.
1490 * This field is valid only on the first BD of a packet.
1492 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1493 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1494 /* indicates packet length < 512B */
1495 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1496 /* indicates 512 <= packet length < 1KB */
1497 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1498 /* indicates 1KB <= packet length < 2KB */
1499 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1500 /* indicates packet length >= 2KB */
1501 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1502 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1503 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1505 * If set to 1, the device immediately updates the Send Consumer
1506 * Index after the buffer associated with this descriptor has
1507 * been transferred via DMA to NIC memory from host memory. An
1508 * interrupt may or may not be generated according to the state
1509 * of the interrupt avoidance mechanisms. If this bit
1510 * is set to 0, then the Consumer Index is only updated as soon
1511 * as one of the host interrupt coalescing conditions has been met.
1513 * This bit must be valid on the first BD of a packet.
1515 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1517 * This is the length of the host physical buffer this BD describes
1520 * This field must be valid on all BDs of a packet.
1524 * The opaque data field is pass through to the completion and can be
1525 * used for any data that the driver wants to associate with the
1528 * This field must be valid on the first BD of a packet.
1532 * This is the host physical address for the portion of the packet
1533 * described by this TX BD.
1535 * This value must be valid on all BDs of a packet.
1538 } __attribute__((packed));
1540 /* tx_bd_long (size:128b/16B) */
1542 /* This value identifies the type of buffer descriptor. */
1543 uint16_t flags_type;
1545 * This value indicates the type of buffer descriptor.
1548 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1549 #define TX_BD_LONG_TYPE_SFT 0
1551 * Indicates that this BD is 32B long and is used for
1552 * normal L2 packet transmission.
1554 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1555 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1557 * All bits in this field must be valid on the first BD of a packet.
1558 * Only the packet_end bit must be valid for the remaining BDs
1561 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1562 #define TX_BD_LONG_FLAGS_SFT 6
1564 * If set to 1, the packet ends with the data in the buffer
1565 * pointed to by this descriptor. This flag must be
1566 * valid on every BD.
1568 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1570 * If set to 1, the device will not generate a completion for
1571 * this transmit packet unless there is an error in it's
1574 * is set to 0, then the packet will be completed normally.
1576 * This bit must be valid only on the first BD of a packet.
1578 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1580 * This value indicates how many 16B BD locations are consumed
1581 * in the ring by this packet.
1582 * A value of 1 indicates that this BD is the only BD (and that
1583 * the it is a short BD). A value
1584 * of 3 indicates either 3 short BDs or 1 long BD and one short
1585 * BD in the packet. A value of 0 indicates
1586 * that there are 32 BD locations in the packet (the maximum).
1588 * This field is valid only on the first BD of a packet.
1590 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1591 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1593 * This value is a hint for the length of the entire packet.
1594 * It is used by the chip to optimize internal processing.
1596 * The packet will be dropped if the hint is too short.
1598 * This field is valid only on the first BD of a packet.
1600 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1601 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1602 /* indicates packet length < 512B */
1603 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1604 /* indicates 512 <= packet length < 1KB */
1605 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1606 /* indicates 1KB <= packet length < 2KB */
1607 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1608 /* indicates packet length >= 2KB */
1609 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1610 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1612 * If set to 1, the device immediately updates the Send Consumer
1613 * Index after the buffer associated with this descriptor has
1614 * been transferred via DMA to NIC memory from host memory. An
1615 * interrupt may or may not be generated according to the state
1616 * of the interrupt avoidance mechanisms. If this bit
1617 * is set to 0, then the Consumer Index is only updated as soon
1618 * as one of the host interrupt coalescing conditions has been met.
1620 * This bit must be valid on the first BD of a packet.
1622 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1624 * This is the length of the host physical buffer this BD describes
1627 * This field must be valid on all BDs of a packet.
1631 * The opaque data field is pass through to the completion and can be
1632 * used for any data that the driver wants to associate with the
1635 * This field must be valid on the first BD of a packet.
1639 * This is the host physical address for the portion of the packet
1640 * described by this TX BD.
1642 * This value must be valid on all BDs of a packet.
1645 } __attribute__((packed));
1647 /* Last 16 bytes of tx_bd_long. */
1648 /* tx_bd_long_hi (size:128b/16B) */
1649 struct tx_bd_long_hi {
1651 * All bits in this field must be valid on the first BD of a packet.
1652 * Their value on other BDs of the packet will be ignored.
1656 * If set to 1, the controller replaces the TCP/UPD checksum
1657 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1658 * checksum field of the encapsulated TCP/UDP packets with the
1659 * hardware calculated TCP/UDP checksum for the packet associated
1660 * with this descriptor. The flag is ignored if the LSO flag is set.
1662 * This bit must be valid on the first BD of a packet.
1664 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1666 * If set to 1, the controller replaces the IP checksum of the
1667 * normal packets, or the inner IP checksum of the encapsulated
1668 * packets with the hardware calculated IP checksum for the
1669 * packet associated with this descriptor.
1671 * This bit must be valid on the first BD of a packet.
1673 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1675 * If set to 1, the controller will not append an Ethernet CRC
1676 * to the end of the frame.
1678 * This bit must be valid on the first BD of a packet.
1680 * Packet must be 64B or longer when this flag is set. It is not
1681 * useful to use this bit with any form of TX offload such as
1682 * CSO or LSO. The intent is that the packet from the host already
1683 * has a valid Ethernet CRC on the packet.
1685 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1687 * If set to 1, the device will record the time at which the packet
1688 * was actually transmitted at the TX MAC.
1690 * This bit must be valid on the first BD of a packet.
1692 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1694 * If set to 1, The controller replaces the tunnel IP checksum
1695 * field with hardware calculated IP checksum for the IP header
1696 * of the packet associated with this descriptor.
1698 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1699 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1700 * bit is set, outer UDP checksum will be calculated for the following
1702 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1703 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1704 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1705 * checksum will not be calculated.
1706 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1707 * as part of LSO operation.
1709 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1711 * If set to 1, the device will treat this packet with LSO(Large
1712 * Send Offload) processing for both normal or encapsulated
1713 * packets, which is a form of TCP segmentation. When this bit
1714 * is 1, the hdr_size and mss fields must be valid. The driver
1715 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1716 * flags since the controller will replace the appropriate
1717 * checksum fields for segmented packets.
1719 * When this bit is 1, the hdr_size and mss fields must be valid.
1721 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1723 * If set to zero when LSO is '1', then the IPID will be treated
1724 * as a 16b number and will be wrapped if it exceeds a value of
1727 * If set to one when LSO is '1', then the IPID will be treated
1728 * as a 15b number and will be wrapped if it exceeds a value 0f
1731 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1733 * If set to zero when LSO is '1', then the IPID of the tunnel
1734 * IP header will not be modified during LSO operations.
1736 * If set to one when LSO is '1', then the IPID of the tunnel
1737 * IP header will be incremented for each subsequent segment of an
1740 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1743 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1745 * If set to '1', then the RoCE ICRC will be appended to the
1746 * packet. Packet must be a valid RoCE format packet.
1748 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1750 * If set to '1', then the FCoE CRC will be appended to the
1751 * packet. Packet must be a valid FCoE format packet.
1753 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1756 * When LSO is '1', this field must contain the offset of the
1757 * TCP payload from the beginning of the packet in as
1758 * 16b words. In case of encapsulated/tunneling packet, this field
1759 * contains the offset of the inner TCP payload from beginning of the
1760 * packet as 16-bit words.
1762 * This value must be valid on the first BD of a packet.
1764 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1765 #define TX_BD_LONG_HDR_SIZE_SFT 0
1768 * This is the MSS value that will be used to do the LSO processing.
1769 * The value is the length in bytes of the TCP payload for each
1770 * segment generated by the LSO operation.
1772 * This value must be valid on the first BD of a packet.
1774 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1775 #define TX_BD_LONG_MSS_SFT 0
1778 * This value selects a CFA action to perform on the packet.
1779 * Set this value to zero if no CFA action is desired.
1781 * This value must be valid on the first BD of a packet.
1783 uint16_t cfa_action;
1785 * This value is action meta-data that defines CFA edit operations
1786 * that are done in addition to any action editing.
1789 /* When key=1, This is the VLAN tag VID value. */
1790 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1791 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1792 /* When key=1, This is the VLAN tag DE value. */
1793 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1794 /* When key=1, This is the VLAN tag PRI value. */
1795 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1796 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1797 /* When key=1, This is the VLAN tag TPID select value. */
1798 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1799 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1801 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1803 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1805 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1807 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1809 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1810 /* Value programmed in CFA VLANTPID register. */
1811 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1812 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1813 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1814 /* When key=1, This is the VLAN tag TPID select value. */
1815 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1816 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1818 * This field identifies the type of edit to be performed
1821 * This value must be valid on the first BD of a packet.
1823 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1824 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1826 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1828 * - meta[17:16] - TPID select value (0 = 0x8100).
1829 * - meta[15:12] - PRI/DE value.
1830 * - meta[11:0] - VID value.
1832 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1833 #define TX_BD_LONG_CFA_META_KEY_LAST \
1834 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1835 } __attribute__((packed));
1838 * This structure is used to inform the NIC of packet data that needs to be
1839 * transmitted with additional processing that requires extra data such as
1840 * VLAN insertion plus attached inline data. This BD type may be used to
1841 * improve latency for small packets needing the additional extended features
1842 * supported by long BDs.
1844 /* tx_bd_long_inline (size:256b/32B) */
1845 struct tx_bd_long_inline {
1846 uint16_t flags_type;
1847 /* This value identifies the type of buffer descriptor. */
1848 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1849 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1851 * This type of BD is 32B long and is used for inline L2 packet
1854 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1855 #define TX_BD_LONG_INLINE_TYPE_LAST \
1856 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1858 * All bits in this field may be set on the first BD of a packet.
1859 * Only the packet_end bit may be set in non-first BDs.
1861 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1862 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1864 * If set to 1, the packet ends with the data in the buffer
1865 * pointed to by this descriptor. This flag must be
1866 * valid on every BD.
1868 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1870 * If set to 1, the device will not generate a completion for
1871 * this transmit packet unless there is an error in its processing.
1872 * If this bit is set to 0, then the packet will be completed
1875 * This bit may be set only on the first BD of a packet.
1877 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1879 * This value indicates how many 16B BD locations are consumed
1880 * in the ring by this packet, including the BD and inline
1883 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1884 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1885 /* This field is deprecated. */
1886 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1887 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1889 * If set to 1, the device immediately updates the Send Consumer
1890 * Index after the buffer associated with this descriptor has
1891 * been transferred via DMA to NIC memory from host memory. An
1892 * interrupt may or may not be generated according to the state
1893 * of the interrupt avoidance mechanisms. If this bit
1894 * is set to 0, then the Consumer Index is only updated as soon
1895 * as one of the host interrupt coalescing conditions has been met.
1897 * This bit must be valid on the first BD of a packet.
1899 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1901 * This is the length of the inline data, not including BD length, in
1903 * The maximum value is 480.
1905 * This field must be valid on all BDs of a packet.
1909 * The opaque data field is passed through to the completion and can be
1910 * used for any data that the driver wants to associate with the transmit
1913 * This field must be valid on the first BD of a packet.
1918 * All bits in this field must be valid on the first BD of a packet.
1919 * Their value on other BDs of the packet is ignored.
1923 * If set to 1, the controller replaces the TCP/UPD checksum
1924 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1925 * checksum field of the encapsulated TCP/UDP packets with the
1926 * hardware calculated TCP/UDP checksum for the packet associated
1927 * with this descriptor. The flag is ignored if the LSO flag is set.
1929 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1931 * If set to 1, the controller replaces the IP checksum of the
1932 * normal packets, or the inner IP checksum of the encapsulated
1933 * packets with the hardware calculated IP checksum for the
1934 * packet associated with this descriptor.
1936 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1938 * If set to 1, the controller will not append an Ethernet CRC
1939 * to the end of the frame.
1941 * Packet must be 64B or longer when this flag is set. It is not
1942 * useful to use this bit with any form of TX offload such as
1943 * CSO or LSO. The intent is that the packet from the host already
1944 * has a valid Ethernet CRC on the packet.
1946 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1948 * If set to 1, the device will record the time at which the packet
1949 * was actually transmitted at the TX MAC.
1951 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1953 * If set to 1, the controller replaces the tunnel IP checksum
1954 * field with hardware calculated IP checksum for the IP header
1955 * of the packet associated with this descriptor. The hardware
1956 * updates an outer UDP checksum if it is non-zero.
1958 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1960 * This bit must be 0 for BDs of this type. LSO is not supported with
1963 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1964 /* Since LSO is not supported with inline BDs, this bit is not used. */
1965 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1966 /* Since LSO is not supported with inline BDs, this bit is not used. */
1967 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1969 * If set to '1', then the RoCE ICRC will be appended to the
1970 * packet. Packet must be a valid RoCE format packet.
1972 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1974 * If set to '1', then the FCoE CRC will be appended to the
1975 * packet. Packet must be a valid FCoE format packet.
1977 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1982 * This value selects a CFA action to perform on the packet.
1983 * Set this value to zero if no CFA action is desired.
1985 * This value must be valid on the first BD of a packet.
1987 uint16_t cfa_action;
1989 * This value is action meta-data that defines CFA edit operations
1990 * that are done in addition to any action editing.
1993 /* When key = 1, this is the VLAN tag VID value. */
1994 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1995 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1996 /* When key = 1, this is the VLAN tag DE value. */
1997 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1998 /* When key = 1, this is the VLAN tag PRI value. */
1999 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2000 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2001 /* When key = 1, this is the VLAN tag TPID select value. */
2002 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2003 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2005 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2006 (UINT32_C(0x0) << 16)
2008 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2009 (UINT32_C(0x1) << 16)
2011 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2012 (UINT32_C(0x2) << 16)
2014 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2015 (UINT32_C(0x3) << 16)
2017 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2018 (UINT32_C(0x4) << 16)
2019 /* Value programmed in CFA VLANTPID register. */
2020 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2021 (UINT32_C(0x5) << 16)
2022 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2023 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2024 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2026 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2028 * This field identifies the type of edit to be performed
2031 * This value must be valid on the first BD of a packet.
2033 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2034 UINT32_C(0xf0000000)
2035 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2037 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2038 (UINT32_C(0x0) << 28)
2040 * - meta[17:16] - TPID select value (0 = 0x8100).
2041 * - meta[15:12] - PRI/DE value.
2042 * - meta[11:0] - VID value.
2044 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2045 (UINT32_C(0x1) << 28)
2046 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2047 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2048 } __attribute__((packed));
2050 /* tx_bd_empty (size:128b/16B) */
2051 struct tx_bd_empty {
2052 /* This value identifies the type of buffer descriptor. */
2054 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2055 #define TX_BD_EMPTY_TYPE_SFT 0
2057 * Indicates that this BD is 1BB long and is an empty
2058 * TX BD. Not valid for use by the driver.
2060 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2061 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2062 uint8_t unused_1[3];
2064 uint8_t unused_3[3];
2065 uint8_t unused_4[8];
2066 } __attribute__((packed));
2068 /* rx_prod_pkt_bd (size:128b/16B) */
2069 struct rx_prod_pkt_bd {
2070 /* This value identifies the type of buffer descriptor. */
2071 uint16_t flags_type;
2072 /* This value identifies the type of buffer descriptor. */
2073 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2074 #define RX_PROD_PKT_BD_TYPE_SFT 0
2076 * Indicates that this BD is 16B long and is an RX Producer
2077 * (ie. empty) buffer descriptor.
2079 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2080 #define RX_PROD_PKT_BD_TYPE_LAST \
2081 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2082 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2083 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2085 * If set to 1, the packet will be placed at the address plus
2086 * 2B. The 2 Bytes of padding will be written as zero.
2088 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2090 * If set to 1, the packet write will be padded out to the
2091 * nearest cache-line with zero value padding.
2093 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2095 * This value is the number of additional buffers in the ring that
2096 * describe the buffer space to be consumed for the this packet.
2097 * If the value is zero, then the packet must fit within the
2098 * space described by this BD. If this value is 1 or more, it
2099 * indicates how many additional "buffer" BDs are in the ring
2100 * immediately following this BD to be used for the same
2103 * Even if the packet to be placed does not need all the
2104 * additional buffers, they will be consumed anyway.
2106 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2107 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2109 * This is the length in Bytes of the host physical buffer where
2110 * data for the packet may be placed in host memory.
2114 * The opaque data field is pass through to the completion and can be
2115 * used for any data that the driver wants to associate with this
2116 * receive buffer set.
2120 * This is the host physical address where data for the packet may
2121 * by placed in host memory.
2124 } __attribute__((packed));
2126 /* rx_prod_bfr_bd (size:128b/16B) */
2127 struct rx_prod_bfr_bd {
2128 /* This value identifies the type of buffer descriptor. */
2129 uint16_t flags_type;
2130 /* This value identifies the type of buffer descriptor. */
2131 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2132 #define RX_PROD_BFR_BD_TYPE_SFT 0
2134 * Indicates that this BD is 16B long and is an RX
2135 * Producer Buffer BD.
2137 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2138 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2139 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2140 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2142 * This is the length in Bytes of the host physical buffer where
2143 * data for the packet may be placed in host memory.
2146 /* This field is not used. */
2149 * This is the host physical address where data for the packet may
2150 * by placed in host memory.
2153 } __attribute__((packed));
2155 /* rx_prod_agg_bd (size:128b/16B) */
2156 struct rx_prod_agg_bd {
2157 /* This value identifies the type of buffer descriptor. */
2158 uint16_t flags_type;
2159 /* This value identifies the type of buffer descriptor. */
2160 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2161 #define RX_PROD_AGG_BD_TYPE_SFT 0
2163 * Indicates that this BD is 16B long and is an
2164 * RX Producer Assembly Buffer Descriptor.
2166 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2167 #define RX_PROD_AGG_BD_TYPE_LAST \
2168 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2169 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2170 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2172 * If set to 1, the packet write will be padded out to the
2173 * nearest cache-line with zero value padding.
2175 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2177 * This is the length in Bytes of the host physical buffer where
2178 * data for the packet may be placed in host memory.
2182 * The opaque data field is pass through to the completion and can be
2183 * used for any data that the driver wants to associate with this
2184 * receive assembly buffer.
2188 * This is the host physical address where data for the packet may
2189 * by placed in host memory.
2192 } __attribute__((packed));
2194 /* cmpl_base (size:128b/16B) */
2198 * This field indicates the exact type of the completion.
2199 * By convention, the LSB identifies the length of the
2200 * record in 16B units. Even values indicate 16B
2201 * records. Odd values indicate 32B
2204 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2205 #define CMPL_BASE_TYPE_SFT 0
2208 * Completion of TX packet. Length = 16B
2210 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2213 * Completion of and L2 RX packet. Length = 32B
2215 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2217 * RX Aggregation Buffer completion :
2218 * Completion of an L2 aggregation buffer in support of
2219 * TPA, HDS, or Jumbo packet completion. Length = 16B
2221 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2223 * RX L2 TPA Start Completion:
2224 * Completion at the beginning of a TPA operation.
2227 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2229 * RX L2 TPA End Completion:
2230 * Completion at the end of a TPA operation.
2233 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2235 * Statistics Ejection Completion:
2236 * Completion of statistics data ejection buffer.
2239 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2241 * HWRM Command Completion:
2242 * Completion of an HWRM command.
2244 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2245 /* Forwarded HWRM Request */
2246 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2247 /* Forwarded HWRM Response */
2248 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2249 /* HWRM Asynchronous Event Information */
2250 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2251 /* CQ Notification */
2252 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2253 /* SRQ Threshold Event */
2254 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2255 /* DBQ Threshold Event */
2256 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2257 /* QP Async Notification */
2258 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2259 /* Function Async Notification */
2260 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2261 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2267 * This value is written by the NIC such that it will be different
2268 * for each pass through the completion queue. The even passes
2269 * will write 1. The odd passes will write 0.
2272 #define CMPL_BASE_V UINT32_C(0x1)
2273 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2274 #define CMPL_BASE_INFO3_SFT 1
2277 } __attribute__((packed));
2279 /* tx_cmpl (size:128b/16B) */
2281 uint16_t flags_type;
2283 * This field indicates the exact type of the completion.
2284 * By convention, the LSB identifies the length of the
2285 * record in 16B units. Even values indicate 16B
2286 * records. Odd values indicate 32B
2289 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2290 #define TX_CMPL_TYPE_SFT 0
2293 * Completion of TX packet. Length = 16B
2295 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2296 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2297 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2298 #define TX_CMPL_FLAGS_SFT 6
2300 * When this bit is '1', it indicates a packet that has an
2301 * error of some type. Type of error is indicated in
2304 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2306 * When this bit is '1', it indicates that the packet completed
2307 * was transmitted using the push acceleration data provided
2308 * by the driver. When this bit is '0', it indicates that the
2309 * packet had not push acceleration data written or was executed
2310 * as a normal packet even though push data was provided.
2312 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2313 /* unused1 is 16 b */
2316 * This is a copy of the opaque field from the first TX BD of this
2317 * transmitted packet.
2322 * This value is written by the NIC such that it will be different
2323 * for each pass through the completion queue. The even passes
2324 * will write 1. The odd passes will write 0.
2326 #define TX_CMPL_V UINT32_C(0x1)
2327 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2328 #define TX_CMPL_ERRORS_SFT 1
2330 * This error indicates that there was some sort of problem
2331 * with the BDs for the packet.
2333 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2334 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2336 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2339 * BDs were not formatted correctly.
2341 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2342 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2343 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2345 * When this bit is '1', it indicates that the length of
2346 * the packet was zero. No packet was transmitted.
2348 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2350 * When this bit is '1', it indicates that the packet
2351 * was longer than the programmed limit in TDI. No
2352 * packet was transmitted.
2354 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2356 * When this bit is '1', it indicates that one or more of the
2357 * BDs associated with this packet generated a PCI error.
2358 * This probably means the address was not valid.
2360 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2362 * When this bit is '1', it indicates that the packet was longer
2363 * than indicated by the hint. No packet was transmitted.
2365 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2367 * When this bit is '1', it indicates that the packet was
2368 * dropped due to Poison TLP error on one or more of the
2369 * TLPs in the PXP completion.
2371 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2372 /* unused2 is 16 b */
2374 /* unused3 is 32 b */
2376 } __attribute__((packed));
2378 /* rx_pkt_cmpl (size:128b/16B) */
2379 struct rx_pkt_cmpl {
2380 uint16_t flags_type;
2382 * This field indicates the exact type of the completion.
2383 * By convention, the LSB identifies the length of the
2384 * record in 16B units. Even values indicate 16B
2385 * records. Odd values indicate 32B
2388 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2389 #define RX_PKT_CMPL_TYPE_SFT 0
2392 * Completion of and L2 RX packet. Length = 32B
2394 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2395 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2396 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2397 #define RX_PKT_CMPL_FLAGS_SFT 6
2399 * When this bit is '1', it indicates a packet that has an
2400 * error of some type. Type of error is indicated in
2403 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2404 /* This field indicates how the packet was placed in the buffer. */
2405 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2406 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2409 * Packet was placed using normal algorithm.
2411 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2414 * Packet was placed using jumbo algorithm.
2416 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2418 * Header/Data Separation:
2419 * Packet was placed using Header/Data separation algorithm.
2420 * The separation location is indicated by the itype field.
2422 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2423 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2424 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2425 /* This bit is '1' if the RSS field in this completion is valid. */
2426 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2428 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2430 * This value indicates what the inner packet determined for the
2433 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2434 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2437 * Indicates that the packet type was not known.
2439 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2440 (UINT32_C(0x0) << 12)
2443 * Indicates that the packet was an IP packet, but further
2444 * classification was not possible.
2446 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2447 (UINT32_C(0x1) << 12)
2450 * Indicates that the packet was IP and TCP.
2451 * This indicates that the payload_offset field is valid.
2453 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2454 (UINT32_C(0x2) << 12)
2457 * Indicates that the packet was IP and UDP.
2458 * This indicates that the payload_offset field is valid.
2460 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2461 (UINT32_C(0x3) << 12)
2464 * Indicates that the packet was recognized as a FCoE.
2465 * This also indicates that the payload_offset field is valid.
2467 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2468 (UINT32_C(0x4) << 12)
2471 * Indicates that the packet was recognized as a RoCE.
2472 * This also indicates that the payload_offset field is valid.
2474 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2475 (UINT32_C(0x5) << 12)
2478 * Indicates that the packet was recognized as ICMP.
2479 * This indicates that the payload_offset field is valid.
2481 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2482 (UINT32_C(0x7) << 12)
2484 * PtP packet wo/timestamp:
2485 * Indicates that the packet was recognized as a PtP
2488 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2489 (UINT32_C(0x8) << 12)
2491 * PtP packet w/timestamp:
2492 * Indicates that the packet was recognized as a PtP
2493 * packet and that a timestamp was taken for the packet.
2495 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2496 (UINT32_C(0x9) << 12)
2497 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2498 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2500 * This is the length of the data for the packet stored in the
2501 * buffer(s) identified by the opaque value. This includes
2502 * the packet BD and any associated buffer BDs. This does not include
2503 * the the length of any data places in aggregation BDs.
2507 * This is a copy of the opaque field from the RX BD this completion
2511 uint8_t agg_bufs_v1;
2513 * This value is written by the NIC such that it will be different
2514 * for each pass through the completion queue. The even passes
2515 * will write 1. The odd passes will write 0.
2517 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2519 * This value is the number of aggregation buffers that follow this
2520 * entry in the completion ring that are a part of this packet.
2521 * If the value is zero, then the packet is completely contained
2522 * in the buffer space provided for the packet in the RX ring.
2524 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2525 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2526 /* unused1 is 2 b */
2527 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2528 #define RX_PKT_CMPL_UNUSED1_SFT 6
2530 * This is the RSS hash type for the packet. The value is packed
2531 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2533 * The value of tuple_extrac_op provides the information about
2534 * what fields the hash was computed on.
2535 * * 0: The RSS hash was computed over source IP address,
2536 * destination IP address, source port, and destination port of inner
2537 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2538 * the packet headers are considered inner packet headers for the RSS
2539 * hash computation purpose.
2540 * * 1: The RSS hash was computed over source IP address and destination
2541 * IP address of inner IP header. Note: For non-tunneled packets,
2542 * the packet headers are considered inner packet headers for the RSS
2543 * hash computation purpose.
2544 * * 2: The RSS hash was computed over source IP address,
2545 * destination IP address, source port, and destination port of
2546 * IP and TCP or UDP headers of outer tunnel headers.
2547 * Note: For non-tunneled packets, this value is not applicable.
2548 * * 3: The RSS hash was computed over source IP address and
2549 * destination IP address of IP header of outer tunnel headers.
2550 * Note: For non-tunneled packets, this value is not applicable.
2552 * Note that 4-tuples values listed above are applicable
2553 * for layer 4 protocols supported and enabled for RSS in the hardware,
2554 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2555 * enabled for TCP traffic only, then the values of tuple_extract_op
2556 * corresponding to 4-tuples are only valid for TCP traffic.
2558 uint8_t rss_hash_type;
2560 * This value indicates the offset in bytes from the beginning of the packet
2561 * where the inner payload starts. This value is valid for TCP, UDP,
2562 * FCoE, and RoCE packets.
2564 * A value of zero indicates that header is 256B into the packet.
2566 uint8_t payload_offset;
2567 /* unused2 is 8 b */
2570 * This value is the RSS hash value calculated for the packet
2571 * based on the mode bits and key value in the VNIC.
2574 } __attribute__((packed));
2576 /* Last 16 bytes of rx_pkt_cmpl. */
2577 /* rx_pkt_cmpl_hi (size:128b/16B) */
2578 struct rx_pkt_cmpl_hi {
2581 * This indicates that the ip checksum was calculated for the
2582 * inner packet and that the ip_cs_error field indicates if there
2585 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2587 * This indicates that the TCP, UDP or ICMP checksum was
2588 * calculated for the inner packet and that the l4_cs_error field
2589 * indicates if there was an error.
2591 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2593 * This indicates that the ip checksum was calculated for the
2594 * tunnel header and that the t_ip_cs_error field indicates if there
2597 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2599 * This indicates that the UDP checksum was
2600 * calculated for the tunnel packet and that the t_l4_cs_error field
2601 * indicates if there was an error.
2603 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2604 /* This value indicates what format the metadata field is. */
2605 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2606 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2607 /* No metadata informtaion. Value is zero. */
2608 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2609 (UINT32_C(0x0) << 4)
2611 * The metadata field contains the VLAN tag and TPID value.
2612 * - metadata[11:0] contains the vlan VID value.
2613 * - metadata[12] contains the vlan DE value.
2614 * - metadata[15:13] contains the vlan PRI value.
2615 * - metadata[31:16] contains the vlan TPID value.
2617 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2618 (UINT32_C(0x1) << 4)
2620 * If ext_meta_format is equal to 1, the metadata field
2621 * contains the lower 16b of the tunnel ID value, justified
2623 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2624 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2625 * - NVGRE = TNI[23:0] -> Tenant Network ID
2626 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2627 * - IPV4 = 0 (not populated)
2628 * - IPV6 = Flow Label[19:0]
2629 * - PPPoE = sessionID[15:0]
2630 * - MPLs = Outer label[19:0]
2631 * - UPAR = Selected[31:0] with bit mask
2633 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2634 (UINT32_C(0x2) << 4)
2636 * if ext_meta_format is equal to 1, metadata field contains
2637 * 16b metadata from the prepended header (chdr_data).
2639 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2640 (UINT32_C(0x3) << 4)
2642 * If ext_meta_format is equal to 1, the metadata field contains
2643 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2645 * - metadata[8:0] contains the outer_l3_offset.
2646 * - metadata[17:9] contains the inner_l2_offset.
2647 * - metadata[26:18] contains the inner_l3_offset.
2648 * - metadata[31:27] contains the inner_l4_size.
2650 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2651 (UINT32_C(0x4) << 4)
2652 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2653 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2655 * This field indicates the IP type for the inner-most IP header.
2656 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2657 * This value is only valid if itype indicates a packet
2658 * with an IP header.
2660 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2662 * This indicates that the complete 1's complement checksum was
2663 * calculated for the packet.
2665 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2667 * The combination of this value and meta_format indicated what
2668 * format the metadata field is.
2670 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2671 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2673 * This value is the complete 1's complement checksum calculated from
2674 * the start of the outer L3 header to the end of the packet (not
2675 * including the ethernet crc). It is valid when the
2676 * 'complete_checksum_calc' flag is set.
2678 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2679 UINT32_C(0xffff0000)
2680 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2682 * This is data from the CFA block as indicated by the meta_format
2686 /* When meta_format=1, this value is the VLAN VID. */
2687 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2688 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2689 /* When meta_format=1, this value is the VLAN DE. */
2690 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2691 /* When meta_format=1, this value is the VLAN PRI. */
2692 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2693 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2694 /* When meta_format=1, this value is the VLAN TPID. */
2695 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2696 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2699 * This value is written by the NIC such that it will be different
2700 * for each pass through the completion queue. The even passes
2701 * will write 1. The odd passes will write 0.
2703 #define RX_PKT_CMPL_V2 \
2705 #define RX_PKT_CMPL_ERRORS_MASK \
2707 #define RX_PKT_CMPL_ERRORS_SFT 1
2709 * This error indicates that there was some sort of problem with
2710 * the BDs for the packet that was found after part of the
2711 * packet was already placed. The packet should be treated as
2714 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2716 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2717 /* No buffer error */
2718 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2719 (UINT32_C(0x0) << 1)
2722 * Packet did not fit into packet buffer provided.
2723 * For regular placement, this means the packet did not fit
2724 * in the buffer provided. For HDS and jumbo placement, this
2725 * means that the packet could not be placed into 7 physical
2728 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2729 (UINT32_C(0x1) << 1)
2732 * All BDs needed for the packet were not on-chip when
2733 * the packet arrived.
2735 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2736 (UINT32_C(0x2) << 1)
2739 * BDs were not formatted correctly.
2741 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2742 (UINT32_C(0x3) << 1)
2745 * There was a bad_format error on the previous operation
2747 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2748 (UINT32_C(0x5) << 1)
2749 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2750 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2752 * This indicates that there was an error in the IP header
2755 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2758 * This indicates that there was an error in the TCP, UDP
2761 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2764 * This indicates that there was an error in the tunnel
2765 * IP header checksum.
2767 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2770 * This indicates that there was an error in the tunnel
2773 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2776 * This indicates that there was a CRC error on either an FCoE
2777 * or RoCE packet. The itype indicates the packet type.
2779 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2782 * This indicates that there was an error in the tunnel
2783 * portion of the packet when this
2784 * field is non-zero.
2786 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2788 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2790 * No additional error occurred on the tunnel portion
2791 * or the packet of the packet does not have a tunnel.
2793 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2794 (UINT32_C(0x0) << 9)
2796 * Indicates that IP header version does not match
2797 * expectation from L2 Ethertype for IPv4 and IPv6
2798 * in the tunnel header.
2800 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2801 (UINT32_C(0x1) << 9)
2803 * Indicates that header length is out of range in the
2804 * tunnel header. Valid for
2807 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2808 (UINT32_C(0x2) << 9)
2810 * Indicates that the physical packet is shorter than that
2811 * claimed by the PPPoE header length for a tunnel PPPoE
2814 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2815 (UINT32_C(0x3) << 9)
2817 * Indicates that physical packet is shorter than that claimed
2818 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2819 * tunnel packet packets.
2821 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2822 (UINT32_C(0x4) << 9)
2824 * Indicates that the physical packet is shorter than that
2825 * claimed by the tunnel UDP header length for a tunnel
2826 * UDP packet that is not fragmented.
2828 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2829 (UINT32_C(0x5) << 9)
2831 * indicates that the IPv4 TTL or IPv6 hop limit check
2832 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2833 * for IPv4, and IPv6.
2835 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2836 (UINT32_C(0x6) << 9)
2837 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2838 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2840 * This indicates that there was an error in the inner
2841 * portion of the packet when this
2842 * field is non-zero.
2844 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2846 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2848 * No additional error occurred on the tunnel portion
2849 * or the packet of the packet does not have a tunnel.
2851 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2852 (UINT32_C(0x0) << 12)
2854 * Indicates that IP header version does not match
2855 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2856 * option other than VFT was parsed on
2859 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2860 (UINT32_C(0x1) << 12)
2862 * indicates that header length is out of range. Valid for
2865 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2866 (UINT32_C(0x2) << 12)
2868 * indicates that the IPv4 TTL or IPv6 hop limit check
2869 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2871 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2872 (UINT32_C(0x3) << 12)
2874 * Indicates that physical packet is shorter than that
2875 * claimed by the l3 header length. Valid for IPv4,
2876 * IPv6 packet or RoCE packets.
2878 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2879 (UINT32_C(0x4) << 12)
2881 * Indicates that the physical packet is shorter than that
2882 * claimed by the UDP header length for a UDP packet that is
2885 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2886 (UINT32_C(0x5) << 12)
2888 * Indicates that TCP header length > IP payload. Valid for
2891 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2892 (UINT32_C(0x6) << 12)
2893 /* Indicates that TCP header length < 5. Valid for TCP. */
2894 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2895 (UINT32_C(0x7) << 12)
2897 * Indicates that TCP option headers result in a TCP header
2898 * size that does not match data offset in TCP header. Valid
2901 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2902 (UINT32_C(0x8) << 12)
2903 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2904 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2906 * This field identifies the CFA action rule that was used for this
2912 * This value holds the reordering sequence number for the packet.
2913 * If the reordering sequence is not valid, then this value is zero.
2914 * The reordering domain for the packet is in the bottom 8 to 10b of
2915 * the rss_hash value. The bottom 20b of this value contain the
2916 * ordering domain value for the packet.
2918 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2919 #define RX_PKT_CMPL_REORDER_SFT 0
2920 } __attribute__((packed));
2923 * This TPA completion structure is used on devices where the
2924 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
2926 /* rx_tpa_start_cmpl (size:128b/16B) */
2927 struct rx_tpa_start_cmpl {
2928 uint16_t flags_type;
2930 * This field indicates the exact type of the completion.
2931 * By convention, the LSB identifies the length of the
2932 * record in 16B units. Even values indicate 16B
2933 * records. Odd values indicate 32B
2936 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2937 #define RX_TPA_START_CMPL_TYPE_SFT 0
2939 * RX L2 TPA Start Completion:
2940 * Completion at the beginning of a TPA operation.
2943 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2944 #define RX_TPA_START_CMPL_TYPE_LAST \
2945 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2946 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2947 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2948 /* This bit will always be '0' for TPA start completions. */
2949 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2950 /* This field indicates how the packet was placed in the buffer. */
2951 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2952 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2955 * TPA Packet was placed using jumbo algorithm. This means
2956 * that the first buffer will be filled with data before
2957 * moving to aggregation buffers. Each aggregation buffer
2958 * will be filled before moving to the next aggregation
2961 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2962 (UINT32_C(0x1) << 7)
2964 * Header/Data Separation:
2965 * Packet was placed using Header/Data separation algorithm.
2966 * The separation location is indicated by the itype field.
2968 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2969 (UINT32_C(0x2) << 7)
2972 * Packet will be placed using GRO/Jumbo where the first
2973 * packet is filled with data. Subsequent packets will be
2974 * placed such that any one packet does not span two
2975 * aggregation buffers unless it starts at the beginning of
2976 * an aggregation buffer.
2978 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2979 (UINT32_C(0x5) << 7)
2981 * GRO/Header-Data Separation:
2982 * Packet will be placed using GRO/HDS where the header
2983 * is in the first packet.
2984 * Payload of each packet will be
2985 * placed such that any one packet does not span two
2986 * aggregation buffers unless it starts at the beginning of
2987 * an aggregation buffer.
2989 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2990 (UINT32_C(0x6) << 7)
2991 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2992 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2993 /* This bit is '1' if the RSS field in this completion is valid. */
2994 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2996 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2998 * This value indicates what the inner packet determined for the
3001 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3002 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
3005 * Indicates that the packet was IP and TCP.
3007 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
3008 (UINT32_C(0x2) << 12)
3009 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
3010 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
3012 * This value indicates the amount of packet data written to the
3013 * buffer the opaque field in this completion corresponds to.
3017 * This is a copy of the opaque field from the RX BD this completion
3022 * This value is written by the NIC such that it will be different
3023 * for each pass through the completion queue. The even passes
3024 * will write 1. The odd passes will write 0.
3028 * This value is written by the NIC such that it will be different
3029 * for each pass through the completion queue. The even passes
3030 * will write 1. The odd passes will write 0.
3032 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
3033 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
3035 * This is the RSS hash type for the packet. The value is packed
3036 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3038 * The value of tuple_extrac_op provides the information about
3039 * what fields the hash was computed on.
3040 * * 0: The RSS hash was computed over source IP address,
3041 * destination IP address, source port, and destination port of inner
3042 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3043 * the packet headers are considered inner packet headers for the RSS
3044 * hash computation purpose.
3045 * * 1: The RSS hash was computed over source IP address and destination
3046 * IP address of inner IP header. Note: For non-tunneled packets,
3047 * the packet headers are considered inner packet headers for the RSS
3048 * hash computation purpose.
3049 * * 2: The RSS hash was computed over source IP address,
3050 * destination IP address, source port, and destination port of
3051 * IP and TCP or UDP headers of outer tunnel headers.
3052 * Note: For non-tunneled packets, this value is not applicable.
3053 * * 3: The RSS hash was computed over source IP address and
3054 * destination IP address of IP header of outer tunnel headers.
3055 * Note: For non-tunneled packets, this value is not applicable.
3057 * Note that 4-tuples values listed above are applicable
3058 * for layer 4 protocols supported and enabled for RSS in the hardware,
3059 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3060 * enabled for TCP traffic only, then the values of tuple_extract_op
3061 * corresponding to 4-tuples are only valid for TCP traffic.
3063 uint8_t rss_hash_type;
3065 * This is the aggregation ID that the completion is associated
3066 * with. Use this number to correlate the TPA start completion
3067 * with the TPA end completion.
3070 /* unused2 is 9 b */
3071 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
3072 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
3074 * This is the aggregation ID that the completion is associated
3075 * with. Use this number to correlate the TPA start completion
3076 * with the TPA end completion.
3078 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3079 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3081 * This value is the RSS hash value calculated for the packet
3082 * based on the mode bits and key value in the VNIC.
3085 } __attribute__((packed));
3088 * Last 16 bytes of rx_tpa_start_cmpl.
3090 * This TPA completion structure is used on devices where the
3091 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3093 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3094 struct rx_tpa_start_cmpl_hi {
3097 * This indicates that the ip checksum was calculated for the
3098 * inner packet and that the sum passed for all segments
3099 * included in the aggregation.
3101 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3103 * This indicates that the TCP, UDP or ICMP checksum was
3104 * calculated for the inner packet and that the sum passed
3105 * for all segments included in the aggregation.
3107 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3109 * This indicates that the ip checksum was calculated for the
3110 * tunnel header and that the sum passed for all segments
3111 * included in the aggregation.
3113 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3115 * This indicates that the UDP checksum was
3116 * calculated for the tunnel packet and that the sum passed for
3117 * all segments included in the aggregation.
3119 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3120 /* This value indicates what format the metadata field is. */
3121 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3122 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3123 /* No metadata information. Value is zero. */
3124 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3125 (UINT32_C(0x0) << 4)
3127 * The metadata field contains the VLAN tag and TPID value.
3128 * - metadata[11:0] contains the vlan VID value.
3129 * - metadata[12] contains the vlan DE value.
3130 * - metadata[15:13] contains the vlan PRI value.
3131 * - metadata[31:16] contains the vlan TPID value.
3133 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3134 (UINT32_C(0x1) << 4)
3135 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3136 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
3138 * This field indicates the IP type for the inner-most IP header.
3139 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3141 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3143 * This is data from the CFA block as indicated by the meta_format
3147 /* When meta_format=1, this value is the VLAN VID. */
3148 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3149 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3150 /* When meta_format=1, this value is the VLAN DE. */
3151 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3152 /* When meta_format=1, this value is the VLAN PRI. */
3153 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3154 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3155 /* When meta_format=1, this value is the VLAN TPID. */
3156 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3157 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3160 * This value is written by the NIC such that it will be different
3161 * for each pass through the completion queue. The even passes
3162 * will write 1. The odd passes will write 0.
3164 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3166 * This field identifies the CFA action rule that was used for this
3171 * This is the size in bytes of the inner most L4 header.
3172 * This can be subtracted from the payload_offset to determine
3173 * the start of the inner most L4 header.
3175 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3177 * This is the offset from the beginning of the packet in bytes for
3178 * the outer L3 header. If there is no outer L3 header, then this
3181 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3182 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3184 * This is the offset from the beginning of the packet in bytes for
3185 * the inner most L2 header.
3187 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3188 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3190 * This is the offset from the beginning of the packet in bytes for
3191 * the inner most L3 header.
3193 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3194 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3196 * This is the size in bytes of the inner most L4 header.
3197 * This can be subtracted from the payload_offset to determine
3198 * the start of the inner most L4 header.
3200 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3201 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3202 } __attribute__((packed));
3205 * This TPA completion structure is used on devices where the
3206 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3208 /* rx_tpa_end_cmpl (size:128b/16B) */
3209 struct rx_tpa_end_cmpl {
3210 uint16_t flags_type;
3212 * This field indicates the exact type of the completion.
3213 * By convention, the LSB identifies the length of the
3214 * record in 16B units. Even values indicate 16B
3215 * records. Odd values indicate 32B
3218 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3219 #define RX_TPA_END_CMPL_TYPE_SFT 0
3221 * RX L2 TPA End Completion:
3222 * Completion at the end of a TPA operation.
3225 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3226 #define RX_TPA_END_CMPL_TYPE_LAST \
3227 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3228 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3229 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3231 * When this bit is '1', it indicates a packet that has an
3232 * error of some type. Type of error is indicated in
3235 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3236 /* This field indicates how the packet was placed in the buffer. */
3237 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3238 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3241 * TPA Packet was placed using jumbo algorithm. This means
3242 * that the first buffer will be filled with data before
3243 * moving to aggregation buffers. Each aggregation buffer
3244 * will be filled before moving to the next aggregation
3247 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3248 (UINT32_C(0x1) << 7)
3250 * Header/Data Separation:
3251 * Packet was placed using Header/Data separation algorithm.
3252 * The separation location is indicated by the itype field.
3254 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3255 (UINT32_C(0x2) << 7)
3258 * Packet will be placed using GRO/Jumbo where the first
3259 * packet is filled with data. Subsequent packets will be
3260 * placed such that any one packet does not span two
3261 * aggregation buffers unless it starts at the beginning of
3262 * an aggregation buffer.
3264 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3265 (UINT32_C(0x5) << 7)
3267 * GRO/Header-Data Separation:
3268 * Packet will be placed using GRO/HDS where the header
3269 * is in the first packet.
3270 * Payload of each packet will be
3271 * placed such that any one packet does not span two
3272 * aggregation buffers unless it starts at the beginning of
3273 * an aggregation buffer.
3275 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3276 (UINT32_C(0x6) << 7)
3277 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3278 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3280 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3281 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3283 * This value indicates what the inner packet determined for the
3286 * Indicates that the packet was IP and TCP. This indicates
3287 * that the ip_cs field is valid and that the tcp_udp_cs
3288 * field is valid and contains the TCP checksum.
3289 * This also indicates that the payload_offset field is valid.
3291 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3292 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3294 * This value is zero for TPA End completions.
3295 * There is no data in the buffer that corresponds to the opaque
3296 * value in this completion.
3300 * This is a copy of the opaque field from the RX BD this completion
3305 * This value is written by the NIC such that it will be different
3306 * for each pass through the completion queue. The even passes
3307 * will write 1. The odd passes will write 0.
3309 uint8_t agg_bufs_v1;
3311 * This value is written by the NIC such that it will be different
3312 * for each pass through the completion queue. The even passes
3313 * will write 1. The odd passes will write 0.
3315 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3317 * This value is the number of aggregation buffers that follow this
3318 * entry in the completion ring that are a part of this aggregation
3320 * If the value is zero, then the packet is completely contained
3321 * in the buffer space provided in the aggregation start completion.
3323 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3324 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3325 /* This value is the number of segments in the TPA operation. */
3328 * This value indicates the offset in bytes from the beginning of the packet
3329 * where the inner payload starts. This value is valid for TCP, UDP,
3330 * FCoE, and RoCE packets.
3332 * A value of zero indicates an offset of 256 bytes.
3334 uint8_t payload_offset;
3336 /* unused2 is 1 b */
3337 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3339 * This is the aggregation ID that the completion is associated
3340 * with. Use this number to correlate the TPA start completion
3341 * with the TPA end completion.
3343 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3344 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3346 * For non-GRO packets, this value is the
3347 * timestamp delta between earliest and latest timestamp values for
3348 * TPA packet. If packets were not time stamped, then delta will be
3351 * For GRO packets, this field is zero except for the following
3354 * Timestamp present indication. When '0', no Timestamp
3355 * option is in the packet. When '1', then a Timestamp
3356 * option is present in the packet.
3359 } __attribute__((packed));
3362 * Last 16 bytes of rx_tpa_end_cmpl.
3364 * This TPA completion structure is used on devices where the
3365 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3367 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3368 struct rx_tpa_end_cmpl_hi {
3369 uint32_t tpa_dup_acks;
3371 * This value is the number of duplicate ACKs that have been
3372 * received as part of the TPA operation.
3374 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3375 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3377 * This value is the valid when TPA completion is active. It
3378 * indicates the length of the longest segment of the TPA operation
3379 * for LRO mode and the length of the first segment in GRO mode.
3381 * This value may be used by GRO software to re-construct the original
3382 * packet stream from the TPA packet. This is the length of all
3383 * but the last segment for GRO. In LRO mode this value may be used
3384 * to indicate MSS size to the stack.
3386 uint16_t tpa_seg_len;
3387 /* unused4 is 16 b */
3391 * This value is written by the NIC such that it will be different
3392 * for each pass through the completion queue. The even passes
3393 * will write 1. The odd passes will write 0.
3395 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3396 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3397 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3399 * This error indicates that there was some sort of problem with
3400 * the BDs for the packet that was found after part of the
3401 * packet was already placed. The packet should be treated as
3404 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3405 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3407 * This error occurs when there is a fatal HW problem in
3408 * the chip only. It indicates that there were not
3409 * BDs on chip but that there was adequate reservation.
3410 * provided by the TPA block.
3412 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3413 (UINT32_C(0x2) << 1)
3415 * This error occurs when TPA block was not configured to
3416 * reserve adequate BDs for TPA operations on this RX
3417 * ring. All data for the TPA operation was not placed.
3419 * This error can also be generated when the number of
3420 * segments is not programmed correctly in TPA and the
3421 * 33 total aggregation buffers allowed for the TPA
3422 * operation has been exceeded.
3424 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3425 (UINT32_C(0x4) << 1)
3426 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3427 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
3428 /* unused5 is 16 b */
3431 * This is the opaque value that was completed for the TPA start
3432 * completion that corresponds to this TPA end completion.
3434 uint32_t start_opaque;
3435 } __attribute__((packed));
3438 * This TPA completion structure is used on devices where the
3439 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3441 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
3442 struct rx_tpa_v2_start_cmpl {
3443 uint16_t flags_type;
3445 * This field indicates the exact type of the completion.
3446 * By convention, the LSB identifies the length of the
3447 * record in 16B units. Even values indicate 16B
3448 * records. Odd values indicate 32B
3451 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
3453 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
3455 * RX L2 TPA Start Completion:
3456 * Completion at the beginning of a TPA operation.
3459 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
3461 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
3462 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
3463 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
3465 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
3466 /* This bit will always be '0' for TPA start completions. */
3467 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
3469 /* This field indicates how the packet was placed in the buffer. */
3470 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
3472 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
3475 * TPA Packet was placed using jumbo algorithm. This means
3476 * that the first buffer will be filled with data before
3477 * moving to aggregation buffers. Each aggregation buffer
3478 * will be filled before moving to the next aggregation
3481 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
3482 (UINT32_C(0x1) << 7)
3484 * Header/Data Separation:
3485 * Packet was placed using Header/Data separation algorithm.
3486 * The separation location is indicated by the itype field.
3488 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
3489 (UINT32_C(0x2) << 7)
3492 * Packet will be placed using GRO/Jumbo where the first
3493 * packet is filled with data. Subsequent packets will be
3494 * placed such that any one packet does not span two
3495 * aggregation buffers unless it starts at the beginning of
3496 * an aggregation buffer.
3498 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3499 (UINT32_C(0x5) << 7)
3501 * GRO/Header-Data Separation:
3502 * Packet will be placed using GRO/HDS where the header
3503 * is in the first packet.
3504 * Payload of each packet will be
3505 * placed such that any one packet does not span two
3506 * aggregation buffers unless it starts at the beginning of
3507 * an aggregation buffer.
3509 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3510 (UINT32_C(0x6) << 7)
3511 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
3512 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3513 /* This bit is '1' if the RSS field in this completion is valid. */
3514 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
3517 * For devices that support timestamps, when this bit is cleared the
3518 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3519 * field contains the 32b timestamp for
3520 * the packet from the MAC. When this bit is set, the
3521 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3522 * field contains the outer_l3_offset, inner_l2_offset,
3523 * inner_l3_offset, and inner_l4_size.
3525 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
3528 * This value indicates what the inner packet determined for the
3531 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
3533 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
3536 * Indicates that the packet was IP and TCP.
3538 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
3539 (UINT32_C(0x2) << 12)
3540 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
3541 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
3543 * This value indicates the amount of packet data written to the
3544 * buffer the opaque field in this completion corresponds to.
3548 * This is a copy of the opaque field from the RX BD this completion
3553 * This value is written by the NIC such that it will be different
3554 * for each pass through the completion queue. The even passes
3555 * will write 1. The odd passes will write 0.
3559 * This value is written by the NIC such that it will be different
3560 * for each pass through the completion queue. The even passes
3561 * will write 1. The odd passes will write 0.
3563 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
3564 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
3566 * This is the RSS hash type for the packet. The value is packed
3567 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3569 * The value of tuple_extrac_op provides the information about
3570 * what fields the hash was computed on.
3571 * * 0: The RSS hash was computed over source IP address,
3572 * destination IP address, source port, and destination port of inner
3573 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3574 * the packet headers are considered inner packet headers for the RSS
3575 * hash computation purpose.
3576 * * 1: The RSS hash was computed over source IP address and destination
3577 * IP address of inner IP header. Note: For non-tunneled packets,
3578 * the packet headers are considered inner packet headers for the RSS
3579 * hash computation purpose.
3580 * * 2: The RSS hash was computed over source IP address,
3581 * destination IP address, source port, and destination port of
3582 * IP and TCP or UDP headers of outer tunnel headers.
3583 * Note: For non-tunneled packets, this value is not applicable.
3584 * * 3: The RSS hash was computed over source IP address and
3585 * destination IP address of IP header of outer tunnel headers.
3586 * Note: For non-tunneled packets, this value is not applicable.
3588 * Note that 4-tuples values listed above are applicable
3589 * for layer 4 protocols supported and enabled for RSS in the hardware,
3590 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3591 * enabled for TCP traffic only, then the values of tuple_extract_op
3592 * corresponding to 4-tuples are only valid for TCP traffic.
3594 uint8_t rss_hash_type;
3596 * This is the aggregation ID that the completion is associated
3597 * with. Use this number to correlate the TPA start completion
3598 * with the TPA end completion.
3602 * This value is the RSS hash value calculated for the packet
3603 * based on the mode bits and key value in the VNIC.
3606 } __attribute__((packed));
3609 * Last 16 bytes of rx_tpa_v2_start_cmpl.
3611 * This TPA completion structure is used on devices where the
3612 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3614 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
3615 struct rx_tpa_v2_start_cmpl_hi {
3618 * This indicates that the ip checksum was calculated for the
3619 * inner packet and that the sum passed for all segments
3620 * included in the aggregation.
3622 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
3625 * This indicates that the TCP, UDP or ICMP checksum was
3626 * calculated for the inner packet and that the sum passed
3627 * for all segments included in the aggregation.
3629 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
3632 * This indicates that the ip checksum was calculated for the
3633 * tunnel header and that the sum passed for all segments
3634 * included in the aggregation.
3636 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
3639 * This indicates that the UDP checksum was
3640 * calculated for the tunnel packet and that the sum passed for
3641 * all segments included in the aggregation.
3643 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
3645 /* This value indicates what format the metadata field is. */
3646 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
3648 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3649 /* No metadata informtaion. Value is zero. */
3650 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
3651 (UINT32_C(0x0) << 4)
3653 * The metadata field contains the VLAN tag and TPID value.
3654 * - metadata[11:0] contains the vlan VID value.
3655 * - metadata[12] contains the vlan DE value.
3656 * - metadata[15:13] contains the vlan PRI value.
3657 * - metadata[31:16] contains the vlan TPID value.
3659 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3660 (UINT32_C(0x1) << 4)
3662 * If ext_meta_format is equal to 1, the metadata field
3663 * contains the lower 16b of the tunnel ID value, justified
3665 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3666 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3667 * - NVGRE = TNI[23:0] -> Tenant Network ID
3668 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3669 * - IPV4 = 0 (not populated)
3670 * - IPV6 = Flow Label[19:0]
3671 * - PPPoE = sessionID[15:0]
3672 * - MPLs = Outer label[19:0]
3673 * - UPAR = Selected[31:0] with bit mask
3675 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3676 (UINT32_C(0x2) << 4)
3678 * if ext_meta_format is equal to 1, metadata field contains
3679 * 16b metadata from the prepended header (chdr_data).
3681 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3682 (UINT32_C(0x3) << 4)
3684 * If ext_meta_format is equal to 1, the metadata field contains
3685 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3687 * - metadata[8:0] contains the outer_l3_offset.
3688 * - metadata[17:9] contains the inner_l2_offset.
3689 * - metadata[26:18] contains the inner_l3_offset.
3690 * - metadata[31:27] contains the inner_l4_size.
3692 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3693 (UINT32_C(0x4) << 4)
3694 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
3695 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3697 * This field indicates the IP type for the inner-most IP header.
3698 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3700 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
3703 * This indicates that the complete 1's complement checksum was
3704 * calculated for the packet.
3706 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3709 * The combination of this value and meta_format indicated what
3710 * format the metadata field is.
3712 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3714 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3716 * This value is the complete 1's complement checksum calculated from
3717 * the start of the outer L3 header to the end of the packet (not
3718 * including the ethernet crc). It is valid when the
3719 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3720 * the complete checksum is calculated for the first packet in the
3723 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3724 UINT32_C(0xffff0000)
3725 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3727 * This is data from the CFA block as indicated by the meta_format
3731 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
3732 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3733 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
3734 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
3735 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
3736 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
3737 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3738 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
3739 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
3740 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3741 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
3744 * This value is written by the NIC such that it will be different
3745 * for each pass through the completion queue. The even passes
3746 * will write 1. The odd passes will write 0.
3748 #define RX_TPA_V2_START_CMPL_V2 \
3750 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
3752 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
3754 * This error indicates that there was some sort of problem with
3755 * the BDs for the packet that was found after part of the
3756 * packet was already placed. The packet should be treated as
3759 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
3761 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3762 /* No buffer error */
3763 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3764 (UINT32_C(0x0) << 1)
3767 * BDs were not formatted correctly.
3769 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3770 (UINT32_C(0x3) << 1)
3773 * There was a bad_format error on the previous operation
3775 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3776 (UINT32_C(0x5) << 1)
3777 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3778 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3780 * This field identifies the CFA action rule that was used for this
3785 * For devices that support timestamps this field is overridden
3786 * with the timestamp value. When `flags.timestamp_fld_format` is
3787 * cleared, this field contains the 32b timestamp for the packet from the
3790 * When `flags.timestamp_fld_format` is set, this field contains the
3791 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
3794 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3796 * This is the offset from the beginning of the packet in bytes for
3797 * the outer L3 header. If there is no outer L3 header, then this
3800 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3801 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
3803 * This is the offset from the beginning of the packet in bytes for
3804 * the inner most L2 header.
3806 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3807 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
3809 * This is the offset from the beginning of the packet in bytes for
3810 * the inner most L3 header.
3812 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3813 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
3815 * This is the size in bytes of the inner most L4 header.
3816 * This can be subtracted from the payload_offset to determine
3817 * the start of the inner most L4 header.
3819 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3820 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
3821 } __attribute__((packed));
3824 * This TPA completion structure is used on devices where the
3825 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3827 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
3828 struct rx_tpa_v2_end_cmpl {
3829 uint16_t flags_type;
3831 * This field indicates the exact type of the completion.
3832 * By convention, the LSB identifies the length of the
3833 * record in 16B units. Even values indicate 16B
3834 * records. Odd values indicate 32B
3837 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3838 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
3840 * RX L2 TPA End Completion:
3841 * Completion at the end of a TPA operation.
3844 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3845 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
3846 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
3847 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3848 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
3850 * When this bit is '1', it indicates a packet that has an
3851 * error of some type. Type of error is indicated in
3854 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3855 /* This field indicates how the packet was placed in the buffer. */
3856 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3857 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
3860 * TPA Packet was placed using jumbo algorithm. This means
3861 * that the first buffer will be filled with data before
3862 * moving to aggregation buffers. Each aggregation buffer
3863 * will be filled before moving to the next aggregation
3866 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3867 (UINT32_C(0x1) << 7)
3869 * Header/Data Separation:
3870 * Packet was placed using Header/Data separation algorithm.
3871 * The separation location is indicated by the itype field.
3873 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
3874 (UINT32_C(0x2) << 7)
3877 * Packet will be placed using GRO/Jumbo where the first
3878 * packet is filled with data. Subsequent packets will be
3879 * placed such that any one packet does not span two
3880 * aggregation buffers unless it starts at the beginning of
3881 * an aggregation buffer.
3883 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3884 (UINT32_C(0x5) << 7)
3886 * GRO/Header-Data Separation:
3887 * Packet will be placed using GRO/HDS where the header
3888 * is in the first packet.
3889 * Payload of each packet will be
3890 * placed such that any one packet does not span two
3891 * aggregation buffers unless it starts at the beginning of
3892 * an aggregation buffer.
3894 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3895 (UINT32_C(0x6) << 7)
3896 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
3897 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3899 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3900 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
3902 * This value indicates what the inner packet determined for the
3905 * Indicates that the packet was IP and TCP. This indicates
3906 * that the ip_cs field is valid and that the tcp_udp_cs
3907 * field is valid and contains the TCP checksum.
3908 * This also indicates that the payload_offset field is valid.
3910 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3911 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
3913 * This value is zero for TPA End completions.
3914 * There is no data in the buffer that corresponds to the opaque
3915 * value in this completion.
3919 * This is a copy of the opaque field from the RX BD this completion
3925 * This value is written by the NIC such that it will be different
3926 * for each pass through the completion queue. The even passes
3927 * will write 1. The odd passes will write 0.
3929 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
3930 /* This value is the number of segments in the TPA operation. */
3933 * This is the aggregation ID that the completion is associated
3934 * with. Use this number to correlate the TPA start completion
3935 * with the TPA end completion.
3939 * For non-GRO packets, this value is the
3940 * timestamp delta between earliest and latest timestamp values for
3941 * TPA packet. If packets were not time stamped, then delta will be
3944 * For GRO packets, this field is zero except for the following
3947 * Timestamp present indication. When '0', no Timestamp
3948 * option is in the packet. When '1', then a Timestamp
3949 * option is present in the packet.
3952 } __attribute__((packed));
3955 * Last 16 bytes of rx_tpa_v2_end_cmpl.
3957 * This TPA completion structure is used on devices where the
3958 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3960 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
3961 struct rx_tpa_v2_end_cmpl_hi {
3963 * This value is the number of duplicate ACKs that have been
3964 * received as part of the TPA operation.
3966 uint16_t tpa_dup_acks;
3968 * This value is the number of duplicate ACKs that have been
3969 * received as part of the TPA operation.
3971 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3972 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
3974 * This value indicated the offset in bytes from the beginning of
3975 * the packet where the inner payload starts. This value is valid
3976 * for TCP, UDP, FCoE and RoCE packets
3978 uint8_t payload_offset;
3980 * The value is the total number of aggregation buffers that were
3981 * used in the TPA operation. All TPA aggregation buffer completions
3982 * precede the TPA End completion. If the value is zero, then the
3983 * aggregation is completely contained in the buffer space provided
3984 * in the aggregation start completion.
3985 * Note that the field is simply provided as a cross check.
3987 uint8_t tpa_agg_bufs;
3989 * This value is the valid when TPA completion is active. It
3990 * indicates the length of the longest segment of the TPA operation
3991 * for LRO mode and the length of the first segment in GRO mode.
3993 * This value may be used by GRO software to re-construct the original
3994 * packet stream from the TPA packet. This is the length of all
3995 * but the last segment for GRO. In LRO mode this value may be used
3996 * to indicate MSS size to the stack.
3998 uint16_t tpa_seg_len;
4002 * This value is written by the NIC such that it will be different
4003 * for each pass through the completion queue. The even passes
4004 * will write 1. The odd passes will write 0.
4006 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
4007 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
4009 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
4011 * This error indicates that there was some sort of problem with
4012 * the BDs for the packet that was found after part of the
4013 * packet was already placed. The packet should be treated as
4016 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
4018 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4019 /* No buffer error */
4020 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4021 (UINT32_C(0x0) << 1)
4023 * This error occurs when there is a fatal HW problem in
4024 * the chip only. It indicates that there were not
4025 * BDs on chip but that there was adequate reservation.
4026 * provided by the TPA block.
4028 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4029 (UINT32_C(0x2) << 1)
4032 * BDs were not formatted correctly.
4034 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4035 (UINT32_C(0x3) << 1)
4037 * This error occurs when TPA block was not configured to
4038 * reserve adequate BDs for TPA operations on this RX
4039 * ring. All data for the TPA operation was not placed.
4041 * This error can also be generated when the number of
4042 * segments is not programmed correctly in TPA and the
4043 * 33 total aggregation buffers allowed for the TPA
4044 * operation has been exceeded.
4046 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4047 (UINT32_C(0x4) << 1)
4050 * There was a bad_format error on the previous operation
4052 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4053 (UINT32_C(0x5) << 1)
4054 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4055 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4058 * This is the opaque value that was completed for the TPA start
4059 * completion that corresponds to this TPA end completion.
4061 uint32_t start_opaque;
4062 } __attribute__((packed));
4065 * This TPA completion structure is used on devices where the
4066 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4068 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
4069 struct rx_tpa_v2_abuf_cmpl {
4072 * This field indicates the exact type of the completion.
4073 * By convention, the LSB identifies the length of the
4074 * record in 16B units. Even values indicate 16B
4075 * records. Odd values indicate 32B
4078 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4079 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
4081 * RX TPA Aggregation Buffer completion :
4082 * Completion of an L2 aggregation buffer in support of
4083 * TPA packet completion. Length = 16B
4085 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
4086 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
4087 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
4089 * This is the length of the data for the packet stored in this
4090 * aggregation buffer identified by the opaque value. This does not
4091 * include the length of any
4092 * data placed in other aggregation BDs or in the packet or buffer
4093 * BDs. This length does not include any space added due to
4094 * hdr_offset register during HDS placement mode.
4098 * This is a copy of the opaque field from the RX BD this aggregation
4099 * buffer corresponds to.
4104 * This value is written by the NIC such that it will be different
4105 * for each pass through the completion queue. The even passes
4106 * will write 1. The odd passes will write 0.
4108 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
4110 * This is the aggregation ID that the completion is associated with. Use
4111 * this number to correlate the TPA agg completion with the TPA start
4112 * completion and the TPA end completion.
4116 } __attribute__((packed));
4118 /* rx_abuf_cmpl (size:128b/16B) */
4119 struct rx_abuf_cmpl {
4122 * This field indicates the exact type of the completion.
4123 * By convention, the LSB identifies the length of the
4124 * record in 16B units. Even values indicate 16B
4125 * records. Odd values indicate 32B
4128 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4129 #define RX_ABUF_CMPL_TYPE_SFT 0
4131 * RX Aggregation Buffer completion :
4132 * Completion of an L2 aggregation buffer in support of
4133 * TPA, HDS, or Jumbo packet completion. Length = 16B
4135 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
4136 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
4138 * This is the length of the data for the packet stored in this
4139 * aggregation buffer identified by the opaque value. This does not
4140 * include the length of any
4141 * data placed in other aggregation BDs or in the packet or buffer
4142 * BDs. This length does not include any space added due to
4143 * hdr_offset register during HDS placement mode.
4147 * This is a copy of the opaque field from the RX BD this aggregation
4148 * buffer corresponds to.
4153 * This value is written by the NIC such that it will be different
4154 * for each pass through the completion queue. The even passes
4155 * will write 1. The odd passes will write 0.
4157 #define RX_ABUF_CMPL_V UINT32_C(0x1)
4158 /* unused3 is 32 b */
4160 } __attribute__((packed));
4162 /* eject_cmpl (size:128b/16B) */
4166 * This field indicates the exact type of the completion.
4167 * By convention, the LSB identifies the length of the
4168 * record in 16B units. Even values indicate 16B
4169 * records. Odd values indicate 32B
4172 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
4173 #define EJECT_CMPL_TYPE_SFT 0
4175 * Statistics Ejection Completion:
4176 * Completion of statistics data ejection buffer.
4179 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
4180 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
4181 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4182 #define EJECT_CMPL_FLAGS_SFT 6
4184 * When this bit is '1', it indicates a packet that has an
4185 * error of some type. Type of error is indicated in
4188 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4190 * This is the length of the statistics data stored in this
4195 * This is a copy of the opaque field from the RX BD this ejection
4196 * buffer corresponds to.
4201 * This value is written by the NIC such that it will be different
4202 * for each pass through the completion queue. The even passes
4203 * will write 1. The odd passes will write 0.
4205 #define EJECT_CMPL_V UINT32_C(0x1)
4206 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4207 #define EJECT_CMPL_ERRORS_SFT 1
4209 * This error indicates that there was some sort of problem with
4210 * the BDs for statistics ejection. The statistics ejection should
4211 * be treated as invalid
4213 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4214 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4215 /* No buffer error */
4216 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4217 (UINT32_C(0x0) << 1)
4220 * Statistics did not fit into aggregation buffer provided.
4222 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4223 (UINT32_C(0x1) << 1)
4226 * BDs were not formatted correctly.
4228 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4229 (UINT32_C(0x3) << 1)
4232 * There was a bad_format error on the previous operation
4234 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4235 (UINT32_C(0x5) << 1)
4236 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4237 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4238 /* reserved16 is 16 b */
4239 uint16_t reserved16;
4240 /* unused3 is 32 b */
4242 } __attribute__((packed));
4244 /* hwrm_cmpl (size:128b/16B) */
4248 * This field indicates the exact type of the completion.
4249 * By convention, the LSB identifies the length of the
4250 * record in 16B units. Even values indicate 16B
4251 * records. Odd values indicate 32B
4254 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
4255 #define HWRM_CMPL_TYPE_SFT 0
4257 * HWRM Command Completion:
4258 * Completion of an HWRM command.
4260 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
4261 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
4262 /* This is the sequence_id of the HWRM command that has completed. */
4263 uint16_t sequence_id;
4264 /* unused2 is 32 b */
4268 * This value is written by the NIC such that it will be different
4269 * for each pass through the completion queue. The even passes
4270 * will write 1. The odd passes will write 0.
4272 #define HWRM_CMPL_V UINT32_C(0x1)
4273 /* unused4 is 32 b */
4275 } __attribute__((packed));
4277 /* hwrm_fwd_req_cmpl (size:128b/16B) */
4278 struct hwrm_fwd_req_cmpl {
4280 * This field indicates the exact type of the completion.
4281 * By convention, the LSB identifies the length of the
4282 * record in 16B units. Even values indicate 16B
4283 * records. Odd values indicate 32B
4286 uint16_t req_len_type;
4288 * This field indicates the exact type of the completion.
4289 * By convention, the LSB identifies the length of the
4290 * record in 16B units. Even values indicate 16B
4291 * records. Odd values indicate 32B
4294 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
4295 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
4296 /* Forwarded HWRM Request */
4297 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
4298 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
4299 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
4300 /* Length of forwarded request in bytes. */
4301 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
4302 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
4304 * Source ID of this request.
4305 * Typically used in forwarding requests and responses.
4306 * 0x0 - 0xFFF8 - Used for function ids
4307 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4311 /* unused1 is 32 b */
4313 /* Address of forwarded request. */
4314 uint32_t req_buf_addr_v[2];
4316 * This value is written by the NIC such that it will be different
4317 * for each pass through the completion queue. The even passes
4318 * will write 1. The odd passes will write 0.
4320 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
4321 /* Address of forwarded request. */
4322 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4323 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
4324 } __attribute__((packed));
4326 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
4327 struct hwrm_fwd_resp_cmpl {
4330 * This field indicates the exact type of the completion.
4331 * By convention, the LSB identifies the length of the
4332 * record in 16B units. Even values indicate 16B
4333 * records. Odd values indicate 32B
4336 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
4337 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
4338 /* Forwarded HWRM Response */
4339 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
4340 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
4341 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
4343 * Source ID of this response.
4344 * Typically used in forwarding requests and responses.
4345 * 0x0 - 0xFFF8 - Used for function ids
4346 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4350 /* Length of forwarded response in bytes. */
4352 /* unused2 is 16 b */
4354 /* Address of forwarded request. */
4355 uint32_t resp_buf_addr_v[2];
4357 * This value is written by the NIC such that it will be different
4358 * for each pass through the completion queue. The even passes
4359 * will write 1. The odd passes will write 0.
4361 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
4362 /* Address of forwarded request. */
4363 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4364 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
4365 } __attribute__((packed));
4367 /* hwrm_async_event_cmpl (size:128b/16B) */
4368 struct hwrm_async_event_cmpl {
4371 * This field indicates the exact type of the completion.
4372 * By convention, the LSB identifies the length of the
4373 * record in 16B units. Even values indicate 16B
4374 * records. Odd values indicate 32B
4377 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
4378 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
4379 /* HWRM Asynchronous Event Information */
4380 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
4381 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
4382 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
4383 /* Identifiers of events. */
4385 /* Link status changed */
4386 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
4388 /* Link MTU changed */
4389 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
4391 /* Link speed changed */
4392 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
4394 /* DCB Configuration changed */
4395 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
4397 /* Port connection not allowed */
4398 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4400 /* Link speed configuration was not allowed */
4401 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4403 /* Link speed configuration change */
4404 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4406 /* Port PHY configuration change */
4407 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
4409 /* Reset notification to clients */
4410 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
4412 /* Master function selection event */
4413 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
4415 /* Function driver unloaded */
4416 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
4418 /* Function driver loaded */
4419 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
4421 /* Function FLR related processing has completed */
4422 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4424 /* PF driver unloaded */
4425 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
4427 /* PF driver loaded */
4428 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
4430 /* VF Function Level Reset (FLR) */
4431 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
4433 /* VF MAC Address Change */
4434 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
4436 /* PF-VF communication channel status change. */
4437 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4439 /* VF Configuration Change */
4440 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
4442 /* LLFC/PFC Configuration Change */
4443 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
4445 /* Default VNIC Configuration Change */
4446 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
4449 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
4452 * A debug notification being posted to the driver. These
4453 * notifications are purely for diagnostic purpose and should not be
4454 * used for functional purpose. The driver is not supposed to act
4455 * on these messages except to log/record it.
4457 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
4460 * An EEM flow cached memory flush for all flows request event being
4461 * posted to the PF driver.
4463 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
4466 * An EEM flow cache memory flush completion event being posted to the
4467 * firmware by the PF driver. This is indication that host EEM flush
4468 * has completed by the PF.
4470 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
4473 * A tcp flag action change event being posted to the PF or trusted VF
4474 * driver by the firmware. The PF or trusted VF driver should query
4475 * the firmware for the new TCP flag action update after receiving
4478 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
4481 * An EEM flow active event being posted to the PF or trusted VF driver
4482 * by the firmware. The PF or trusted VF driver should update the
4483 * flow's aging timer after receiving this async event.
4485 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
4488 * A eem cfg change event being posted to the trusted VF driver by the
4489 * firmware if the parent PF EEM configuration changed.
4491 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
4493 /* TFLIB unique default VNIC Configuration Change */
4494 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
4496 /* TFLIB unique link status changed */
4497 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
4500 * A trace log message. This contains firmware trace logs string
4501 * embedded in the asynchronous message. This is an experimental
4502 * event, not meant for production use at this time.
4504 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
4507 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
4509 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
4510 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
4511 /* Event specific data */
4512 uint32_t event_data2;
4515 * This value is written by the NIC such that it will be different
4516 * for each pass through the completion queue. The even passes
4517 * will write 1. The odd passes will write 0.
4519 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
4521 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
4522 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
4523 /* 8-lsb timestamp from POR (100-msec resolution) */
4524 uint8_t timestamp_lo;
4525 /* 16-lsb timestamp from POR (100-msec resolution) */
4526 uint16_t timestamp_hi;
4527 /* Event specific data */
4528 uint32_t event_data1;
4529 } __attribute__((packed));
4531 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
4532 struct hwrm_async_event_cmpl_link_status_change {
4535 * This field indicates the exact type of the completion.
4536 * By convention, the LSB identifies the length of the
4537 * record in 16B units. Even values indicate 16B
4538 * records. Odd values indicate 32B
4541 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
4543 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
4544 /* HWRM Asynchronous Event Information */
4545 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4547 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
4548 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4549 /* Identifiers of events. */
4551 /* Link status changed */
4552 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
4554 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
4555 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
4556 /* Event specific data */
4557 uint32_t event_data2;
4560 * This value is written by the NIC such that it will be different
4561 * for each pass through the completion queue. The even passes
4562 * will write 1. The odd passes will write 0.
4564 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
4567 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
4569 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
4570 /* 8-lsb timestamp from POR (100-msec resolution) */
4571 uint8_t timestamp_lo;
4572 /* 16-lsb timestamp from POR (100-msec resolution) */
4573 uint16_t timestamp_hi;
4574 /* Event specific data */
4575 uint32_t event_data1;
4576 /* Indicates link status change */
4577 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
4580 * If this bit set to 0, then it indicates that the link
4581 * was up and it went down.
4583 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
4586 * If this bit is set to 1, then it indicates that the link
4587 * was down and it went up.
4589 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
4591 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
4592 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
4593 /* Indicates the physical port this link status change occur */
4594 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
4596 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
4599 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4601 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4603 /* Indicates the physical function this event occurred on. */
4604 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
4606 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
4608 } __attribute__((packed));
4610 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
4611 struct hwrm_async_event_cmpl_link_mtu_change {
4614 * This field indicates the exact type of the completion.
4615 * By convention, the LSB identifies the length of the
4616 * record in 16B units. Even values indicate 16B
4617 * records. Odd values indicate 32B
4620 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
4622 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
4623 /* HWRM Asynchronous Event Information */
4624 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4626 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
4627 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
4628 /* Identifiers of events. */
4630 /* Link MTU changed */
4631 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
4633 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
4634 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
4635 /* Event specific data */
4636 uint32_t event_data2;
4639 * This value is written by the NIC such that it will be different
4640 * for each pass through the completion queue. The even passes
4641 * will write 1. The odd passes will write 0.
4643 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
4645 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
4647 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
4648 /* 8-lsb timestamp from POR (100-msec resolution) */
4649 uint8_t timestamp_lo;
4650 /* 16-lsb timestamp from POR (100-msec resolution) */
4651 uint16_t timestamp_hi;
4652 /* Event specific data */
4653 uint32_t event_data1;
4654 /* The new MTU of the link in bytes. */
4655 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4657 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4658 } __attribute__((packed));
4660 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4661 struct hwrm_async_event_cmpl_link_speed_change {
4664 * This field indicates the exact type of the completion.
4665 * By convention, the LSB identifies the length of the
4666 * record in 16B units. Even values indicate 16B
4667 * records. Odd values indicate 32B
4670 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4672 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4673 /* HWRM Asynchronous Event Information */
4674 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4676 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4677 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4678 /* Identifiers of events. */
4680 /* Link speed changed */
4681 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4683 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4684 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4685 /* Event specific data */
4686 uint32_t event_data2;
4689 * This value is written by the NIC such that it will be different
4690 * for each pass through the completion queue. The even passes
4691 * will write 1. The odd passes will write 0.
4693 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4696 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4698 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4699 /* 8-lsb timestamp from POR (100-msec resolution) */
4700 uint8_t timestamp_lo;
4701 /* 16-lsb timestamp from POR (100-msec resolution) */
4702 uint16_t timestamp_hi;
4703 /* Event specific data */
4704 uint32_t event_data1;
4706 * When this bit is '1', the link was forced to the
4707 * force_link_speed value.
4709 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4711 /* The new link speed in 100 Mbps units. */
4712 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4714 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4716 /* 100Mb link speed */
4717 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4718 (UINT32_C(0x1) << 1)
4719 /* 1Gb link speed */
4720 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4721 (UINT32_C(0xa) << 1)
4722 /* 2Gb link speed */
4723 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4724 (UINT32_C(0x14) << 1)
4725 /* 25Gb link speed */
4726 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4727 (UINT32_C(0x19) << 1)
4728 /* 10Gb link speed */
4729 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4730 (UINT32_C(0x64) << 1)
4731 /* 20Mb link speed */
4732 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4733 (UINT32_C(0xc8) << 1)
4734 /* 25Gb link speed */
4735 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4736 (UINT32_C(0xfa) << 1)
4737 /* 40Gb link speed */
4738 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4739 (UINT32_C(0x190) << 1)
4740 /* 50Gb link speed */
4741 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4742 (UINT32_C(0x1f4) << 1)
4743 /* 100Gb link speed */
4744 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4745 (UINT32_C(0x3e8) << 1)
4746 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4747 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4749 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4750 UINT32_C(0xffff0000)
4751 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4753 } __attribute__((packed));
4755 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4756 struct hwrm_async_event_cmpl_dcb_config_change {
4759 * This field indicates the exact type of the completion.
4760 * By convention, the LSB identifies the length of the
4761 * record in 16B units. Even values indicate 16B
4762 * records. Odd values indicate 32B
4765 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4767 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4768 /* HWRM Asynchronous Event Information */
4769 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4771 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4772 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4773 /* Identifiers of events. */
4775 /* DCB Configuration changed */
4776 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4778 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4779 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4780 /* Event specific data */
4781 uint32_t event_data2;
4782 /* ETS configuration change */
4783 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4785 /* PFC configuration change */
4786 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4788 /* APP configuration change */
4789 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4793 * This value is written by the NIC such that it will be different
4794 * for each pass through the completion queue. The even passes
4795 * will write 1. The odd passes will write 0.
4797 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4800 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4802 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4803 /* 8-lsb timestamp from POR (100-msec resolution) */
4804 uint8_t timestamp_lo;
4805 /* 16-lsb timestamp from POR (100-msec resolution) */
4806 uint16_t timestamp_hi;
4807 /* Event specific data */
4808 uint32_t event_data1;
4810 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4812 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4814 /* Priority recommended for RoCE traffic */
4815 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4817 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4820 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4821 (UINT32_C(0xff) << 16)
4822 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4823 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4824 /* Priority recommended for L2 traffic */
4825 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4826 UINT32_C(0xff000000)
4827 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4830 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4831 (UINT32_C(0xff) << 24)
4832 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4833 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4834 } __attribute__((packed));
4836 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4837 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4840 * This field indicates the exact type of the completion.
4841 * By convention, the LSB identifies the length of the
4842 * record in 16B units. Even values indicate 16B
4843 * records. Odd values indicate 32B
4846 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4848 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4850 /* HWRM Asynchronous Event Information */
4851 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4853 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4854 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4855 /* Identifiers of events. */
4857 /* Port connection not allowed */
4858 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4860 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4861 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4862 /* Event specific data */
4863 uint32_t event_data2;
4866 * This value is written by the NIC such that it will be different
4867 * for each pass through the completion queue. The even passes
4868 * will write 1. The odd passes will write 0.
4870 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4873 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4875 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4876 /* 8-lsb timestamp from POR (100-msec resolution) */
4877 uint8_t timestamp_lo;
4878 /* 16-lsb timestamp from POR (100-msec resolution) */
4879 uint16_t timestamp_hi;
4880 /* Event specific data */
4881 uint32_t event_data1;
4883 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4885 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4888 * This value indicates the current port level enforcement policy
4889 * for the optics module when there is an optical module mismatch
4890 * and port is not connected.
4892 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4894 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4896 /* No enforcement */
4897 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4898 (UINT32_C(0x0) << 16)
4899 /* Disable Transmit side Laser. */
4900 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4901 (UINT32_C(0x1) << 16)
4902 /* Raise a warning message. */
4903 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4904 (UINT32_C(0x2) << 16)
4905 /* Power down the module. */
4906 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4907 (UINT32_C(0x3) << 16)
4908 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4909 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4910 } __attribute__((packed));
4912 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4913 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4916 * This field indicates the exact type of the completion.
4917 * By convention, the LSB identifies the length of the
4918 * record in 16B units. Even values indicate 16B
4919 * records. Odd values indicate 32B
4922 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4924 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4926 /* HWRM Asynchronous Event Information */
4927 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4929 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4930 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4931 /* Identifiers of events. */
4933 /* Link speed configuration was not allowed */
4934 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4936 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4937 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4938 /* Event specific data */
4939 uint32_t event_data2;
4942 * This value is written by the NIC such that it will be different
4943 * for each pass through the completion queue. The even passes
4944 * will write 1. The odd passes will write 0.
4946 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4949 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4951 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4952 /* 8-lsb timestamp from POR (100-msec resolution) */
4953 uint8_t timestamp_lo;
4954 /* 16-lsb timestamp from POR (100-msec resolution) */
4955 uint16_t timestamp_hi;
4956 /* Event specific data */
4957 uint32_t event_data1;
4959 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4961 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4963 } __attribute__((packed));
4965 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4966 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4969 * This field indicates the exact type of the completion.
4970 * By convention, the LSB identifies the length of the
4971 * record in 16B units. Even values indicate 16B
4972 * records. Odd values indicate 32B
4975 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
4977 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
4979 /* HWRM Asynchronous Event Information */
4980 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4982 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
4983 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4984 /* Identifiers of events. */
4986 /* Link speed configuration change */
4987 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4989 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
4990 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
4991 /* Event specific data */
4992 uint32_t event_data2;
4995 * This value is written by the NIC such that it will be different
4996 * for each pass through the completion queue. The even passes
4997 * will write 1. The odd passes will write 0.
4999 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
5002 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
5004 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
5005 /* 8-lsb timestamp from POR (100-msec resolution) */
5006 uint8_t timestamp_lo;
5007 /* 16-lsb timestamp from POR (100-msec resolution) */
5008 uint16_t timestamp_hi;
5009 /* Event specific data */
5010 uint32_t event_data1;
5012 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5014 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5017 * If set to 1, it indicates that the supported link speeds
5018 * configuration on the port has changed.
5019 * If set to 0, then there is no change in supported link speeds
5022 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
5025 * If set to 1, it indicates that the link speed configuration
5026 * on the port has become illegal or invalid.
5027 * If set to 0, then the link speed configuration on the port is
5030 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
5032 } __attribute__((packed));
5034 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
5035 struct hwrm_async_event_cmpl_port_phy_cfg_change {
5038 * This field indicates the exact type of the completion.
5039 * By convention, the LSB identifies the length of the
5040 * record in 16B units. Even values indicate 16B
5041 * records. Odd values indicate 32B
5044 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
5046 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
5048 /* HWRM Asynchronous Event Information */
5049 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5051 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
5052 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5053 /* Identifiers of events. */
5055 /* Port PHY configuration change */
5056 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
5058 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
5059 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
5060 /* Event specific data */
5061 uint32_t event_data2;
5064 * This value is written by the NIC such that it will be different
5065 * for each pass through the completion queue. The even passes
5066 * will write 1. The odd passes will write 0.
5068 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
5071 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
5073 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
5074 /* 8-lsb timestamp from POR (100-msec resolution) */
5075 uint8_t timestamp_lo;
5076 /* 16-lsb timestamp from POR (100-msec resolution) */
5077 uint16_t timestamp_hi;
5078 /* Event specific data */
5079 uint32_t event_data1;
5081 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5083 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5086 * If set to 1, it indicates that the FEC
5087 * configuration on the port has changed.
5088 * If set to 0, then there is no change in FEC configuration.
5090 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
5093 * If set to 1, it indicates that the EEE configuration
5094 * on the port has changed.
5095 * If set to 0, then there is no change in EEE configuration
5098 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
5101 * If set to 1, it indicates that the pause configuration
5102 * on the PHY has changed.
5103 * If set to 0, then there is no change in the pause
5104 * configuration on the PHY.
5106 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
5108 } __attribute__((packed));
5110 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
5111 struct hwrm_async_event_cmpl_reset_notify {
5114 * This field indicates the exact type of the completion.
5115 * By convention, the LSB identifies the length of the
5116 * record in 16B units. Even values indicate 16B
5117 * records. Odd values indicate 32B
5120 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
5122 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
5123 /* HWRM Asynchronous Event Information */
5124 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
5126 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
5127 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
5128 /* Identifiers of events. */
5130 /* Notify clients of imminent reset. */
5131 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
5133 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
5134 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
5135 /* Event specific data */
5136 uint32_t event_data2;
5139 * This value is written by the NIC such that it will be different
5140 * for each pass through the completion queue. The even passes
5141 * will write 1. The odd passes will write 0.
5143 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
5145 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
5146 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
5148 * 8-lsb timestamp (100-msec resolution)
5149 * The Minimum time required for the Firmware readiness after sending this
5150 * notification to the driver instances.
5152 uint8_t timestamp_lo;
5154 * 16-lsb timestamp (100-msec resolution)
5155 * The Maximum Firmware Reset bail out value in the order of 100
5156 * milli seconds. The driver instances will use this value to re-initiate the
5157 * registration process again if the core firmware didn’t set the ready
5160 uint16_t timestamp_hi;
5161 /* Event specific data */
5162 uint32_t event_data1;
5163 /* Indicates driver action requested */
5164 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
5166 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
5169 * If set to 1, it indicates that the l2 client should
5170 * stop sending in band traffic to Nitro.
5171 * if set to 0, there is no change in L2 client behavior.
5173 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
5176 * If set to 1, it indicates that the L2 client should
5177 * bring down the interface.
5178 * If set to 0, then there is no change in L2 client behavior.
5180 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
5182 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
5183 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
5184 /* Indicates reason for reset. */
5185 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
5187 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
5189 /* A management client has requested reset. */
5190 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
5191 (UINT32_C(0x1) << 8)
5192 /* A fatal firmware exception has occurred. */
5193 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
5194 (UINT32_C(0x2) << 8)
5195 /* A non-fatal firmware exception has occurred. */
5196 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
5197 (UINT32_C(0x3) << 8)
5198 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
5199 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
5201 * Minimum time before driver should attempt access - units 100ms ticks.
5204 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
5205 UINT32_C(0xffff0000)
5206 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
5208 } __attribute__((packed));
5210 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
5211 struct hwrm_async_event_cmpl_error_recovery {
5214 * This field indicates the exact type of the completion.
5215 * By convention, the LSB identifies the length of the
5216 * record in 16B units. Even values indicate 16B
5217 * records. Odd values indicate 32B
5220 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
5222 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
5223 /* HWRM Asynchronous Event Information */
5224 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
5226 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
5227 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
5228 /* Identifiers of events. */
5231 * This async notification message can be used for selecting or
5232 * deselecting master function for error recovery,
5233 * and to communicate to all the functions whether error recovery
5234 * was enabled/disabled.
5236 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
5238 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
5239 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
5240 /* Event specific data */
5241 uint32_t event_data2;
5244 * This value is written by the NIC such that it will be different
5245 * for each pass through the completion queue. The even passes
5246 * will write 1. The odd passes will write 0.
5248 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
5250 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
5251 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
5252 /* 8-lsb timestamp (100-msec resolution) */
5253 uint8_t timestamp_lo;
5254 /* 16-lsb timestamp (100-msec resolution) */
5255 uint16_t timestamp_hi;
5256 /* Event specific data */
5257 uint32_t event_data1;
5258 /* Indicates driver action requested */
5259 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
5261 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
5264 * If set to 1, this function is selected as Master function.
5265 * This function has responsibility to do 'chip reset' when it
5266 * detects a fatal error. If set to 0, master function functionality
5267 * is disabled on this function.
5269 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
5272 * If set to 1, error recovery is enabled.
5273 * If set to 0, error recovery is disabled.
5275 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
5277 } __attribute__((packed));
5279 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
5280 struct hwrm_async_event_cmpl_func_drvr_unload {
5283 * This field indicates the exact type of the completion.
5284 * By convention, the LSB identifies the length of the
5285 * record in 16B units. Even values indicate 16B
5286 * records. Odd values indicate 32B
5289 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
5291 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
5292 /* HWRM Asynchronous Event Information */
5293 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5295 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
5296 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5297 /* Identifiers of events. */
5299 /* Function driver unloaded */
5300 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
5302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
5303 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
5304 /* Event specific data */
5305 uint32_t event_data2;
5308 * This value is written by the NIC such that it will be different
5309 * for each pass through the completion queue. The even passes
5310 * will write 1. The odd passes will write 0.
5312 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
5314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
5316 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
5317 /* 8-lsb timestamp from POR (100-msec resolution) */
5318 uint8_t timestamp_lo;
5319 /* 16-lsb timestamp from POR (100-msec resolution) */
5320 uint16_t timestamp_hi;
5321 /* Event specific data */
5322 uint32_t event_data1;
5324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5326 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
5328 } __attribute__((packed));
5330 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
5331 struct hwrm_async_event_cmpl_func_drvr_load {
5334 * This field indicates the exact type of the completion.
5335 * By convention, the LSB identifies the length of the
5336 * record in 16B units. Even values indicate 16B
5337 * records. Odd values indicate 32B
5340 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
5342 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
5343 /* HWRM Asynchronous Event Information */
5344 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5346 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
5347 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5348 /* Identifiers of events. */
5350 /* Function driver loaded */
5351 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
5353 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
5354 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
5355 /* Event specific data */
5356 uint32_t event_data2;
5359 * This value is written by the NIC such that it will be different
5360 * for each pass through the completion queue. The even passes
5361 * will write 1. The odd passes will write 0.
5363 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
5365 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5366 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
5367 /* 8-lsb timestamp from POR (100-msec resolution) */
5368 uint8_t timestamp_lo;
5369 /* 16-lsb timestamp from POR (100-msec resolution) */
5370 uint16_t timestamp_hi;
5371 /* Event specific data */
5372 uint32_t event_data1;
5374 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5376 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5377 } __attribute__((packed));
5379 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
5380 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
5383 * This field indicates the exact type of the completion.
5384 * By convention, the LSB identifies the length of the
5385 * record in 16B units. Even values indicate 16B
5386 * records. Odd values indicate 32B
5389 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
5391 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
5393 /* HWRM Asynchronous Event Information */
5394 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
5396 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
5397 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
5398 /* Identifiers of events. */
5400 /* Function FLR related processing has completed */
5401 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
5403 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
5404 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
5405 /* Event specific data */
5406 uint32_t event_data2;
5409 * This value is written by the NIC such that it will be different
5410 * for each pass through the completion queue. The even passes
5411 * will write 1. The odd passes will write 0.
5413 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
5416 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
5418 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
5419 /* 8-lsb timestamp from POR (100-msec resolution) */
5420 uint8_t timestamp_lo;
5421 /* 16-lsb timestamp from POR (100-msec resolution) */
5422 uint16_t timestamp_hi;
5423 /* Event specific data */
5424 uint32_t event_data1;
5426 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
5428 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
5430 } __attribute__((packed));
5432 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
5433 struct hwrm_async_event_cmpl_pf_drvr_unload {
5436 * This field indicates the exact type of the completion.
5437 * By convention, the LSB identifies the length of the
5438 * record in 16B units. Even values indicate 16B
5439 * records. Odd values indicate 32B
5442 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
5444 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
5445 /* HWRM Asynchronous Event Information */
5446 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5448 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
5449 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5450 /* Identifiers of events. */
5452 /* PF driver unloaded */
5453 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
5455 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
5456 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
5457 /* Event specific data */
5458 uint32_t event_data2;
5461 * This value is written by the NIC such that it will be different
5462 * for each pass through the completion queue. The even passes
5463 * will write 1. The odd passes will write 0.
5465 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
5467 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
5468 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
5469 /* 8-lsb timestamp from POR (100-msec resolution) */
5470 uint8_t timestamp_lo;
5471 /* 16-lsb timestamp from POR (100-msec resolution) */
5472 uint16_t timestamp_hi;
5473 /* Event specific data */
5474 uint32_t event_data1;
5476 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5478 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
5479 /* Indicates the physical port this pf belongs to */
5480 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
5482 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
5483 } __attribute__((packed));
5485 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
5486 struct hwrm_async_event_cmpl_pf_drvr_load {
5489 * This field indicates the exact type of the completion.
5490 * By convention, the LSB identifies the length of the
5491 * record in 16B units. Even values indicate 16B
5492 * records. Odd values indicate 32B
5495 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
5497 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
5498 /* HWRM Asynchronous Event Information */
5499 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5501 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
5502 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5503 /* Identifiers of events. */
5505 /* PF driver loaded */
5506 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
5508 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
5509 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
5510 /* Event specific data */
5511 uint32_t event_data2;
5514 * This value is written by the NIC such that it will be different
5515 * for each pass through the completion queue. The even passes
5516 * will write 1. The odd passes will write 0.
5518 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
5520 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5521 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
5522 /* 8-lsb timestamp from POR (100-msec resolution) */
5523 uint8_t timestamp_lo;
5524 /* 16-lsb timestamp from POR (100-msec resolution) */
5525 uint16_t timestamp_hi;
5526 /* Event specific data */
5527 uint32_t event_data1;
5529 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5531 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5532 /* Indicates the physical port this pf belongs to */
5533 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
5535 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
5536 } __attribute__((packed));
5538 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
5539 struct hwrm_async_event_cmpl_vf_flr {
5542 * This field indicates the exact type of the completion.
5543 * By convention, the LSB identifies the length of the
5544 * record in 16B units. Even values indicate 16B
5545 * records. Odd values indicate 32B
5548 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
5550 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
5551 /* HWRM Asynchronous Event Information */
5552 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
5554 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
5555 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
5556 /* Identifiers of events. */
5558 /* VF Function Level Reset (FLR) */
5559 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
5560 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
5561 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
5562 /* Event specific data */
5563 uint32_t event_data2;
5566 * This value is written by the NIC such that it will be different
5567 * for each pass through the completion queue. The even passes
5568 * will write 1. The odd passes will write 0.
5570 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
5572 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
5573 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
5574 /* 8-lsb timestamp from POR (100-msec resolution) */
5575 uint8_t timestamp_lo;
5576 /* 16-lsb timestamp from POR (100-msec resolution) */
5577 uint16_t timestamp_hi;
5578 /* Event specific data */
5579 uint32_t event_data1;
5581 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
5583 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
5584 /* Indicates the physical function this event occurred on. */
5585 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
5587 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
5588 } __attribute__((packed));
5590 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
5591 struct hwrm_async_event_cmpl_vf_mac_addr_change {
5594 * This field indicates the exact type of the completion.
5595 * By convention, the LSB identifies the length of the
5596 * record in 16B units. Even values indicate 16B
5597 * records. Odd values indicate 32B
5600 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
5602 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
5603 /* HWRM Asynchronous Event Information */
5604 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5606 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
5607 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
5608 /* Identifiers of events. */
5610 /* VF MAC Address Change */
5611 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
5613 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
5614 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
5615 /* Event specific data */
5616 uint32_t event_data2;
5619 * This value is written by the NIC such that it will be different
5620 * for each pass through the completion queue. The even passes
5621 * will write 1. The odd passes will write 0.
5623 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
5626 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
5628 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
5629 /* 8-lsb timestamp from POR (100-msec resolution) */
5630 uint8_t timestamp_lo;
5631 /* 16-lsb timestamp from POR (100-msec resolution) */
5632 uint16_t timestamp_hi;
5633 /* Event specific data */
5634 uint32_t event_data1;
5636 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
5638 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
5640 } __attribute__((packed));
5642 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
5643 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
5646 * This field indicates the exact type of the completion.
5647 * By convention, the LSB identifies the length of the
5648 * record in 16B units. Even values indicate 16B
5649 * records. Odd values indicate 32B
5652 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5654 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5656 /* HWRM Asynchronous Event Information */
5657 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5659 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5660 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5661 /* Identifiers of events. */
5663 /* PF-VF communication channel status change. */
5664 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5666 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5667 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5668 /* Event specific data */
5669 uint32_t event_data2;
5672 * This value is written by the NIC such that it will be different
5673 * for each pass through the completion queue. The even passes
5674 * will write 1. The odd passes will write 0.
5676 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5679 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5681 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5682 /* 8-lsb timestamp from POR (100-msec resolution) */
5683 uint8_t timestamp_lo;
5684 /* 16-lsb timestamp from POR (100-msec resolution) */
5685 uint16_t timestamp_hi;
5686 /* Event specific data */
5687 uint32_t event_data1;
5689 * If this bit is set to 1, then it indicates that the PF-VF
5690 * communication was lost and it is established.
5691 * If this bit set to 0, then it indicates that the PF-VF
5692 * communication was established and it is lost.
5694 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5696 } __attribute__((packed));
5698 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5699 struct hwrm_async_event_cmpl_vf_cfg_change {
5702 * This field indicates the exact type of the completion.
5703 * By convention, the LSB identifies the length of the
5704 * record in 16B units. Even values indicate 16B
5705 * records. Odd values indicate 32B
5708 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5710 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5711 /* HWRM Asynchronous Event Information */
5712 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5714 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5715 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5716 /* Identifiers of events. */
5718 /* VF Configuration Change */
5719 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5721 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5722 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5723 /* Event specific data */
5724 uint32_t event_data2;
5727 * This value is written by the NIC such that it will be different
5728 * for each pass through the completion queue. The even passes
5729 * will write 1. The odd passes will write 0.
5731 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5733 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5734 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5735 /* 8-lsb timestamp from POR (100-msec resolution) */
5736 uint8_t timestamp_lo;
5737 /* 16-lsb timestamp from POR (100-msec resolution) */
5738 uint16_t timestamp_hi;
5740 * Each flag provided in this field indicates a specific VF
5741 * configuration change. At least one of these flags shall be set to 1
5742 * when an asynchronous event completion of this type is provided
5745 uint32_t event_data1;
5747 * If this bit is set to 1, then the value of MTU
5748 * was changed on this VF.
5749 * If set to 0, then this bit should be ignored.
5751 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5754 * If this bit is set to 1, then the value of MRU
5755 * was changed on this VF.
5756 * If set to 0, then this bit should be ignored.
5758 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5761 * If this bit is set to 1, then the value of default MAC
5762 * address was changed on this VF.
5763 * If set to 0, then this bit should be ignored.
5765 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5768 * If this bit is set to 1, then the value of default VLAN
5769 * was changed on this VF.
5770 * If set to 0, then this bit should be ignored.
5772 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5775 * If this bit is set to 1, then the value of trusted VF enable
5776 * was changed on this VF.
5777 * If set to 0, then this bit should be ignored.
5779 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5781 } __attribute__((packed));
5783 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5784 struct hwrm_async_event_cmpl_llfc_pfc_change {
5787 * This field indicates the exact type of the completion.
5788 * By convention, the LSB identifies the length of the
5789 * record in 16B units. Even values indicate 16B
5790 * records. Odd values indicate 32B
5793 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5795 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5796 /* HWRM Asynchronous Event Information */
5797 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5799 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5800 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5801 /* unused1 is 10 b */
5802 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5804 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5805 /* Identifiers of events. */
5807 /* LLFC/PFC Configuration Change */
5808 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5810 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5811 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5812 /* Event specific data */
5813 uint32_t event_data2;
5816 * This value is written by the NIC such that it will be different
5817 * for each pass through the completion queue. The even passes
5818 * will write 1. The odd passes will write 0.
5820 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5822 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5824 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5825 /* 8-lsb timestamp from POR (100-msec resolution) */
5826 uint8_t timestamp_lo;
5827 /* 16-lsb timestamp from POR (100-msec resolution) */
5828 uint16_t timestamp_hi;
5829 /* Event specific data */
5830 uint32_t event_data1;
5831 /* Indicates llfc pfc status change */
5832 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5834 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5837 * If this field set to 1, then it indicates that llfc is
5840 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5843 * If this field is set to 2, then it indicates that pfc
5846 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5848 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5849 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5850 /* Indicates the physical port this llfc pfc change occur */
5851 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5853 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5856 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5858 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5860 } __attribute__((packed));
5862 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5863 struct hwrm_async_event_cmpl_default_vnic_change {
5866 * This field indicates the exact type of the completion.
5867 * By convention, the LSB identifies the length of the
5868 * record in 16B units. Even values indicate 16B
5869 * records. Odd values indicate 32B
5872 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5874 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5876 /* HWRM Asynchronous Event Information */
5877 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5879 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5880 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5881 /* unused1 is 10 b */
5882 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5884 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5886 /* Identifiers of events. */
5888 /* Notification of a default vnic allocaiton or free */
5889 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5891 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5892 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5893 /* Event specific data */
5894 uint32_t event_data2;
5897 * This value is written by the NIC such that it will be different
5898 * for each pass through the completion queue. The even passes
5899 * will write 1. The odd passes will write 0.
5901 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5904 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5906 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5907 /* 8-lsb timestamp from POR (100-msec resolution) */
5908 uint8_t timestamp_lo;
5909 /* 16-lsb timestamp from POR (100-msec resolution) */
5910 uint16_t timestamp_hi;
5911 /* Event specific data */
5912 uint32_t event_data1;
5913 /* Indicates default vnic configuration change */
5914 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5916 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5919 * If this field is set to 1, then it indicates that
5920 * a default VNIC has been allocate.
5922 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5925 * If this field is set to 2, then it indicates that
5926 * a default VNIC has been freed.
5928 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5930 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5931 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5932 /* Indicates the physical function this event occurred on. */
5933 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5935 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5937 /* Indicates the virtual function this event occurred on */
5938 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5940 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5942 } __attribute__((packed));
5944 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5945 struct hwrm_async_event_cmpl_hw_flow_aged {
5948 * This field indicates the exact type of the completion.
5949 * By convention, the LSB identifies the length of the
5950 * record in 16B units. Even values indicate 16B
5951 * records. Odd values indicate 32B
5954 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5956 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5957 /* HWRM Asynchronous Event Information */
5958 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5960 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5961 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5962 /* Identifiers of events. */
5964 /* Notification of a hw flow aged */
5965 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5967 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5968 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5969 /* Event specific data */
5970 uint32_t event_data2;
5973 * This value is written by the NIC such that it will be different
5974 * for each pass through the completion queue. The even passes
5975 * will write 1. The odd passes will write 0.
5977 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
5979 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
5980 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
5981 /* 8-lsb timestamp from POR (100-msec resolution) */
5982 uint8_t timestamp_lo;
5983 /* 16-lsb timestamp from POR (100-msec resolution) */
5984 uint16_t timestamp_hi;
5985 /* Event specific data */
5986 uint32_t event_data1;
5987 /* Indicates flow ID this event occurred on. */
5988 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
5989 UINT32_C(0x7fffffff)
5990 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
5992 /* Indicates flow direction this event occurred on. */
5993 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
5994 UINT32_C(0x80000000)
5996 * If this bit set to 0, then it indicates that the aged
5997 * event was rx flow.
5999 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
6000 (UINT32_C(0x0) << 31)
6002 * If this bit is set to 1, then it indicates that the aged
6003 * event was tx flow.
6005 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
6006 (UINT32_C(0x1) << 31)
6007 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
6008 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
6009 } __attribute__((packed));
6011 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
6012 struct hwrm_async_event_cmpl_eem_cache_flush_req {
6015 * This field indicates the exact type of the completion.
6016 * By convention, the LSB identifies the length of the
6017 * record in 16B units. Even values indicate 16B
6018 * records. Odd values indicate 32B
6021 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
6023 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
6025 /* HWRM Asynchronous Event Information */
6026 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
6028 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
6029 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
6030 /* Identifiers of events. */
6032 /* Notification of a eem_cache_flush request */
6033 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6035 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
6036 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
6037 /* Event specific data */
6038 uint32_t event_data2;
6041 * This value is written by the NIC such that it will be different
6042 * for each pass through the completion queue. The even passes
6043 * will write 1. The odd passes will write 0.
6045 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
6048 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
6050 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
6051 /* 8-lsb timestamp from POR (100-msec resolution) */
6052 uint8_t timestamp_lo;
6053 /* 16-lsb timestamp from POR (100-msec resolution) */
6054 uint16_t timestamp_hi;
6055 /* Event specific data */
6056 uint32_t event_data1;
6057 } __attribute__((packed));
6059 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
6060 struct hwrm_async_event_cmpl_eem_cache_flush_done {
6063 * This field indicates the exact type of the completion.
6064 * By convention, the LSB identifies the length of the
6065 * record in 16B units. Even values indicate 16B
6066 * records. Odd values indicate 32B
6069 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
6071 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
6073 /* HWRM Asynchronous Event Information */
6074 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
6076 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
6077 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
6078 /* Identifiers of events. */
6081 * Notification of a host eem_cache_flush has completed. This event
6082 * is generated by the host driver.
6084 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6086 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
6087 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
6088 /* Event specific data */
6089 uint32_t event_data2;
6092 * This value is written by the NIC such that it will be different
6093 * for each pass through the completion queue. The even passes
6094 * will write 1. The odd passes will write 0.
6096 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
6099 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
6101 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
6102 /* 8-lsb timestamp from POR (100-msec resolution) */
6103 uint8_t timestamp_lo;
6104 /* 16-lsb timestamp from POR (100-msec resolution) */
6105 uint16_t timestamp_hi;
6106 /* Event specific data */
6107 uint32_t event_data1;
6108 /* Indicates function ID that this event occurred on. */
6109 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
6111 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
6113 } __attribute__((packed));
6115 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
6116 struct hwrm_async_event_cmpl_tcp_flag_action_change {
6119 * This field indicates the exact type of the completion.
6120 * By convention, the LSB identifies the length of the
6121 * record in 16B units. Even values indicate 16B
6122 * records. Odd values indicate 32B
6125 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
6127 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
6129 /* HWRM Asynchronous Event Information */
6130 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6132 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
6133 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
6134 /* Identifiers of events. */
6136 /* Notification of tcp flag action change */
6137 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6139 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
6140 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
6141 /* Event specific data */
6142 uint32_t event_data2;
6145 * This value is written by the NIC such that it will be different
6146 * for each pass through the completion queue. The even passes
6147 * will write 1. The odd passes will write 0.
6149 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
6152 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
6154 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
6155 /* 8-lsb timestamp from POR (100-msec resolution) */
6156 uint8_t timestamp_lo;
6157 /* 16-lsb timestamp from POR (100-msec resolution) */
6158 uint16_t timestamp_hi;
6159 /* Event specific data */
6160 uint32_t event_data1;
6161 } __attribute__((packed));
6163 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
6164 struct hwrm_async_event_cmpl_eem_flow_active {
6167 * This field indicates the exact type of the completion.
6168 * By convention, the LSB identifies the length of the
6169 * record in 16B units. Even values indicate 16B
6170 * records. Odd values indicate 32B
6173 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
6175 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
6176 /* HWRM Asynchronous Event Information */
6177 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
6179 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
6180 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
6181 /* Identifiers of events. */
6183 /* Notification of an active eem flow */
6184 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
6186 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
6187 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
6188 /* Event specific data */
6189 uint32_t event_data2;
6190 /* Indicates the 2nd global id this event occurred on. */
6191 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
6192 UINT32_C(0x3fffffff)
6193 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
6196 * Indicates flow direction of the flow identified by
6199 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
6200 UINT32_C(0x40000000)
6201 /* If this bit is set to 0, then it indicates that this rx flow. */
6202 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
6203 (UINT32_C(0x0) << 30)
6204 /* If this bit is set to 1, then it indicates that this tx flow. */
6205 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
6206 (UINT32_C(0x1) << 30)
6207 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
6208 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
6211 * This value is written by the NIC such that it will be different
6212 * for each pass through the completion queue. The even passes
6213 * will write 1. The odd passes will write 0.
6215 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
6217 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
6219 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
6220 /* 8-lsb timestamp from POR (100-msec resolution) */
6221 uint8_t timestamp_lo;
6222 /* 16-lsb timestamp from POR (100-msec resolution) */
6223 uint16_t timestamp_hi;
6224 /* Event specific data */
6225 uint32_t event_data1;
6226 /* Indicates the 1st global id this event occurred on. */
6227 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
6228 UINT32_C(0x3fffffff)
6229 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
6232 * Indicates flow direction of the flow identified by the
6235 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
6236 UINT32_C(0x40000000)
6237 /* If this bit is set to 0, then it indicates that this is rx flow. */
6238 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
6239 (UINT32_C(0x0) << 30)
6240 /* If this bit is set to 1, then it indicates that this is tx flow. */
6241 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
6242 (UINT32_C(0x1) << 30)
6243 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
6244 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
6246 * Indicates EEM flow aging mode this event occurred on. If
6247 * this bit is set to 0, the event_data1 is the EEM global
6248 * ID. If this bit is set to 1, the event_data1 is the number
6249 * of global ID in the context memory.
6251 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
6252 UINT32_C(0x80000000)
6253 /* EEM flow aging mode 0. */
6254 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
6255 (UINT32_C(0x0) << 31)
6256 /* EEM flow aging mode 1. */
6257 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
6258 (UINT32_C(0x1) << 31)
6259 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
6260 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
6261 } __attribute__((packed));
6263 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
6264 struct hwrm_async_event_cmpl_eem_cfg_change {
6267 * This field indicates the exact type of the completion.
6268 * By convention, the LSB identifies the length of the
6269 * record in 16B units. Even values indicate 16B
6270 * records. Odd values indicate 32B
6273 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
6275 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
6276 /* HWRM Asynchronous Event Information */
6277 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6279 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
6280 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6281 /* Identifiers of events. */
6283 /* Notification of EEM configuration change */
6284 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
6286 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
6287 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
6288 /* Event specific data */
6289 uint32_t event_data2;
6292 * This value is written by the NIC such that it will be different
6293 * for each pass through the completion queue. The even passes
6294 * will write 1. The odd passes will write 0.
6296 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
6298 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
6299 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
6300 /* 8-lsb timestamp from POR (100-msec resolution) */
6301 uint8_t timestamp_lo;
6302 /* 16-lsb timestamp from POR (100-msec resolution) */
6303 uint16_t timestamp_hi;
6304 /* Event specific data */
6305 uint32_t event_data1;
6307 * Value of 1 to indicate EEM TX configuration is enabled. Value of
6308 * 0 to indicate the EEM TX configuration is disabled.
6310 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
6313 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
6314 * to indicate the EEM RX configuration is disabled.
6316 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
6318 } __attribute__((packed));
6320 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
6321 struct hwrm_async_event_cmpl_fw_trace_msg {
6324 * This field indicates the exact type of the completion.
6325 * By convention, the LSB identifies the length of the
6326 * record in 16B units. Even values indicate 16B
6327 * records. Odd values indicate 32B
6330 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
6332 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
6333 /* HWRM Asynchronous Event Information */
6334 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
6336 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
6337 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
6338 /* Identifiers of events. */
6340 /* Firmware trace log message */
6341 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
6343 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
6344 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
6345 /* Trace byte 0 to 3 */
6346 uint32_t event_data2;
6348 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
6350 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
6352 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
6354 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
6356 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
6358 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
6360 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
6361 UINT32_C(0xff000000)
6362 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
6365 * This value is written by the NIC such that it will be different
6366 * for each pass through the completion queue. The even passes
6367 * will write 1. The odd passes will write 0.
6369 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
6371 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
6372 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
6374 uint8_t timestamp_lo;
6375 /* Indicates if the string is partial or complete. */
6376 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
6378 /* Complete string */
6379 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
6381 /* Partial string */
6382 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
6384 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
6385 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
6386 /* Indicates the firmware that sent the trace message. */
6387 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
6389 /* Primary firmware */
6390 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
6391 (UINT32_C(0x0) << 1)
6392 /* Secondary firmware */
6393 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
6394 (UINT32_C(0x1) << 1)
6395 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
6396 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
6397 /* Trace byte 4 to 5 */
6398 uint16_t timestamp_hi;
6400 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
6402 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
6404 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
6406 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
6407 /* Trace byte 6 to 9 */
6408 uint32_t event_data1;
6410 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
6412 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
6414 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
6416 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
6418 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
6420 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
6422 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
6423 UINT32_C(0xff000000)
6424 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
6425 } __attribute__((packed));
6427 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
6428 struct hwrm_async_event_cmpl_hwrm_error {
6431 * This field indicates the exact type of the completion.
6432 * By convention, the LSB identifies the length of the
6433 * record in 16B units. Even values indicate 16B
6434 * records. Odd values indicate 32B
6437 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
6439 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
6440 /* HWRM Asynchronous Event Information */
6441 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
6443 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
6444 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
6445 /* Identifiers of events. */
6448 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
6450 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
6451 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
6452 /* Event specific data */
6453 uint32_t event_data2;
6454 /* Severity of HWRM Error */
6455 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
6457 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
6459 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
6461 /* Non-fatal Error */
6462 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
6465 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
6467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
6468 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
6471 * This value is written by the NIC such that it will be different
6472 * for each pass through the completion queue. The even passes
6473 * will write 1. The odd passes will write 0.
6475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
6477 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
6478 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
6479 /* 8-lsb timestamp from POR (100-msec resolution) */
6480 uint8_t timestamp_lo;
6481 /* 16-lsb timestamp from POR (100-msec resolution) */
6482 uint16_t timestamp_hi;
6483 /* Event specific data */
6484 uint32_t event_data1;
6485 /* Time stamp for error event */
6486 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
6488 } __attribute__((packed));
6490 /*******************
6492 *******************/
6495 /* hwrm_func_reset_input (size:192b/24B) */
6496 struct hwrm_func_reset_input {
6497 /* The HWRM command request type. */
6500 * The completion ring to send the completion event on. This should
6501 * be the NQ ID returned from the `nq_alloc` HWRM command.
6505 * The sequence ID is used by the driver for tracking multiple
6506 * commands. This ID is treated as opaque data by the firmware and
6507 * the value is returned in the `hwrm_resp_hdr` upon completion.
6511 * The target ID of the command:
6512 * * 0x0-0xFFF8 - The function ID
6513 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6514 * * 0xFFFD - Reserved for user-space HWRM interface
6519 * A physical address pointer pointing to a host buffer that the
6520 * command's response data will be written. This can be either a host
6521 * physical address (HPA) or a guest physical address (GPA) and must
6522 * point to a physically contiguous block of memory.
6527 * This bit must be '1' for the vf_id_valid field to be
6530 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
6532 * The ID of the VF that this PF is trying to reset.
6533 * Only the parent PF shall be allowed to reset a child VF.
6535 * A parent PF driver shall use this field only when a specific child VF
6536 * is requested to be reset.
6539 /* This value indicates the level of a function reset. */
6540 uint8_t func_reset_level;
6542 * Reset the caller function and its children VFs (if any). If no
6543 * children functions exist, then reset the caller function only.
6545 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
6547 /* Reset the caller function only */
6548 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
6551 * Reset all children VFs of the caller function driver if the
6552 * caller is a PF driver.
6553 * It is an error to specify this level by a VF driver.
6554 * It is an error to specify this level by a PF driver with
6557 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
6560 * Reset a specific VF of the caller function driver if the caller
6561 * is the parent PF driver.
6562 * It is an error to specify this level by a VF driver.
6563 * It is an error to specify this level by a PF driver that is not
6564 * the parent of the VF that is being requested to reset.
6566 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
6568 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
6569 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
6571 } __attribute__((packed));
6573 /* hwrm_func_reset_output (size:128b/16B) */
6574 struct hwrm_func_reset_output {
6575 /* The specific error status for the command. */
6576 uint16_t error_code;
6577 /* The HWRM command request type. */
6579 /* The sequence ID from the original command. */
6581 /* The length of the response data in number of bytes. */
6583 uint8_t unused_0[7];
6585 * This field is used in Output records to indicate that the output
6586 * is completely written to RAM. This field should be read as '1'
6587 * to indicate that the output has been completely written.
6588 * When writing a command completion or response to an internal processor,
6589 * the order of writes has to be such that this field is written last.
6592 } __attribute__((packed));
6594 /********************
6595 * hwrm_func_getfid *
6596 ********************/
6599 /* hwrm_func_getfid_input (size:192b/24B) */
6600 struct hwrm_func_getfid_input {
6601 /* The HWRM command request type. */
6604 * The completion ring to send the completion event on. This should
6605 * be the NQ ID returned from the `nq_alloc` HWRM command.
6609 * The sequence ID is used by the driver for tracking multiple
6610 * commands. This ID is treated as opaque data by the firmware and
6611 * the value is returned in the `hwrm_resp_hdr` upon completion.
6615 * The target ID of the command:
6616 * * 0x0-0xFFF8 - The function ID
6617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6618 * * 0xFFFD - Reserved for user-space HWRM interface
6623 * A physical address pointer pointing to a host buffer that the
6624 * command's response data will be written. This can be either a host
6625 * physical address (HPA) or a guest physical address (GPA) and must
6626 * point to a physically contiguous block of memory.
6631 * This bit must be '1' for the pci_id field to be
6634 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
6636 * This value is the PCI ID of the queried function.
6637 * If ARI is enabled, then it is
6638 * Bus Number (8b):Function Number(8b). Otherwise, it is
6639 * Bus Number (8b):Device Number (5b):Function Number(3b).
6642 uint8_t unused_0[2];
6643 } __attribute__((packed));
6645 /* hwrm_func_getfid_output (size:128b/16B) */
6646 struct hwrm_func_getfid_output {
6647 /* The specific error status for the command. */
6648 uint16_t error_code;
6649 /* The HWRM command request type. */
6651 /* The sequence ID from the original command. */
6653 /* The length of the response data in number of bytes. */
6656 * FID value. This value is used to identify operations on the PCI
6657 * bus as belonging to a particular PCI function.
6660 uint8_t unused_0[5];
6662 * This field is used in Output records to indicate that the output
6663 * is completely written to RAM. This field should be read as '1'
6664 * to indicate that the output has been completely written.
6665 * When writing a command completion or response to an internal processor,
6666 * the order of writes has to be such that this field is written last.
6669 } __attribute__((packed));
6671 /**********************
6672 * hwrm_func_vf_alloc *
6673 **********************/
6676 /* hwrm_func_vf_alloc_input (size:192b/24B) */
6677 struct hwrm_func_vf_alloc_input {
6678 /* The HWRM command request type. */
6681 * The completion ring to send the completion event on. This should
6682 * be the NQ ID returned from the `nq_alloc` HWRM command.
6686 * The sequence ID is used by the driver for tracking multiple
6687 * commands. This ID is treated as opaque data by the firmware and
6688 * the value is returned in the `hwrm_resp_hdr` upon completion.
6692 * The target ID of the command:
6693 * * 0x0-0xFFF8 - The function ID
6694 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6695 * * 0xFFFD - Reserved for user-space HWRM interface
6700 * A physical address pointer pointing to a host buffer that the
6701 * command's response data will be written. This can be either a host
6702 * physical address (HPA) or a guest physical address (GPA) and must
6703 * point to a physically contiguous block of memory.
6708 * This bit must be '1' for the first_vf_id field to be
6711 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6713 * This value is used to identify a Virtual Function (VF).
6714 * The scope of VF ID is local within a PF.
6716 uint16_t first_vf_id;
6717 /* The number of virtual functions requested. */
6719 } __attribute__((packed));
6721 /* hwrm_func_vf_alloc_output (size:128b/16B) */
6722 struct hwrm_func_vf_alloc_output {
6723 /* The specific error status for the command. */
6724 uint16_t error_code;
6725 /* The HWRM command request type. */
6727 /* The sequence ID from the original command. */
6729 /* The length of the response data in number of bytes. */
6731 /* The ID of the first VF allocated. */
6732 uint16_t first_vf_id;
6733 uint8_t unused_0[5];
6735 * This field is used in Output records to indicate that the output
6736 * is completely written to RAM. This field should be read as '1'
6737 * to indicate that the output has been completely written.
6738 * When writing a command completion or response to an internal processor,
6739 * the order of writes has to be such that this field is written last.
6742 } __attribute__((packed));
6744 /*********************
6745 * hwrm_func_vf_free *
6746 *********************/
6749 /* hwrm_func_vf_free_input (size:192b/24B) */
6750 struct hwrm_func_vf_free_input {
6751 /* The HWRM command request type. */
6754 * The completion ring to send the completion event on. This should
6755 * be the NQ ID returned from the `nq_alloc` HWRM command.
6759 * The sequence ID is used by the driver for tracking multiple
6760 * commands. This ID is treated as opaque data by the firmware and
6761 * the value is returned in the `hwrm_resp_hdr` upon completion.
6765 * The target ID of the command:
6766 * * 0x0-0xFFF8 - The function ID
6767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6768 * * 0xFFFD - Reserved for user-space HWRM interface
6773 * A physical address pointer pointing to a host buffer that the
6774 * command's response data will be written. This can be either a host
6775 * physical address (HPA) or a guest physical address (GPA) and must
6776 * point to a physically contiguous block of memory.
6781 * This bit must be '1' for the first_vf_id field to be
6784 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6786 * This value is used to identify a Virtual Function (VF).
6787 * The scope of VF ID is local within a PF.
6789 uint16_t first_vf_id;
6791 * The number of virtual functions requested.
6792 * 0xFFFF - Cleanup all children of this PF.
6795 } __attribute__((packed));
6797 /* hwrm_func_vf_free_output (size:128b/16B) */
6798 struct hwrm_func_vf_free_output {
6799 /* The specific error status for the command. */
6800 uint16_t error_code;
6801 /* The HWRM command request type. */
6803 /* The sequence ID from the original command. */
6805 /* The length of the response data in number of bytes. */
6807 uint8_t unused_0[7];
6809 * This field is used in Output records to indicate that the output
6810 * is completely written to RAM. This field should be read as '1'
6811 * to indicate that the output has been completely written.
6812 * When writing a command completion or response to an internal processor,
6813 * the order of writes has to be such that this field is written last.
6816 } __attribute__((packed));
6818 /********************
6819 * hwrm_func_vf_cfg *
6820 ********************/
6823 /* hwrm_func_vf_cfg_input (size:448b/56B) */
6824 struct hwrm_func_vf_cfg_input {
6825 /* The HWRM command request type. */
6828 * The completion ring to send the completion event on. This should
6829 * be the NQ ID returned from the `nq_alloc` HWRM command.
6833 * The sequence ID is used by the driver for tracking multiple
6834 * commands. This ID is treated as opaque data by the firmware and
6835 * the value is returned in the `hwrm_resp_hdr` upon completion.
6839 * The target ID of the command:
6840 * * 0x0-0xFFF8 - The function ID
6841 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6842 * * 0xFFFD - Reserved for user-space HWRM interface
6847 * A physical address pointer pointing to a host buffer that the
6848 * command's response data will be written. This can be either a host
6849 * physical address (HPA) or a guest physical address (GPA) and must
6850 * point to a physically contiguous block of memory.
6855 * This bit must be '1' for the mtu field to be
6858 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
6861 * This bit must be '1' for the guest_vlan field to be
6864 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
6867 * This bit must be '1' for the async_event_cr field to be
6870 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6873 * This bit must be '1' for the dflt_mac_addr field to be
6876 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6879 * This bit must be '1' for the num_rsscos_ctxs field to be
6882 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6885 * This bit must be '1' for the num_cmpl_rings field to be
6888 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6891 * This bit must be '1' for the num_tx_rings field to be
6894 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6897 * This bit must be '1' for the num_rx_rings field to be
6900 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6903 * This bit must be '1' for the num_l2_ctxs field to be
6906 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6909 * This bit must be '1' for the num_vnics field to be
6912 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
6915 * This bit must be '1' for the num_stat_ctxs field to be
6918 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6921 * This bit must be '1' for the num_hw_ring_grps field to be
6924 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6927 * The maximum transmission unit requested on the function.
6928 * The HWRM should make sure that the mtu of
6929 * the function does not exceed the mtu of the physical
6930 * port that this function is associated with.
6932 * In addition to requesting mtu per function, it is
6933 * possible to configure mtu per transmit ring.
6934 * By default, the mtu of each transmit ring associated
6935 * with a function is equal to the mtu of the function.
6936 * The HWRM should make sure that the mtu of each transmit
6937 * ring that is assigned to a function has a valid mtu.
6941 * The guest VLAN for the function being configured.
6942 * This field's format is same as 802.1Q Tag's
6943 * Tag Control Information (TCI) format that includes both
6944 * Priority Code Point (PCP) and VLAN Identifier (VID).
6946 uint16_t guest_vlan;
6948 * ID of the target completion ring for receiving asynchronous
6949 * event completions. If this field is not valid, then the
6950 * HWRM shall use the default completion ring of the function
6951 * that is being configured as the target completion ring for
6952 * providing any asynchronous event completions for that
6954 * If this field is valid, then the HWRM shall use the
6955 * completion ring identified by this ID as the target
6956 * completion ring for providing any asynchronous event
6957 * completions for the function that is being configured.
6959 uint16_t async_event_cr;
6961 * This value is the current MAC address requested by the VF
6962 * driver to be configured on this VF. A value of
6963 * 00-00-00-00-00-00 indicates no MAC address configuration
6964 * is requested by the VF driver.
6965 * The parent PF driver may reject or overwrite this
6968 uint8_t dflt_mac_addr[6];
6971 * This bit requests that the firmware test to see if all the assets
6972 * requested in this command (i.e. number of TX rings) are available.
6973 * The firmware will return an error if the requested assets are
6974 * not available. The firwmare will NOT reserve the assets if they
6977 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6980 * This bit requests that the firmware test to see if all the assets
6981 * requested in this command (i.e. number of RX rings) are available.
6982 * The firmware will return an error if the requested assets are
6983 * not available. The firwmare will NOT reserve the assets if they
6986 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6989 * This bit requests that the firmware test to see if all the assets
6990 * requested in this command (i.e. number of CMPL rings) are available.
6991 * The firmware will return an error if the requested assets are
6992 * not available. The firwmare will NOT reserve the assets if they
6995 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6998 * This bit requests that the firmware test to see if all the assets
6999 * requested in this command (i.e. number of RSS ctx) are available.
7000 * The firmware will return an error if the requested assets are
7001 * not available. The firwmare will NOT reserve the assets if they
7004 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7007 * This bit requests that the firmware test to see if all the assets
7008 * requested in this command (i.e. number of ring groups) are available.
7009 * The firmware will return an error if the requested assets are
7010 * not available. The firwmare will NOT reserve the assets if they
7013 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7016 * This bit requests that the firmware test to see if all the assets
7017 * requested in this command (i.e. number of stat ctx) are available.
7018 * The firmware will return an error if the requested assets are
7019 * not available. The firwmare will NOT reserve the assets if they
7022 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7025 * This bit requests that the firmware test to see if all the assets
7026 * requested in this command (i.e. number of VNICs) are available.
7027 * The firmware will return an error if the requested assets are
7028 * not available. The firwmare will NOT reserve the assets if they
7031 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7034 * This bit requests that the firmware test to see if all the assets
7035 * requested in this command (i.e. number of L2 ctx) are available.
7036 * The firmware will return an error if the requested assets are
7037 * not available. The firwmare will NOT reserve the assets if they
7040 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7042 /* The number of RSS/COS contexts requested for the VF. */
7043 uint16_t num_rsscos_ctxs;
7044 /* The number of completion rings requested for the VF. */
7045 uint16_t num_cmpl_rings;
7046 /* The number of transmit rings requested for the VF. */
7047 uint16_t num_tx_rings;
7048 /* The number of receive rings requested for the VF. */
7049 uint16_t num_rx_rings;
7050 /* The number of L2 contexts requested for the VF. */
7051 uint16_t num_l2_ctxs;
7052 /* The number of vnics requested for the VF. */
7054 /* The number of statistic contexts requested for the VF. */
7055 uint16_t num_stat_ctxs;
7056 /* The number of HW ring groups requested for the VF. */
7057 uint16_t num_hw_ring_grps;
7058 uint8_t unused_0[4];
7059 } __attribute__((packed));
7061 /* hwrm_func_vf_cfg_output (size:128b/16B) */
7062 struct hwrm_func_vf_cfg_output {
7063 /* The specific error status for the command. */
7064 uint16_t error_code;
7065 /* The HWRM command request type. */
7067 /* The sequence ID from the original command. */
7069 /* The length of the response data in number of bytes. */
7071 uint8_t unused_0[7];
7073 * This field is used in Output records to indicate that the output
7074 * is completely written to RAM. This field should be read as '1'
7075 * to indicate that the output has been completely written.
7076 * When writing a command completion or response to an internal processor,
7077 * the order of writes has to be such that this field is written last.
7080 } __attribute__((packed));
7082 /*******************
7084 *******************/
7087 /* hwrm_func_qcaps_input (size:192b/24B) */
7088 struct hwrm_func_qcaps_input {
7089 /* The HWRM command request type. */
7092 * The completion ring to send the completion event on. This should
7093 * be the NQ ID returned from the `nq_alloc` HWRM command.
7097 * The sequence ID is used by the driver for tracking multiple
7098 * commands. This ID is treated as opaque data by the firmware and
7099 * the value is returned in the `hwrm_resp_hdr` upon completion.
7103 * The target ID of the command:
7104 * * 0x0-0xFFF8 - The function ID
7105 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7106 * * 0xFFFD - Reserved for user-space HWRM interface
7111 * A physical address pointer pointing to a host buffer that the
7112 * command's response data will be written. This can be either a host
7113 * physical address (HPA) or a guest physical address (GPA) and must
7114 * point to a physically contiguous block of memory.
7118 * Function ID of the function that is being queried.
7119 * 0xFF... (All Fs) if the query is for the requesting
7123 uint8_t unused_0[6];
7124 } __attribute__((packed));
7126 /* hwrm_func_qcaps_output (size:640b/80B) */
7127 struct hwrm_func_qcaps_output {
7128 /* The specific error status for the command. */
7129 uint16_t error_code;
7130 /* The HWRM command request type. */
7132 /* The sequence ID from the original command. */
7134 /* The length of the response data in number of bytes. */
7137 * FID value. This value is used to identify operations on the PCI
7138 * bus as belonging to a particular PCI function.
7142 * Port ID of port that this function is associated with.
7143 * Valid only for the PF.
7144 * 0xFF... (All Fs) if this function is not associated with
7146 * 0xFF... (All Fs) if this function is called from a VF.
7150 /* If 1, then Push mode is supported on this function. */
7151 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
7154 * If 1, then the global MSI-X auto-masking is enabled for the
7157 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
7160 * If 1, then the Precision Time Protocol (PTP) processing
7161 * is supported on this function.
7162 * The HWRM should enable PTP on only a single Physical
7163 * Function (PF) per port.
7165 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
7168 * If 1, then RDMA over Converged Ethernet (RoCE) v1
7169 * is supported on this function.
7171 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
7174 * If 1, then RDMA over Converged Ethernet (RoCE) v2
7175 * is supported on this function.
7177 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
7180 * If 1, then control and configuration of WoL magic packet
7181 * are supported on this function.
7183 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
7186 * If 1, then control and configuration of bitmap pattern
7187 * packet are supported on this function.
7189 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
7192 * If set to 1, then the control and configuration of rate limit
7193 * of an allocated TX ring on the queried function is supported.
7195 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
7198 * If 1, then control and configuration of minimum and
7199 * maximum bandwidths are supported on the queried function.
7201 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
7204 * If the query is for a VF, then this flag shall be ignored.
7205 * If this query is for a PF and this flag is set to 1,
7206 * then the PF has the capability to set the rate limits
7207 * on the TX rings of its children VFs.
7208 * If this query is for a PF and this flag is set to 0, then
7209 * the PF does not have the capability to set the rate limits
7210 * on the TX rings of its children VFs.
7212 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
7215 * If the query is for a VF, then this flag shall be ignored.
7216 * If this query is for a PF and this flag is set to 1,
7217 * then the PF has the capability to set the minimum and/or
7218 * maximum bandwidths for its children VFs.
7219 * If this query is for a PF and this flag is set to 0, then
7220 * the PF does not have the capability to set the minimum or
7221 * maximum bandwidths for its children VFs.
7223 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
7226 * Standard TX Ring mode is used for the allocation of TX ring
7227 * and underlying scheduling resources that allow bandwidth
7228 * reservation and limit settings on the queried function.
7229 * If set to 1, then standard TX ring mode is supported
7230 * on the queried function.
7231 * If set to 0, then standard TX ring mode is not available
7232 * on the queried function.
7234 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
7237 * If the query is for a VF, then this flag shall be ignored,
7238 * If this query is for a PF and this flag is set to 1,
7239 * then the PF has the capability to detect GENEVE tunnel
7242 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
7245 * If the query is for a VF, then this flag shall be ignored,
7246 * If this query is for a PF and this flag is set to 1,
7247 * then the PF has the capability to detect NVGRE tunnel
7250 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
7253 * If the query is for a VF, then this flag shall be ignored,
7254 * If this query is for a PF and this flag is set to 1,
7255 * then the PF has the capability to detect GRE tunnel
7258 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
7261 * If the query is for a VF, then this flag shall be ignored,
7262 * If this query is for a PF and this flag is set to 1,
7263 * then the PF has the capability to detect MPLS tunnel
7266 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
7269 * If the query is for a VF, then this flag shall be ignored,
7270 * If this query is for a PF and this flag is set to 1,
7271 * then the PF has the capability to support pcie stats.
7273 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
7276 * If the query is for a VF, then this flag shall be ignored,
7277 * If this query is for a PF and this flag is set to 1,
7278 * then the PF has the capability to adopt the VF's belonging
7281 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
7284 * If the query is for a VF, then this flag shall be ignored,
7285 * If this query is for a PF and this flag is set to 1,
7286 * then the PF has the administrative privilege to configure another PF
7288 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
7291 * If the query is for a VF, then this flag shall be ignored.
7292 * If this query is for a PF and this flag is set to 1, then
7293 * the PF will know that the firmware has the capability to track
7294 * the virtual link status.
7296 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
7299 * If 1, then this function supports the push mode that uses
7300 * write combine buffers and the long inline tx buffer descriptor.
7302 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
7305 * If 1, then FW has capability to allocate TX rings dynamically
7306 * in ring alloc even if PF reserved pool is zero.
7307 * This bit will be used only for PFs.
7309 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7312 * When this bit is '1', it indicates that core firmware is
7313 * capable of Hot Reset.
7315 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
7318 * This flag will be set to 1 by the FW if FW supports adapter error
7321 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
7324 * If the query is for a VF, then this flag shall be ignored.
7325 * If this query is for a PF and this flag is set to 1, then
7326 * the PF has the capability to support extended stats.
7328 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
7331 * This value is current MAC address configured for this
7332 * function. A value of 00-00-00-00-00-00 indicates no
7333 * MAC address is currently configured.
7335 uint8_t mac_address[6];
7337 * The maximum number of RSS/COS contexts that can be
7338 * allocated to the function.
7340 uint16_t max_rsscos_ctx;
7342 * The maximum number of completion rings that can be
7343 * allocated to the function.
7345 uint16_t max_cmpl_rings;
7347 * The maximum number of transmit rings that can be
7348 * allocated to the function.
7350 uint16_t max_tx_rings;
7352 * The maximum number of receive rings that can be
7353 * allocated to the function.
7355 uint16_t max_rx_rings;
7357 * The maximum number of L2 contexts that can be
7358 * allocated to the function.
7360 uint16_t max_l2_ctxs;
7362 * The maximum number of VNICs that can be
7363 * allocated to the function.
7367 * The identifier for the first VF enabled on a PF. This
7368 * is valid only on the PF with SR-IOV enabled.
7369 * 0xFF... (All Fs) if this command is called on a PF with
7370 * SR-IOV disabled or on a VF.
7372 uint16_t first_vf_id;
7374 * The maximum number of VFs that can be
7375 * allocated to the function. This is valid only on the
7376 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
7377 * command is called on a PF with SR-IOV disabled or
7382 * The maximum number of statistic contexts that can be
7383 * allocated to the function.
7385 uint16_t max_stat_ctx;
7387 * The maximum number of Encapsulation records that can be
7388 * offloaded by this function.
7390 uint32_t max_encap_records;
7392 * The maximum number of decapsulation records that can
7393 * be offloaded by this function.
7395 uint32_t max_decap_records;
7397 * The maximum number of Exact Match (EM) flows that can be
7398 * offloaded by this function on the TX side.
7400 uint32_t max_tx_em_flows;
7402 * The maximum number of Wildcard Match (WM) flows that can
7403 * be offloaded by this function on the TX side.
7405 uint32_t max_tx_wm_flows;
7407 * The maximum number of Exact Match (EM) flows that can be
7408 * offloaded by this function on the RX side.
7410 uint32_t max_rx_em_flows;
7412 * The maximum number of Wildcard Match (WM) flows that can
7413 * be offloaded by this function on the RX side.
7415 uint32_t max_rx_wm_flows;
7417 * The maximum number of multicast filters that can
7418 * be supported by this function on the RX side.
7420 uint32_t max_mcast_filters;
7422 * The maximum value of flow_id that can be supported
7423 * in completion records.
7425 uint32_t max_flow_id;
7427 * The maximum number of HW ring groups that can be
7428 * supported on this function.
7430 uint32_t max_hw_ring_grps;
7432 * The maximum number of strict priority transmit rings
7433 * that can be allocated to the function.
7434 * This number indicates the maximum number of TX rings
7435 * that can be assigned strict priorities out of the
7436 * maximum number of TX rings that can be allocated
7437 * (max_tx_rings) to the function.
7439 uint16_t max_sp_tx_rings;
7442 * This field is used in Output records to indicate that the output
7443 * is completely written to RAM. This field should be read as '1'
7444 * to indicate that the output has been completely written.
7445 * When writing a command completion or response to an internal processor,
7446 * the order of writes has to be such that this field is written last.
7449 } __attribute__((packed));
7456 /* hwrm_func_qcfg_input (size:192b/24B) */
7457 struct hwrm_func_qcfg_input {
7458 /* The HWRM command request type. */
7461 * The completion ring to send the completion event on. This should
7462 * be the NQ ID returned from the `nq_alloc` HWRM command.
7466 * The sequence ID is used by the driver for tracking multiple
7467 * commands. This ID is treated as opaque data by the firmware and
7468 * the value is returned in the `hwrm_resp_hdr` upon completion.
7472 * The target ID of the command:
7473 * * 0x0-0xFFF8 - The function ID
7474 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7475 * * 0xFFFD - Reserved for user-space HWRM interface
7480 * A physical address pointer pointing to a host buffer that the
7481 * command's response data will be written. This can be either a host
7482 * physical address (HPA) or a guest physical address (GPA) and must
7483 * point to a physically contiguous block of memory.
7487 * Function ID of the function that is being queried.
7488 * 0xFF... (All Fs) if the query is for the requesting
7492 uint8_t unused_0[6];
7493 } __attribute__((packed));
7495 /* hwrm_func_qcfg_output (size:704b/88B) */
7496 struct hwrm_func_qcfg_output {
7497 /* The specific error status for the command. */
7498 uint16_t error_code;
7499 /* The HWRM command request type. */
7501 /* The sequence ID from the original command. */
7503 /* The length of the response data in number of bytes. */
7506 * FID value. This value is used to identify operations on the PCI
7507 * bus as belonging to a particular PCI function.
7511 * Port ID of port that this function is associated with.
7512 * 0xFF... (All Fs) if this function is not associated with
7517 * This value is the current VLAN setting for this
7518 * function. The value of 0 for this field indicates
7519 * no priority tagging or VLAN is used.
7520 * This field's format is same as 802.1Q Tag's
7521 * Tag Control Information (TCI) format that includes both
7522 * Priority Code Point (PCP) and VLAN Identifier (VID).
7527 * If 1, then magic packet based Out-Of-Box WoL is enabled on
7528 * the port associated with this function.
7530 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
7533 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
7534 * on the port associated with this function.
7536 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
7539 * If set to 1, then FW based DCBX agent is enabled and running on
7540 * the port associated with this function.
7541 * If set to 0, then DCBX agent is not running in the firmware.
7543 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
7546 * Standard TX Ring mode is used for the allocation of TX ring
7547 * and underlying scheduling resources that allow bandwidth
7548 * reservation and limit settings on the queried function.
7549 * If set to 1, then standard TX ring mode is enabled
7550 * on the queried function.
7551 * If set to 0, then the standard TX ring mode is disabled
7552 * on the queried function. In this extended TX ring resource
7553 * mode, the minimum and maximum bandwidth settings are not
7554 * supported to allow the allocation of TX rings to span multiple
7557 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
7560 * If set to 1 then FW based LLDP agent is enabled and running on
7561 * the port associated with this function.
7562 * If set to 0 then the LLDP agent is not running in the firmware.
7564 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
7567 * If set to 1, then multi-host mode is active for this function.
7568 * If set to 0, then multi-host mode is inactive for this function
7569 * or not applicable for this device.
7571 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
7574 * If the function that is being queried is a PF, then the HWRM shall
7575 * set this field to 0 and the HWRM client shall ignore this field.
7576 * If the function that is being queried is a VF, then the HWRM shall
7577 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
7578 * shall set this field to 0.
7580 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
7583 * If set to 1, then secure mode is enabled for this function or device.
7584 * If set to 0, then secure mode is disabled (or normal mode) for this
7585 * function or device.
7587 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
7590 * If set to 1, then this PF is enabled with a preboot driver that
7591 * requires access to the legacy L2 ring model and legacy 32b
7592 * doorbells. If set to 0, then this PF is not allowed to use
7593 * the legacy L2 rings. This feature is not allowed on VFs and
7594 * is only relevant for devices that require a context backing
7597 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
7600 * This value is current MAC address configured for this
7601 * function. A value of 00-00-00-00-00-00 indicates no
7602 * MAC address is currently configured.
7604 uint8_t mac_address[6];
7606 * This value is current PCI ID of this
7607 * function. If ARI is enabled, then it is
7608 * Bus Number (8b):Function Number(8b). Otherwise, it is
7609 * Bus Number (8b):Device Number (4b):Function Number(4b).
7610 * If multi-host mode is active, the 4 lsb will indicate
7611 * the PF index for this function.
7615 * The number of RSS/COS contexts currently
7616 * allocated to the function.
7618 uint16_t alloc_rsscos_ctx;
7620 * The number of completion rings currently allocated to
7621 * the function. This does not include the rings allocated
7622 * to any children functions if any.
7624 uint16_t alloc_cmpl_rings;
7626 * The number of transmit rings currently allocated to
7627 * the function. This does not include the rings allocated
7628 * to any children functions if any.
7630 uint16_t alloc_tx_rings;
7632 * The number of receive rings currently allocated to
7633 * the function. This does not include the rings allocated
7634 * to any children functions if any.
7636 uint16_t alloc_rx_rings;
7637 /* The allocated number of L2 contexts to the function. */
7638 uint16_t alloc_l2_ctx;
7639 /* The allocated number of vnics to the function. */
7640 uint16_t alloc_vnics;
7642 * The maximum transmission unit of the function.
7643 * If the reported mtu value is non-zero then it will used for the
7644 * rings allocated on this function. otherwise the default
7645 * value is used if ring MTU is not specified.
7649 * The maximum receive unit of the function.
7650 * For vnics allocated on this function, this default
7651 * value is used if vnic MRU is not specified.
7654 /* The statistics context assigned to a function. */
7655 uint16_t stat_ctx_id;
7657 * The HWRM shall return Unknown value for this field
7658 * when this command is used to query VF's configuration.
7660 uint8_t port_partition_type;
7661 /* Single physical function */
7662 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
7663 /* Multiple physical functions */
7664 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
7665 /* Network Partitioning 1.0 */
7666 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
7667 /* Network Partitioning 1.5 */
7668 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
7669 /* Network Partitioning 2.0 */
7670 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
7672 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
7674 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
7675 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
7677 * This field will indicate number of physical functions on this port_partition.
7678 * HWRM shall return unavail (i.e. value of 0) for this field
7679 * when this command is used to query VF's configuration or
7680 * from older firmware that doesn't support this field.
7682 uint8_t port_pf_cnt;
7683 /* number of PFs is not available */
7684 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
7685 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
7686 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
7688 * The default VNIC ID assigned to a function that is
7691 uint16_t dflt_vnic_id;
7692 uint16_t max_mtu_configured;
7694 * Minimum BW allocated for this function.
7695 * The HWRM will translate this value into byte counter and
7696 * time interval used for the scheduler inside the device.
7697 * A value of 0 indicates the minimum bandwidth is not
7701 /* The bandwidth value. */
7702 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
7704 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
7705 /* The granularity of the value (bits or bytes). */
7706 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
7707 UINT32_C(0x10000000)
7708 /* Value is in bits. */
7709 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
7710 (UINT32_C(0x0) << 28)
7711 /* Value is in bytes. */
7712 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
7713 (UINT32_C(0x1) << 28)
7714 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
7715 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
7716 /* bw_value_unit is 3 b */
7717 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7718 UINT32_C(0xe0000000)
7719 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7720 /* Value is in Mb or MB (base 10). */
7721 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7722 (UINT32_C(0x0) << 29)
7723 /* Value is in Kb or KB (base 10). */
7724 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7725 (UINT32_C(0x2) << 29)
7726 /* Value is in bits or bytes. */
7727 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7728 (UINT32_C(0x4) << 29)
7729 /* Value is in Gb or GB (base 10). */
7730 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7731 (UINT32_C(0x6) << 29)
7732 /* Value is in 1/100th of a percentage of total bandwidth. */
7733 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7734 (UINT32_C(0x1) << 29)
7736 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7737 (UINT32_C(0x7) << 29)
7738 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7739 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7741 * Maximum BW allocated for this function.
7742 * The HWRM will translate this value into byte counter and
7743 * time interval used for the scheduler inside the device.
7744 * A value of 0 indicates that the maximum bandwidth is not
7748 /* The bandwidth value. */
7749 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
7751 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
7752 /* The granularity of the value (bits or bytes). */
7753 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
7754 UINT32_C(0x10000000)
7755 /* Value is in bits. */
7756 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
7757 (UINT32_C(0x0) << 28)
7758 /* Value is in bytes. */
7759 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
7760 (UINT32_C(0x1) << 28)
7761 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
7762 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
7763 /* bw_value_unit is 3 b */
7764 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7765 UINT32_C(0xe0000000)
7766 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7767 /* Value is in Mb or MB (base 10). */
7768 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7769 (UINT32_C(0x0) << 29)
7770 /* Value is in Kb or KB (base 10). */
7771 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7772 (UINT32_C(0x2) << 29)
7773 /* Value is in bits or bytes. */
7774 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7775 (UINT32_C(0x4) << 29)
7776 /* Value is in Gb or GB (base 10). */
7777 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7778 (UINT32_C(0x6) << 29)
7779 /* Value is in 1/100th of a percentage of total bandwidth. */
7780 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7781 (UINT32_C(0x1) << 29)
7783 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7784 (UINT32_C(0x7) << 29)
7785 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7786 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7788 * This value indicates the Edge virtual bridge mode for the
7789 * domain that this function belongs to.
7792 /* No Edge Virtual Bridging (EVB) */
7793 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7794 /* Virtual Ethernet Bridge (VEB) */
7795 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
7796 /* Virtual Ethernet Port Aggregator (VEPA) */
7797 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
7798 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
7799 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
7802 * This value indicates the PCIE device cache line size.
7803 * The cache line size allows the DMA writes to terminate and
7804 * start at the cache boundary.
7806 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
7808 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7809 /* Cache Line Size 64 bytes */
7810 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7812 /* Cache Line Size 128 bytes */
7813 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7815 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
7816 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7817 /* This value is the virtual link admin state setting. */
7818 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7820 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7821 /* Admin link state is in forced down mode. */
7822 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7823 (UINT32_C(0x0) << 2)
7824 /* Admin link state is in forced up mode. */
7825 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7826 (UINT32_C(0x1) << 2)
7827 /* Admin link state is in auto mode - follows the physical link state. */
7828 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7829 (UINT32_C(0x2) << 2)
7830 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7831 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7832 /* Reserved for future. */
7833 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
7835 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
7837 * The number of VFs that are allocated to the function.
7838 * This is valid only on the PF with SR-IOV enabled.
7839 * 0xFF... (All Fs) if this command is called on a PF with
7840 * SR-IOV disabled or on a VF.
7844 * The number of allocated multicast filters for this
7845 * function on the RX side.
7847 uint32_t alloc_mcast_filters;
7849 * The number of allocated HW ring groups for this
7852 uint32_t alloc_hw_ring_grps;
7854 * The number of strict priority transmit rings out of
7855 * currently allocated TX rings to the function
7858 uint16_t alloc_sp_tx_rings;
7860 * The number of statistics contexts
7861 * currently reserved for the function.
7863 uint16_t alloc_stat_ctx;
7865 * This field specifies how many NQs are reserved for the PF.
7866 * Remaining NQs that belong to the PF are available for VFs.
7867 * Once a PF has created VFs, it cannot change how many NQs are
7868 * reserved for itself (since the NQs must be contiguous in HW).
7870 uint16_t alloc_msix;
7872 * The number of registered VF’s associated with the PF. This field
7873 * should be ignored when the request received on the VF interface.
7874 * This field will be updated on the PF interface to initiate
7875 * the unregister request on PF in the HOT Reset Process.
7877 uint16_t registered_vfs;
7879 * The size of the doorbell BAR in KBytes reserved for L2 including
7880 * any area that is shared between L2 and RoCE. The L2 driver
7881 * should only map the L2 portion of the doorbell BAR. Any rounding
7882 * of the BAR size to the native CPU page size should be performed
7883 * by the driver. If the value is zero, no special partitioning
7884 * of the doorbell BAR between L2 and RoCE is required.
7886 uint16_t l2_doorbell_bar_size_kb;
7889 * For backward compatibility this field must be set to 1.
7890 * Older drivers might look for this field to be 1 before
7891 * processing the message.
7895 * This GRC address location is used by the Host driver interfaces to poll
7896 * the adapter ready state to re-initiate the registration process again
7897 * after receiving the RESET Notify event.
7899 uint32_t reset_addr_poll;
7900 uint8_t unused_2[3];
7902 * This field is used in Output records to indicate that the output
7903 * is completely written to RAM. This field should be read as '1'
7904 * to indicate that the output has been completely written.
7905 * When writing a command completion or response to an internal processor,
7906 * the order of writes has to be such that this field is written last.
7909 } __attribute__((packed));
7916 /* hwrm_func_cfg_input (size:704b/88B) */
7917 struct hwrm_func_cfg_input {
7918 /* The HWRM command request type. */
7921 * The completion ring to send the completion event on. This should
7922 * be the NQ ID returned from the `nq_alloc` HWRM command.
7926 * The sequence ID is used by the driver for tracking multiple
7927 * commands. This ID is treated as opaque data by the firmware and
7928 * the value is returned in the `hwrm_resp_hdr` upon completion.
7932 * The target ID of the command:
7933 * * 0x0-0xFFF8 - The function ID
7934 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7935 * * 0xFFFD - Reserved for user-space HWRM interface
7940 * A physical address pointer pointing to a host buffer that the
7941 * command's response data will be written. This can be either a host
7942 * physical address (HPA) or a guest physical address (GPA) and must
7943 * point to a physically contiguous block of memory.
7947 * Function ID of the function that is being
7949 * If set to 0xFF... (All Fs), then the the configuration is
7950 * for the requesting function.
7954 * This field specifies how many NQs will be reserved for the PF.
7955 * Remaining NQs that belong to the PF become available for VFs.
7956 * Once a PF has created VFs, it cannot change how many NQs are
7957 * reserved for itself (since the NQs must be contiguous in HW).
7962 * When this bit is '1', the function is disabled with
7963 * source MAC address check.
7964 * This is an anti-spoofing check. If this flag is set,
7965 * then the function shall be configured to disallow
7966 * transmission of frames with the source MAC address that
7967 * is configured for this function.
7969 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
7972 * When this bit is '1', the function is enabled with
7973 * source MAC address check.
7974 * This is an anti-spoofing check. If this flag is set,
7975 * then the function shall be configured to allow
7976 * transmission of frames with the source MAC address that
7977 * is configured for this function.
7979 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
7982 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
7984 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
7986 * Standard TX Ring mode is used for the allocation of TX ring
7987 * and underlying scheduling resources that allow bandwidth
7988 * reservation and limit settings on the queried function.
7989 * If set to 1, then standard TX ring mode is requested to be
7990 * enabled on the function being configured.
7992 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
7995 * Standard TX Ring mode is used for the allocation of TX ring
7996 * and underlying scheduling resources that allow bandwidth
7997 * reservation and limit settings on the queried function.
7998 * If set to 1, then the standard TX ring mode is requested to
7999 * be disabled on the function being configured. In this extended
8000 * TX ring resource mode, the minimum and maximum bandwidth settings
8001 * are not supported to allow the allocation of TX rings to
8002 * span multiple scheduler nodes.
8004 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
8007 * If this bit is set, virtual mac address configured
8008 * in this command will be persistent over warm boot.
8010 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
8013 * This bit only applies to the VF. If this bit is set, the statistic
8014 * context counters will not be cleared when the statistic context is freed
8015 * or a function reset is called on VF. This bit will be cleared when the PF
8016 * is unloaded or a function reset is called on the PF.
8018 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
8021 * This bit requests that the firmware test to see if all the assets
8022 * requested in this command (i.e. number of TX rings) are available.
8023 * The firmware will return an error if the requested assets are
8024 * not available. The firwmare will NOT reserve the assets if they
8027 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8030 * This bit requests that the firmware test to see if all the assets
8031 * requested in this command (i.e. number of RX rings) are available.
8032 * The firmware will return an error if the requested assets are
8033 * not available. The firwmare will NOT reserve the assets if they
8036 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8039 * This bit requests that the firmware test to see if all the assets
8040 * requested in this command (i.e. number of CMPL rings) are available.
8041 * The firmware will return an error if the requested assets are
8042 * not available. The firwmare will NOT reserve the assets if they
8045 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8048 * This bit requests that the firmware test to see if all the assets
8049 * requested in this command (i.e. number of RSS ctx) are available.
8050 * The firmware will return an error if the requested assets are
8051 * not available. The firwmare will NOT reserve the assets if they
8054 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8057 * This bit requests that the firmware test to see if all the assets
8058 * requested in this command (i.e. number of ring groups) are available.
8059 * The firmware will return an error if the requested assets are
8060 * not available. The firwmare will NOT reserve the assets if they
8063 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8066 * This bit requests that the firmware test to see if all the assets
8067 * requested in this command (i.e. number of stat ctx) are available.
8068 * The firmware will return an error if the requested assets are
8069 * not available. The firwmare will NOT reserve the assets if they
8072 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8075 * This bit requests that the firmware test to see if all the assets
8076 * requested in this command (i.e. number of VNICs) are available.
8077 * The firmware will return an error if the requested assets are
8078 * not available. The firwmare will NOT reserve the assets if they
8081 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8084 * This bit requests that the firmware test to see if all the assets
8085 * requested in this command (i.e. number of L2 ctx) are available.
8086 * The firmware will return an error if the requested assets are
8087 * not available. The firwmare will NOT reserve the assets if they
8090 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8093 * This configuration change can be initiated by a PF driver. This
8094 * configuration request shall be targeted to a VF. From local host
8095 * resident HWRM clients, only the parent PF driver shall be allowed
8096 * to initiate this change on one of its children VFs. If this bit is
8097 * set to 1, then the VF that is being configured is requested to be
8100 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
8103 * When this bit it set, even if PF reserved pool size is zero,
8104 * FW will allow driver to create TX rings in ring alloc,
8105 * by reserving TX ring, S3 node dynamically.
8107 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
8110 * This bit requests that the firmware test to see if all the assets
8111 * requested in this command (i.e. number of NQ rings) are available.
8112 * The firmware will return an error if the requested assets are
8113 * not available. The firwmare will NOT reserve the assets if they
8116 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
8119 * This configuration change can be initiated by a PF driver. This
8120 * configuration request shall be targeted to a VF. From local host
8121 * resident HWRM clients, only the parent PF driver shall be allowed
8122 * to initiate this change on one of its children VFs. If this bit is
8123 * set to 1, then the VF that is being configured is requested to be
8126 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
8129 * This bit is used by preboot drivers on a PF that require access
8130 * to the legacy L2 ring model and legacy 32b doorbells. This
8131 * feature is not allowed on VFs and is only relevant for devices
8132 * that require a context backing store.
8134 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
8138 * This bit must be '1' for the mtu field to be
8141 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
8144 * This bit must be '1' for the mru field to be
8147 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
8150 * This bit must be '1' for the num_rsscos_ctxs field to be
8153 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8156 * This bit must be '1' for the num_cmpl_rings field to be
8159 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8162 * This bit must be '1' for the num_tx_rings field to be
8165 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8168 * This bit must be '1' for the num_rx_rings field to be
8171 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8174 * This bit must be '1' for the num_l2_ctxs field to be
8177 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8180 * This bit must be '1' for the num_vnics field to be
8183 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
8186 * This bit must be '1' for the num_stat_ctxs field to be
8189 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8192 * This bit must be '1' for the dflt_mac_addr field to be
8195 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8198 * This bit must be '1' for the dflt_vlan field to be
8201 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
8204 * This bit must be '1' for the dflt_ip_addr field to be
8207 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
8210 * This bit must be '1' for the min_bw field to be
8213 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
8216 * This bit must be '1' for the max_bw field to be
8219 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
8222 * This bit must be '1' for the async_event_cr field to be
8225 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8228 * This bit must be '1' for the vlan_antispoof_mode field to be
8231 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
8234 * This bit must be '1' for the allowed_vlan_pris field to be
8237 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
8240 * This bit must be '1' for the evb_mode field to be
8243 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
8246 * This bit must be '1' for the num_mcast_filters field to be
8249 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
8252 * This bit must be '1' for the num_hw_ring_grps field to be
8255 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8258 * This bit must be '1' for the cache_linesize field to be
8261 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
8264 * This bit must be '1' for the num_msix field to be
8267 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
8270 * This bit must be '1' for the link admin state field to be
8273 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
8276 * The maximum transmission unit of the function.
8277 * The HWRM should make sure that the mtu of
8278 * the function does not exceed the mtu of the physical
8279 * port that this function is associated with.
8281 * In addition to configuring mtu per function, it is
8282 * possible to configure mtu per transmit ring.
8283 * By default, the mtu of each transmit ring associated
8284 * with a function is equal to the mtu of the function.
8285 * The HWRM should make sure that the mtu of each transmit
8286 * ring that is assigned to a function has a valid mtu.
8290 * The maximum receive unit of the function.
8291 * The HWRM should make sure that the mru of
8292 * the function does not exceed the mru of the physical
8293 * port that this function is associated with.
8295 * In addition to configuring mru per function, it is
8296 * possible to configure mru per vnic.
8297 * By default, the mru of each vnic associated
8298 * with a function is equal to the mru of the function.
8299 * The HWRM should make sure that the mru of each vnic
8300 * that is assigned to a function has a valid mru.
8304 * The number of RSS/COS contexts requested for the
8307 uint16_t num_rsscos_ctxs;
8309 * The number of completion rings requested for the
8310 * function. This does not include the rings allocated
8311 * to any children functions if any.
8313 uint16_t num_cmpl_rings;
8315 * The number of transmit rings requested for the function.
8316 * This does not include the rings allocated to any
8317 * children functions if any.
8319 uint16_t num_tx_rings;
8321 * The number of receive rings requested for the function.
8322 * This does not include the rings allocated
8323 * to any children functions if any.
8325 uint16_t num_rx_rings;
8326 /* The requested number of L2 contexts for the function. */
8327 uint16_t num_l2_ctxs;
8328 /* The requested number of vnics for the function. */
8330 /* The requested number of statistic contexts for the function. */
8331 uint16_t num_stat_ctxs;
8333 * The number of HW ring groups that should
8334 * be reserved for this function.
8336 uint16_t num_hw_ring_grps;
8337 /* The default MAC address for the function being configured. */
8338 uint8_t dflt_mac_addr[6];
8340 * The default VLAN for the function being configured.
8341 * This field's format is same as 802.1Q Tag's
8342 * Tag Control Information (TCI) format that includes both
8343 * Priority Code Point (PCP) and VLAN Identifier (VID).
8347 * The default IP address for the function being configured.
8348 * This address is only used in enabling source property check.
8350 uint32_t dflt_ip_addr[4];
8352 * Minimum BW allocated for this function.
8353 * The HWRM will translate this value into byte counter and
8354 * time interval used for the scheduler inside the device.
8357 /* The bandwidth value. */
8358 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
8360 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
8361 /* The granularity of the value (bits or bytes). */
8362 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
8363 UINT32_C(0x10000000)
8364 /* Value is in bits. */
8365 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
8366 (UINT32_C(0x0) << 28)
8367 /* Value is in bytes. */
8368 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
8369 (UINT32_C(0x1) << 28)
8370 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
8371 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
8372 /* bw_value_unit is 3 b */
8373 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
8374 UINT32_C(0xe0000000)
8375 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
8376 /* Value is in Mb or MB (base 10). */
8377 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
8378 (UINT32_C(0x0) << 29)
8379 /* Value is in Kb or KB (base 10). */
8380 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
8381 (UINT32_C(0x2) << 29)
8382 /* Value is in bits or bytes. */
8383 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
8384 (UINT32_C(0x4) << 29)
8385 /* Value is in Gb or GB (base 10). */
8386 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
8387 (UINT32_C(0x6) << 29)
8388 /* Value is in 1/100th of a percentage of total bandwidth. */
8389 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
8390 (UINT32_C(0x1) << 29)
8392 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
8393 (UINT32_C(0x7) << 29)
8394 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
8395 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
8397 * Maximum BW allocated for this function.
8398 * The HWRM will translate this value into byte counter and
8399 * time interval used for the scheduler inside the device.
8402 /* The bandwidth value. */
8403 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
8405 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
8406 /* The granularity of the value (bits or bytes). */
8407 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
8408 UINT32_C(0x10000000)
8409 /* Value is in bits. */
8410 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
8411 (UINT32_C(0x0) << 28)
8412 /* Value is in bytes. */
8413 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
8414 (UINT32_C(0x1) << 28)
8415 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
8416 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
8417 /* bw_value_unit is 3 b */
8418 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
8419 UINT32_C(0xe0000000)
8420 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
8421 /* Value is in Mb or MB (base 10). */
8422 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
8423 (UINT32_C(0x0) << 29)
8424 /* Value is in Kb or KB (base 10). */
8425 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
8426 (UINT32_C(0x2) << 29)
8427 /* Value is in bits or bytes. */
8428 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
8429 (UINT32_C(0x4) << 29)
8430 /* Value is in Gb or GB (base 10). */
8431 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
8432 (UINT32_C(0x6) << 29)
8433 /* Value is in 1/100th of a percentage of total bandwidth. */
8434 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
8435 (UINT32_C(0x1) << 29)
8437 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
8438 (UINT32_C(0x7) << 29)
8439 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
8440 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
8442 * ID of the target completion ring for receiving asynchronous
8443 * event completions. If this field is not valid, then the
8444 * HWRM shall use the default completion ring of the function
8445 * that is being configured as the target completion ring for
8446 * providing any asynchronous event completions for that
8448 * If this field is valid, then the HWRM shall use the
8449 * completion ring identified by this ID as the target
8450 * completion ring for providing any asynchronous event
8451 * completions for the function that is being configured.
8453 uint16_t async_event_cr;
8454 /* VLAN Anti-spoofing mode. */
8455 uint8_t vlan_antispoof_mode;
8456 /* No VLAN anti-spoofing checks are enabled */
8457 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
8459 /* Validate VLAN against the configured VLAN(s) */
8460 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
8462 /* Insert VLAN if it does not exist, otherwise discard */
8463 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
8465 /* Insert VLAN if it does not exist, override VLAN if it exists */
8466 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
8468 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
8469 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
8471 * This bit field defines VLAN PRIs that are allowed on
8473 * If nth bit is set, then VLAN PRI n is allowed on this
8476 uint8_t allowed_vlan_pris;
8478 * The HWRM shall allow a PF driver to change EVB mode for the
8479 * partition it belongs to.
8480 * The HWRM shall not allow a VF driver to change the EVB mode.
8481 * The HWRM shall take into account the switching of EVB mode
8482 * from one to another and reconfigure hardware resources as
8484 * The switching from VEB to VEPA mode requires
8485 * the disabling of the loopback traffic. Additionally,
8486 * source knock outs are handled differently in VEB and VEPA
8490 /* No Edge Virtual Bridging (EVB) */
8491 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
8492 /* Virtual Ethernet Bridge (VEB) */
8493 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
8494 /* Virtual Ethernet Port Aggregator (VEPA) */
8495 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
8496 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
8497 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
8500 * This value indicates the PCIE device cache line size.
8501 * The cache line size allows the DMA writes to terminate and
8502 * start at the cache boundary.
8504 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
8506 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
8507 /* Cache Line Size 64 bytes */
8508 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
8510 /* Cache Line Size 128 bytes */
8511 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
8513 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
8514 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
8515 /* This value is the virtual link admin state setting. */
8516 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
8518 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
8519 /* Admin state is forced down. */
8520 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
8521 (UINT32_C(0x0) << 2)
8522 /* Admin state is forced up. */
8523 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
8524 (UINT32_C(0x1) << 2)
8525 /* Admin state is in auto mode - is to follow the physical link state. */
8526 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
8527 (UINT32_C(0x2) << 2)
8528 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
8529 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
8530 /* Reserved for future. */
8531 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
8533 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
8535 * The number of multicast filters that should
8536 * be reserved for this function on the RX side.
8538 uint16_t num_mcast_filters;
8539 } __attribute__((packed));
8541 /* hwrm_func_cfg_output (size:128b/16B) */
8542 struct hwrm_func_cfg_output {
8543 /* The specific error status for the command. */
8544 uint16_t error_code;
8545 /* The HWRM command request type. */
8547 /* The sequence ID from the original command. */
8549 /* The length of the response data in number of bytes. */
8551 uint8_t unused_0[7];
8553 * This field is used in Output records to indicate that the output
8554 * is completely written to RAM. This field should be read as '1'
8555 * to indicate that the output has been completely written.
8556 * When writing a command completion or response to an internal processor,
8557 * the order of writes has to be such that this field is written last.
8560 } __attribute__((packed));
8562 /********************
8563 * hwrm_func_qstats *
8564 ********************/
8567 /* hwrm_func_qstats_input (size:192b/24B) */
8568 struct hwrm_func_qstats_input {
8569 /* The HWRM command request type. */
8572 * The completion ring to send the completion event on. This should
8573 * be the NQ ID returned from the `nq_alloc` HWRM command.
8577 * The sequence ID is used by the driver for tracking multiple
8578 * commands. This ID is treated as opaque data by the firmware and
8579 * the value is returned in the `hwrm_resp_hdr` upon completion.
8583 * The target ID of the command:
8584 * * 0x0-0xFFF8 - The function ID
8585 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8586 * * 0xFFFD - Reserved for user-space HWRM interface
8591 * A physical address pointer pointing to a host buffer that the
8592 * command's response data will be written. This can be either a host
8593 * physical address (HPA) or a guest physical address (GPA) and must
8594 * point to a physically contiguous block of memory.
8598 * Function ID of the function that is being queried.
8599 * 0xFF... (All Fs) if the query is for the requesting
8603 uint8_t unused_0[6];
8604 } __attribute__((packed));
8606 /* hwrm_func_qstats_output (size:1408b/176B) */
8607 struct hwrm_func_qstats_output {
8608 /* The specific error status for the command. */
8609 uint16_t error_code;
8610 /* The HWRM command request type. */
8612 /* The sequence ID from the original command. */
8614 /* The length of the response data in number of bytes. */
8616 /* Number of transmitted unicast packets on the function. */
8617 uint64_t tx_ucast_pkts;
8618 /* Number of transmitted multicast packets on the function. */
8619 uint64_t tx_mcast_pkts;
8620 /* Number of transmitted broadcast packets on the function. */
8621 uint64_t tx_bcast_pkts;
8623 * Number of transmitted packets that were discarded due to
8624 * internal NIC resource problems. For transmit, this
8625 * can only happen if TMP is configured to allow dropping
8626 * in HOL blocking conditions, which is not a normal
8629 uint64_t tx_discard_pkts;
8631 * Number of dropped packets on transmit path on the function.
8632 * These are packets that have been marked for drop by
8633 * the TE CFA block or are packets that exceeded the
8634 * transmit MTU limit for the function.
8636 uint64_t tx_drop_pkts;
8637 /* Number of transmitted bytes for unicast traffic on the function. */
8638 uint64_t tx_ucast_bytes;
8639 /* Number of transmitted bytes for multicast traffic on the function. */
8640 uint64_t tx_mcast_bytes;
8641 /* Number of transmitted bytes for broadcast traffic on the function. */
8642 uint64_t tx_bcast_bytes;
8643 /* Number of received unicast packets on the function. */
8644 uint64_t rx_ucast_pkts;
8645 /* Number of received multicast packets on the function. */
8646 uint64_t rx_mcast_pkts;
8647 /* Number of received broadcast packets on the function. */
8648 uint64_t rx_bcast_pkts;
8650 * Number of received packets that were discarded on the function
8651 * due to resource limitations. This can happen for 3 reasons.
8652 * # The BD used for the packet has a bad format.
8653 * # There were no BDs available in the ring for the packet.
8654 * # There were no BDs available on-chip for the packet.
8656 uint64_t rx_discard_pkts;
8658 * Number of dropped packets on received path on the function.
8659 * These are packets that have been marked for drop by the
8662 uint64_t rx_drop_pkts;
8663 /* Number of received bytes for unicast traffic on the function. */
8664 uint64_t rx_ucast_bytes;
8665 /* Number of received bytes for multicast traffic on the function. */
8666 uint64_t rx_mcast_bytes;
8667 /* Number of received bytes for broadcast traffic on the function. */
8668 uint64_t rx_bcast_bytes;
8669 /* Number of aggregated unicast packets on the function. */
8670 uint64_t rx_agg_pkts;
8671 /* Number of aggregated unicast bytes on the function. */
8672 uint64_t rx_agg_bytes;
8673 /* Number of aggregation events on the function. */
8674 uint64_t rx_agg_events;
8675 /* Number of aborted aggregations on the function. */
8676 uint64_t rx_agg_aborts;
8677 uint8_t unused_0[7];
8679 * This field is used in Output records to indicate that the output
8680 * is completely written to RAM. This field should be read as '1'
8681 * to indicate that the output has been completely written.
8682 * When writing a command completion or response to an internal processor,
8683 * the order of writes has to be such that this field is written last.
8686 } __attribute__((packed));
8688 /***********************
8689 * hwrm_func_clr_stats *
8690 ***********************/
8693 /* hwrm_func_clr_stats_input (size:192b/24B) */
8694 struct hwrm_func_clr_stats_input {
8695 /* The HWRM command request type. */
8698 * The completion ring to send the completion event on. This should
8699 * be the NQ ID returned from the `nq_alloc` HWRM command.
8703 * The sequence ID is used by the driver for tracking multiple
8704 * commands. This ID is treated as opaque data by the firmware and
8705 * the value is returned in the `hwrm_resp_hdr` upon completion.
8709 * The target ID of the command:
8710 * * 0x0-0xFFF8 - The function ID
8711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8712 * * 0xFFFD - Reserved for user-space HWRM interface
8717 * A physical address pointer pointing to a host buffer that the
8718 * command's response data will be written. This can be either a host
8719 * physical address (HPA) or a guest physical address (GPA) and must
8720 * point to a physically contiguous block of memory.
8724 * Function ID of the function.
8725 * 0xFF... (All Fs) if the query is for the requesting
8729 uint8_t unused_0[6];
8730 } __attribute__((packed));
8732 /* hwrm_func_clr_stats_output (size:128b/16B) */
8733 struct hwrm_func_clr_stats_output {
8734 /* The specific error status for the command. */
8735 uint16_t error_code;
8736 /* The HWRM command request type. */
8738 /* The sequence ID from the original command. */
8740 /* The length of the response data in number of bytes. */
8742 uint8_t unused_0[7];
8744 * This field is used in Output records to indicate that the output
8745 * is completely written to RAM. This field should be read as '1'
8746 * to indicate that the output has been completely written.
8747 * When writing a command completion or response to an internal processor,
8748 * the order of writes has to be such that this field is written last.
8751 } __attribute__((packed));
8753 /**************************
8754 * hwrm_func_vf_resc_free *
8755 **************************/
8758 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
8759 struct hwrm_func_vf_resc_free_input {
8760 /* The HWRM command request type. */
8763 * The completion ring to send the completion event on. This should
8764 * be the NQ ID returned from the `nq_alloc` HWRM command.
8768 * The sequence ID is used by the driver for tracking multiple
8769 * commands. This ID is treated as opaque data by the firmware and
8770 * the value is returned in the `hwrm_resp_hdr` upon completion.
8774 * The target ID of the command:
8775 * * 0x0-0xFFF8 - The function ID
8776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8777 * * 0xFFFD - Reserved for user-space HWRM interface
8782 * A physical address pointer pointing to a host buffer that the
8783 * command's response data will be written. This can be either a host
8784 * physical address (HPA) or a guest physical address (GPA) and must
8785 * point to a physically contiguous block of memory.
8789 * This value is used to identify a Virtual Function (VF).
8790 * The scope of VF ID is local within a PF.
8793 uint8_t unused_0[6];
8794 } __attribute__((packed));
8796 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
8797 struct hwrm_func_vf_resc_free_output {
8798 /* The specific error status for the command. */
8799 uint16_t error_code;
8800 /* The HWRM command request type. */
8802 /* The sequence ID from the original command. */
8804 /* The length of the response data in number of bytes. */
8806 uint8_t unused_0[7];
8808 * This field is used in Output records to indicate that the output
8809 * is completely written to RAM. This field should be read as '1'
8810 * to indicate that the output has been completely written.
8811 * When writing a command completion or response to an internal processor,
8812 * the order of writes has to be such that this field is written last.
8815 } __attribute__((packed));
8817 /**********************
8818 * hwrm_func_drv_rgtr *
8819 **********************/
8822 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
8823 struct hwrm_func_drv_rgtr_input {
8824 /* The HWRM command request type. */
8827 * The completion ring to send the completion event on. This should
8828 * be the NQ ID returned from the `nq_alloc` HWRM command.
8832 * The sequence ID is used by the driver for tracking multiple
8833 * commands. This ID is treated as opaque data by the firmware and
8834 * the value is returned in the `hwrm_resp_hdr` upon completion.
8838 * The target ID of the command:
8839 * * 0x0-0xFFF8 - The function ID
8840 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8841 * * 0xFFFD - Reserved for user-space HWRM interface
8846 * A physical address pointer pointing to a host buffer that the
8847 * command's response data will be written. This can be either a host
8848 * physical address (HPA) or a guest physical address (GPA) and must
8849 * point to a physically contiguous block of memory.
8854 * When this bit is '1', the function driver is requesting
8855 * all requests from its children VF drivers to be
8856 * forwarded to itself.
8857 * This flag can only be set by the PF driver.
8858 * If a VF driver sets this flag, it should be ignored
8861 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
8864 * When this bit is '1', the function is requesting none of
8865 * the requests from its children VF drivers to be
8866 * forwarded to itself.
8867 * This flag can only be set by the PF driver.
8868 * If a VF driver sets this flag, it should be ignored
8871 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
8874 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
8875 * fields shall be ignored and ver_maj, ver_min, ver_upd
8876 * and ver_patch shall be used for the driver version information.
8877 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
8878 * fields shall be used for the driver version information and
8879 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
8881 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
8884 * When this bit is '1', the function is indicating support of
8885 * 64bit flow handle. The firmware that only supports 64bit flow
8886 * handle should check this bit before allowing processing of
8887 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
8888 * with 64bit flow handle support can only be compatible with drivers
8889 * that support 64bit flow handle. The legacy drivers that don't support
8890 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
8891 * running with new firmware that only supports 64bit flow handle. The new
8892 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
8893 * status to the legacy driver when encounters these commands.
8895 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
8898 * When this bit is '1', the function is indicating support of
8899 * Hot Reset. The driver interface will destroy the resources,
8900 * unregister the function and register again up on receiving
8901 * the RESET_NOTIFY Async notification from the core firmware.
8902 * The core firmware will this use flag and trigger the Hot Reset
8903 * process only if all the registered driver instances are capable
8906 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
8909 * When this bit is 1, the function is indicating the support of the
8910 * error recovery capability. Error recovery support will be used by
8911 * firmware only if all the driver instances support error recovery
8912 * process. By setting this bit, driver is indicating support for
8913 * corresponding async event completion message. These will be
8914 * delivered to the driver even if they did not register for it.
8915 * If supported, after receiving reset notify async event with fatal
8916 * flag set in event data1, then all the drivers have to tear down
8917 * their resources without sending any HWRM commands to FW.
8919 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
8922 * When this bit is 1, the function is indicating the support of the
8923 * Master capability. The Firmware will use this capability to select
8924 * the Master function. The master function will be used to initiate
8925 * designated functionality like error recovery etc. If none of the
8926 * registered PFs or trusted VFs indicate this support, then
8927 * firmware will select the 1st registered PF as Master capable
8930 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
8934 * This bit must be '1' for the os_type field to be
8937 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
8940 * This bit must be '1' for the ver field to be
8943 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
8946 * This bit must be '1' for the timestamp field to be
8949 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
8952 * This bit must be '1' for the vf_req_fwd field to be
8955 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
8958 * This bit must be '1' for the async_event_fwd field to be
8961 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
8963 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8966 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8967 /* Other OS not listed below. */
8968 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
8970 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8972 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8974 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8976 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
8978 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8979 /* VMware ESXi OS. */
8980 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
8981 /* Microsoft Windows 8 64-bit OS. */
8982 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8983 /* Microsoft Windows Server 2012 R2 OS. */
8984 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8986 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8987 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
8988 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
8989 /* This is the 8bit major version of the driver. */
8991 /* This is the 8bit minor version of the driver. */
8993 /* This is the 8bit update version of the driver. */
8995 uint8_t unused_0[3];
8997 * This is a 32-bit timestamp provided by the driver for
8999 * The timestamp is in multiples of 1ms.
9002 uint8_t unused_1[4];
9004 * This is a 256-bit bit mask provided by the PF driver for
9005 * letting the HWRM know what commands issued by the VF driver
9006 * to the HWRM should be forwarded to the PF driver.
9007 * Nth bit refers to the Nth req_type.
9009 * Setting Nth bit to 1 indicates that requests from the
9010 * VF driver with req_type equal to N shall be forwarded to
9011 * the parent PF driver.
9013 * This field is not valid for the VF driver.
9015 uint32_t vf_req_fwd[8];
9017 * This is a 256-bit bit mask provided by the function driver
9018 * (PF or VF driver) to indicate the list of asynchronous event
9019 * completions to be forwarded.
9021 * Nth bit refers to the Nth event_id.
9023 * Setting Nth bit to 1 by the function driver shall result in
9024 * the HWRM forwarding asynchronous event completion with
9025 * event_id equal to N.
9027 * If all bits are set to 0 (value of 0), then the HWRM shall
9028 * not forward any asynchronous event completion to this
9031 uint32_t async_event_fwd[8];
9032 /* This is the 16bit major version of the driver. */
9034 /* This is the 16bit minor version of the driver. */
9036 /* This is the 16bit update version of the driver. */
9038 /* This is the 16bit patch version of the driver. */
9040 } __attribute__((packed));
9042 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
9043 struct hwrm_func_drv_rgtr_output {
9044 /* The specific error status for the command. */
9045 uint16_t error_code;
9046 /* The HWRM command request type. */
9048 /* The sequence ID from the original command. */
9050 /* The length of the response data in number of bytes. */
9054 * When this bit is '1', it indicates that the
9055 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
9057 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
9059 uint8_t unused_0[3];
9061 * This field is used in Output records to indicate that the output
9062 * is completely written to RAM. This field should be read as '1'
9063 * to indicate that the output has been completely written.
9064 * When writing a command completion or response to an internal processor,
9065 * the order of writes has to be such that this field is written last.
9068 } __attribute__((packed));
9070 /************************
9071 * hwrm_func_drv_unrgtr *
9072 ************************/
9075 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
9076 struct hwrm_func_drv_unrgtr_input {
9077 /* The HWRM command request type. */
9080 * The completion ring to send the completion event on. This should
9081 * be the NQ ID returned from the `nq_alloc` HWRM command.
9085 * The sequence ID is used by the driver for tracking multiple
9086 * commands. This ID is treated as opaque data by the firmware and
9087 * the value is returned in the `hwrm_resp_hdr` upon completion.
9091 * The target ID of the command:
9092 * * 0x0-0xFFF8 - The function ID
9093 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9094 * * 0xFFFD - Reserved for user-space HWRM interface
9099 * A physical address pointer pointing to a host buffer that the
9100 * command's response data will be written. This can be either a host
9101 * physical address (HPA) or a guest physical address (GPA) and must
9102 * point to a physically contiguous block of memory.
9107 * When this bit is '1', the function driver is notifying
9108 * the HWRM to prepare for the shutdown.
9110 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
9112 uint8_t unused_0[4];
9113 } __attribute__((packed));
9115 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
9116 struct hwrm_func_drv_unrgtr_output {
9117 /* The specific error status for the command. */
9118 uint16_t error_code;
9119 /* The HWRM command request type. */
9121 /* The sequence ID from the original command. */
9123 /* The length of the response data in number of bytes. */
9125 uint8_t unused_0[7];
9127 * This field is used in Output records to indicate that the output
9128 * is completely written to RAM. This field should be read as '1'
9129 * to indicate that the output has been completely written.
9130 * When writing a command completion or response to an internal processor,
9131 * the order of writes has to be such that this field is written last.
9134 } __attribute__((packed));
9136 /**********************
9137 * hwrm_func_buf_rgtr *
9138 **********************/
9141 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
9142 struct hwrm_func_buf_rgtr_input {
9143 /* The HWRM command request type. */
9146 * The completion ring to send the completion event on. This should
9147 * be the NQ ID returned from the `nq_alloc` HWRM command.
9151 * The sequence ID is used by the driver for tracking multiple
9152 * commands. This ID is treated as opaque data by the firmware and
9153 * the value is returned in the `hwrm_resp_hdr` upon completion.
9157 * The target ID of the command:
9158 * * 0x0-0xFFF8 - The function ID
9159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9160 * * 0xFFFD - Reserved for user-space HWRM interface
9165 * A physical address pointer pointing to a host buffer that the
9166 * command's response data will be written. This can be either a host
9167 * physical address (HPA) or a guest physical address (GPA) and must
9168 * point to a physically contiguous block of memory.
9173 * This bit must be '1' for the vf_id field to be
9176 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9178 * This bit must be '1' for the err_buf_addr field to be
9181 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
9183 * This value is used to identify a Virtual Function (VF).
9184 * The scope of VF ID is local within a PF.
9188 * This field represents the number of pages used for request
9191 uint16_t req_buf_num_pages;
9193 * This field represents the page size used for request
9196 uint16_t req_buf_page_size;
9198 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
9200 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
9202 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
9204 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
9206 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
9208 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
9210 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
9211 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
9212 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
9213 /* The length of the request buffer per VF in bytes. */
9214 uint16_t req_buf_len;
9215 /* The length of the response buffer in bytes. */
9216 uint16_t resp_buf_len;
9217 uint8_t unused_0[2];
9218 /* This field represents the page address of page #0. */
9219 uint64_t req_buf_page_addr0;
9220 /* This field represents the page address of page #1. */
9221 uint64_t req_buf_page_addr1;
9222 /* This field represents the page address of page #2. */
9223 uint64_t req_buf_page_addr2;
9224 /* This field represents the page address of page #3. */
9225 uint64_t req_buf_page_addr3;
9226 /* This field represents the page address of page #4. */
9227 uint64_t req_buf_page_addr4;
9228 /* This field represents the page address of page #5. */
9229 uint64_t req_buf_page_addr5;
9230 /* This field represents the page address of page #6. */
9231 uint64_t req_buf_page_addr6;
9232 /* This field represents the page address of page #7. */
9233 uint64_t req_buf_page_addr7;
9234 /* This field represents the page address of page #8. */
9235 uint64_t req_buf_page_addr8;
9236 /* This field represents the page address of page #9. */
9237 uint64_t req_buf_page_addr9;
9239 * This field is used to receive the error reporting from
9240 * the chipset. Only applicable for PFs.
9242 uint64_t error_buf_addr;
9244 * This field is used to receive the response forwarded by the
9247 uint64_t resp_buf_addr;
9248 } __attribute__((packed));
9250 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
9251 struct hwrm_func_buf_rgtr_output {
9252 /* The specific error status for the command. */
9253 uint16_t error_code;
9254 /* The HWRM command request type. */
9256 /* The sequence ID from the original command. */
9258 /* The length of the response data in number of bytes. */
9260 uint8_t unused_0[7];
9262 * This field is used in Output records to indicate that the output
9263 * is completely written to RAM. This field should be read as '1'
9264 * to indicate that the output has been completely written.
9265 * When writing a command completion or response to an internal processor,
9266 * the order of writes has to be such that this field is written last.
9269 } __attribute__((packed));
9271 /************************
9272 * hwrm_func_buf_unrgtr *
9273 ************************/
9276 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
9277 struct hwrm_func_buf_unrgtr_input {
9278 /* The HWRM command request type. */
9281 * The completion ring to send the completion event on. This should
9282 * be the NQ ID returned from the `nq_alloc` HWRM command.
9286 * The sequence ID is used by the driver for tracking multiple
9287 * commands. This ID is treated as opaque data by the firmware and
9288 * the value is returned in the `hwrm_resp_hdr` upon completion.
9292 * The target ID of the command:
9293 * * 0x0-0xFFF8 - The function ID
9294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9295 * * 0xFFFD - Reserved for user-space HWRM interface
9300 * A physical address pointer pointing to a host buffer that the
9301 * command's response data will be written. This can be either a host
9302 * physical address (HPA) or a guest physical address (GPA) and must
9303 * point to a physically contiguous block of memory.
9308 * This bit must be '1' for the vf_id field to be
9311 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9313 * This value is used to identify a Virtual Function (VF).
9314 * The scope of VF ID is local within a PF.
9317 uint8_t unused_0[2];
9318 } __attribute__((packed));
9320 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
9321 struct hwrm_func_buf_unrgtr_output {
9322 /* The specific error status for the command. */
9323 uint16_t error_code;
9324 /* The HWRM command request type. */
9326 /* The sequence ID from the original command. */
9328 /* The length of the response data in number of bytes. */
9330 uint8_t unused_0[7];
9332 * This field is used in Output records to indicate that the output
9333 * is completely written to RAM. This field should be read as '1'
9334 * to indicate that the output has been completely written.
9335 * When writing a command completion or response to an internal processor,
9336 * the order of writes has to be such that this field is written last.
9339 } __attribute__((packed));
9341 /**********************
9342 * hwrm_func_drv_qver *
9343 **********************/
9346 /* hwrm_func_drv_qver_input (size:192b/24B) */
9347 struct hwrm_func_drv_qver_input {
9348 /* The HWRM command request type. */
9351 * The completion ring to send the completion event on. This should
9352 * be the NQ ID returned from the `nq_alloc` HWRM command.
9356 * The sequence ID is used by the driver for tracking multiple
9357 * commands. This ID is treated as opaque data by the firmware and
9358 * the value is returned in the `hwrm_resp_hdr` upon completion.
9362 * The target ID of the command:
9363 * * 0x0-0xFFF8 - The function ID
9364 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9365 * * 0xFFFD - Reserved for user-space HWRM interface
9370 * A physical address pointer pointing to a host buffer that the
9371 * command's response data will be written. This can be either a host
9372 * physical address (HPA) or a guest physical address (GPA) and must
9373 * point to a physically contiguous block of memory.
9376 /* Reserved for future use. */
9379 * Function ID of the function that is being queried.
9380 * 0xFF... (All Fs) if the query is for the requesting
9384 uint8_t unused_0[2];
9385 } __attribute__((packed));
9387 /* hwrm_func_drv_qver_output (size:256b/32B) */
9388 struct hwrm_func_drv_qver_output {
9389 /* The specific error status for the command. */
9390 uint16_t error_code;
9391 /* The HWRM command request type. */
9393 /* The sequence ID from the original command. */
9395 /* The length of the response data in number of bytes. */
9397 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9400 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9401 /* Other OS not listed below. */
9402 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
9404 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9406 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9408 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9410 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
9412 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9413 /* VMware ESXi OS. */
9414 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
9415 /* Microsoft Windows 8 64-bit OS. */
9416 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9417 /* Microsoft Windows Server 2012 R2 OS. */
9418 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9420 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9421 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
9422 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
9423 /* This is the 8bit major version of the driver. */
9425 /* This is the 8bit minor version of the driver. */
9427 /* This is the 8bit update version of the driver. */
9429 uint8_t unused_0[3];
9430 /* This is the 16bit major version of the driver. */
9432 /* This is the 16bit minor version of the driver. */
9434 /* This is the 16bit update version of the driver. */
9436 /* This is the 16bit patch version of the driver. */
9438 uint8_t unused_1[7];
9440 * This field is used in Output records to indicate that the output
9441 * is completely written to RAM. This field should be read as '1'
9442 * to indicate that the output has been completely written.
9443 * When writing a command completion or response to an internal processor,
9444 * the order of writes has to be such that this field is written last.
9447 } __attribute__((packed));
9449 /****************************
9450 * hwrm_func_resource_qcaps *
9451 ****************************/
9454 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
9455 struct hwrm_func_resource_qcaps_input {
9456 /* The HWRM command request type. */
9459 * The completion ring to send the completion event on. This should
9460 * be the NQ ID returned from the `nq_alloc` HWRM command.
9464 * The sequence ID is used by the driver for tracking multiple
9465 * commands. This ID is treated as opaque data by the firmware and
9466 * the value is returned in the `hwrm_resp_hdr` upon completion.
9470 * The target ID of the command:
9471 * * 0x0-0xFFF8 - The function ID
9472 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9473 * * 0xFFFD - Reserved for user-space HWRM interface
9478 * A physical address pointer pointing to a host buffer that the
9479 * command's response data will be written. This can be either a host
9480 * physical address (HPA) or a guest physical address (GPA) and must
9481 * point to a physically contiguous block of memory.
9485 * Function ID of the function that is being queried.
9486 * 0xFF... (All Fs) if the query is for the requesting
9490 uint8_t unused_0[6];
9491 } __attribute__((packed));
9493 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
9494 struct hwrm_func_resource_qcaps_output {
9495 /* The specific error status for the command. */
9496 uint16_t error_code;
9497 /* The HWRM command request type. */
9499 /* The sequence ID from the original command. */
9501 /* The length of the response data in number of bytes. */
9503 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
9505 /* Maximum guaranteed number of MSI-X vectors supported by function */
9507 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
9508 uint16_t vf_reservation_strategy;
9509 /* The PF driver should evenly divide its remaining resources among all VFs. */
9510 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
9512 /* The PF driver should only reserve minimal resources for each VF. */
9513 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
9516 * The PF driver should not reserve any resources for each VF until the
9517 * the VF interface is brought up.
9519 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
9521 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
9522 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
9523 /* Minimum guaranteed number of RSS/COS contexts */
9524 uint16_t min_rsscos_ctx;
9525 /* Maximum non-guaranteed number of RSS/COS contexts */
9526 uint16_t max_rsscos_ctx;
9527 /* Minimum guaranteed number of completion rings */
9528 uint16_t min_cmpl_rings;
9529 /* Maximum non-guaranteed number of completion rings */
9530 uint16_t max_cmpl_rings;
9531 /* Minimum guaranteed number of transmit rings */
9532 uint16_t min_tx_rings;
9533 /* Maximum non-guaranteed number of transmit rings */
9534 uint16_t max_tx_rings;
9535 /* Minimum guaranteed number of receive rings */
9536 uint16_t min_rx_rings;
9537 /* Maximum non-guaranteed number of receive rings */
9538 uint16_t max_rx_rings;
9539 /* Minimum guaranteed number of L2 contexts */
9540 uint16_t min_l2_ctxs;
9541 /* Maximum non-guaranteed number of L2 contexts */
9542 uint16_t max_l2_ctxs;
9543 /* Minimum guaranteed number of VNICs */
9545 /* Maximum non-guaranteed number of VNICs */
9547 /* Minimum guaranteed number of statistic contexts */
9548 uint16_t min_stat_ctx;
9549 /* Maximum non-guaranteed number of statistic contexts */
9550 uint16_t max_stat_ctx;
9551 /* Minimum guaranteed number of ring groups */
9552 uint16_t min_hw_ring_grps;
9553 /* Maximum non-guaranteed number of ring groups */
9554 uint16_t max_hw_ring_grps;
9556 * Maximum number of inputs into the transmit scheduler for this function.
9557 * The number of TX rings assigned to the function cannot exceed this value.
9559 uint16_t max_tx_scheduler_inputs;
9562 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
9563 * feature to reserve all minimum resources when minimum >= 1, otherwise
9566 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
9568 uint8_t unused_0[5];
9570 * This field is used in Output records to indicate that the output
9571 * is completely written to RAM. This field should be read as '1'
9572 * to indicate that the output has been completely written.
9573 * When writing a command completion or response to an internal processor,
9574 * the order of writes has to be such that this field is written last.
9577 } __attribute__((packed));
9579 /*********************************
9580 * hwrm_func_backing_store_qcaps *
9581 *********************************/
9584 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
9585 struct hwrm_func_backing_store_qcaps_input {
9586 /* The HWRM command request type. */
9589 * The completion ring to send the completion event on. This should
9590 * be the NQ ID returned from the `nq_alloc` HWRM command.
9594 * The sequence ID is used by the driver for tracking multiple
9595 * commands. This ID is treated as opaque data by the firmware and
9596 * the value is returned in the `hwrm_resp_hdr` upon completion.
9600 * The target ID of the command:
9601 * * 0x0-0xFFF8 - The function ID
9602 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9603 * * 0xFFFD - Reserved for user-space HWRM interface
9608 * A physical address pointer pointing to a host buffer that the
9609 * command's response data will be written. This can be either a host
9610 * physical address (HPA) or a guest physical address (GPA) and must
9611 * point to a physically contiguous block of memory.
9614 } __attribute__((packed));
9616 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
9617 struct hwrm_func_backing_store_qcaps_output {
9618 /* The specific error status for the command. */
9619 uint16_t error_code;
9620 /* The HWRM command request type. */
9622 /* The sequence ID from the original command. */
9624 /* The length of the response data in number of bytes. */
9626 /* Maximum number of QP context entries supported for this function. */
9627 uint32_t qp_max_entries;
9629 * Minimum number of QP context entries that are needed to be reserved
9630 * for QP1 for the PF and its VFs. PF drivers must allocate at least
9631 * this many QP context entries, even if RoCE will not be used.
9633 uint16_t qp_min_qp1_entries;
9634 /* Maximum number of QP context entries that can be used for L2. */
9635 uint16_t qp_max_l2_entries;
9636 /* Number of bytes that must be allocated for each context entry. */
9637 uint16_t qp_entry_size;
9638 /* Maximum number of SRQ context entries that can be used for L2. */
9639 uint16_t srq_max_l2_entries;
9640 /* Maximum number of SRQ context entries supported for this function. */
9641 uint32_t srq_max_entries;
9642 /* Number of bytes that must be allocated for each context entry. */
9643 uint16_t srq_entry_size;
9644 /* Maximum number of CQ context entries that can be used for L2. */
9645 uint16_t cq_max_l2_entries;
9646 /* Maximum number of CQ context entries supported for this function. */
9647 uint32_t cq_max_entries;
9648 /* Number of bytes that must be allocated for each context entry. */
9649 uint16_t cq_entry_size;
9650 /* Maximum number of VNIC context entries supported for this function. */
9651 uint16_t vnic_max_vnic_entries;
9652 /* Maximum number of Ring table context entries supported for this function. */
9653 uint16_t vnic_max_ring_table_entries;
9654 /* Number of bytes that must be allocated for each context entry. */
9655 uint16_t vnic_entry_size;
9656 /* Maximum number of statistic context entries supported for this function. */
9657 uint32_t stat_max_entries;
9658 /* Number of bytes that must be allocated for each context entry. */
9659 uint16_t stat_entry_size;
9660 /* Number of bytes that must be allocated for each context entry. */
9661 uint16_t tqm_entry_size;
9662 /* Minimum number of TQM context entries required per ring. */
9663 uint32_t tqm_min_entries_per_ring;
9665 * Maximum number of TQM context entries supported per ring. This is
9666 * actually a recommended TQM queue size based on worst case usage of
9669 * TQM fastpath rings should be sized large enough to accommodate the
9670 * maximum number of QPs (either L2 or RoCE, or both if shared)
9671 * that can be enqueued to the TQM ring.
9673 * TQM slowpath rings should be sized as follows:
9675 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9678 * num_vnics is the number of VNICs allocated in the VNIC backing store
9679 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9680 * num_roce_qps is the number of RoCE QPs in the QP backing store
9681 * tqm_min_size is tqm_min_entries_per_ring reported by
9682 * HWRM_FUNC_BACKING_STORE_QCAPS
9684 * Note that TQM ring sizes cannot be extended while the system is
9685 * operational. If a PF driver needs to extend a TQM ring, it needs
9686 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9687 * the backing store.
9689 uint32_t tqm_max_entries_per_ring;
9691 * Maximum number of MR plus AV context entries supported for this
9694 uint32_t mrav_max_entries;
9695 /* Number of bytes that must be allocated for each context entry. */
9696 uint16_t mrav_entry_size;
9697 /* Number of bytes that must be allocated for each context entry. */
9698 uint16_t tim_entry_size;
9699 /* Maximum number of Timer context entries supported for this function. */
9700 uint32_t tim_max_entries;
9702 * When this field is zero, the 32b `mrav_num_entries` field in the
9703 * `backing_store_cfg` and `backing_store_qcfg` commands represents
9704 * the total number of MR plus AV entries allowed in the MR/AV backing
9707 * When this field is non-zero, the 32b `mrav_num_entries` field in
9708 * the `backing_store_cfg` and `backing_store_qcfg` commands is
9709 * logically divided into two 16b fields. Bits `[31:16]` represents
9710 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
9711 * Both of these values are represented in a unit granularity
9712 * specified by this field. For example, if this field is 16 and
9713 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
9714 * is 8192 and the number of AV entries is 4096.
9716 uint16_t mrav_num_entries_units;
9718 * The number of entries specified for any TQM ring must be a
9719 * multiple of this value to prevent any resource allocation
9722 uint8_t tqm_entries_multiple;
9724 * This field is used in Output records to indicate that the output
9725 * is completely written to RAM. This field should be read as '1'
9726 * to indicate that the output has been completely written.
9727 * When writing a command completion or response to an internal processor,
9728 * the order of writes has to be such that this field is written last.
9731 } __attribute__((packed));
9733 /*******************************
9734 * hwrm_func_backing_store_cfg *
9735 *******************************/
9738 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
9739 struct hwrm_func_backing_store_cfg_input {
9740 /* The HWRM command request type. */
9743 * The completion ring to send the completion event on. This should
9744 * be the NQ ID returned from the `nq_alloc` HWRM command.
9748 * The sequence ID is used by the driver for tracking multiple
9749 * commands. This ID is treated as opaque data by the firmware and
9750 * the value is returned in the `hwrm_resp_hdr` upon completion.
9754 * The target ID of the command:
9755 * * 0x0-0xFFF8 - The function ID
9756 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9757 * * 0xFFFD - Reserved for user-space HWRM interface
9762 * A physical address pointer pointing to a host buffer that the
9763 * command's response data will be written. This can be either a host
9764 * physical address (HPA) or a guest physical address (GPA) and must
9765 * point to a physically contiguous block of memory.
9770 * When set, the firmware only uses on-chip resources and does not
9771 * expect any backing store to be provided by the host driver. This
9772 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9775 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
9778 * When set, the 32b `mrav_num_entries` field is logically divided
9779 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
9781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
9785 * This bit must be '1' for the qp fields to be
9788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
9791 * This bit must be '1' for the srq fields to be
9794 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
9797 * This bit must be '1' for the cq fields to be
9800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
9803 * This bit must be '1' for the vnic fields to be
9806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
9809 * This bit must be '1' for the stat fields to be
9812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
9815 * This bit must be '1' for the tqm_sp fields to be
9818 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
9821 * This bit must be '1' for the tqm_ring0 fields to be
9824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
9827 * This bit must be '1' for the tqm_ring1 fields to be
9830 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
9833 * This bit must be '1' for the tqm_ring2 fields to be
9836 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
9839 * This bit must be '1' for the tqm_ring3 fields to be
9842 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
9845 * This bit must be '1' for the tqm_ring4 fields to be
9848 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
9851 * This bit must be '1' for the tqm_ring5 fields to be
9854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
9857 * This bit must be '1' for the tqm_ring6 fields to be
9860 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
9863 * This bit must be '1' for the tqm_ring7 fields to be
9866 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
9869 * This bit must be '1' for the mrav fields to be
9872 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
9875 * This bit must be '1' for the tim fields to be
9878 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
9880 /* QPC page size and level. */
9881 uint8_t qpc_pg_size_qpc_lvl;
9882 /* QPC PBL indirect levels. */
9883 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
9885 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
9886 /* PBL pointer is physical start address. */
9887 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
9889 /* PBL pointer points to PTE table. */
9890 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
9892 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
9895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
9896 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
9897 /* QPC page size. */
9898 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
9900 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
9902 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
9903 (UINT32_C(0x0) << 4)
9905 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
9906 (UINT32_C(0x1) << 4)
9908 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
9909 (UINT32_C(0x2) << 4)
9911 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
9912 (UINT32_C(0x3) << 4)
9914 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
9915 (UINT32_C(0x4) << 4)
9917 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
9918 (UINT32_C(0x5) << 4)
9919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
9920 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
9921 /* SRQ page size and level. */
9922 uint8_t srq_pg_size_srq_lvl;
9923 /* SRQ PBL indirect levels. */
9924 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
9926 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
9927 /* PBL pointer is physical start address. */
9928 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
9930 /* PBL pointer points to PTE table. */
9931 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
9933 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
9936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
9937 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
9938 /* SRQ page size. */
9939 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
9941 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
9943 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
9944 (UINT32_C(0x0) << 4)
9946 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
9947 (UINT32_C(0x1) << 4)
9949 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
9950 (UINT32_C(0x2) << 4)
9952 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
9953 (UINT32_C(0x3) << 4)
9955 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
9956 (UINT32_C(0x4) << 4)
9958 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
9959 (UINT32_C(0x5) << 4)
9960 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
9961 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
9962 /* CQ page size and level. */
9963 uint8_t cq_pg_size_cq_lvl;
9964 /* CQ PBL indirect levels. */
9965 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
9967 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
9968 /* PBL pointer is physical start address. */
9969 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
9971 /* PBL pointer points to PTE table. */
9972 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
9974 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9975 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
9977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
9978 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
9980 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
9982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
9984 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
9985 (UINT32_C(0x0) << 4)
9987 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
9988 (UINT32_C(0x1) << 4)
9990 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
9991 (UINT32_C(0x2) << 4)
9993 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
9994 (UINT32_C(0x3) << 4)
9996 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
9997 (UINT32_C(0x4) << 4)
9999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
10000 (UINT32_C(0x5) << 4)
10001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
10002 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
10003 /* VNIC page size and level. */
10004 uint8_t vnic_pg_size_vnic_lvl;
10005 /* VNIC PBL indirect levels. */
10006 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
10008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
10009 /* PBL pointer is physical start address. */
10010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
10012 /* PBL pointer points to PTE table. */
10013 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
10015 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
10018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
10019 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
10020 /* VNIC page size. */
10021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
10023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
10025 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
10026 (UINT32_C(0x0) << 4)
10028 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
10029 (UINT32_C(0x1) << 4)
10031 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
10032 (UINT32_C(0x2) << 4)
10034 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
10035 (UINT32_C(0x3) << 4)
10037 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
10038 (UINT32_C(0x4) << 4)
10040 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
10041 (UINT32_C(0x5) << 4)
10042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
10043 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
10044 /* Stat page size and level. */
10045 uint8_t stat_pg_size_stat_lvl;
10046 /* Stat PBL indirect levels. */
10047 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
10049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
10050 /* PBL pointer is physical start address. */
10051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
10053 /* PBL pointer points to PTE table. */
10054 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
10056 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
10059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
10060 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
10061 /* Stat page size. */
10062 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
10064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
10066 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
10067 (UINT32_C(0x0) << 4)
10069 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
10070 (UINT32_C(0x1) << 4)
10072 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
10073 (UINT32_C(0x2) << 4)
10075 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
10076 (UINT32_C(0x3) << 4)
10078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
10079 (UINT32_C(0x4) << 4)
10081 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
10082 (UINT32_C(0x5) << 4)
10083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
10084 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
10085 /* TQM slow path page size and level. */
10086 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10087 /* TQM slow path PBL indirect levels. */
10088 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
10090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
10091 /* PBL pointer is physical start address. */
10092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
10094 /* PBL pointer points to PTE table. */
10095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
10097 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10098 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
10100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
10101 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
10102 /* TQM slow path page size. */
10103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
10105 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
10107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
10108 (UINT32_C(0x0) << 4)
10110 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
10111 (UINT32_C(0x1) << 4)
10113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
10114 (UINT32_C(0x2) << 4)
10116 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
10117 (UINT32_C(0x3) << 4)
10119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
10120 (UINT32_C(0x4) << 4)
10122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
10123 (UINT32_C(0x5) << 4)
10124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
10125 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
10126 /* TQM ring 0 page size and level. */
10127 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10128 /* TQM ring 0 PBL indirect levels. */
10129 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
10131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
10132 /* PBL pointer is physical start address. */
10133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
10135 /* PBL pointer points to PTE table. */
10136 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
10138 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10139 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
10141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
10142 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
10143 /* TQM ring 0 page size. */
10144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
10146 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
10148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
10149 (UINT32_C(0x0) << 4)
10151 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
10152 (UINT32_C(0x1) << 4)
10154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
10155 (UINT32_C(0x2) << 4)
10157 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
10158 (UINT32_C(0x3) << 4)
10160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
10161 (UINT32_C(0x4) << 4)
10163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
10164 (UINT32_C(0x5) << 4)
10165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
10166 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
10167 /* TQM ring 1 page size and level. */
10168 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10169 /* TQM ring 1 PBL indirect levels. */
10170 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
10172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
10173 /* PBL pointer is physical start address. */
10174 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
10176 /* PBL pointer points to PTE table. */
10177 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
10179 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10180 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
10182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
10183 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
10184 /* TQM ring 1 page size. */
10185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
10187 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
10189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
10190 (UINT32_C(0x0) << 4)
10192 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
10193 (UINT32_C(0x1) << 4)
10195 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
10196 (UINT32_C(0x2) << 4)
10198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
10199 (UINT32_C(0x3) << 4)
10201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
10202 (UINT32_C(0x4) << 4)
10204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
10205 (UINT32_C(0x5) << 4)
10206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
10207 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
10208 /* TQM ring 2 page size and level. */
10209 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10210 /* TQM ring 2 PBL indirect levels. */
10211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
10213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
10214 /* PBL pointer is physical start address. */
10215 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
10217 /* PBL pointer points to PTE table. */
10218 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
10220 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10221 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
10223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
10224 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
10225 /* TQM ring 2 page size. */
10226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
10228 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
10230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
10231 (UINT32_C(0x0) << 4)
10233 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
10234 (UINT32_C(0x1) << 4)
10236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
10237 (UINT32_C(0x2) << 4)
10239 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
10240 (UINT32_C(0x3) << 4)
10242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
10243 (UINT32_C(0x4) << 4)
10245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
10246 (UINT32_C(0x5) << 4)
10247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
10248 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
10249 /* TQM ring 3 page size and level. */
10250 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10251 /* TQM ring 3 PBL indirect levels. */
10252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
10254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
10255 /* PBL pointer is physical start address. */
10256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
10258 /* PBL pointer points to PTE table. */
10259 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
10261 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
10264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
10265 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
10266 /* TQM ring 3 page size. */
10267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
10269 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
10271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
10272 (UINT32_C(0x0) << 4)
10274 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
10275 (UINT32_C(0x1) << 4)
10277 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
10278 (UINT32_C(0x2) << 4)
10280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
10281 (UINT32_C(0x3) << 4)
10283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
10284 (UINT32_C(0x4) << 4)
10286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
10287 (UINT32_C(0x5) << 4)
10288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
10289 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
10290 /* TQM ring 4 page size and level. */
10291 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10292 /* TQM ring 4 PBL indirect levels. */
10293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
10295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
10296 /* PBL pointer is physical start address. */
10297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
10299 /* PBL pointer points to PTE table. */
10300 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
10302 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10303 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
10305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
10306 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
10307 /* TQM ring 4 page size. */
10308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
10310 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
10312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
10313 (UINT32_C(0x0) << 4)
10315 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
10316 (UINT32_C(0x1) << 4)
10318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
10319 (UINT32_C(0x2) << 4)
10321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
10322 (UINT32_C(0x3) << 4)
10324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
10325 (UINT32_C(0x4) << 4)
10327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
10328 (UINT32_C(0x5) << 4)
10329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
10330 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
10331 /* TQM ring 5 page size and level. */
10332 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10333 /* TQM ring 5 PBL indirect levels. */
10334 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
10336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
10337 /* PBL pointer is physical start address. */
10338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
10340 /* PBL pointer points to PTE table. */
10341 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
10343 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
10346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
10347 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
10348 /* TQM ring 5 page size. */
10349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
10351 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
10353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
10354 (UINT32_C(0x0) << 4)
10356 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
10357 (UINT32_C(0x1) << 4)
10359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
10360 (UINT32_C(0x2) << 4)
10362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
10363 (UINT32_C(0x3) << 4)
10365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
10366 (UINT32_C(0x4) << 4)
10368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
10369 (UINT32_C(0x5) << 4)
10370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
10371 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
10372 /* TQM ring 6 page size and level. */
10373 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10374 /* TQM ring 6 PBL indirect levels. */
10375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
10377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
10378 /* PBL pointer is physical start address. */
10379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
10381 /* PBL pointer points to PTE table. */
10382 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
10384 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10385 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
10387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
10388 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
10389 /* TQM ring 6 page size. */
10390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
10392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
10394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
10395 (UINT32_C(0x0) << 4)
10397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
10398 (UINT32_C(0x1) << 4)
10400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
10401 (UINT32_C(0x2) << 4)
10403 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
10404 (UINT32_C(0x3) << 4)
10406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
10407 (UINT32_C(0x4) << 4)
10409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
10410 (UINT32_C(0x5) << 4)
10411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
10412 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
10413 /* TQM ring 7 page size and level. */
10414 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10415 /* TQM ring 7 PBL indirect levels. */
10416 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
10418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
10419 /* PBL pointer is physical start address. */
10420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
10422 /* PBL pointer points to PTE table. */
10423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
10425 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
10428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
10429 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
10430 /* TQM ring 7 page size. */
10431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
10433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
10435 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
10436 (UINT32_C(0x0) << 4)
10438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
10439 (UINT32_C(0x1) << 4)
10441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
10442 (UINT32_C(0x2) << 4)
10444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
10445 (UINT32_C(0x3) << 4)
10447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
10448 (UINT32_C(0x4) << 4)
10450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
10451 (UINT32_C(0x5) << 4)
10452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
10453 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
10454 /* MR/AV page size and level. */
10455 uint8_t mrav_pg_size_mrav_lvl;
10456 /* MR/AV PBL indirect levels. */
10457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
10459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
10460 /* PBL pointer is physical start address. */
10461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
10463 /* PBL pointer points to PTE table. */
10464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
10466 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10467 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
10469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
10470 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
10471 /* MR/AV page size. */
10472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
10474 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
10476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
10477 (UINT32_C(0x0) << 4)
10479 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
10480 (UINT32_C(0x1) << 4)
10482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
10483 (UINT32_C(0x2) << 4)
10485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
10486 (UINT32_C(0x3) << 4)
10488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
10489 (UINT32_C(0x4) << 4)
10491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
10492 (UINT32_C(0x5) << 4)
10493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
10494 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
10495 /* Timer page size and level. */
10496 uint8_t tim_pg_size_tim_lvl;
10497 /* Timer PBL indirect levels. */
10498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
10500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
10501 /* PBL pointer is physical start address. */
10502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
10504 /* PBL pointer points to PTE table. */
10505 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
10507 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10508 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
10510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
10511 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
10512 /* Timer page size. */
10513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
10515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
10517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
10518 (UINT32_C(0x0) << 4)
10520 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
10521 (UINT32_C(0x1) << 4)
10523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
10524 (UINT32_C(0x2) << 4)
10526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
10527 (UINT32_C(0x3) << 4)
10529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
10530 (UINT32_C(0x4) << 4)
10532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
10533 (UINT32_C(0x5) << 4)
10534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
10535 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
10536 /* QP page directory. */
10537 uint64_t qpc_page_dir;
10538 /* SRQ page directory. */
10539 uint64_t srq_page_dir;
10540 /* CQ page directory. */
10541 uint64_t cq_page_dir;
10542 /* VNIC page directory. */
10543 uint64_t vnic_page_dir;
10544 /* Stat page directory. */
10545 uint64_t stat_page_dir;
10546 /* TQM slowpath page directory. */
10547 uint64_t tqm_sp_page_dir;
10548 /* TQM ring 0 page directory. */
10549 uint64_t tqm_ring0_page_dir;
10550 /* TQM ring 1 page directory. */
10551 uint64_t tqm_ring1_page_dir;
10552 /* TQM ring 2 page directory. */
10553 uint64_t tqm_ring2_page_dir;
10554 /* TQM ring 3 page directory. */
10555 uint64_t tqm_ring3_page_dir;
10556 /* TQM ring 4 page directory. */
10557 uint64_t tqm_ring4_page_dir;
10558 /* TQM ring 5 page directory. */
10559 uint64_t tqm_ring5_page_dir;
10560 /* TQM ring 6 page directory. */
10561 uint64_t tqm_ring6_page_dir;
10562 /* TQM ring 7 page directory. */
10563 uint64_t tqm_ring7_page_dir;
10564 /* MR/AV page directory. */
10565 uint64_t mrav_page_dir;
10566 /* Timer page directory. */
10567 uint64_t tim_page_dir;
10568 /* Number of QPs. */
10569 uint32_t qp_num_entries;
10570 /* Number of SRQs. */
10571 uint32_t srq_num_entries;
10572 /* Number of CQs. */
10573 uint32_t cq_num_entries;
10574 /* Number of Stats. */
10575 uint32_t stat_num_entries;
10577 * Number of TQM slowpath entries.
10579 * TQM slowpath rings should be sized as follows:
10581 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
10584 * num_vnics is the number of VNICs allocated in the VNIC backing store
10585 * num_l2_tx_rings is the number of L2 rings in the QP backing store
10586 * num_roce_qps is the number of RoCE QPs in the QP backing store
10587 * tqm_min_size is tqm_min_entries_per_ring reported by
10588 * HWRM_FUNC_BACKING_STORE_QCAPS
10590 * Note that TQM ring sizes cannot be extended while the system is
10591 * operational. If a PF driver needs to extend a TQM ring, it needs
10592 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10593 * the backing store.
10595 uint32_t tqm_sp_num_entries;
10597 * Number of TQM ring 0 entries.
10599 * TQM fastpath rings should be sized large enough to accommodate the
10600 * maximum number of QPs (either L2 or RoCE, or both if shared)
10601 * that can be enqueued to the TQM ring.
10603 * Note that TQM ring sizes cannot be extended while the system is
10604 * operational. If a PF driver needs to extend a TQM ring, it needs
10605 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10606 * the backing store.
10608 uint32_t tqm_ring0_num_entries;
10610 * Number of TQM ring 1 entries.
10612 * TQM fastpath rings should be sized large enough to accommodate the
10613 * maximum number of QPs (either L2 or RoCE, or both if shared)
10614 * that can be enqueued to the TQM ring.
10616 * Note that TQM ring sizes cannot be extended while the system is
10617 * operational. If a PF driver needs to extend a TQM ring, it needs
10618 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10619 * the backing store.
10621 uint32_t tqm_ring1_num_entries;
10623 * Number of TQM ring 2 entries.
10625 * TQM fastpath rings should be sized large enough to accommodate the
10626 * maximum number of QPs (either L2 or RoCE, or both if shared)
10627 * that can be enqueued to the TQM ring.
10629 * Note that TQM ring sizes cannot be extended while the system is
10630 * operational. If a PF driver needs to extend a TQM ring, it needs
10631 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10632 * the backing store.
10634 uint32_t tqm_ring2_num_entries;
10636 * Number of TQM ring 3 entries.
10638 * TQM fastpath rings should be sized large enough to accommodate the
10639 * maximum number of QPs (either L2 or RoCE, or both if shared)
10640 * that can be enqueued to the TQM ring.
10642 * Note that TQM ring sizes cannot be extended while the system is
10643 * operational. If a PF driver needs to extend a TQM ring, it needs
10644 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10645 * the backing store.
10647 uint32_t tqm_ring3_num_entries;
10649 * Number of TQM ring 4 entries.
10651 * TQM fastpath rings should be sized large enough to accommodate the
10652 * maximum number of QPs (either L2 or RoCE, or both if shared)
10653 * that can be enqueued to the TQM ring.
10655 * Note that TQM ring sizes cannot be extended while the system is
10656 * operational. If a PF driver needs to extend a TQM ring, it needs
10657 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10658 * the backing store.
10660 uint32_t tqm_ring4_num_entries;
10662 * Number of TQM ring 5 entries.
10664 * TQM fastpath rings should be sized large enough to accommodate the
10665 * maximum number of QPs (either L2 or RoCE, or both if shared)
10666 * that can be enqueued to the TQM ring.
10668 * Note that TQM ring sizes cannot be extended while the system is
10669 * operational. If a PF driver needs to extend a TQM ring, it needs
10670 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10671 * the backing store.
10673 uint32_t tqm_ring5_num_entries;
10675 * Number of TQM ring 6 entries.
10677 * TQM fastpath rings should be sized large enough to accommodate the
10678 * maximum number of QPs (either L2 or RoCE, or both if shared)
10679 * that can be enqueued to the TQM ring.
10681 * Note that TQM ring sizes cannot be extended while the system is
10682 * operational. If a PF driver needs to extend a TQM ring, it needs
10683 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10684 * the backing store.
10686 uint32_t tqm_ring6_num_entries;
10688 * Number of TQM ring 7 entries.
10690 * TQM fastpath rings should be sized large enough to accommodate the
10691 * maximum number of QPs (either L2 or RoCE, or both if shared)
10692 * that can be enqueued to the TQM ring.
10694 * Note that TQM ring sizes cannot be extended while the system is
10695 * operational. If a PF driver needs to extend a TQM ring, it needs
10696 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10697 * the backing store.
10699 uint32_t tqm_ring7_num_entries;
10701 * If the MR/AV split reservation flag is not set, then this field
10702 * represents the total number of MR plus AV entries. For versions
10703 * of firmware that support the split reservation, when it is not
10704 * specified half of the entries will be reserved for MRs and the
10705 * other half for AVs.
10707 * If the MR/AV split reservation flag is set, then this
10708 * field is logically divided into two 16b fields. Bits `[31:16]`
10709 * represents the `mr_num_entries` and bits `[15:0]` represents
10710 * `av_num_entries`. The granularity of these values is defined by
10711 * the `mrav_num_entries_unit` field returned by the
10712 * `backing_store_qcaps` command.
10714 uint32_t mrav_num_entries;
10715 /* Number of Timer entries. */
10716 uint32_t tim_num_entries;
10717 /* Number of entries to reserve for QP1 */
10718 uint16_t qp_num_qp1_entries;
10719 /* Number of entries to reserve for L2 */
10720 uint16_t qp_num_l2_entries;
10721 /* Number of bytes that have been allocated for each context entry. */
10722 uint16_t qp_entry_size;
10723 /* Number of entries to reserve for L2 */
10724 uint16_t srq_num_l2_entries;
10725 /* Number of bytes that have been allocated for each context entry. */
10726 uint16_t srq_entry_size;
10727 /* Number of entries to reserve for L2 */
10728 uint16_t cq_num_l2_entries;
10729 /* Number of bytes that have been allocated for each context entry. */
10730 uint16_t cq_entry_size;
10731 /* Number of entries to reserve for VNIC entries */
10732 uint16_t vnic_num_vnic_entries;
10733 /* Number of entries to reserve for Ring table entries */
10734 uint16_t vnic_num_ring_table_entries;
10735 /* Number of bytes that have been allocated for each context entry. */
10736 uint16_t vnic_entry_size;
10737 /* Number of bytes that have been allocated for each context entry. */
10738 uint16_t stat_entry_size;
10739 /* Number of bytes that have been allocated for each context entry. */
10740 uint16_t tqm_entry_size;
10741 /* Number of bytes that have been allocated for each context entry. */
10742 uint16_t mrav_entry_size;
10743 /* Number of bytes that have been allocated for each context entry. */
10744 uint16_t tim_entry_size;
10745 } __attribute__((packed));
10747 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
10748 struct hwrm_func_backing_store_cfg_output {
10749 /* The specific error status for the command. */
10750 uint16_t error_code;
10751 /* The HWRM command request type. */
10753 /* The sequence ID from the original command. */
10755 /* The length of the response data in number of bytes. */
10757 uint8_t unused_0[7];
10759 * This field is used in Output records to indicate that the output
10760 * is completely written to RAM. This field should be read as '1'
10761 * to indicate that the output has been completely written.
10762 * When writing a command completion or response to an internal processor,
10763 * the order of writes has to be such that this field is written last.
10766 } __attribute__((packed));
10768 /********************************
10769 * hwrm_func_backing_store_qcfg *
10770 ********************************/
10773 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
10774 struct hwrm_func_backing_store_qcfg_input {
10775 /* The HWRM command request type. */
10778 * The completion ring to send the completion event on. This should
10779 * be the NQ ID returned from the `nq_alloc` HWRM command.
10781 uint16_t cmpl_ring;
10783 * The sequence ID is used by the driver for tracking multiple
10784 * commands. This ID is treated as opaque data by the firmware and
10785 * the value is returned in the `hwrm_resp_hdr` upon completion.
10789 * The target ID of the command:
10790 * * 0x0-0xFFF8 - The function ID
10791 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10792 * * 0xFFFD - Reserved for user-space HWRM interface
10795 uint16_t target_id;
10797 * A physical address pointer pointing to a host buffer that the
10798 * command's response data will be written. This can be either a host
10799 * physical address (HPA) or a guest physical address (GPA) and must
10800 * point to a physically contiguous block of memory.
10802 uint64_t resp_addr;
10803 } __attribute__((packed));
10805 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
10806 struct hwrm_func_backing_store_qcfg_output {
10807 /* The specific error status for the command. */
10808 uint16_t error_code;
10809 /* The HWRM command request type. */
10811 /* The sequence ID from the original command. */
10813 /* The length of the response data in number of bytes. */
10817 * When set, the firmware only uses on-chip resources and does not
10818 * expect any backing store to be provided by the host driver. This
10819 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10822 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
10825 * When set, the 32b `mrav_num_entries` field is logically divided
10826 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
10828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
10830 uint8_t unused_0[4];
10832 * This bit must be '1' for the qp fields to be
10835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
10838 * This bit must be '1' for the srq fields to be
10841 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
10844 * This bit must be '1' for the cq fields to be
10847 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
10850 * This bit must be '1' for the vnic fields to be
10853 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
10856 * This bit must be '1' for the stat fields to be
10859 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
10862 * This bit must be '1' for the tqm_sp fields to be
10865 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
10868 * This bit must be '1' for the tqm_ring0 fields to be
10871 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
10874 * This bit must be '1' for the tqm_ring1 fields to be
10877 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
10880 * This bit must be '1' for the tqm_ring2 fields to be
10883 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
10886 * This bit must be '1' for the tqm_ring3 fields to be
10889 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
10892 * This bit must be '1' for the tqm_ring4 fields to be
10895 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
10898 * This bit must be '1' for the tqm_ring5 fields to be
10901 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
10904 * This bit must be '1' for the tqm_ring6 fields to be
10907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
10910 * This bit must be '1' for the tqm_ring7 fields to be
10913 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
10916 * This bit must be '1' for the mrav fields to be
10919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
10922 * This bit must be '1' for the tim fields to be
10925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
10927 /* QPC page size and level. */
10928 uint8_t qpc_pg_size_qpc_lvl;
10929 /* QPC PBL indirect levels. */
10930 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
10932 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
10933 /* PBL pointer is physical start address. */
10934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
10936 /* PBL pointer points to PTE table. */
10937 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
10939 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
10942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
10943 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
10944 /* QPC page size. */
10945 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
10947 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
10949 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
10950 (UINT32_C(0x0) << 4)
10952 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
10953 (UINT32_C(0x1) << 4)
10955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
10956 (UINT32_C(0x2) << 4)
10958 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
10959 (UINT32_C(0x3) << 4)
10961 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
10962 (UINT32_C(0x4) << 4)
10964 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
10965 (UINT32_C(0x5) << 4)
10966 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
10967 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
10968 /* SRQ page size and level. */
10969 uint8_t srq_pg_size_srq_lvl;
10970 /* SRQ PBL indirect levels. */
10971 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
10973 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
10974 /* PBL pointer is physical start address. */
10975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
10977 /* PBL pointer points to PTE table. */
10978 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
10980 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
10983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
10984 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
10985 /* SRQ page size. */
10986 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
10988 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
10990 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
10991 (UINT32_C(0x0) << 4)
10993 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
10994 (UINT32_C(0x1) << 4)
10996 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
10997 (UINT32_C(0x2) << 4)
10999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
11000 (UINT32_C(0x3) << 4)
11002 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
11003 (UINT32_C(0x4) << 4)
11005 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
11006 (UINT32_C(0x5) << 4)
11007 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
11008 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
11009 /* CQ page size and level. */
11010 uint8_t cq_pg_size_cq_lvl;
11011 /* CQ PBL indirect levels. */
11012 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
11014 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
11015 /* PBL pointer is physical start address. */
11016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
11018 /* PBL pointer points to PTE table. */
11019 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
11021 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
11024 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
11025 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
11026 /* CQ page size. */
11027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
11029 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
11031 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
11032 (UINT32_C(0x0) << 4)
11034 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
11035 (UINT32_C(0x1) << 4)
11037 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
11038 (UINT32_C(0x2) << 4)
11040 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
11041 (UINT32_C(0x3) << 4)
11043 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
11044 (UINT32_C(0x4) << 4)
11046 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
11047 (UINT32_C(0x5) << 4)
11048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
11049 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
11050 /* VNIC page size and level. */
11051 uint8_t vnic_pg_size_vnic_lvl;
11052 /* VNIC PBL indirect levels. */
11053 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
11055 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
11056 /* PBL pointer is physical start address. */
11057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
11059 /* PBL pointer points to PTE table. */
11060 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
11062 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
11065 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
11066 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
11067 /* VNIC page size. */
11068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
11070 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
11072 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
11073 (UINT32_C(0x0) << 4)
11075 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
11076 (UINT32_C(0x1) << 4)
11078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
11079 (UINT32_C(0x2) << 4)
11081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
11082 (UINT32_C(0x3) << 4)
11084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
11085 (UINT32_C(0x4) << 4)
11087 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
11088 (UINT32_C(0x5) << 4)
11089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
11090 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
11091 /* Stat page size and level. */
11092 uint8_t stat_pg_size_stat_lvl;
11093 /* Stat PBL indirect levels. */
11094 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
11096 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
11097 /* PBL pointer is physical start address. */
11098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
11100 /* PBL pointer points to PTE table. */
11101 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
11103 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11104 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
11106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
11107 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
11108 /* Stat page size. */
11109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
11111 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
11113 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
11114 (UINT32_C(0x0) << 4)
11116 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
11117 (UINT32_C(0x1) << 4)
11119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
11120 (UINT32_C(0x2) << 4)
11122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
11123 (UINT32_C(0x3) << 4)
11125 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
11126 (UINT32_C(0x4) << 4)
11128 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
11129 (UINT32_C(0x5) << 4)
11130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
11131 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
11132 /* TQM slow path page size and level. */
11133 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
11134 /* TQM slow path PBL indirect levels. */
11135 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
11137 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
11138 /* PBL pointer is physical start address. */
11139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
11141 /* PBL pointer points to PTE table. */
11142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
11144 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
11147 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
11148 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
11149 /* TQM slow path page size. */
11150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
11152 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
11154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
11155 (UINT32_C(0x0) << 4)
11157 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
11158 (UINT32_C(0x1) << 4)
11160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
11161 (UINT32_C(0x2) << 4)
11163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
11164 (UINT32_C(0x3) << 4)
11166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
11167 (UINT32_C(0x4) << 4)
11169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
11170 (UINT32_C(0x5) << 4)
11171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
11172 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
11173 /* TQM ring 0 page size and level. */
11174 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
11175 /* TQM ring 0 PBL indirect levels. */
11176 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
11178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
11179 /* PBL pointer is physical start address. */
11180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
11182 /* PBL pointer points to PTE table. */
11183 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
11185 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
11188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
11189 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
11190 /* TQM ring 0 page size. */
11191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
11193 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
11195 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
11196 (UINT32_C(0x0) << 4)
11198 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
11199 (UINT32_C(0x1) << 4)
11201 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
11202 (UINT32_C(0x2) << 4)
11204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
11205 (UINT32_C(0x3) << 4)
11207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
11208 (UINT32_C(0x4) << 4)
11210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
11211 (UINT32_C(0x5) << 4)
11212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
11213 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
11214 /* TQM ring 1 page size and level. */
11215 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
11216 /* TQM ring 1 PBL indirect levels. */
11217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
11219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
11220 /* PBL pointer is physical start address. */
11221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
11223 /* PBL pointer points to PTE table. */
11224 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
11226 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
11229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
11230 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
11231 /* TQM ring 1 page size. */
11232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
11234 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
11236 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
11237 (UINT32_C(0x0) << 4)
11239 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
11240 (UINT32_C(0x1) << 4)
11242 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
11243 (UINT32_C(0x2) << 4)
11245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
11246 (UINT32_C(0x3) << 4)
11248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
11249 (UINT32_C(0x4) << 4)
11251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
11252 (UINT32_C(0x5) << 4)
11253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
11254 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
11255 /* TQM ring 2 page size and level. */
11256 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
11257 /* TQM ring 2 PBL indirect levels. */
11258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
11260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
11261 /* PBL pointer is physical start address. */
11262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
11264 /* PBL pointer points to PTE table. */
11265 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
11267 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11268 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
11270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
11271 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
11272 /* TQM ring 2 page size. */
11273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
11275 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
11277 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
11278 (UINT32_C(0x0) << 4)
11280 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
11281 (UINT32_C(0x1) << 4)
11283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
11284 (UINT32_C(0x2) << 4)
11286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
11287 (UINT32_C(0x3) << 4)
11289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
11290 (UINT32_C(0x4) << 4)
11292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
11293 (UINT32_C(0x5) << 4)
11294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
11295 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
11296 /* TQM ring 3 page size and level. */
11297 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
11298 /* TQM ring 3 PBL indirect levels. */
11299 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
11301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
11302 /* PBL pointer is physical start address. */
11303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
11305 /* PBL pointer points to PTE table. */
11306 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
11308 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11309 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
11311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
11312 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
11313 /* TQM ring 3 page size. */
11314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
11316 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
11318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
11319 (UINT32_C(0x0) << 4)
11321 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
11322 (UINT32_C(0x1) << 4)
11324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
11325 (UINT32_C(0x2) << 4)
11327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
11328 (UINT32_C(0x3) << 4)
11330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
11331 (UINT32_C(0x4) << 4)
11333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
11334 (UINT32_C(0x5) << 4)
11335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
11336 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
11337 /* TQM ring 4 page size and level. */
11338 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
11339 /* TQM ring 4 PBL indirect levels. */
11340 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
11342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
11343 /* PBL pointer is physical start address. */
11344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
11346 /* PBL pointer points to PTE table. */
11347 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
11349 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
11352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
11353 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
11354 /* TQM ring 4 page size. */
11355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
11357 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
11359 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
11360 (UINT32_C(0x0) << 4)
11362 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
11363 (UINT32_C(0x1) << 4)
11365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
11366 (UINT32_C(0x2) << 4)
11368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
11369 (UINT32_C(0x3) << 4)
11371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
11372 (UINT32_C(0x4) << 4)
11374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
11375 (UINT32_C(0x5) << 4)
11376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
11377 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
11378 /* TQM ring 5 page size and level. */
11379 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
11380 /* TQM ring 5 PBL indirect levels. */
11381 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
11383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
11384 /* PBL pointer is physical start address. */
11385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
11387 /* PBL pointer points to PTE table. */
11388 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
11390 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11391 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
11393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
11394 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
11395 /* TQM ring 5 page size. */
11396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
11398 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
11400 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
11401 (UINT32_C(0x0) << 4)
11403 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
11404 (UINT32_C(0x1) << 4)
11406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
11407 (UINT32_C(0x2) << 4)
11409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
11410 (UINT32_C(0x3) << 4)
11412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
11413 (UINT32_C(0x4) << 4)
11415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
11416 (UINT32_C(0x5) << 4)
11417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
11418 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
11419 /* TQM ring 6 page size and level. */
11420 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
11421 /* TQM ring 6 PBL indirect levels. */
11422 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
11424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
11425 /* PBL pointer is physical start address. */
11426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
11428 /* PBL pointer points to PTE table. */
11429 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
11431 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11432 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
11434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
11435 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
11436 /* TQM ring 6 page size. */
11437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
11439 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
11441 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
11442 (UINT32_C(0x0) << 4)
11444 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
11445 (UINT32_C(0x1) << 4)
11447 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
11448 (UINT32_C(0x2) << 4)
11450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
11451 (UINT32_C(0x3) << 4)
11453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
11454 (UINT32_C(0x4) << 4)
11456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
11457 (UINT32_C(0x5) << 4)
11458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
11459 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
11460 /* TQM ring 7 page size and level. */
11461 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
11462 /* TQM ring 7 PBL indirect levels. */
11463 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
11465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
11466 /* PBL pointer is physical start address. */
11467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
11469 /* PBL pointer points to PTE table. */
11470 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
11472 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11473 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
11475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
11476 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
11477 /* TQM ring 7 page size. */
11478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
11480 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
11482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
11483 (UINT32_C(0x0) << 4)
11485 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
11486 (UINT32_C(0x1) << 4)
11488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
11489 (UINT32_C(0x2) << 4)
11491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
11492 (UINT32_C(0x3) << 4)
11494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
11495 (UINT32_C(0x4) << 4)
11497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
11498 (UINT32_C(0x5) << 4)
11499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
11500 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
11501 /* MR/AV page size and level. */
11502 uint8_t mrav_pg_size_mrav_lvl;
11503 /* MR/AV PBL indirect levels. */
11504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
11506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
11507 /* PBL pointer is physical start address. */
11508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
11510 /* PBL pointer points to PTE table. */
11511 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
11513 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
11516 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
11517 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
11518 /* MR/AV page size. */
11519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
11521 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
11523 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
11524 (UINT32_C(0x0) << 4)
11526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
11527 (UINT32_C(0x1) << 4)
11529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
11530 (UINT32_C(0x2) << 4)
11532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
11533 (UINT32_C(0x3) << 4)
11535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
11536 (UINT32_C(0x4) << 4)
11538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
11539 (UINT32_C(0x5) << 4)
11540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
11541 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
11542 /* Timer page size and level. */
11543 uint8_t tim_pg_size_tim_lvl;
11544 /* Timer PBL indirect levels. */
11545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
11547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
11548 /* PBL pointer is physical start address. */
11549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
11551 /* PBL pointer points to PTE table. */
11552 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
11554 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
11557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
11558 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
11559 /* Timer page size. */
11560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
11562 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
11564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
11565 (UINT32_C(0x0) << 4)
11567 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
11568 (UINT32_C(0x1) << 4)
11570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
11571 (UINT32_C(0x2) << 4)
11573 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
11574 (UINT32_C(0x3) << 4)
11576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
11577 (UINT32_C(0x4) << 4)
11579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
11580 (UINT32_C(0x5) << 4)
11581 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
11582 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
11583 /* QP page directory. */
11584 uint64_t qpc_page_dir;
11585 /* SRQ page directory. */
11586 uint64_t srq_page_dir;
11587 /* CQ page directory. */
11588 uint64_t cq_page_dir;
11589 /* VNIC page directory. */
11590 uint64_t vnic_page_dir;
11591 /* Stat page directory. */
11592 uint64_t stat_page_dir;
11593 /* TQM slowpath page directory. */
11594 uint64_t tqm_sp_page_dir;
11595 /* TQM ring 0 page directory. */
11596 uint64_t tqm_ring0_page_dir;
11597 /* TQM ring 1 page directory. */
11598 uint64_t tqm_ring1_page_dir;
11599 /* TQM ring 2 page directory. */
11600 uint64_t tqm_ring2_page_dir;
11601 /* TQM ring 3 page directory. */
11602 uint64_t tqm_ring3_page_dir;
11603 /* TQM ring 4 page directory. */
11604 uint64_t tqm_ring4_page_dir;
11605 /* TQM ring 5 page directory. */
11606 uint64_t tqm_ring5_page_dir;
11607 /* TQM ring 6 page directory. */
11608 uint64_t tqm_ring6_page_dir;
11609 /* TQM ring 7 page directory. */
11610 uint64_t tqm_ring7_page_dir;
11611 /* MR/AV page directory. */
11612 uint64_t mrav_page_dir;
11613 /* Timer page directory. */
11614 uint64_t tim_page_dir;
11615 /* Number of entries to reserve for QP1 */
11616 uint16_t qp_num_qp1_entries;
11617 /* Number of entries to reserve for L2 */
11618 uint16_t qp_num_l2_entries;
11619 /* Number of QPs. */
11620 uint32_t qp_num_entries;
11621 /* Number of SRQs. */
11622 uint32_t srq_num_entries;
11623 /* Number of entries to reserve for L2 */
11624 uint16_t srq_num_l2_entries;
11625 /* Number of entries to reserve for L2 */
11626 uint16_t cq_num_l2_entries;
11627 /* Number of CQs. */
11628 uint32_t cq_num_entries;
11629 /* Number of entries to reserve for VNIC entries */
11630 uint16_t vnic_num_vnic_entries;
11631 /* Number of entries to reserve for Ring table entries */
11632 uint16_t vnic_num_ring_table_entries;
11633 /* Number of Stats. */
11634 uint32_t stat_num_entries;
11635 /* Number of TQM slowpath entries. */
11636 uint32_t tqm_sp_num_entries;
11637 /* Number of TQM ring 0 entries. */
11638 uint32_t tqm_ring0_num_entries;
11639 /* Number of TQM ring 1 entries. */
11640 uint32_t tqm_ring1_num_entries;
11641 /* Number of TQM ring 2 entries. */
11642 uint32_t tqm_ring2_num_entries;
11643 /* Number of TQM ring 3 entries. */
11644 uint32_t tqm_ring3_num_entries;
11645 /* Number of TQM ring 4 entries. */
11646 uint32_t tqm_ring4_num_entries;
11647 /* Number of TQM ring 5 entries. */
11648 uint32_t tqm_ring5_num_entries;
11649 /* Number of TQM ring 6 entries. */
11650 uint32_t tqm_ring6_num_entries;
11651 /* Number of TQM ring 7 entries. */
11652 uint32_t tqm_ring7_num_entries;
11654 * If the MR/AV split reservation flag is not set, then this field
11655 * represents the total number of MR plus AV entries. For versions
11656 * of firmware that support the split reservation, when it is not
11657 * specified half of the entries will be reserved for MRs and the
11658 * other half for AVs.
11660 * If the MR/AV split reservation flag is set, then this
11661 * field is logically divided into two 16b fields. Bits `[31:16]`
11662 * represents the `mr_num_entries` and bits `[15:0]` represents
11663 * `av_num_entries`. The granularity of these values is defined by
11664 * the `mrav_num_entries_unit` field returned by the
11665 * `backing_store_qcaps` command.
11667 uint32_t mrav_num_entries;
11668 /* Number of Timer entries. */
11669 uint32_t tim_num_entries;
11670 uint8_t unused_1[7];
11672 * This field is used in Output records to indicate that the output
11673 * is completely written to RAM. This field should be read as 1
11674 * to indicate that the output has been completely written.
11675 * When writing a command completion or response to an internal
11676 * processor, the order of writes has to be such that this field
11680 } __attribute__((packed));
11682 /****************************
11683 * hwrm_error_recovery_qcfg *
11684 ****************************/
11687 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
11688 struct hwrm_error_recovery_qcfg_input {
11689 /* The HWRM command request type. */
11692 * The completion ring to send the completion event on. This should
11693 * be the NQ ID returned from the `nq_alloc` HWRM command.
11695 uint16_t cmpl_ring;
11697 * The sequence ID is used by the driver for tracking multiple
11698 * commands. This ID is treated as opaque data by the firmware and
11699 * the value is returned in the `hwrm_resp_hdr` upon completion.
11703 * The target ID of the command:
11704 * * 0x0-0xFFF8 - The function ID
11705 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11706 * * 0xFFFD - Reserved for user-space HWRM interface
11709 uint16_t target_id;
11711 * A physical address pointer pointing to a host buffer that the
11712 * command's response data will be written. This can be either a host
11713 * physical address (HPA) or a guest physical address (GPA) and must
11714 * point to a physically contiguous block of memory.
11716 uint64_t resp_addr;
11717 uint8_t unused_0[8];
11718 } __attribute__((packed));
11720 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
11721 struct hwrm_error_recovery_qcfg_output {
11722 /* The specific error status for the command. */
11723 uint16_t error_code;
11724 /* The HWRM command request type. */
11726 /* The sequence ID from the original command. */
11728 /* The length of the response data in number of bytes. */
11732 * When this flag is set to 1, error recovery will be initiated
11733 * through master function driver.
11735 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
11737 * When this flag is set to 1, error recovery will be performed
11738 * through Co processor.
11740 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
11742 * Driver Polling frequency. This value is in units of 100msec.
11743 * Typical value would be 10 to indicate 1sec.
11744 * Drivers can poll FW health status, Heartbeat, reset_counter with
11747 uint32_t driver_polling_freq;
11749 * This value is in units of 100msec.
11750 * Typical value would be 30 to indicate 3sec.
11751 * Master function wait period from detecting a fatal error to
11752 * initiating reset. In this time period Master PF expects every
11753 * active driver will detect fatal error.
11755 uint32_t master_func_wait_period;
11757 * This value is in units of 100msec.
11758 * Typical value would be 50 to indicate 5sec.
11759 * Normal function wait period from fatal error detection to
11760 * polling FW health status. In this time period, drivers should not
11761 * do any PCIe MMIO transaction and should not send any HWRM commands.
11763 uint32_t normal_func_wait_period;
11765 * This value is in units of 100msec.
11766 * Typical value would be 20 to indicate 2sec.
11767 * This field indicates that, master function wait period after chip
11768 * reset. After this time, master function should reinitialize with
11771 uint32_t master_func_wait_period_after_reset;
11773 * This value is in units of 100msec.
11774 * Typical value would be 60 to indicate 6sec.
11775 * This field is applicable to both master and normal functions.
11776 * Even after chip reset, if FW status not changed to ready,
11777 * then all the functions can poll for this much time and bailout.
11779 uint32_t max_bailout_time_after_reset;
11781 * FW health status register.
11782 * Lower 2 bits indicates address space location and upper 30 bits
11783 * indicates upper 30bits of the register address.
11784 * A value of 0xFFFF-FFFF indicates this register does not exist.
11786 uint32_t fw_health_status_reg;
11787 /* Lower 2 bits indicates address space location. */
11788 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
11790 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
11793 * If value is 0, this register is located in PCIe config space.
11794 * Drivers have to map appropriate window to access this
11797 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
11800 * If value is 1, this register is located in GRC address space.
11801 * Drivers have to map appropriate window to access this
11804 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
11807 * If value is 2, this register is located in first BAR address
11808 * space. Drivers have to map appropriate window to access this
11811 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
11814 * If value is 3, this register is located in second BAR address
11815 * space. Drivers have to map appropriate window to access this
11816 * Drivers have to map appropriate window to access this
11819 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
11821 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
11822 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
11823 /* Upper 30bits of the register address. */
11824 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
11825 UINT32_C(0xfffffffc)
11826 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
11829 * FW HeartBeat register.
11830 * Lower 2 bits indicates address space location and upper 30 bits
11831 * indicates actual address.
11832 * A value of 0xFFFF-FFFF indicates this register does not exist.
11834 uint32_t fw_heartbeat_reg;
11835 /* Lower 2 bits indicates address space location. */
11836 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
11838 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
11841 * If value is 0, this register is located in PCIe config space.
11842 * Drivers have to map appropriate window to access this
11845 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
11848 * If value is 1, this register is located in GRC address space.
11849 * Drivers have to map appropriate window to access this
11852 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
11855 * If value is 2, this register is located in first BAR address
11856 * space. Drivers have to map appropriate window to access this
11859 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
11862 * If value is 3, this register is located in second BAR address
11863 * space. Drivers have to map appropriate window to access this
11866 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
11868 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
11869 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
11870 /* Upper 30bits of the register address. */
11871 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
11872 UINT32_C(0xfffffffc)
11873 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
11876 * FW reset counter.
11877 * Lower 2 bits indicates address space location and upper 30 bits
11878 * indicates actual address.
11879 * A value of 0xFFFF-FFFF indicates this register does not exist.
11881 uint32_t fw_reset_cnt_reg;
11882 /* Lower 2 bits indicates address space location. */
11883 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
11885 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
11888 * If value is 0, this register is located in PCIe config space.
11889 * Drivers have to map appropriate window to access this
11892 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
11895 * If value is 1, this register is located in GRC address space.
11896 * Drivers have to map appropriate window to access this
11899 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
11902 * If value is 2, this register is located in first BAR address
11903 * space. Drivers have to map appropriate window to access this
11906 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
11909 * If value is 3, this register is located in second BAR address
11910 * space. Drivers have to map appropriate window to access this
11913 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
11915 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
11916 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
11917 /* Upper 30bits of the register address. */
11918 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
11919 UINT32_C(0xfffffffc)
11920 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
11923 * Reset Inprogress Register address for PFs.
11924 * Lower 2 bits indicates address space location and upper 30 bits
11925 * indicates actual address.
11926 * A value of 0xFFFF-FFFF indicates this register does not exist.
11928 uint32_t reset_inprogress_reg;
11929 /* Lower 2 bits indicates address space location. */
11930 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
11932 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
11935 * If value is 0, this register is located in PCIe config space.
11936 * Drivers have to map appropriate window to access this
11939 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
11942 * If value is 1, this register is located in GRC address space.
11943 * Drivers have to map appropriate window to access this
11946 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
11949 * If value is 2, this register is located in first BAR address
11950 * space. Drivers have to map appropriate window to access this
11953 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
11956 * If value is 3, this register is located in second BAR address
11957 * space. Drivers have to map appropriate window to access this
11960 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
11962 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
11963 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
11964 /* Upper 30bits of the register address. */
11965 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
11966 UINT32_C(0xfffffffc)
11967 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
11969 /* This field indicates the mask value for reset_inprogress_reg. */
11970 uint32_t reset_inprogress_reg_mask;
11971 uint8_t unused_0[3];
11973 * Array of registers and value count to reset the Chip
11974 * Each array count has reset_reg, reset_reg_val, delay_after_reset
11975 * in TLV format. Depending upon Chip type, number of reset registers
11976 * will vary. Drivers have to write reset_reg_val in the reset_reg
11977 * location in the same sequence in order to recover from a fatal
11980 uint8_t reg_array_cnt;
11983 * Lower 2 bits indicates address space location and upper 30 bits
11984 * indicates actual address.
11985 * A value of 0xFFFF-FFFF indicates this register does not exist.
11987 uint32_t reset_reg[16];
11988 /* Lower 2 bits indicates address space location. */
11989 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
11991 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
11993 * If value is 0, this register is located in PCIe config space.
11994 * Drivers have to map appropriate window to access this
11997 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
12000 * If value is 1, this register is located in GRC address space.
12001 * Drivers have to map appropriate window to access this
12004 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
12007 * If value is 2, this register is located in first BAR address
12008 * space. Drivers have to map appropriate window to access this
12011 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
12014 * If value is 3, this register is located in second BAR address
12015 * space. Drivers have to map appropriate window to access this
12018 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
12020 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
12021 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
12022 /* Upper 30bits of the register address. */
12023 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
12024 UINT32_C(0xfffffffc)
12025 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
12026 /* Value to be written in reset_reg to reset the controller. */
12027 uint32_t reset_reg_val[16];
12029 * This value is in units of 1msec.
12030 * Typical value would be 10 to indicate 10msec.
12031 * Some of the operations like Core reset require delay before
12032 * accessing PCIE MMIO register space.
12033 * If this value is non-zero, drivers have to wait for
12034 * this much time after writing reset_reg_val in reset_reg.
12036 uint8_t delay_after_reset[16];
12037 uint8_t unused_1[7];
12039 * This field is used in Output records to indicate that the output
12040 * is completely written to RAM. This field should be read as '1'
12041 * to indicate that the output has been completely written.
12042 * When writing a command completion or response to an internal
12043 * processor, the order of writes has to be such that this field
12047 } __attribute__((packed));
12049 /***********************
12050 * hwrm_func_vlan_qcfg *
12051 ***********************/
12054 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
12055 struct hwrm_func_vlan_qcfg_input {
12056 /* The HWRM command request type. */
12059 * The completion ring to send the completion event on. This should
12060 * be the NQ ID returned from the `nq_alloc` HWRM command.
12062 uint16_t cmpl_ring;
12064 * The sequence ID is used by the driver for tracking multiple
12065 * commands. This ID is treated as opaque data by the firmware and
12066 * the value is returned in the `hwrm_resp_hdr` upon completion.
12070 * The target ID of the command:
12071 * * 0x0-0xFFF8 - The function ID
12072 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12073 * * 0xFFFD - Reserved for user-space HWRM interface
12076 uint16_t target_id;
12078 * A physical address pointer pointing to a host buffer that the
12079 * command's response data will be written. This can be either a host
12080 * physical address (HPA) or a guest physical address (GPA) and must
12081 * point to a physically contiguous block of memory.
12083 uint64_t resp_addr;
12085 * Function ID of the function that is being
12087 * If set to 0xFF... (All Fs), then the configuration is
12088 * for the requesting function.
12091 uint8_t unused_0[6];
12092 } __attribute__((packed));
12094 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
12095 struct hwrm_func_vlan_qcfg_output {
12096 /* The specific error status for the command. */
12097 uint16_t error_code;
12098 /* The HWRM command request type. */
12100 /* The sequence ID from the original command. */
12102 /* The length of the response data in number of bytes. */
12105 /* S-TAG VLAN identifier configured for the function. */
12107 /* S-TAG PCP value configured for the function. */
12111 * S-TAG TPID value configured for the function. This field is specified in
12112 * network byte order.
12114 uint16_t stag_tpid;
12115 /* C-TAG VLAN identifier configured for the function. */
12117 /* C-TAG PCP value configured for the function. */
12121 * C-TAG TPID value configured for the function. This field is specified in
12122 * network byte order.
12124 uint16_t ctag_tpid;
12129 uint8_t unused_3[3];
12131 * This field is used in Output records to indicate that the output
12132 * is completely written to RAM. This field should be read as '1'
12133 * to indicate that the output has been completely written.
12134 * When writing a command completion or response to an internal processor,
12135 * the order of writes has to be such that this field is written last.
12138 } __attribute__((packed));
12140 /**********************
12141 * hwrm_func_vlan_cfg *
12142 **********************/
12145 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
12146 struct hwrm_func_vlan_cfg_input {
12147 /* The HWRM command request type. */
12150 * The completion ring to send the completion event on. This should
12151 * be the NQ ID returned from the `nq_alloc` HWRM command.
12153 uint16_t cmpl_ring;
12155 * The sequence ID is used by the driver for tracking multiple
12156 * commands. This ID is treated as opaque data by the firmware and
12157 * the value is returned in the `hwrm_resp_hdr` upon completion.
12161 * The target ID of the command:
12162 * * 0x0-0xFFF8 - The function ID
12163 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12164 * * 0xFFFD - Reserved for user-space HWRM interface
12167 uint16_t target_id;
12169 * A physical address pointer pointing to a host buffer that the
12170 * command's response data will be written. This can be either a host
12171 * physical address (HPA) or a guest physical address (GPA) and must
12172 * point to a physically contiguous block of memory.
12174 uint64_t resp_addr;
12176 * Function ID of the function that is being
12178 * If set to 0xFF... (All Fs), then the configuration is
12179 * for the requesting function.
12182 uint8_t unused_0[2];
12185 * This bit must be '1' for the stag_vid field to be
12188 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
12190 * This bit must be '1' for the ctag_vid field to be
12193 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
12195 * This bit must be '1' for the stag_pcp field to be
12198 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
12200 * This bit must be '1' for the ctag_pcp field to be
12203 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
12205 * This bit must be '1' for the stag_tpid field to be
12208 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
12210 * This bit must be '1' for the ctag_tpid field to be
12213 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
12214 /* S-TAG VLAN identifier configured for the function. */
12216 /* S-TAG PCP value configured for the function. */
12220 * S-TAG TPID value configured for the function. This field is specified in
12221 * network byte order.
12223 uint16_t stag_tpid;
12224 /* C-TAG VLAN identifier configured for the function. */
12226 /* C-TAG PCP value configured for the function. */
12230 * C-TAG TPID value configured for the function. This field is specified in
12231 * network byte order.
12233 uint16_t ctag_tpid;
12238 uint8_t unused_3[4];
12239 } __attribute__((packed));
12241 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
12242 struct hwrm_func_vlan_cfg_output {
12243 /* The specific error status for the command. */
12244 uint16_t error_code;
12245 /* The HWRM command request type. */
12247 /* The sequence ID from the original command. */
12249 /* The length of the response data in number of bytes. */
12251 uint8_t unused_0[7];
12253 * This field is used in Output records to indicate that the output
12254 * is completely written to RAM. This field should be read as '1'
12255 * to indicate that the output has been completely written.
12256 * When writing a command completion or response to an internal processor,
12257 * the order of writes has to be such that this field is written last.
12260 } __attribute__((packed));
12262 /*******************************
12263 * hwrm_func_vf_vnic_ids_query *
12264 *******************************/
12267 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
12268 struct hwrm_func_vf_vnic_ids_query_input {
12269 /* The HWRM command request type. */
12272 * The completion ring to send the completion event on. This should
12273 * be the NQ ID returned from the `nq_alloc` HWRM command.
12275 uint16_t cmpl_ring;
12277 * The sequence ID is used by the driver for tracking multiple
12278 * commands. This ID is treated as opaque data by the firmware and
12279 * the value is returned in the `hwrm_resp_hdr` upon completion.
12283 * The target ID of the command:
12284 * * 0x0-0xFFF8 - The function ID
12285 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12286 * * 0xFFFD - Reserved for user-space HWRM interface
12289 uint16_t target_id;
12291 * A physical address pointer pointing to a host buffer that the
12292 * command's response data will be written. This can be either a host
12293 * physical address (HPA) or a guest physical address (GPA) and must
12294 * point to a physically contiguous block of memory.
12296 uint64_t resp_addr;
12298 * This value is used to identify a Virtual Function (VF).
12299 * The scope of VF ID is local within a PF.
12302 uint8_t unused_0[2];
12303 /* Max number of vnic ids in vnic id table */
12304 uint32_t max_vnic_id_cnt;
12305 /* This is the address for VF VNIC ID table */
12306 uint64_t vnic_id_tbl_addr;
12307 } __attribute__((packed));
12309 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
12310 struct hwrm_func_vf_vnic_ids_query_output {
12311 /* The specific error status for the command. */
12312 uint16_t error_code;
12313 /* The HWRM command request type. */
12315 /* The sequence ID from the original command. */
12317 /* The length of the response data in number of bytes. */
12320 * Actual number of vnic ids
12322 * Each VNIC ID is written as a 32-bit number.
12324 uint32_t vnic_id_cnt;
12325 uint8_t unused_0[3];
12327 * This field is used in Output records to indicate that the output
12328 * is completely written to RAM. This field should be read as '1'
12329 * to indicate that the output has been completely written.
12330 * When writing a command completion or response to an internal processor,
12331 * the order of writes has to be such that this field is written last.
12334 } __attribute__((packed));
12336 /***********************
12337 * hwrm_func_vf_bw_cfg *
12338 ***********************/
12341 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
12342 struct hwrm_func_vf_bw_cfg_input {
12343 /* The HWRM command request type. */
12346 * The completion ring to send the completion event on. This should
12347 * be the NQ ID returned from the `nq_alloc` HWRM command.
12349 uint16_t cmpl_ring;
12351 * The sequence ID is used by the driver for tracking multiple
12352 * commands. This ID is treated as opaque data by the firmware and
12353 * the value is returned in the `hwrm_resp_hdr` upon completion.
12357 * The target ID of the command:
12358 * * 0x0-0xFFF8 - The function ID
12359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12360 * * 0xFFFD - Reserved for user-space HWRM interface
12363 uint16_t target_id;
12365 * A physical address pointer pointing to a host buffer that the
12366 * command's response data will be written. This can be either a host
12367 * physical address (HPA) or a guest physical address (GPA) and must
12368 * point to a physically contiguous block of memory.
12370 uint64_t resp_addr;
12372 * The number of VF functions that are being configured.
12373 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
12376 uint16_t unused[3];
12377 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12379 /* The physical VF id the adjustment will be made to. */
12380 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12381 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
12383 * This field configures the rate scale percentage of the VF as specified
12384 * by the physical VF id.
12386 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
12387 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
12388 /* 0% of the max tx rate */
12389 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
12390 (UINT32_C(0x0) << 12)
12391 /* 6.66% of the max tx rate */
12392 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
12393 (UINT32_C(0x1) << 12)
12394 /* 13.33% of the max tx rate */
12395 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
12396 (UINT32_C(0x2) << 12)
12397 /* 20% of the max tx rate */
12398 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
12399 (UINT32_C(0x3) << 12)
12400 /* 26.66% of the max tx rate */
12401 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
12402 (UINT32_C(0x4) << 12)
12403 /* 33% of the max tx rate */
12404 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
12405 (UINT32_C(0x5) << 12)
12406 /* 40% of the max tx rate */
12407 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
12408 (UINT32_C(0x6) << 12)
12409 /* 46.66% of the max tx rate */
12410 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
12411 (UINT32_C(0x7) << 12)
12412 /* 53.33% of the max tx rate */
12413 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
12414 (UINT32_C(0x8) << 12)
12415 /* 60% of the max tx rate */
12416 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
12417 (UINT32_C(0x9) << 12)
12418 /* 66.66% of the max tx rate */
12419 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
12420 (UINT32_C(0xa) << 12)
12421 /* 53.33% of the max tx rate */
12422 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
12423 (UINT32_C(0xb) << 12)
12424 /* 80% of the max tx rate */
12425 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
12426 (UINT32_C(0xc) << 12)
12427 /* 86.66% of the max tx rate */
12428 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
12429 (UINT32_C(0xd) << 12)
12430 /* 93.33% of the max tx rate */
12431 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
12432 (UINT32_C(0xe) << 12)
12433 /* 100% of the max tx rate */
12434 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
12435 (UINT32_C(0xf) << 12)
12436 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
12437 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
12438 } __attribute__((packed));
12440 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
12441 struct hwrm_func_vf_bw_cfg_output {
12442 /* The specific error status for the command. */
12443 uint16_t error_code;
12444 /* The HWRM command request type. */
12446 /* The sequence ID from the original command. */
12448 /* The length of the response data in number of bytes. */
12450 uint8_t unused_0[7];
12452 * This field is used in Output records to indicate that the output
12453 * is completely written to RAM. This field should be read as '1'
12454 * to indicate that the output has been completely written.
12455 * When writing a command completion or response to an internal processor,
12456 * the order of writes has to be such that this field is written last.
12459 } __attribute__((packed));
12461 /************************
12462 * hwrm_func_vf_bw_qcfg *
12463 ************************/
12466 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
12467 struct hwrm_func_vf_bw_qcfg_input {
12468 /* The HWRM command request type. */
12471 * The completion ring to send the completion event on. This should
12472 * be the NQ ID returned from the `nq_alloc` HWRM command.
12474 uint16_t cmpl_ring;
12476 * The sequence ID is used by the driver for tracking multiple
12477 * commands. This ID is treated as opaque data by the firmware and
12478 * the value is returned in the `hwrm_resp_hdr` upon completion.
12482 * The target ID of the command:
12483 * * 0x0-0xFFF8 - The function ID
12484 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12485 * * 0xFFFD - Reserved for user-space HWRM interface
12488 uint16_t target_id;
12490 * A physical address pointer pointing to a host buffer that the
12491 * command's response data will be written. This can be either a host
12492 * physical address (HPA) or a guest physical address (GPA) and must
12493 * point to a physically contiguous block of memory.
12495 uint64_t resp_addr;
12497 * The number of VF functions that are being queried.
12498 * The inline response space allows the host to query up to 50 VFs'
12499 * rate scale percentage
12502 uint16_t unused[3];
12503 /* These 16-bit fields contain the VF fid */
12505 /* The physical VF id of interest */
12506 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12507 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
12508 } __attribute__((packed));
12510 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
12511 struct hwrm_func_vf_bw_qcfg_output {
12512 /* The specific error status for the command. */
12513 uint16_t error_code;
12514 /* The HWRM command request type. */
12516 /* The sequence ID from the original command. */
12518 /* The length of the response data in number of bytes. */
12521 * The number of VF functions that are being queried.
12522 * The inline response space allows the host to query up to 50 VFs' rate
12526 uint16_t unused[3];
12527 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12529 /* The physical VF id the adjustment will be made to. */
12530 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
12531 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
12533 * This field configures the rate scale percentage of the VF as specified
12534 * by the physical VF id.
12536 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
12537 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
12538 /* 0% of the max tx rate */
12539 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
12540 (UINT32_C(0x0) << 12)
12541 /* 6.66% of the max tx rate */
12542 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
12543 (UINT32_C(0x1) << 12)
12544 /* 13.33% of the max tx rate */
12545 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
12546 (UINT32_C(0x2) << 12)
12547 /* 20% of the max tx rate */
12548 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
12549 (UINT32_C(0x3) << 12)
12550 /* 26.66% of the max tx rate */
12551 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
12552 (UINT32_C(0x4) << 12)
12553 /* 33% of the max tx rate */
12554 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
12555 (UINT32_C(0x5) << 12)
12556 /* 40% of the max tx rate */
12557 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
12558 (UINT32_C(0x6) << 12)
12559 /* 46.66% of the max tx rate */
12560 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
12561 (UINT32_C(0x7) << 12)
12562 /* 53.33% of the max tx rate */
12563 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
12564 (UINT32_C(0x8) << 12)
12565 /* 60% of the max tx rate */
12566 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
12567 (UINT32_C(0x9) << 12)
12568 /* 66.66% of the max tx rate */
12569 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
12570 (UINT32_C(0xa) << 12)
12571 /* 53.33% of the max tx rate */
12572 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
12573 (UINT32_C(0xb) << 12)
12574 /* 80% of the max tx rate */
12575 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
12576 (UINT32_C(0xc) << 12)
12577 /* 86.66% of the max tx rate */
12578 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
12579 (UINT32_C(0xd) << 12)
12580 /* 93.33% of the max tx rate */
12581 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
12582 (UINT32_C(0xe) << 12)
12583 /* 100% of the max tx rate */
12584 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
12585 (UINT32_C(0xf) << 12)
12586 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
12587 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
12588 uint8_t unused_0[7];
12590 * This field is used in Output records to indicate that the output
12591 * is completely written to RAM. This field should be read as '1'
12592 * to indicate that the output has been completely written.
12593 * When writing a command completion or response to an internal processor,
12594 * the order of writes has to be such that this field is written last.
12597 } __attribute__((packed));
12599 /***************************
12600 * hwrm_func_drv_if_change *
12601 ***************************/
12604 /* hwrm_func_drv_if_change_input (size:192b/24B) */
12605 struct hwrm_func_drv_if_change_input {
12606 /* The HWRM command request type. */
12609 * The completion ring to send the completion event on. This should
12610 * be the NQ ID returned from the `nq_alloc` HWRM command.
12612 uint16_t cmpl_ring;
12614 * The sequence ID is used by the driver for tracking multiple
12615 * commands. This ID is treated as opaque data by the firmware and
12616 * the value is returned in the `hwrm_resp_hdr` upon completion.
12620 * The target ID of the command:
12621 * * 0x0-0xFFF8 - The function ID
12622 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12623 * * 0xFFFD - Reserved for user-space HWRM interface
12626 uint16_t target_id;
12628 * A physical address pointer pointing to a host buffer that the
12629 * command's response data will be written. This can be either a host
12630 * physical address (HPA) or a guest physical address (GPA) and must
12631 * point to a physically contiguous block of memory.
12633 uint64_t resp_addr;
12636 * When this bit is '1', the function driver is indicating
12637 * that the IF state is changing to UP state. The call should
12638 * be made at the beginning of the driver's open call before
12639 * resources are allocated. After making the call, the driver
12640 * should check the response to see if any resources may have
12641 * changed (see the response below). If the driver fails
12642 * the open call, the driver should make this call again with
12643 * this bit cleared to indicate that the IF state is not UP.
12644 * During the driver's close call when the IF state is changing
12645 * to DOWN, the driver should make this call with the bit cleared
12646 * after all resources have been freed.
12648 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
12650 } __attribute__((packed));
12652 /* hwrm_func_drv_if_change_output (size:128b/16B) */
12653 struct hwrm_func_drv_if_change_output {
12654 /* The specific error status for the command. */
12655 uint16_t error_code;
12656 /* The HWRM command request type. */
12658 /* The sequence ID from the original command. */
12660 /* The length of the response data in number of bytes. */
12664 * When this bit is '1', it indicates that the resources reserved
12665 * for this function may have changed. The driver should check
12666 * resource capabilities and reserve resources again before
12667 * allocating resources.
12669 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
12672 * When this bit is '1', it indicates that the firmware got changed / reset.
12673 * The driver should do complete re-initialization when that bit is set.
12675 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
12677 uint8_t unused_0[3];
12679 * This field is used in Output records to indicate that the output
12680 * is completely written to RAM. This field should be read as '1'
12681 * to indicate that the output has been completely written.
12682 * When writing a command completion or response to an internal processor,
12683 * the order of writes has to be such that this field is written last.
12686 } __attribute__((packed));
12688 /*******************************
12689 * hwrm_func_host_pf_ids_query *
12690 *******************************/
12693 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
12694 struct hwrm_func_host_pf_ids_query_input {
12695 /* The HWRM command request type. */
12698 * The completion ring to send the completion event on. This should
12699 * be the NQ ID returned from the `nq_alloc` HWRM command.
12701 uint16_t cmpl_ring;
12703 * The sequence ID is used by the driver for tracking multiple
12704 * commands. This ID is treated as opaque data by the firmware and
12705 * the value is returned in the `hwrm_resp_hdr` upon completion.
12709 * The target ID of the command:
12710 * * 0x0-0xFFF8 - The function ID
12711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12712 * * 0xFFFD - Reserved for user-space HWRM interface
12715 uint16_t target_id;
12717 * A physical address pointer pointing to a host buffer that the
12718 * command's response data will be written. This can be either a host
12719 * physical address (HPA) or a guest physical address (GPA) and must
12720 * point to a physically contiguous block of memory.
12722 uint64_t resp_addr;
12725 * # If this bit is set to '1', the query will contain PF(s)
12726 * belongs to SOC host.
12728 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
12730 * # If this bit is set to '1', the query will contain PF(s)
12731 * belongs to EP0 host.
12733 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
12735 * # If this bit is set to '1', the query will contain PF(s)
12736 * belongs to EP1 host.
12738 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
12740 * # If this bit is set to '1', the query will contain PF(s)
12741 * belongs to EP2 host.
12743 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
12745 * # If this bit is set to '1', the query will contain PF(s)
12746 * belongs to EP3 host.
12748 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
12750 * This provides a filter of what PF(s) will be returned in the
12755 * all available PF(s) belong to the host(s) (defined in the
12756 * host field). This includes the hidden PFs.
12758 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
12760 * all available PF(s) belong to the host(s) (defined in the
12761 * host field) that is available for L2 traffic.
12763 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
12765 * all available PF(s) belong to the host(s) (defined in the
12766 * host field) that is available for ROCE traffic.
12768 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
12769 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
12770 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
12771 uint8_t unused_1[6];
12772 } __attribute__((packed));
12774 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
12775 struct hwrm_func_host_pf_ids_query_output {
12776 /* The specific error status for the command. */
12777 uint16_t error_code;
12778 /* The HWRM command request type. */
12780 /* The sequence ID from the original command. */
12782 /* The length of the response data in number of bytes. */
12784 /* This provides the first PF ID of the device. */
12785 uint16_t first_pf_id;
12786 uint16_t pf_ordinal_mask;
12788 * When this bit is '1', it indicates first PF belongs to one of
12789 * the hosts defined in the input request.
12791 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
12794 * When this bit is '1', it indicates 2nd PF belongs to one of the
12795 * hosts defined in the input request.
12797 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
12800 * When this bit is '1', it indicates 3rd PF belongs to one of the
12801 * hosts defined in the input request.
12803 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
12806 * When this bit is '1', it indicates 4th PF belongs to one of the
12807 * hosts defined in the input request.
12809 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
12812 * When this bit is '1', it indicates 5th PF belongs to one of the
12813 * hosts defined in the input request.
12815 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
12818 * When this bit is '1', it indicates 6th PF belongs to one of the
12819 * hosts defined in the input request.
12821 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
12824 * When this bit is '1', it indicates 7th PF belongs to one of the
12825 * hosts defined in the input request.
12827 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
12830 * When this bit is '1', it indicates 8th PF belongs to one of the
12831 * hosts defined in the input request.
12833 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
12836 * When this bit is '1', it indicates 9th PF belongs to one of the
12837 * hosts defined in the input request.
12839 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
12842 * When this bit is '1', it indicates 10th PF belongs to one of the
12843 * hosts defined in the input request.
12845 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
12848 * When this bit is '1', it indicates 11th PF belongs to one of the
12849 * hosts defined in the input request.
12851 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
12854 * When this bit is '1', it indicates 12th PF belongs to one of the
12855 * hosts defined in the input request.
12857 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
12860 * When this bit is '1', it indicates 13th PF belongs to one of the
12861 * hosts defined in the input request.
12863 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
12866 * When this bit is '1', it indicates 14th PF belongs to one of the
12867 * hosts defined in the input request.
12869 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
12872 * When this bit is '1', it indicates 15th PF belongs to one of the
12873 * hosts defined in the input request.
12875 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
12878 * When this bit is '1', it indicates 16th PF belongs to one of the
12879 * hosts defined in the input request.
12881 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
12883 uint8_t unused_1[3];
12885 * This field is used in Output records to indicate that the output
12886 * is completely written to RAM. This field should be read as '1'
12887 * to indicate that the output has been completely written.
12888 * When writing a command completion or response to an internal processor,
12889 * the order of writes has to be such that this field is written last.
12892 } __attribute__((packed));
12894 /*********************
12895 * hwrm_port_phy_cfg *
12896 *********************/
12899 /* hwrm_port_phy_cfg_input (size:448b/56B) */
12900 struct hwrm_port_phy_cfg_input {
12901 /* The HWRM command request type. */
12904 * The completion ring to send the completion event on. This should
12905 * be the NQ ID returned from the `nq_alloc` HWRM command.
12907 uint16_t cmpl_ring;
12909 * The sequence ID is used by the driver for tracking multiple
12910 * commands. This ID is treated as opaque data by the firmware and
12911 * the value is returned in the `hwrm_resp_hdr` upon completion.
12915 * The target ID of the command:
12916 * * 0x0-0xFFF8 - The function ID
12917 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12918 * * 0xFFFD - Reserved for user-space HWRM interface
12921 uint16_t target_id;
12923 * A physical address pointer pointing to a host buffer that the
12924 * command's response data will be written. This can be either a host
12925 * physical address (HPA) or a guest physical address (GPA) and must
12926 * point to a physically contiguous block of memory.
12928 uint64_t resp_addr;
12931 * When this bit is set to '1', the PHY for the port shall
12934 * # If this bit is set to 1, then the HWRM shall reset the
12935 * PHY after applying PHY configuration changes specified
12937 * # In order to guarantee that PHY configuration changes
12938 * specified in this command take effect, the HWRM
12939 * client should set this flag to 1.
12940 * # If this bit is not set to 1, then the HWRM may reset
12941 * the PHY depending on the current PHY configuration and
12942 * settings specified in this command.
12944 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
12946 /* deprecated bit. Do not use!!! */
12947 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
12950 * When this bit is set to '1', the link shall be forced to
12951 * the force_link_speed value.
12953 * When this bit is set to '1', the HWRM client should
12954 * not enable any of the auto negotiation related
12955 * fields represented by auto_XXX fields in this command.
12956 * When this bit is set to '1' and the HWRM client has
12957 * enabled a auto_XXX field in this command, then the
12958 * HWRM shall ignore the enabled auto_XXX field.
12960 * When this bit is set to zero, the link
12961 * shall be allowed to autoneg.
12963 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
12966 * When this bit is set to '1', the auto-negotiation process
12967 * shall be restarted on the link.
12969 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
12972 * When this bit is set to '1', Energy Efficient Ethernet
12973 * (EEE) is requested to be enabled on this link.
12974 * If EEE is not supported on this port, then this flag
12975 * shall be ignored by the HWRM.
12977 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
12980 * When this bit is set to '1', Energy Efficient Ethernet
12981 * (EEE) is requested to be disabled on this link.
12982 * If EEE is not supported on this port, then this flag
12983 * shall be ignored by the HWRM.
12985 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
12988 * When this bit is set to '1' and EEE is enabled on this
12989 * link, then TX LPI is requested to be enabled on the link.
12990 * If EEE is not supported on this port, then this flag
12991 * shall be ignored by the HWRM.
12992 * If EEE is disabled on this port, then this flag shall be
12993 * ignored by the HWRM.
12995 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
12998 * When this bit is set to '1' and EEE is enabled on this
12999 * link, then TX LPI is requested to be disabled on the link.
13000 * If EEE is not supported on this port, then this flag
13001 * shall be ignored by the HWRM.
13002 * If EEE is disabled on this port, then this flag shall be
13003 * ignored by the HWRM.
13005 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
13008 * When set to 1, then the HWRM shall enable FEC autonegotitation
13009 * on this port if supported.
13010 * When set to 0, then this flag shall be ignored.
13011 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13014 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
13017 * When set to 1, then the HWRM shall disable FEC autonegotiation
13018 * on this port if supported.
13019 * When set to 0, then this flag shall be ignored.
13020 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13023 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
13026 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
13027 * on this port if supported.
13028 * When set to 0, then this flag shall be ignored.
13029 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13032 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
13035 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
13036 * on this port if supported.
13037 * When set to 0, then this flag shall be ignored.
13038 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13041 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
13044 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
13045 * on this port if supported.
13046 * When set to 0, then this flag shall be ignored.
13047 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13050 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
13053 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
13054 * on this port if supported.
13055 * When set to 0, then this flag shall be ignored.
13056 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13059 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
13062 * When this bit is set to '1', the link shall be forced to
13065 * # When this bit is set to '1", all other
13066 * command input settings related to the link speed shall
13068 * Once the link state is forced down, it can be
13069 * explicitly cleared from that state by setting this flag
13071 * # If this flag is set to '0', then the link shall be
13072 * cleared from forced down state if the link is in forced
13074 * There may be conditions (e.g. out-of-band or sideband
13075 * configuration changes for the link) outside the scope
13076 * of the HWRM implementation that may clear forced down
13079 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
13083 * This bit must be '1' for the auto_mode field to be
13086 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
13089 * This bit must be '1' for the auto_duplex field to be
13092 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
13095 * This bit must be '1' for the auto_pause field to be
13098 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
13101 * This bit must be '1' for the auto_link_speed field to be
13104 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
13107 * This bit must be '1' for the auto_link_speed_mask field to be
13110 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
13113 * This bit must be '1' for the wirespeed field to be
13116 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
13119 * This bit must be '1' for the lpbk field to be
13122 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
13125 * This bit must be '1' for the preemphasis field to be
13128 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
13131 * This bit must be '1' for the force_pause field to be
13134 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
13137 * This bit must be '1' for the eee_link_speed_mask field to be
13140 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
13143 * This bit must be '1' for the tx_lpi_timer field to be
13146 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
13148 /* Port ID of port that is to be configured. */
13151 * This is the speed that will be used if the force
13152 * bit is '1'. If unsupported speed is selected, an error
13153 * will be generated.
13155 uint16_t force_link_speed;
13156 /* 100Mb link speed */
13157 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13158 /* 1Gb link speed */
13159 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13160 /* 2Gb link speed */
13161 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13162 /* 25Gb link speed */
13163 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13164 /* 10Gb link speed */
13165 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13166 /* 20Mb link speed */
13167 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13168 /* 25Gb link speed */
13169 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13170 /* 40Gb link speed */
13171 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
13172 /* 50Gb link speed */
13173 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
13174 /* 100Gb link speed */
13175 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
13176 /* 200Gb link speed */
13177 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
13178 /* 10Mb link speed */
13179 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
13180 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
13181 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
13183 * This value is used to identify what autoneg mode is
13184 * used when the link speed is not being forced.
13187 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13188 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
13189 /* Select all possible speeds for autoneg mode. */
13190 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13192 * Select only the auto_link_speed speed for autoneg mode. This mode has
13193 * been DEPRECATED. An HWRM client should not use this mode.
13195 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13197 * Select the auto_link_speed or any speed below that speed for autoneg.
13198 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13200 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13202 * Select the speeds based on the corresponding link speed mask value
13203 * that is provided.
13205 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13206 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
13207 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
13209 * This is the duplex setting that will be used if the autoneg_mode
13210 * is "one_speed" or "one_or_below".
13212 uint8_t auto_duplex;
13213 /* Half Duplex will be requested. */
13214 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
13215 /* Full duplex will be requested. */
13216 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
13217 /* Both Half and Full dupex will be requested. */
13218 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
13219 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
13220 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
13222 * This value is used to configure the pause that will be
13223 * used for autonegotiation.
13224 * Add text on the usage of auto_pause and force_pause.
13226 uint8_t auto_pause;
13228 * When this bit is '1', Generation of tx pause messages
13229 * has been requested. Disabled otherwise.
13231 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
13234 * When this bit is '1', Reception of rx pause messages
13235 * has been requested. Disabled otherwise.
13237 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
13240 * When set to 1, the advertisement of pause is enabled.
13242 * # When the auto_mode is not set to none and this flag is
13243 * set to 1, then the auto_pause bits on this port are being
13244 * advertised and autoneg pause results are being interpreted.
13245 * # When the auto_mode is not set to none and this
13246 * flag is set to 0, the pause is forced as indicated in
13247 * force_pause, and also advertised as auto_pause bits, but
13248 * the autoneg results are not interpreted since the pause
13249 * configuration is being forced.
13250 * # When the auto_mode is set to none and this flag is set to
13251 * 1, auto_pause bits should be ignored and should be set to 0.
13253 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13257 * This is the speed that will be used if the autoneg_mode
13258 * is "one_speed" or "one_or_below". If an unsupported speed
13259 * is selected, an error will be generated.
13261 uint16_t auto_link_speed;
13262 /* 100Mb link speed */
13263 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13264 /* 1Gb link speed */
13265 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13266 /* 2Gb link speed */
13267 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13268 /* 25Gb link speed */
13269 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13270 /* 10Gb link speed */
13271 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13272 /* 20Mb link speed */
13273 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13274 /* 25Gb link speed */
13275 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13276 /* 40Gb link speed */
13277 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13278 /* 50Gb link speed */
13279 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13280 /* 100Gb link speed */
13281 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13282 /* 200Gb link speed */
13283 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13284 /* 10Mb link speed */
13285 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
13286 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
13287 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
13289 * This is a mask of link speeds that will be used if
13290 * autoneg_mode is "mask". If unsupported speed is enabled
13291 * an error will be generated.
13293 uint16_t auto_link_speed_mask;
13294 /* 100Mb link speed (Half-duplex) */
13295 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13297 /* 100Mb link speed (Full-duplex) */
13298 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
13300 /* 1Gb link speed (Half-duplex) */
13301 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13303 /* 1Gb link speed (Full-duplex) */
13304 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
13306 /* 2Gb link speed */
13307 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
13309 /* 25Gb link speed */
13310 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13312 /* 10Gb link speed */
13313 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
13315 /* 20Gb link speed */
13316 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
13318 /* 25Gb link speed */
13319 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
13321 /* 40Gb link speed */
13322 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
13324 /* 50Gb link speed */
13325 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
13327 /* 100Gb link speed */
13328 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
13330 /* 10Mb link speed (Half-duplex) */
13331 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13333 /* 10Mb link speed (Full-duplex) */
13334 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
13336 /* 200Gb link speed */
13337 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
13339 /* This value controls the wirespeed feature. */
13341 /* Wirespeed feature is disabled. */
13342 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
13343 /* Wirespeed feature is enabled. */
13344 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
13345 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
13346 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
13347 /* This value controls the loopback setting for the PHY. */
13349 /* No loopback is selected. Normal operation. */
13350 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13352 * The HW will be configured with local loopback such that
13353 * host data is sent back to the host without modification.
13355 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13357 * The HW will be configured with remote loopback such that
13358 * port logic will send packets back out the transmitter that
13361 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13363 * The HW will be configured with external loopback such that
13364 * host data is sent on the trasmitter and based on the external
13365 * loopback connection the data will be received without modification.
13367 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
13368 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
13369 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
13371 * This value is used to configure the pause that will be
13372 * used for force mode.
13374 uint8_t force_pause;
13376 * When this bit is '1', Generation of tx pause messages
13377 * is supported. Disabled otherwise.
13379 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13381 * When this bit is '1', Reception of rx pause messages
13382 * is supported. Disabled otherwise.
13384 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13387 * This value controls the pre-emphasis to be used for the
13388 * link. Driver should not set this value (use
13389 * enable.preemphasis = 0) unless driver is sure of setting.
13390 * Normally HWRM FW will determine proper pre-emphasis.
13392 uint32_t preemphasis;
13394 * Setting for link speed mask that is used to
13395 * advertise speeds during autonegotiation when EEE is enabled.
13396 * This field is valid only when EEE is enabled.
13397 * The speeds specified in this field shall be a subset of
13398 * speeds specified in auto_link_speed_mask.
13399 * If EEE is enabled,then at least one speed shall be provided
13402 uint16_t eee_link_speed_mask;
13404 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
13406 /* 100Mb link speed (Full-duplex) */
13407 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
13410 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
13412 /* 1Gb link speed (Full-duplex) */
13413 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
13416 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
13419 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
13421 /* 10Gb link speed */
13422 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
13424 uint8_t unused_2[2];
13426 * Reuested setting of TX LPI timer in microseconds.
13427 * This field is valid only when EEE is enabled and TX LPI is
13430 uint32_t tx_lpi_timer;
13431 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
13432 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
13434 } __attribute__((packed));
13436 /* hwrm_port_phy_cfg_output (size:128b/16B) */
13437 struct hwrm_port_phy_cfg_output {
13438 /* The specific error status for the command. */
13439 uint16_t error_code;
13440 /* The HWRM command request type. */
13442 /* The sequence ID from the original command. */
13444 /* The length of the response data in number of bytes. */
13446 uint8_t unused_0[7];
13448 * This field is used in Output records to indicate that the output
13449 * is completely written to RAM. This field should be read as '1'
13450 * to indicate that the output has been completely written.
13451 * When writing a command completion or response to an internal processor,
13452 * the order of writes has to be such that this field is written last.
13455 } __attribute__((packed));
13457 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
13458 struct hwrm_port_phy_cfg_cmd_err {
13460 * command specific error codes that goes to
13461 * the cmd_err field in Common HWRM Error Response.
13464 /* Unknown error */
13465 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
13466 /* Unable to complete operation due to invalid speed */
13467 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
13469 * retry the command since the phy is not ready.
13470 * retry count is returned in opaque_0.
13471 * This is only valid for the first command and
13472 * this value will not change for successive calls.
13473 * but if a 0 is returned at any time then this should
13474 * be treated as an un recoverable failure,
13476 * retry interval in milli seconds is returned in opaque_1.
13477 * This specifies the time that user should wait before
13478 * issuing the next port_phy_cfg command.
13480 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
13481 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
13482 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
13483 uint8_t unused_0[7];
13484 } __attribute__((packed));
13486 /**********************
13487 * hwrm_port_phy_qcfg *
13488 **********************/
13491 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
13492 struct hwrm_port_phy_qcfg_input {
13493 /* The HWRM command request type. */
13496 * The completion ring to send the completion event on. This should
13497 * be the NQ ID returned from the `nq_alloc` HWRM command.
13499 uint16_t cmpl_ring;
13501 * The sequence ID is used by the driver for tracking multiple
13502 * commands. This ID is treated as opaque data by the firmware and
13503 * the value is returned in the `hwrm_resp_hdr` upon completion.
13507 * The target ID of the command:
13508 * * 0x0-0xFFF8 - The function ID
13509 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13510 * * 0xFFFD - Reserved for user-space HWRM interface
13513 uint16_t target_id;
13515 * A physical address pointer pointing to a host buffer that the
13516 * command's response data will be written. This can be either a host
13517 * physical address (HPA) or a guest physical address (GPA) and must
13518 * point to a physically contiguous block of memory.
13520 uint64_t resp_addr;
13521 /* Port ID of port that is to be queried. */
13523 uint8_t unused_0[6];
13524 } __attribute__((packed));
13526 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
13527 struct hwrm_port_phy_qcfg_output {
13528 /* The specific error status for the command. */
13529 uint16_t error_code;
13530 /* The HWRM command request type. */
13532 /* The sequence ID from the original command. */
13534 /* The length of the response data in number of bytes. */
13536 /* This value indicates the current link status. */
13538 /* There is no link or cable detected. */
13539 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
13540 /* There is no link, but a cable has been detected. */
13541 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
13542 /* There is a link. */
13543 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
13544 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
13545 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
13547 /* This value indicates the current link speed of the connection. */
13548 uint16_t link_speed;
13549 /* 100Mb link speed */
13550 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
13551 /* 1Gb link speed */
13552 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
13553 /* 2Gb link speed */
13554 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
13555 /* 25Gb link speed */
13556 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
13557 /* 10Gb link speed */
13558 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
13559 /* 20Mb link speed */
13560 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
13561 /* 25Gb link speed */
13562 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
13563 /* 40Gb link speed */
13564 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
13565 /* 50Gb link speed */
13566 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
13567 /* 100Gb link speed */
13568 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
13569 /* 200Gb link speed */
13570 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
13571 /* 10Mb link speed */
13572 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
13573 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
13574 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
13576 * This value is indicates the duplex of the current
13579 uint8_t duplex_cfg;
13580 /* Half Duplex connection. */
13581 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
13582 /* Full duplex connection. */
13583 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
13584 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
13585 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
13587 * This value is used to indicate the current
13588 * pause configuration. When autoneg is enabled, this value
13589 * represents the autoneg results of pause configuration.
13593 * When this bit is '1', Generation of tx pause messages
13594 * is supported. Disabled otherwise.
13596 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
13598 * When this bit is '1', Reception of rx pause messages
13599 * is supported. Disabled otherwise.
13601 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
13603 * The supported speeds for the port. This is a bit mask.
13604 * For each speed that is supported, the corrresponding
13605 * bit will be set to '1'.
13607 uint16_t support_speeds;
13608 /* 100Mb link speed (Half-duplex) */
13609 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
13611 /* 100Mb link speed (Full-duplex) */
13612 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
13614 /* 1Gb link speed (Half-duplex) */
13615 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
13617 /* 1Gb link speed (Full-duplex) */
13618 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
13620 /* 2Gb link speed */
13621 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
13623 /* 25Gb link speed */
13624 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
13626 /* 10Gb link speed */
13627 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
13629 /* 20Gb link speed */
13630 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
13632 /* 25Gb link speed */
13633 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
13635 /* 40Gb link speed */
13636 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
13638 /* 50Gb link speed */
13639 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
13641 /* 100Gb link speed */
13642 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
13644 /* 10Mb link speed (Half-duplex) */
13645 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
13647 /* 10Mb link speed (Full-duplex) */
13648 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
13650 /* 200Gb link speed */
13651 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
13654 * Current setting of forced link speed.
13655 * When the link speed is not being forced, this
13656 * value shall be set to 0.
13658 uint16_t force_link_speed;
13659 /* 100Mb link speed */
13660 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13661 /* 1Gb link speed */
13662 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13663 /* 2Gb link speed */
13664 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13665 /* 25Gb link speed */
13666 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13667 /* 10Gb link speed */
13668 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13669 /* 20Mb link speed */
13670 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13671 /* 25Gb link speed */
13672 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13673 /* 40Gb link speed */
13674 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
13676 /* 50Gb link speed */
13677 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
13679 /* 100Gb link speed */
13680 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
13682 /* 200Gb link speed */
13683 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
13685 /* 10Mb link speed */
13686 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
13688 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
13689 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
13690 /* Current setting of auto negotiation mode. */
13692 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13693 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
13694 /* Select all possible speeds for autoneg mode. */
13695 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13697 * Select only the auto_link_speed speed for autoneg mode. This mode has
13698 * been DEPRECATED. An HWRM client should not use this mode.
13700 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13702 * Select the auto_link_speed or any speed below that speed for autoneg.
13703 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13705 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13707 * Select the speeds based on the corresponding link speed mask value
13708 * that is provided.
13710 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13711 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
13712 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
13714 * Current setting of pause autonegotiation.
13715 * Move autoneg_pause flag here.
13717 uint8_t auto_pause;
13719 * When this bit is '1', Generation of tx pause messages
13720 * has been requested. Disabled otherwise.
13722 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
13725 * When this bit is '1', Reception of rx pause messages
13726 * has been requested. Disabled otherwise.
13728 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
13731 * When set to 1, the advertisement of pause is enabled.
13733 * # When the auto_mode is not set to none and this flag is
13734 * set to 1, then the auto_pause bits on this port are being
13735 * advertised and autoneg pause results are being interpreted.
13736 * # When the auto_mode is not set to none and this
13737 * flag is set to 0, the pause is forced as indicated in
13738 * force_pause, and also advertised as auto_pause bits, but
13739 * the autoneg results are not interpreted since the pause
13740 * configuration is being forced.
13741 * # When the auto_mode is set to none and this flag is set to
13742 * 1, auto_pause bits should be ignored and should be set to 0.
13744 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13747 * Current setting for auto_link_speed. This field is only
13748 * valid when auto_mode is set to "one_speed" or "one_or_below".
13750 uint16_t auto_link_speed;
13751 /* 100Mb link speed */
13752 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13753 /* 1Gb link speed */
13754 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13755 /* 2Gb link speed */
13756 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13757 /* 25Gb link speed */
13758 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13759 /* 10Gb link speed */
13760 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13761 /* 20Mb link speed */
13762 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13763 /* 25Gb link speed */
13764 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13765 /* 40Gb link speed */
13766 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13767 /* 50Gb link speed */
13768 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13769 /* 100Gb link speed */
13770 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13771 /* 200Gb link speed */
13772 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13773 /* 10Mb link speed */
13774 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
13776 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
13777 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
13779 * Current setting for auto_link_speed_mask that is used to
13780 * advertise speeds during autonegotiation.
13781 * This field is only valid when auto_mode is set to "mask".
13782 * The speeds specified in this field shall be a subset of
13783 * supported speeds on this port.
13785 uint16_t auto_link_speed_mask;
13786 /* 100Mb link speed (Half-duplex) */
13787 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13789 /* 100Mb link speed (Full-duplex) */
13790 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
13792 /* 1Gb link speed (Half-duplex) */
13793 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13795 /* 1Gb link speed (Full-duplex) */
13796 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
13798 /* 2Gb link speed */
13799 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
13801 /* 25Gb link speed */
13802 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13804 /* 10Gb link speed */
13805 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
13807 /* 20Gb link speed */
13808 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
13810 /* 25Gb link speed */
13811 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
13813 /* 40Gb link speed */
13814 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
13816 /* 50Gb link speed */
13817 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
13819 /* 100Gb link speed */
13820 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
13822 /* 10Mb link speed (Half-duplex) */
13823 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13825 /* 10Mb link speed (Full-duplex) */
13826 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
13828 /* 200Gb link speed */
13829 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
13831 /* Current setting for wirespeed. */
13833 /* Wirespeed feature is disabled. */
13834 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
13835 /* Wirespeed feature is enabled. */
13836 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
13837 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
13838 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
13839 /* Current setting for loopback. */
13841 /* No loopback is selected. Normal operation. */
13842 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13844 * The HW will be configured with local loopback such that
13845 * host data is sent back to the host without modification.
13847 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13849 * The HW will be configured with remote loopback such that
13850 * port logic will send packets back out the transmitter that
13853 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13855 * The HW will be configured with external loopback such that
13856 * host data is sent on the trasmitter and based on the external
13857 * loopback connection the data will be received without modification.
13859 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
13860 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
13861 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
13863 * Current setting of forced pause.
13864 * When the pause configuration is not being forced, then
13865 * this value shall be set to 0.
13867 uint8_t force_pause;
13869 * When this bit is '1', Generation of tx pause messages
13870 * is supported. Disabled otherwise.
13872 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13874 * When this bit is '1', Reception of rx pause messages
13875 * is supported. Disabled otherwise.
13877 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13879 * This value indicates the current status of the optics module on
13882 uint8_t module_status;
13883 /* Module is inserted and accepted */
13884 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
13886 /* Module is rejected and transmit side Laser is disabled. */
13887 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
13889 /* Module mismatch warning. */
13890 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
13892 /* Module is rejected and powered down. */
13893 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
13895 /* Module is not inserted. */
13896 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
13898 /* Module status is not applicable. */
13899 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
13901 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
13902 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
13903 /* Current setting for preemphasis. */
13904 uint32_t preemphasis;
13905 /* This field represents the major version of the PHY. */
13907 /* This field represents the minor version of the PHY. */
13909 /* This field represents the build version of the PHY. */
13911 /* This value represents a PHY type. */
13914 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
13917 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
13919 /* BASE-KR4 (Deprecated) */
13920 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
13923 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
13926 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
13928 /* BASE-KR2 (Deprecated) */
13929 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
13932 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
13935 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
13938 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
13940 /* EEE capable BASE-T */
13941 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
13943 /* SGMII connected external PHY */
13944 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
13946 /* 25G_BASECR_CA_L */
13947 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
13949 /* 25G_BASECR_CA_S */
13950 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
13952 /* 25G_BASECR_CA_N */
13953 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
13956 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
13959 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
13962 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
13965 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
13968 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
13970 /* 100G_BASESR10 */
13971 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
13974 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
13977 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
13980 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
13983 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
13985 /* 40G_ACTIVE_CABLE */
13986 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
13989 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
13992 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
13995 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
13998 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
14001 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
14004 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
14007 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
14009 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
14010 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
14011 /* This value represents a media type. */
14012 uint8_t media_type;
14014 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
14016 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
14017 /* Direct Attached Copper */
14018 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
14020 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
14021 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
14022 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
14023 /* This value represents a transceiver type. */
14024 uint8_t xcvr_pkg_type;
14025 /* PHY and MAC are in the same package */
14026 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
14028 /* PHY and MAC are in different packages */
14029 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
14031 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
14032 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
14033 uint8_t eee_config_phy_addr;
14034 /* This field represents PHY address. */
14035 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
14037 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
14039 * This field represents flags related to EEE configuration.
14040 * These EEE configuration flags are valid only when the
14041 * auto_mode is not set to none (in other words autonegotiation
14044 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
14046 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
14048 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
14049 * Speeds for autoneg with EEE mode enabled
14050 * are based on eee_link_speed_mask.
14052 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
14055 * This flag is valid only when eee_enabled is set to 1.
14057 * # If eee_enabled is set to 0, then EEE mode is disabled
14058 * and this flag shall be ignored.
14059 * # If eee_enabled is set to 1 and this flag is set to 1,
14060 * then Energy Efficient Ethernet (EEE) mode is enabled
14062 * # If eee_enabled is set to 1 and this flag is set to 0,
14063 * then Energy Efficient Ethernet (EEE) mode is enabled
14064 * but is currently not in use.
14066 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
14069 * This flag is valid only when eee_enabled is set to 1.
14071 * # If eee_enabled is set to 0, then EEE mode is disabled
14072 * and this flag shall be ignored.
14073 * # If eee_enabled is set to 1 and this flag is set to 1,
14074 * then Energy Efficient Ethernet (EEE) mode is enabled
14075 * and TX LPI is enabled.
14076 * # If eee_enabled is set to 1 and this flag is set to 0,
14077 * then Energy Efficient Ethernet (EEE) mode is enabled
14078 * but TX LPI is disabled.
14080 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
14083 * When set to 1, the parallel detection is used to determine
14084 * the speed of the link partner.
14086 * Parallel detection is used when a autonegotiation capable
14087 * device is connected to a link parter that is not capable
14088 * of autonegotiation.
14090 uint8_t parallel_detect;
14092 * When set to 1, the parallel detection is used to determine
14093 * the speed of the link partner.
14095 * Parallel detection is used when a autonegotiation capable
14096 * device is connected to a link parter that is not capable
14097 * of autonegotiation.
14099 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
14101 * The advertised speeds for the port by the link partner.
14102 * Each advertised speed will be set to '1'.
14104 uint16_t link_partner_adv_speeds;
14105 /* 100Mb link speed (Half-duplex) */
14106 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
14108 /* 100Mb link speed (Full-duplex) */
14109 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
14111 /* 1Gb link speed (Half-duplex) */
14112 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
14114 /* 1Gb link speed (Full-duplex) */
14115 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
14117 /* 2Gb link speed */
14118 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
14120 /* 25Gb link speed */
14121 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
14123 /* 10Gb link speed */
14124 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
14126 /* 20Gb link speed */
14127 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
14129 /* 25Gb link speed */
14130 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
14132 /* 40Gb link speed */
14133 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
14135 /* 50Gb link speed */
14136 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
14138 /* 100Gb link speed */
14139 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
14141 /* 10Mb link speed (Half-duplex) */
14142 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
14144 /* 10Mb link speed (Full-duplex) */
14145 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
14148 * The advertised autoneg for the port by the link partner.
14149 * This field is deprecated and should be set to 0.
14151 uint8_t link_partner_adv_auto_mode;
14152 /* Disable autoneg or autoneg disabled. No speeds are selected. */
14153 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
14155 /* Select all possible speeds for autoneg mode. */
14156 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
14159 * Select only the auto_link_speed speed for autoneg mode. This mode has
14160 * been DEPRECATED. An HWRM client should not use this mode.
14162 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
14165 * Select the auto_link_speed or any speed below that speed for autoneg.
14166 * This mode has been DEPRECATED. An HWRM client should not use this mode.
14168 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
14171 * Select the speeds based on the corresponding link speed mask value
14172 * that is provided.
14174 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
14176 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
14177 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
14178 /* The advertised pause settings on the port by the link partner. */
14179 uint8_t link_partner_adv_pause;
14181 * When this bit is '1', Generation of tx pause messages
14182 * is supported. Disabled otherwise.
14184 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
14187 * When this bit is '1', Reception of rx pause messages
14188 * is supported. Disabled otherwise.
14190 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
14193 * Current setting for link speed mask that is used to
14194 * advertise speeds during autonegotiation when EEE is enabled.
14195 * This field is valid only when eee_enabled flags is set to 1.
14196 * The speeds specified in this field shall be a subset of
14197 * speeds specified in auto_link_speed_mask.
14199 uint16_t adv_eee_link_speed_mask;
14201 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14203 /* 100Mb link speed (Full-duplex) */
14204 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
14207 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14209 /* 1Gb link speed (Full-duplex) */
14210 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
14213 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14216 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14218 /* 10Gb link speed */
14219 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
14222 * Current setting for link speed mask that is advertised by
14223 * the link partner when EEE is enabled.
14224 * This field is valid only when eee_enabled flags is set to 1.
14226 uint16_t link_partner_adv_eee_link_speed_mask;
14228 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14230 /* 100Mb link speed (Full-duplex) */
14231 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
14234 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14236 /* 1Gb link speed (Full-duplex) */
14237 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
14240 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14243 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14245 /* 10Gb link speed */
14246 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
14248 uint32_t xcvr_identifier_type_tx_lpi_timer;
14250 * Current setting of TX LPI timer in microseconds.
14251 * This field is valid only when_eee_enabled flag is set to 1
14252 * and tx_lpi_enabled is set to 1.
14254 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
14256 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
14257 /* This value represents transceiver identifier type. */
14258 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
14259 UINT32_C(0xff000000)
14260 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
14262 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
14263 (UINT32_C(0x0) << 24)
14264 /* SFP/SFP+/SFP28 */
14265 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
14266 (UINT32_C(0x3) << 24)
14268 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
14269 (UINT32_C(0xc) << 24)
14271 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
14272 (UINT32_C(0xd) << 24)
14274 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
14275 (UINT32_C(0x11) << 24)
14276 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
14277 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
14279 * This value represents the current configuration of
14280 * Forward Error Correction (FEC) on the port.
14284 * When set to 1, then FEC is not supported on this port. If this flag
14285 * is set to 1, then all other FEC configuration flags shall be ignored.
14286 * When set to 0, then FEC is supported as indicated by other
14287 * configuration flags.
14288 * If no cable is attached and the HWRM does not yet know the FEC
14289 * capability, then the HWRM shall set this flag to 1 when reporting
14292 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
14295 * When set to 1, then FEC autonegotiation is supported on this port.
14296 * When set to 0, then FEC autonegotiation is not supported on this port.
14298 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
14301 * When set to 1, then FEC autonegotiation is enabled on this port.
14302 * When set to 0, then FEC autonegotiation is disabled if supported.
14303 * This flag should be ignored if FEC autonegotiation is not supported on this port.
14305 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
14308 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
14309 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
14311 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
14314 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
14315 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
14316 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
14318 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
14321 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
14322 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
14324 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
14327 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
14328 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
14329 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
14331 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
14334 * This value is indicates the duplex of the current
14335 * connection state.
14337 uint8_t duplex_state;
14338 /* Half Duplex connection. */
14339 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
14340 /* Full duplex connection. */
14341 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
14342 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
14343 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
14344 /* Option flags fields. */
14345 uint8_t option_flags;
14346 /* When this bit is '1', Media auto detect is enabled. */
14347 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
14350 * Up to 16 bytes of null padded ASCII string representing
14352 * If the string is set to null, then the vendor name is not
14355 char phy_vendor_name[16];
14357 * Up to 16 bytes of null padded ASCII string that
14358 * identifies vendor specific part number of the PHY.
14359 * If the string is set to null, then the vendor specific
14360 * part number is not available.
14362 char phy_vendor_partnumber[16];
14363 uint8_t unused_2[7];
14365 * This field is used in Output records to indicate that the output
14366 * is completely written to RAM. This field should be read as '1'
14367 * to indicate that the output has been completely written.
14368 * When writing a command completion or response to an internal processor,
14369 * the order of writes has to be such that this field is written last.
14372 } __attribute__((packed));
14374 /*********************
14375 * hwrm_port_mac_cfg *
14376 *********************/
14379 /* hwrm_port_mac_cfg_input (size:384b/48B) */
14380 struct hwrm_port_mac_cfg_input {
14381 /* The HWRM command request type. */
14384 * The completion ring to send the completion event on. This should
14385 * be the NQ ID returned from the `nq_alloc` HWRM command.
14387 uint16_t cmpl_ring;
14389 * The sequence ID is used by the driver for tracking multiple
14390 * commands. This ID is treated as opaque data by the firmware and
14391 * the value is returned in the `hwrm_resp_hdr` upon completion.
14395 * The target ID of the command:
14396 * * 0x0-0xFFF8 - The function ID
14397 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14398 * * 0xFFFD - Reserved for user-space HWRM interface
14401 uint16_t target_id;
14403 * A physical address pointer pointing to a host buffer that the
14404 * command's response data will be written. This can be either a host
14405 * physical address (HPA) or a guest physical address (GPA) and must
14406 * point to a physically contiguous block of memory.
14408 uint64_t resp_addr;
14410 * In this field, there are a number of CoS mappings related flags
14411 * that are used to configure CoS mappings and their corresponding
14412 * priorities in the hardware.
14413 * For the priorities of CoS mappings, the HWRM uses the following
14414 * priority order (high to low) by default:
14417 * # tunnel_vlan_pri
14420 * A subset of CoS mappings can be enabled.
14421 * If a priority is not specified for an enabled CoS mapping, the
14422 * priority will be assigned in the above order for the enabled CoS
14423 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
14424 * enabled and their priorities are not specified, the following
14425 * priority order (high to low) will be used by the HWRM:
14430 * vlan_pri CoS mapping together with default CoS with lower priority
14431 * are enabled by default by the HWRM.
14435 * When this bit is '1', this command will configure
14436 * the MAC to match the current link state of the PHY.
14437 * If the link is not established on the PHY, then this
14438 * bit has no effect.
14440 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
14443 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14444 * is requested to be enabled.
14446 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14449 * When this bit is set to '1', tunnel VLAN PRI field to
14450 * CoS mapping is requested to be enabled.
14452 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14455 * When this bit is set to '1', the IP DSCP to CoS mapping is
14456 * requested to be enabled.
14458 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
14461 * When this bit is '1', the HWRM is requested to
14462 * enable timestamp capture capability on the receive side
14465 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14468 * When this bit is '1', the HWRM is requested to
14469 * disable timestamp capture capability on the receive side
14472 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
14475 * When this bit is '1', the HWRM is requested to
14476 * enable timestamp capture capability on the transmit side
14479 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14482 * When this bit is '1', the HWRM is requested to
14483 * disable timestamp capture capability on the transmit side
14486 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
14489 * When this bit is '1', the Out-Of-Box WoL is requested to
14490 * be enabled on this port.
14492 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
14495 * When this bit is '1', the the Out-Of-Box WoL is requested to
14496 * be disabled on this port.
14498 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
14501 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14502 * is requested to be disabled.
14504 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
14507 * When this bit is set to '1', tunnel VLAN PRI field to
14508 * CoS mapping is requested to be disabled.
14510 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
14513 * When this bit is set to '1', the IP DSCP to CoS mapping is
14514 * requested to be disabled.
14516 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
14519 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
14520 * bit is set, then the device uses one step Tx timestamping.
14521 * This bit is temporary and used for experimental purposes.
14523 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
14527 * This bit must be '1' for the ipg field to be
14530 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
14533 * This bit must be '1' for the lpbk field to be
14536 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
14539 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
14542 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
14545 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
14548 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
14551 * This bit must be '1' for the dscp2cos_map_pri field to be
14554 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
14557 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
14560 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
14563 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
14566 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
14569 * This bit must be '1' for the cos_field_cfg field to be
14572 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
14575 * This bit must be '1' for the ptp_freq_adj_ppb field to be
14578 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
14580 /* Port ID of port that is to be configured. */
14583 * This value is used to configure the minimum IPG that will
14584 * be sent between packets by this port.
14587 /* This value controls the loopback setting for the MAC. */
14589 /* No loopback is selected. Normal operation. */
14590 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
14592 * The HW will be configured with local loopback such that
14593 * host data is sent back to the host without modification.
14595 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
14597 * The HW will be configured with remote loopback such that
14598 * port logic will send packets back out the transmitter that
14601 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
14602 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
14603 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
14605 * This value controls the priority setting of VLAN PRI to CoS
14606 * mapping based on VLAN Tags of inner packet headers of
14607 * tunneled packets or packet headers of non-tunneled packets.
14609 * # Each XXX_pri variable shall have a unique priority value
14610 * when it is being specified.
14611 * # When comparing priorities of mappings, higher value
14612 * indicates higher priority.
14613 * For example, a value of 0-3 is returned where 0 is being
14614 * the lowest priority and 3 is being the highest priority.
14616 uint8_t vlan_pri2cos_map_pri;
14617 /* Reserved field. */
14620 * This value controls the priority setting of VLAN PRI to CoS
14621 * mapping based on VLAN Tags of tunneled header.
14622 * This mapping only applies when tunneled headers
14625 * # Each XXX_pri variable shall have a unique priority value
14626 * when it is being specified.
14627 * # When comparing priorities of mappings, higher value
14628 * indicates higher priority.
14629 * For example, a value of 0-3 is returned where 0 is being
14630 * the lowest priority and 3 is being the highest priority.
14632 uint8_t tunnel_pri2cos_map_pri;
14634 * This value controls the priority setting of IP DSCP to CoS
14635 * mapping based on inner IP header of tunneled packets or
14636 * IP header of non-tunneled packets.
14638 * # Each XXX_pri variable shall have a unique priority value
14639 * when it is being specified.
14640 * # When comparing priorities of mappings, higher value
14641 * indicates higher priority.
14642 * For example, a value of 0-3 is returned where 0 is being
14643 * the lowest priority and 3 is being the highest priority.
14645 uint8_t dscp2pri_map_pri;
14647 * This is a 16-bit bit mask that is used to request a
14648 * specific configuration of time stamp capture of PTP messages
14649 * on the receive side of this port.
14650 * This field shall be ignored if the ptp_rx_ts_capture_enable
14651 * flag is not set in this command.
14652 * Otherwise, if bit 'i' is set, then the HWRM is being
14653 * requested to configure the receive side of the port to
14654 * capture the time stamp of every received PTP message
14655 * with messageType field value set to i.
14657 uint16_t rx_ts_capture_ptp_msg_type;
14659 * This is a 16-bit bit mask that is used to request a
14660 * specific configuration of time stamp capture of PTP messages
14661 * on the transmit side of this port.
14662 * This field shall be ignored if the ptp_tx_ts_capture_enable
14663 * flag is not set in this command.
14664 * Otherwise, if bit 'i' is set, then the HWRM is being
14665 * requested to configure the transmit sied of the port to
14666 * capture the time stamp of every transmitted PTP message
14667 * with messageType field value set to i.
14669 uint16_t tx_ts_capture_ptp_msg_type;
14670 /* Configuration of CoS fields. */
14671 uint8_t cos_field_cfg;
14673 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
14676 * This field is used to specify selection of VLAN PRI value
14677 * based on whether one or two VLAN Tags are present in
14678 * the inner packet headers of tunneled packets or
14679 * non-tunneled packets.
14680 * This field is valid only if inner VLAN PRI to CoS mapping
14682 * If VLAN PRI to CoS mapping is not enabled, then this
14683 * field shall be ignored.
14685 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
14687 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
14690 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14691 * present in the inner packet headers
14693 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
14694 (UINT32_C(0x0) << 1)
14696 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14697 * present in the inner packet headers.
14698 * No VLAN PRI shall be selected for this configuration
14699 * if only one VLAN Tag is present in the inner
14702 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
14703 (UINT32_C(0x1) << 1)
14705 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14706 * are present in the inner packet headers
14708 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
14709 (UINT32_C(0x2) << 1)
14711 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
14712 (UINT32_C(0x3) << 1)
14713 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
14714 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
14716 * This field is used to specify selection of tunnel VLAN
14717 * PRI value based on whether one or two VLAN Tags are
14718 * present in tunnel headers.
14719 * This field is valid only if tunnel VLAN PRI to CoS mapping
14721 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
14722 * field shall be ignored.
14724 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
14726 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
14729 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14730 * present in the tunnel packet headers
14732 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
14733 (UINT32_C(0x0) << 3)
14735 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14736 * present in the tunnel packet headers.
14737 * No tunnel VLAN PRI shall be selected for this
14738 * configuration if only one VLAN Tag is present in
14739 * the tunnel packet headers.
14741 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
14742 (UINT32_C(0x1) << 3)
14744 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14745 * are present in the tunnel packet headers
14747 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
14748 (UINT32_C(0x2) << 3)
14750 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
14751 (UINT32_C(0x3) << 3)
14752 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
14753 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
14755 * This field shall be used to provide default CoS value
14756 * that has been configured on this port.
14757 * This field is valid only if default CoS mapping
14759 * If default CoS mapping is not enabled, then this
14760 * field shall be ignored.
14762 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
14764 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
14766 uint8_t unused_0[3];
14768 * This signed field specifies by how much to adjust the frequency
14769 * of sync timer updates (measured in parts per billion).
14771 int32_t ptp_freq_adj_ppb;
14772 uint8_t unused_1[4];
14773 } __attribute__((packed));
14775 /* hwrm_port_mac_cfg_output (size:128b/16B) */
14776 struct hwrm_port_mac_cfg_output {
14777 /* The specific error status for the command. */
14778 uint16_t error_code;
14779 /* The HWRM command request type. */
14781 /* The sequence ID from the original command. */
14783 /* The length of the response data in number of bytes. */
14786 * This is the configured maximum length of Ethernet packet
14787 * payload that is allowed to be received on the port.
14788 * This value does not include the number of bytes used by
14789 * Ethernet header and trailer (CRC).
14793 * This is the configured maximum length of Ethernet packet
14794 * payload that is allowed to be transmitted on the port.
14795 * This value does not include the number of bytes used by
14796 * Ethernet header and trailer (CRC).
14799 /* Current configuration of the IPG value. */
14801 /* Current value of the loopback value. */
14803 /* No loopback is selected. Normal operation. */
14804 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14806 * The HW will be configured with local loopback such that
14807 * host data is sent back to the host without modification.
14809 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14811 * The HW will be configured with remote loopback such that
14812 * port logic will send packets back out the transmitter that
14815 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14816 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
14817 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
14820 * This field is used in Output records to indicate that the output
14821 * is completely written to RAM. This field should be read as '1'
14822 * to indicate that the output has been completely written.
14823 * When writing a command completion or response to an internal processor,
14824 * the order of writes has to be such that this field is written last.
14827 } __attribute__((packed));
14829 /**********************
14830 * hwrm_port_mac_qcfg *
14831 **********************/
14834 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
14835 struct hwrm_port_mac_qcfg_input {
14836 /* The HWRM command request type. */
14839 * The completion ring to send the completion event on. This should
14840 * be the NQ ID returned from the `nq_alloc` HWRM command.
14842 uint16_t cmpl_ring;
14844 * The sequence ID is used by the driver for tracking multiple
14845 * commands. This ID is treated as opaque data by the firmware and
14846 * the value is returned in the `hwrm_resp_hdr` upon completion.
14850 * The target ID of the command:
14851 * * 0x0-0xFFF8 - The function ID
14852 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14853 * * 0xFFFD - Reserved for user-space HWRM interface
14856 uint16_t target_id;
14858 * A physical address pointer pointing to a host buffer that the
14859 * command's response data will be written. This can be either a host
14860 * physical address (HPA) or a guest physical address (GPA) and must
14861 * point to a physically contiguous block of memory.
14863 uint64_t resp_addr;
14864 /* Port ID of port that is to be configured. */
14866 uint8_t unused_0[6];
14867 } __attribute__((packed));
14869 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
14870 struct hwrm_port_mac_qcfg_output {
14871 /* The specific error status for the command. */
14872 uint16_t error_code;
14873 /* The HWRM command request type. */
14875 /* The sequence ID from the original command. */
14877 /* The length of the response data in number of bytes. */
14880 * This is the configured maximum length of Ethernet packet
14881 * payload that is allowed to be received on the port.
14882 * This value does not include the number of bytes used by the
14883 * Ethernet header and trailer (CRC).
14887 * This is the configured maximum length of Ethernet packet
14888 * payload that is allowed to be transmitted on the port.
14889 * This value does not include the number of bytes used by the
14890 * Ethernet header and trailer (CRC).
14894 * The minimum IPG that will
14895 * be sent between packets by this port.
14898 /* The loopback setting for the MAC. */
14900 /* No loopback is selected. Normal operation. */
14901 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14903 * The HW will be configured with local loopback such that
14904 * host data is sent back to the host without modification.
14906 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14908 * The HW will be configured with remote loopback such that
14909 * port logic will send packets back out the transmitter that
14912 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14913 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
14914 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
14916 * Priority setting for VLAN PRI to CoS mapping.
14917 * # Each XXX_pri variable shall have a unique priority value
14918 * when it is being used.
14919 * # When comparing priorities of mappings, higher value
14920 * indicates higher priority.
14921 * For example, a value of 0-3 is returned where 0 is being
14922 * the lowest priority and 3 is being the highest priority.
14923 * # If the correspoding CoS mapping is not enabled, then this
14924 * field should be ignored.
14925 * # This value indicates the normalized priority value retained
14928 uint8_t vlan_pri2cos_map_pri;
14930 * In this field, a number of CoS mappings related flags
14931 * are used to indicate configured CoS mappings.
14935 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14938 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14941 * When this bit is set to '1', tunnel VLAN PRI field to
14942 * CoS mapping is enabled.
14944 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14947 * When this bit is set to '1', the IP DSCP to CoS mapping is
14950 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
14953 * When this bit is '1', the Out-Of-Box WoL is enabled on this
14956 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
14958 /* When this bit is '1', PTP is enabled for RX on this port. */
14959 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14961 /* When this bit is '1', PTP is enabled for TX on this port. */
14962 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14965 * Priority setting for tunnel VLAN PRI to CoS mapping.
14966 * # Each XXX_pri variable shall have a unique priority value
14967 * when it is being used.
14968 * # When comparing priorities of mappings, higher value
14969 * indicates higher priority.
14970 * For example, a value of 0-3 is returned where 0 is being
14971 * the lowest priority and 3 is being the highest priority.
14972 * # If the correspoding CoS mapping is not enabled, then this
14973 * field should be ignored.
14974 * # This value indicates the normalized priority value retained
14977 uint8_t tunnel_pri2cos_map_pri;
14979 * Priority setting for DSCP to PRI mapping.
14980 * # Each XXX_pri variable shall have a unique priority value
14981 * when it is being used.
14982 * # When comparing priorities of mappings, higher value
14983 * indicates higher priority.
14984 * For example, a value of 0-3 is returned where 0 is being
14985 * the lowest priority and 3 is being the highest priority.
14986 * # If the correspoding CoS mapping is not enabled, then this
14987 * field should be ignored.
14988 * # This value indicates the normalized priority value retained
14991 uint8_t dscp2pri_map_pri;
14993 * This is a 16-bit bit mask that represents the
14994 * current configuration of time stamp capture of PTP messages
14995 * on the receive side of this port.
14996 * If bit 'i' is set, then the receive side of the port
14997 * is configured to capture the time stamp of every
14998 * received PTP message with messageType field value set
15000 * If all bits are set to 0 (i.e. field value set 0),
15001 * then the receive side of the port is not configured
15002 * to capture timestamp for PTP messages.
15003 * If all bits are set to 1, then the receive side of the
15004 * port is configured to capture timestamp for all PTP
15007 uint16_t rx_ts_capture_ptp_msg_type;
15009 * This is a 16-bit bit mask that represents the
15010 * current configuration of time stamp capture of PTP messages
15011 * on the transmit side of this port.
15012 * If bit 'i' is set, then the transmit side of the port
15013 * is configured to capture the time stamp of every
15014 * received PTP message with messageType field value set
15016 * If all bits are set to 0 (i.e. field value set 0),
15017 * then the transmit side of the port is not configured
15018 * to capture timestamp for PTP messages.
15019 * If all bits are set to 1, then the transmit side of the
15020 * port is configured to capture timestamp for all PTP
15023 uint16_t tx_ts_capture_ptp_msg_type;
15024 /* Configuration of CoS fields. */
15025 uint8_t cos_field_cfg;
15027 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
15030 * This field is used for selecting VLAN PRI value
15031 * based on whether one or two VLAN Tags are present in
15032 * the inner packet headers of tunneled packets or
15033 * non-tunneled packets.
15035 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
15037 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
15040 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15041 * present in the inner packet headers
15043 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
15044 (UINT32_C(0x0) << 1)
15046 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15047 * present in the inner packet headers.
15048 * No VLAN PRI is selected for this configuration
15049 * if only one VLAN Tag is present in the inner
15052 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
15053 (UINT32_C(0x1) << 1)
15055 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15056 * are present in the inner packet headers
15058 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
15059 (UINT32_C(0x2) << 1)
15061 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
15062 (UINT32_C(0x3) << 1)
15063 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
15064 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
15066 * This field is used for selecting tunnel VLAN PRI value
15067 * based on whether one or two VLAN Tags are present in
15068 * the tunnel headers of tunneled packets. This selection
15069 * does not apply to non-tunneled packets.
15071 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
15073 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
15076 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15077 * present in the tunnel packet headers
15079 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
15080 (UINT32_C(0x0) << 3)
15082 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15083 * present in the tunnel packet headers.
15084 * No VLAN PRI is selected for this configuration
15085 * if only one VLAN Tag is present in the tunnel
15088 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
15089 (UINT32_C(0x1) << 3)
15091 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15092 * are present in the tunnel packet headers
15094 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
15095 (UINT32_C(0x2) << 3)
15097 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
15098 (UINT32_C(0x3) << 3)
15099 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
15100 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
15102 * This field is used to provide default CoS value that
15103 * has been configured on this port.
15105 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
15107 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
15110 * This field is used in Output records to indicate that the output
15111 * is completely written to RAM. This field should be read as '1'
15112 * to indicate that the output has been completely written.
15113 * When writing a command completion or response to an internal processor,
15114 * the order of writes has to be such that this field is written last.
15117 } __attribute__((packed));
15119 /**************************
15120 * hwrm_port_mac_ptp_qcfg *
15121 **************************/
15124 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
15125 struct hwrm_port_mac_ptp_qcfg_input {
15126 /* The HWRM command request type. */
15129 * The completion ring to send the completion event on. This should
15130 * be the NQ ID returned from the `nq_alloc` HWRM command.
15132 uint16_t cmpl_ring;
15134 * The sequence ID is used by the driver for tracking multiple
15135 * commands. This ID is treated as opaque data by the firmware and
15136 * the value is returned in the `hwrm_resp_hdr` upon completion.
15140 * The target ID of the command:
15141 * * 0x0-0xFFF8 - The function ID
15142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15143 * * 0xFFFD - Reserved for user-space HWRM interface
15146 uint16_t target_id;
15148 * A physical address pointer pointing to a host buffer that the
15149 * command's response data will be written. This can be either a host
15150 * physical address (HPA) or a guest physical address (GPA) and must
15151 * point to a physically contiguous block of memory.
15153 uint64_t resp_addr;
15154 /* Port ID of port that is being queried. */
15156 uint8_t unused_0[6];
15157 } __attribute__((packed));
15159 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
15160 struct hwrm_port_mac_ptp_qcfg_output {
15161 /* The specific error status for the command. */
15162 uint16_t error_code;
15163 /* The HWRM command request type. */
15165 /* The sequence ID from the original command. */
15167 /* The length of the response data in number of bytes. */
15170 * In this field, a number of PTP related flags
15171 * are used to indicate configured PTP capabilities.
15175 * When this bit is set to '1', the PTP related registers are
15176 * directly accessible by the host.
15178 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
15181 * When this bit is set to '1', the PTP information is accessible
15182 * via HWRM commands.
15184 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
15187 * When this bit is set to '1', the device supports one-step
15190 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
15192 uint8_t unused_0[3];
15193 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
15194 uint32_t rx_ts_reg_off_lower;
15195 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
15196 uint32_t rx_ts_reg_off_upper;
15197 /* Offset of the PTP register for the sequence ID for RX. */
15198 uint32_t rx_ts_reg_off_seq_id;
15199 /* Offset of the first PTP source ID for RX. */
15200 uint32_t rx_ts_reg_off_src_id_0;
15201 /* Offset of the second PTP source ID for RX. */
15202 uint32_t rx_ts_reg_off_src_id_1;
15203 /* Offset of the third PTP source ID for RX. */
15204 uint32_t rx_ts_reg_off_src_id_2;
15205 /* Offset of the domain ID for RX. */
15206 uint32_t rx_ts_reg_off_domain_id;
15207 /* Offset of the PTP FIFO register for RX. */
15208 uint32_t rx_ts_reg_off_fifo;
15209 /* Offset of the PTP advance FIFO register for RX. */
15210 uint32_t rx_ts_reg_off_fifo_adv;
15211 /* PTP timestamp granularity for RX. */
15212 uint32_t rx_ts_reg_off_granularity;
15213 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
15214 uint32_t tx_ts_reg_off_lower;
15215 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
15216 uint32_t tx_ts_reg_off_upper;
15217 /* Offset of the PTP register for the sequence ID for TX. */
15218 uint32_t tx_ts_reg_off_seq_id;
15219 /* Offset of the PTP FIFO register for TX. */
15220 uint32_t tx_ts_reg_off_fifo;
15221 /* PTP timestamp granularity for TX. */
15222 uint32_t tx_ts_reg_off_granularity;
15223 uint8_t unused_1[7];
15225 * This field is used in Output records to indicate that the output
15226 * is completely written to RAM. This field should be read as '1'
15227 * to indicate that the output has been completely written.
15228 * When writing a command completion or response to an internal processor,
15229 * the order of writes has to be such that this field is written last.
15232 } __attribute__((packed));
15234 /* Port Tx Statistics Formats */
15235 /* tx_port_stats (size:3264b/408B) */
15236 struct tx_port_stats {
15237 /* Total Number of 64 Bytes frames transmitted */
15238 uint64_t tx_64b_frames;
15239 /* Total Number of 65-127 Bytes frames transmitted */
15240 uint64_t tx_65b_127b_frames;
15241 /* Total Number of 128-255 Bytes frames transmitted */
15242 uint64_t tx_128b_255b_frames;
15243 /* Total Number of 256-511 Bytes frames transmitted */
15244 uint64_t tx_256b_511b_frames;
15245 /* Total Number of 512-1023 Bytes frames transmitted */
15246 uint64_t tx_512b_1023b_frames;
15247 /* Total Number of 1024-1518 Bytes frames transmitted */
15248 uint64_t tx_1024b_1518b_frames;
15250 * Total Number of each good VLAN (exludes FCS errors)
15251 * frame transmitted which is 1519 to 1522 bytes in length
15252 * inclusive (excluding framing bits but including FCS bytes).
15254 uint64_t tx_good_vlan_frames;
15255 /* Total Number of 1519-2047 Bytes frames transmitted */
15256 uint64_t tx_1519b_2047b_frames;
15257 /* Total Number of 2048-4095 Bytes frames transmitted */
15258 uint64_t tx_2048b_4095b_frames;
15259 /* Total Number of 4096-9216 Bytes frames transmitted */
15260 uint64_t tx_4096b_9216b_frames;
15261 /* Total Number of 9217-16383 Bytes frames transmitted */
15262 uint64_t tx_9217b_16383b_frames;
15263 /* Total Number of good frames transmitted */
15264 uint64_t tx_good_frames;
15265 /* Total Number of frames transmitted */
15266 uint64_t tx_total_frames;
15267 /* Total number of unicast frames transmitted */
15268 uint64_t tx_ucast_frames;
15269 /* Total number of multicast frames transmitted */
15270 uint64_t tx_mcast_frames;
15271 /* Total number of broadcast frames transmitted */
15272 uint64_t tx_bcast_frames;
15273 /* Total number of PAUSE control frames transmitted */
15274 uint64_t tx_pause_frames;
15276 * Total number of PFC/per-priority PAUSE
15277 * control frames transmitted
15279 uint64_t tx_pfc_frames;
15280 /* Total number of jabber frames transmitted */
15281 uint64_t tx_jabber_frames;
15282 /* Total number of frames transmitted with FCS error */
15283 uint64_t tx_fcs_err_frames;
15284 /* Total number of control frames transmitted */
15285 uint64_t tx_control_frames;
15286 /* Total number of over-sized frames transmitted */
15287 uint64_t tx_oversz_frames;
15288 /* Total number of frames with single deferral */
15289 uint64_t tx_single_dfrl_frames;
15290 /* Total number of frames with multiple deferrals */
15291 uint64_t tx_multi_dfrl_frames;
15292 /* Total number of frames with single collision */
15293 uint64_t tx_single_coll_frames;
15294 /* Total number of frames with multiple collisions */
15295 uint64_t tx_multi_coll_frames;
15296 /* Total number of frames with late collisions */
15297 uint64_t tx_late_coll_frames;
15298 /* Total number of frames with excessive collisions */
15299 uint64_t tx_excessive_coll_frames;
15300 /* Total number of fragmented frames transmitted */
15301 uint64_t tx_frag_frames;
15302 /* Total number of transmit errors */
15304 /* Total number of single VLAN tagged frames transmitted */
15305 uint64_t tx_tagged_frames;
15306 /* Total number of double VLAN tagged frames transmitted */
15307 uint64_t tx_dbl_tagged_frames;
15308 /* Total number of runt frames transmitted */
15309 uint64_t tx_runt_frames;
15310 /* Total number of TX FIFO under runs */
15311 uint64_t tx_fifo_underruns;
15313 * Total number of PFC frames with PFC enabled bit for
15314 * Pri 0 transmitted
15316 uint64_t tx_pfc_ena_frames_pri0;
15318 * Total number of PFC frames with PFC enabled bit for
15319 * Pri 1 transmitted
15321 uint64_t tx_pfc_ena_frames_pri1;
15323 * Total number of PFC frames with PFC enabled bit for
15324 * Pri 2 transmitted
15326 uint64_t tx_pfc_ena_frames_pri2;
15328 * Total number of PFC frames with PFC enabled bit for
15329 * Pri 3 transmitted
15331 uint64_t tx_pfc_ena_frames_pri3;
15333 * Total number of PFC frames with PFC enabled bit for
15334 * Pri 4 transmitted
15336 uint64_t tx_pfc_ena_frames_pri4;
15338 * Total number of PFC frames with PFC enabled bit for
15339 * Pri 5 transmitted
15341 uint64_t tx_pfc_ena_frames_pri5;
15343 * Total number of PFC frames with PFC enabled bit for
15344 * Pri 6 transmitted
15346 uint64_t tx_pfc_ena_frames_pri6;
15348 * Total number of PFC frames with PFC enabled bit for
15349 * Pri 7 transmitted
15351 uint64_t tx_pfc_ena_frames_pri7;
15352 /* Total number of EEE LPI Events on TX */
15353 uint64_t tx_eee_lpi_events;
15354 /* EEE LPI Duration Counter on TX */
15355 uint64_t tx_eee_lpi_duration;
15357 * Total number of Link Level Flow Control (LLFC) messages
15360 uint64_t tx_llfc_logical_msgs;
15361 /* Total number of HCFC messages transmitted */
15362 uint64_t tx_hcfc_msgs;
15363 /* Total number of TX collisions */
15364 uint64_t tx_total_collisions;
15365 /* Total number of transmitted bytes */
15367 /* Total number of end-to-end HOL frames */
15368 uint64_t tx_xthol_frames;
15369 /* Total Tx Drops per Port reported by STATS block */
15370 uint64_t tx_stat_discard;
15371 /* Total Tx Error Drops per Port reported by STATS block */
15372 uint64_t tx_stat_error;
15373 } __attribute__((packed));
15375 /* Port Rx Statistics Formats */
15376 /* rx_port_stats (size:4224b/528B) */
15377 struct rx_port_stats {
15378 /* Total Number of 64 Bytes frames received */
15379 uint64_t rx_64b_frames;
15380 /* Total Number of 65-127 Bytes frames received */
15381 uint64_t rx_65b_127b_frames;
15382 /* Total Number of 128-255 Bytes frames received */
15383 uint64_t rx_128b_255b_frames;
15384 /* Total Number of 256-511 Bytes frames received */
15385 uint64_t rx_256b_511b_frames;
15386 /* Total Number of 512-1023 Bytes frames received */
15387 uint64_t rx_512b_1023b_frames;
15388 /* Total Number of 1024-1518 Bytes frames received */
15389 uint64_t rx_1024b_1518b_frames;
15391 * Total Number of each good VLAN (exludes FCS errors)
15392 * frame received which is 1519 to 1522 bytes in length
15393 * inclusive (excluding framing bits but including FCS bytes).
15395 uint64_t rx_good_vlan_frames;
15396 /* Total Number of 1519-2047 Bytes frames received */
15397 uint64_t rx_1519b_2047b_frames;
15398 /* Total Number of 2048-4095 Bytes frames received */
15399 uint64_t rx_2048b_4095b_frames;
15400 /* Total Number of 4096-9216 Bytes frames received */
15401 uint64_t rx_4096b_9216b_frames;
15402 /* Total Number of 9217-16383 Bytes frames received */
15403 uint64_t rx_9217b_16383b_frames;
15404 /* Total number of frames received */
15405 uint64_t rx_total_frames;
15406 /* Total number of unicast frames received */
15407 uint64_t rx_ucast_frames;
15408 /* Total number of multicast frames received */
15409 uint64_t rx_mcast_frames;
15410 /* Total number of broadcast frames received */
15411 uint64_t rx_bcast_frames;
15412 /* Total number of received frames with FCS error */
15413 uint64_t rx_fcs_err_frames;
15414 /* Total number of control frames received */
15415 uint64_t rx_ctrl_frames;
15416 /* Total number of PAUSE frames received */
15417 uint64_t rx_pause_frames;
15418 /* Total number of PFC frames received */
15419 uint64_t rx_pfc_frames;
15421 * Total number of frames received with an unsupported
15424 uint64_t rx_unsupported_opcode_frames;
15426 * Total number of frames received with an unsupported
15427 * DA for pause and PFC
15429 uint64_t rx_unsupported_da_pausepfc_frames;
15430 /* Total number of frames received with an unsupported SA */
15431 uint64_t rx_wrong_sa_frames;
15432 /* Total number of received packets with alignment error */
15433 uint64_t rx_align_err_frames;
15434 /* Total number of received frames with out-of-range length */
15435 uint64_t rx_oor_len_frames;
15436 /* Total number of received frames with error termination */
15437 uint64_t rx_code_err_frames;
15439 * Total number of received frames with a false carrier is
15440 * detected during idle, as defined by RX_ER samples active
15441 * and RXD is 0xE. The event is reported along with the
15442 * statistics generated on the next received frame. Only
15443 * one false carrier condition can be detected and logged
15446 * Carrier event, valid for 10M/100M speed modes only.
15448 uint64_t rx_false_carrier_frames;
15449 /* Total number of over-sized frames received */
15450 uint64_t rx_ovrsz_frames;
15451 /* Total number of jabber packets received */
15452 uint64_t rx_jbr_frames;
15453 /* Total number of received frames with MTU error */
15454 uint64_t rx_mtu_err_frames;
15455 /* Total number of received frames with CRC match */
15456 uint64_t rx_match_crc_frames;
15457 /* Total number of frames received promiscuously */
15458 uint64_t rx_promiscuous_frames;
15460 * Total number of received frames with one or two VLAN
15463 uint64_t rx_tagged_frames;
15464 /* Total number of received frames with two VLAN tags */
15465 uint64_t rx_double_tagged_frames;
15466 /* Total number of truncated frames received */
15467 uint64_t rx_trunc_frames;
15468 /* Total number of good frames (without errors) received */
15469 uint64_t rx_good_frames;
15471 * Total number of received PFC frames with transition from
15472 * XON to XOFF on Pri 0
15474 uint64_t rx_pfc_xon2xoff_frames_pri0;
15476 * Total number of received PFC frames with transition from
15477 * XON to XOFF on Pri 1
15479 uint64_t rx_pfc_xon2xoff_frames_pri1;
15481 * Total number of received PFC frames with transition from
15482 * XON to XOFF on Pri 2
15484 uint64_t rx_pfc_xon2xoff_frames_pri2;
15486 * Total number of received PFC frames with transition from
15487 * XON to XOFF on Pri 3
15489 uint64_t rx_pfc_xon2xoff_frames_pri3;
15491 * Total number of received PFC frames with transition from
15492 * XON to XOFF on Pri 4
15494 uint64_t rx_pfc_xon2xoff_frames_pri4;
15496 * Total number of received PFC frames with transition from
15497 * XON to XOFF on Pri 5
15499 uint64_t rx_pfc_xon2xoff_frames_pri5;
15501 * Total number of received PFC frames with transition from
15502 * XON to XOFF on Pri 6
15504 uint64_t rx_pfc_xon2xoff_frames_pri6;
15506 * Total number of received PFC frames with transition from
15507 * XON to XOFF on Pri 7
15509 uint64_t rx_pfc_xon2xoff_frames_pri7;
15511 * Total number of received PFC frames with PFC enabled
15514 uint64_t rx_pfc_ena_frames_pri0;
15516 * Total number of received PFC frames with PFC enabled
15519 uint64_t rx_pfc_ena_frames_pri1;
15521 * Total number of received PFC frames with PFC enabled
15524 uint64_t rx_pfc_ena_frames_pri2;
15526 * Total number of received PFC frames with PFC enabled
15529 uint64_t rx_pfc_ena_frames_pri3;
15531 * Total number of received PFC frames with PFC enabled
15534 uint64_t rx_pfc_ena_frames_pri4;
15536 * Total number of received PFC frames with PFC enabled
15539 uint64_t rx_pfc_ena_frames_pri5;
15541 * Total number of received PFC frames with PFC enabled
15544 uint64_t rx_pfc_ena_frames_pri6;
15546 * Total number of received PFC frames with PFC enabled
15549 uint64_t rx_pfc_ena_frames_pri7;
15550 /* Total Number of frames received with SCH CRC error */
15551 uint64_t rx_sch_crc_err_frames;
15552 /* Total Number of under-sized frames received */
15553 uint64_t rx_undrsz_frames;
15554 /* Total Number of fragmented frames received */
15555 uint64_t rx_frag_frames;
15556 /* Total number of RX EEE LPI Events */
15557 uint64_t rx_eee_lpi_events;
15558 /* EEE LPI Duration Counter on RX */
15559 uint64_t rx_eee_lpi_duration;
15561 * Total number of physical type Link Level Flow Control
15562 * (LLFC) messages received
15564 uint64_t rx_llfc_physical_msgs;
15566 * Total number of logical type Link Level Flow Control
15567 * (LLFC) messages received
15569 uint64_t rx_llfc_logical_msgs;
15571 * Total number of logical type Link Level Flow Control
15572 * (LLFC) messages received with CRC error
15574 uint64_t rx_llfc_msgs_with_crc_err;
15575 /* Total number of HCFC messages received */
15576 uint64_t rx_hcfc_msgs;
15577 /* Total number of HCFC messages received with CRC error */
15578 uint64_t rx_hcfc_msgs_with_crc_err;
15579 /* Total number of received bytes */
15581 /* Total number of bytes received in runt frames */
15582 uint64_t rx_runt_bytes;
15583 /* Total number of runt frames received */
15584 uint64_t rx_runt_frames;
15585 /* Total Rx Discards per Port reported by STATS block */
15586 uint64_t rx_stat_discard;
15587 uint64_t rx_stat_err;
15588 } __attribute__((packed));
15590 /********************
15591 * hwrm_port_qstats *
15592 ********************/
15595 /* hwrm_port_qstats_input (size:320b/40B) */
15596 struct hwrm_port_qstats_input {
15597 /* The HWRM command request type. */
15600 * The completion ring to send the completion event on. This should
15601 * be the NQ ID returned from the `nq_alloc` HWRM command.
15603 uint16_t cmpl_ring;
15605 * The sequence ID is used by the driver for tracking multiple
15606 * commands. This ID is treated as opaque data by the firmware and
15607 * the value is returned in the `hwrm_resp_hdr` upon completion.
15611 * The target ID of the command:
15612 * * 0x0-0xFFF8 - The function ID
15613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15614 * * 0xFFFD - Reserved for user-space HWRM interface
15617 uint16_t target_id;
15619 * A physical address pointer pointing to a host buffer that the
15620 * command's response data will be written. This can be either a host
15621 * physical address (HPA) or a guest physical address (GPA) and must
15622 * point to a physically contiguous block of memory.
15624 uint64_t resp_addr;
15625 /* Port ID of port that is being queried. */
15627 uint8_t unused_0[6];
15629 * This is the host address where
15630 * Tx port statistics will be stored
15632 uint64_t tx_stat_host_addr;
15634 * This is the host address where
15635 * Rx port statistics will be stored
15637 uint64_t rx_stat_host_addr;
15638 } __attribute__((packed));
15640 /* hwrm_port_qstats_output (size:128b/16B) */
15641 struct hwrm_port_qstats_output {
15642 /* The specific error status for the command. */
15643 uint16_t error_code;
15644 /* The HWRM command request type. */
15646 /* The sequence ID from the original command. */
15648 /* The length of the response data in number of bytes. */
15650 /* The size of TX port statistics block in bytes. */
15651 uint16_t tx_stat_size;
15652 /* The size of RX port statistics block in bytes. */
15653 uint16_t rx_stat_size;
15654 uint8_t unused_0[3];
15656 * This field is used in Output records to indicate that the output
15657 * is completely written to RAM. This field should be read as '1'
15658 * to indicate that the output has been completely written.
15659 * When writing a command completion or response to an internal processor,
15660 * the order of writes has to be such that this field is written last.
15663 } __attribute__((packed));
15665 /* Port Tx Statistics extended Formats */
15666 /* tx_port_stats_ext (size:2048b/256B) */
15667 struct tx_port_stats_ext {
15668 /* Total number of tx bytes count on cos queue 0 */
15669 uint64_t tx_bytes_cos0;
15670 /* Total number of tx bytes count on cos queue 1 */
15671 uint64_t tx_bytes_cos1;
15672 /* Total number of tx bytes count on cos queue 2 */
15673 uint64_t tx_bytes_cos2;
15674 /* Total number of tx bytes count on cos queue 3 */
15675 uint64_t tx_bytes_cos3;
15676 /* Total number of tx bytes count on cos queue 4 */
15677 uint64_t tx_bytes_cos4;
15678 /* Total number of tx bytes count on cos queue 5 */
15679 uint64_t tx_bytes_cos5;
15680 /* Total number of tx bytes count on cos queue 6 */
15681 uint64_t tx_bytes_cos6;
15682 /* Total number of tx bytes count on cos queue 7 */
15683 uint64_t tx_bytes_cos7;
15684 /* Total number of tx packets count on cos queue 0 */
15685 uint64_t tx_packets_cos0;
15686 /* Total number of tx packets count on cos queue 1 */
15687 uint64_t tx_packets_cos1;
15688 /* Total number of tx packets count on cos queue 2 */
15689 uint64_t tx_packets_cos2;
15690 /* Total number of tx packets count on cos queue 3 */
15691 uint64_t tx_packets_cos3;
15692 /* Total number of tx packets count on cos queue 4 */
15693 uint64_t tx_packets_cos4;
15694 /* Total number of tx packets count on cos queue 5 */
15695 uint64_t tx_packets_cos5;
15696 /* Total number of tx packets count on cos queue 6 */
15697 uint64_t tx_packets_cos6;
15698 /* Total number of tx packets count on cos queue 7 */
15699 uint64_t tx_packets_cos7;
15700 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15701 uint64_t pfc_pri0_tx_duration_us;
15702 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15703 uint64_t pfc_pri0_tx_transitions;
15704 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15705 uint64_t pfc_pri1_tx_duration_us;
15706 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15707 uint64_t pfc_pri1_tx_transitions;
15708 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15709 uint64_t pfc_pri2_tx_duration_us;
15710 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15711 uint64_t pfc_pri2_tx_transitions;
15712 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15713 uint64_t pfc_pri3_tx_duration_us;
15714 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15715 uint64_t pfc_pri3_tx_transitions;
15716 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15717 uint64_t pfc_pri4_tx_duration_us;
15718 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15719 uint64_t pfc_pri4_tx_transitions;
15720 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15721 uint64_t pfc_pri5_tx_duration_us;
15722 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15723 uint64_t pfc_pri5_tx_transitions;
15724 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15725 uint64_t pfc_pri6_tx_duration_us;
15726 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15727 uint64_t pfc_pri6_tx_transitions;
15728 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15729 uint64_t pfc_pri7_tx_duration_us;
15730 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15731 uint64_t pfc_pri7_tx_transitions;
15732 } __attribute__((packed));
15734 /* Port Rx Statistics extended Formats */
15735 /* rx_port_stats_ext (size:3648b/456B) */
15736 struct rx_port_stats_ext {
15737 /* Number of times link state changed to down */
15738 uint64_t link_down_events;
15739 /* Number of times the idle rings with pause bit are found */
15740 uint64_t continuous_pause_events;
15741 /* Number of times the active rings pause bit resumed back */
15742 uint64_t resume_pause_events;
15743 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
15744 uint64_t continuous_roce_pause_events;
15745 /* Number of times, the ROCE cos queue PFC is enabled back */
15746 uint64_t resume_roce_pause_events;
15747 /* Total number of rx bytes count on cos queue 0 */
15748 uint64_t rx_bytes_cos0;
15749 /* Total number of rx bytes count on cos queue 1 */
15750 uint64_t rx_bytes_cos1;
15751 /* Total number of rx bytes count on cos queue 2 */
15752 uint64_t rx_bytes_cos2;
15753 /* Total number of rx bytes count on cos queue 3 */
15754 uint64_t rx_bytes_cos3;
15755 /* Total number of rx bytes count on cos queue 4 */
15756 uint64_t rx_bytes_cos4;
15757 /* Total number of rx bytes count on cos queue 5 */
15758 uint64_t rx_bytes_cos5;
15759 /* Total number of rx bytes count on cos queue 6 */
15760 uint64_t rx_bytes_cos6;
15761 /* Total number of rx bytes count on cos queue 7 */
15762 uint64_t rx_bytes_cos7;
15763 /* Total number of rx packets count on cos queue 0 */
15764 uint64_t rx_packets_cos0;
15765 /* Total number of rx packets count on cos queue 1 */
15766 uint64_t rx_packets_cos1;
15767 /* Total number of rx packets count on cos queue 2 */
15768 uint64_t rx_packets_cos2;
15769 /* Total number of rx packets count on cos queue 3 */
15770 uint64_t rx_packets_cos3;
15771 /* Total number of rx packets count on cos queue 4 */
15772 uint64_t rx_packets_cos4;
15773 /* Total number of rx packets count on cos queue 5 */
15774 uint64_t rx_packets_cos5;
15775 /* Total number of rx packets count on cos queue 6 */
15776 uint64_t rx_packets_cos6;
15777 /* Total number of rx packets count on cos queue 7 */
15778 uint64_t rx_packets_cos7;
15779 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15780 uint64_t pfc_pri0_rx_duration_us;
15781 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15782 uint64_t pfc_pri0_rx_transitions;
15783 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15784 uint64_t pfc_pri1_rx_duration_us;
15785 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15786 uint64_t pfc_pri1_rx_transitions;
15787 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15788 uint64_t pfc_pri2_rx_duration_us;
15789 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15790 uint64_t pfc_pri2_rx_transitions;
15791 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15792 uint64_t pfc_pri3_rx_duration_us;
15793 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15794 uint64_t pfc_pri3_rx_transitions;
15795 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15796 uint64_t pfc_pri4_rx_duration_us;
15797 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15798 uint64_t pfc_pri4_rx_transitions;
15799 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15800 uint64_t pfc_pri5_rx_duration_us;
15801 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15802 uint64_t pfc_pri5_rx_transitions;
15803 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15804 uint64_t pfc_pri6_rx_duration_us;
15805 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15806 uint64_t pfc_pri6_rx_transitions;
15807 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15808 uint64_t pfc_pri7_rx_duration_us;
15809 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15810 uint64_t pfc_pri7_rx_transitions;
15811 /* Total number of received bits */
15813 /* The number of events where the port receive buffer was over 85% full */
15814 uint64_t rx_buffer_passed_threshold;
15816 * The number of symbol errors that wasn't corrected by FEC correction
15819 uint64_t rx_pcs_symbol_err;
15820 /* The number of corrected bits on the port according to active FEC */
15821 uint64_t rx_corrected_bits;
15822 /* Total number of rx discard bytes count on cos queue 0 */
15823 uint64_t rx_discard_bytes_cos0;
15824 /* Total number of rx discard bytes count on cos queue 1 */
15825 uint64_t rx_discard_bytes_cos1;
15826 /* Total number of rx discard bytes count on cos queue 2 */
15827 uint64_t rx_discard_bytes_cos2;
15828 /* Total number of rx discard bytes count on cos queue 3 */
15829 uint64_t rx_discard_bytes_cos3;
15830 /* Total number of rx discard bytes count on cos queue 4 */
15831 uint64_t rx_discard_bytes_cos4;
15832 /* Total number of rx discard bytes count on cos queue 5 */
15833 uint64_t rx_discard_bytes_cos5;
15834 /* Total number of rx discard bytes count on cos queue 6 */
15835 uint64_t rx_discard_bytes_cos6;
15836 /* Total number of rx discard bytes count on cos queue 7 */
15837 uint64_t rx_discard_bytes_cos7;
15838 /* Total number of rx discard packets count on cos queue 0 */
15839 uint64_t rx_discard_packets_cos0;
15840 /* Total number of rx discard packets count on cos queue 1 */
15841 uint64_t rx_discard_packets_cos1;
15842 /* Total number of rx discard packets count on cos queue 2 */
15843 uint64_t rx_discard_packets_cos2;
15844 /* Total number of rx discard packets count on cos queue 3 */
15845 uint64_t rx_discard_packets_cos3;
15846 /* Total number of rx discard packets count on cos queue 4 */
15847 uint64_t rx_discard_packets_cos4;
15848 /* Total number of rx discard packets count on cos queue 5 */
15849 uint64_t rx_discard_packets_cos5;
15850 /* Total number of rx discard packets count on cos queue 6 */
15851 uint64_t rx_discard_packets_cos6;
15852 /* Total number of rx discard packets count on cos queue 7 */
15853 uint64_t rx_discard_packets_cos7;
15854 } __attribute__((packed));
15856 /************************
15857 * hwrm_port_qstats_ext *
15858 ************************/
15861 /* hwrm_port_qstats_ext_input (size:320b/40B) */
15862 struct hwrm_port_qstats_ext_input {
15863 /* The HWRM command request type. */
15866 * The completion ring to send the completion event on. This should
15867 * be the NQ ID returned from the `nq_alloc` HWRM command.
15869 uint16_t cmpl_ring;
15871 * The sequence ID is used by the driver for tracking multiple
15872 * commands. This ID is treated as opaque data by the firmware and
15873 * the value is returned in the `hwrm_resp_hdr` upon completion.
15877 * The target ID of the command:
15878 * * 0x0-0xFFF8 - The function ID
15879 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15880 * * 0xFFFD - Reserved for user-space HWRM interface
15883 uint16_t target_id;
15885 * A physical address pointer pointing to a host buffer that the
15886 * command's response data will be written. This can be either a host
15887 * physical address (HPA) or a guest physical address (GPA) and must
15888 * point to a physically contiguous block of memory.
15890 uint64_t resp_addr;
15891 /* Port ID of port that is being queried. */
15894 * The size of TX port extended
15895 * statistics block in bytes.
15897 uint16_t tx_stat_size;
15899 * The size of RX port extended
15900 * statistics block in bytes
15902 uint16_t rx_stat_size;
15903 uint8_t unused_0[2];
15905 * This is the host address where
15906 * Tx port statistics will be stored
15908 uint64_t tx_stat_host_addr;
15910 * This is the host address where
15911 * Rx port statistics will be stored
15913 uint64_t rx_stat_host_addr;
15914 } __attribute__((packed));
15916 /* hwrm_port_qstats_ext_output (size:128b/16B) */
15917 struct hwrm_port_qstats_ext_output {
15918 /* The specific error status for the command. */
15919 uint16_t error_code;
15920 /* The HWRM command request type. */
15922 /* The sequence ID from the original command. */
15924 /* The length of the response data in number of bytes. */
15926 /* The size of TX port statistics block in bytes. */
15927 uint16_t tx_stat_size;
15928 /* The size of RX port statistics block in bytes. */
15929 uint16_t rx_stat_size;
15930 /* Total number of active cos queues available. */
15931 uint16_t total_active_cos_queues;
15934 * If set to 1, then this field indicates that clear
15935 * roce specific counters is supported.
15937 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
15940 * This field is used in Output records to indicate that the output
15941 * is completely written to RAM. This field should be read as '1'
15942 * to indicate that the output has been completely written.
15943 * When writing a command completion or response to an internal processor,
15944 * the order of writes has to be such that this field is written last.
15947 } __attribute__((packed));
15949 /*************************
15950 * hwrm_port_lpbk_qstats *
15951 *************************/
15954 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
15955 struct hwrm_port_lpbk_qstats_input {
15956 /* The HWRM command request type. */
15959 * The completion ring to send the completion event on. This should
15960 * be the NQ ID returned from the `nq_alloc` HWRM command.
15962 uint16_t cmpl_ring;
15964 * The sequence ID is used by the driver for tracking multiple
15965 * commands. This ID is treated as opaque data by the firmware and
15966 * the value is returned in the `hwrm_resp_hdr` upon completion.
15970 * The target ID of the command:
15971 * * 0x0-0xFFF8 - The function ID
15972 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15973 * * 0xFFFD - Reserved for user-space HWRM interface
15976 uint16_t target_id;
15978 * A physical address pointer pointing to a host buffer that the
15979 * command's response data will be written. This can be either a host
15980 * physical address (HPA) or a guest physical address (GPA) and must
15981 * point to a physically contiguous block of memory.
15983 uint64_t resp_addr;
15984 } __attribute__((packed));
15986 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
15987 struct hwrm_port_lpbk_qstats_output {
15988 /* The specific error status for the command. */
15989 uint16_t error_code;
15990 /* The HWRM command request type. */
15992 /* The sequence ID from the original command. */
15994 /* The length of the response data in number of bytes. */
15996 /* Number of transmitted unicast frames */
15997 uint64_t lpbk_ucast_frames;
15998 /* Number of transmitted multicast frames */
15999 uint64_t lpbk_mcast_frames;
16000 /* Number of transmitted broadcast frames */
16001 uint64_t lpbk_bcast_frames;
16002 /* Number of transmitted bytes for unicast traffic */
16003 uint64_t lpbk_ucast_bytes;
16004 /* Number of transmitted bytes for multicast traffic */
16005 uint64_t lpbk_mcast_bytes;
16006 /* Number of transmitted bytes for broadcast traffic */
16007 uint64_t lpbk_bcast_bytes;
16008 /* Total Tx Drops for loopback traffic reported by STATS block */
16009 uint64_t tx_stat_discard;
16010 /* Total Tx Error Drops for loopback traffic reported by STATS block */
16011 uint64_t tx_stat_error;
16012 /* Total Rx Drops for loopback traffic reported by STATS block */
16013 uint64_t rx_stat_discard;
16014 /* Total Rx Error Drops for loopback traffic reported by STATS block */
16015 uint64_t rx_stat_error;
16016 uint8_t unused_0[7];
16018 * This field is used in Output records to indicate that the output
16019 * is completely written to RAM. This field should be read as '1'
16020 * to indicate that the output has been completely written.
16021 * When writing a command completion or response to an internal processor,
16022 * the order of writes has to be such that this field is written last.
16025 } __attribute__((packed));
16027 /***********************
16028 * hwrm_port_clr_stats *
16029 ***********************/
16032 /* hwrm_port_clr_stats_input (size:192b/24B) */
16033 struct hwrm_port_clr_stats_input {
16034 /* The HWRM command request type. */
16037 * The completion ring to send the completion event on. This should
16038 * be the NQ ID returned from the `nq_alloc` HWRM command.
16040 uint16_t cmpl_ring;
16042 * The sequence ID is used by the driver for tracking multiple
16043 * commands. This ID is treated as opaque data by the firmware and
16044 * the value is returned in the `hwrm_resp_hdr` upon completion.
16048 * The target ID of the command:
16049 * * 0x0-0xFFF8 - The function ID
16050 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16051 * * 0xFFFD - Reserved for user-space HWRM interface
16054 uint16_t target_id;
16056 * A physical address pointer pointing to a host buffer that the
16057 * command's response data will be written. This can be either a host
16058 * physical address (HPA) or a guest physical address (GPA) and must
16059 * point to a physically contiguous block of memory.
16061 uint64_t resp_addr;
16062 /* Port ID of port that is being queried. */
16066 * If set to 1, then this field indicates clear the following RoCE
16067 * specific counters.
16068 * RoCE associated TX/RX cos counters
16069 * CNP associated TX/RX cos counters
16070 * RoCE/CNP specific TX/RX flow counters
16071 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
16072 * This flag is honored only when RoCE is enabled on that port.
16074 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
16075 uint8_t unused_0[5];
16076 } __attribute__((packed));
16078 /* hwrm_port_clr_stats_output (size:128b/16B) */
16079 struct hwrm_port_clr_stats_output {
16080 /* The specific error status for the command. */
16081 uint16_t error_code;
16082 /* The HWRM command request type. */
16084 /* The sequence ID from the original command. */
16086 /* The length of the response data in number of bytes. */
16088 uint8_t unused_0[7];
16090 * This field is used in Output records to indicate that the output
16091 * is completely written to RAM. This field should be read as '1'
16092 * to indicate that the output has been completely written.
16093 * When writing a command completion or response to an internal processor,
16094 * the order of writes has to be such that this field is written last.
16097 } __attribute__((packed));
16099 /***********************
16100 * hwrm_port_phy_qcaps *
16101 ***********************/
16104 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
16105 struct hwrm_port_phy_qcaps_input {
16106 /* The HWRM command request type. */
16109 * The completion ring to send the completion event on. This should
16110 * be the NQ ID returned from the `nq_alloc` HWRM command.
16112 uint16_t cmpl_ring;
16114 * The sequence ID is used by the driver for tracking multiple
16115 * commands. This ID is treated as opaque data by the firmware and
16116 * the value is returned in the `hwrm_resp_hdr` upon completion.
16120 * The target ID of the command:
16121 * * 0x0-0xFFF8 - The function ID
16122 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16123 * * 0xFFFD - Reserved for user-space HWRM interface
16126 uint16_t target_id;
16128 * A physical address pointer pointing to a host buffer that the
16129 * command's response data will be written. This can be either a host
16130 * physical address (HPA) or a guest physical address (GPA) and must
16131 * point to a physically contiguous block of memory.
16133 uint64_t resp_addr;
16134 /* Port ID of port that is being queried. */
16136 uint8_t unused_0[6];
16137 } __attribute__((packed));
16139 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
16140 struct hwrm_port_phy_qcaps_output {
16141 /* The specific error status for the command. */
16142 uint16_t error_code;
16143 /* The HWRM command request type. */
16145 /* The sequence ID from the original command. */
16147 /* The length of the response data in number of bytes. */
16149 /* PHY capability flags */
16152 * If set to 1, then this field indicates that the
16153 * link is capable of supporting EEE.
16155 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
16158 * If set to 1, then this field indicates that the
16159 * PHY is capable of supporting external loopback.
16161 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
16164 * Reserved field. The HWRM shall set this field to 0.
16165 * An HWRM client shall ignore this field.
16167 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
16169 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
16170 /* Number of front panel ports for this device. */
16172 /* Not supported or unknown */
16173 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
16174 /* single port device */
16175 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
16176 /* 2-port device */
16177 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
16178 /* 3-port device */
16179 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
16180 /* 4-port device */
16181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
16182 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
16183 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
16185 * This is a bit mask to indicate what speeds are supported
16186 * as forced speeds on this link.
16187 * For each speed that can be forced on this link, the
16188 * corresponding mask bit shall be set to '1'.
16190 uint16_t supported_speeds_force_mode;
16191 /* 100Mb link speed (Half-duplex) */
16192 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
16194 /* 100Mb link speed (Full-duplex) */
16195 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
16197 /* 1Gb link speed (Half-duplex) */
16198 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
16200 /* 1Gb link speed (Full-duplex) */
16201 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
16203 /* 2Gb link speed */
16204 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
16206 /* 25Gb link speed */
16207 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
16209 /* 10Gb link speed */
16210 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
16212 /* 20Gb link speed */
16213 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
16215 /* 25Gb link speed */
16216 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
16218 /* 40Gb link speed */
16219 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
16221 /* 50Gb link speed */
16222 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
16224 /* 100Gb link speed */
16225 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
16227 /* 10Mb link speed (Half-duplex) */
16228 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
16230 /* 10Mb link speed (Full-duplex) */
16231 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
16233 /* 200Gb link speed */
16234 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
16237 * This is a bit mask to indicate what speeds are supported
16238 * for autonegotiation on this link.
16239 * For each speed that can be autonegotiated on this link, the
16240 * corresponding mask bit shall be set to '1'.
16242 uint16_t supported_speeds_auto_mode;
16243 /* 100Mb link speed (Half-duplex) */
16244 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
16246 /* 100Mb link speed (Full-duplex) */
16247 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
16249 /* 1Gb link speed (Half-duplex) */
16250 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
16252 /* 1Gb link speed (Full-duplex) */
16253 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
16255 /* 2Gb link speed */
16256 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
16258 /* 25Gb link speed */
16259 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
16261 /* 10Gb link speed */
16262 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
16264 /* 20Gb link speed */
16265 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
16267 /* 25Gb link speed */
16268 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
16270 /* 40Gb link speed */
16271 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
16273 /* 50Gb link speed */
16274 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
16276 /* 100Gb link speed */
16277 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
16279 /* 10Mb link speed (Half-duplex) */
16280 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
16282 /* 10Mb link speed (Full-duplex) */
16283 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
16285 /* 200Gb link speed */
16286 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
16289 * This is a bit mask to indicate what speeds are supported
16290 * for EEE on this link.
16291 * For each speed that can be autonegotiated when EEE is enabled
16292 * on this link, the corresponding mask bit shall be set to '1'.
16293 * This field is only valid when the eee_suppotred is set to '1'.
16295 uint16_t supported_speeds_eee_mode;
16297 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
16299 /* 100Mb link speed (Full-duplex) */
16300 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
16303 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
16305 /* 1Gb link speed (Full-duplex) */
16306 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
16309 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
16312 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
16314 /* 10Gb link speed */
16315 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
16317 uint32_t tx_lpi_timer_low;
16319 * The lowest value of TX LPI timer that can be set on this link
16320 * when EEE is enabled. This value is in microseconds.
16321 * This field is valid only when_eee_supported is set to '1'.
16323 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
16325 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
16327 * Reserved field. The HWRM shall set this field to 0.
16328 * An HWRM client shall ignore this field.
16330 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
16331 UINT32_C(0xff000000)
16332 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
16333 uint32_t valid_tx_lpi_timer_high;
16335 * The highest value of TX LPI timer that can be set on this link
16336 * when EEE is enabled. This value is in microseconds.
16337 * This field is valid only when_eee_supported is set to '1'.
16339 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
16341 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
16343 * This field is used in Output records to indicate that the output
16344 * is completely written to RAM. This field should be read as '1'
16345 * to indicate that the output has been completely written.
16346 * When writing a command completion or response to an internal processor,
16347 * the order of writes has to be such that this field is written last.
16349 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
16350 UINT32_C(0xff000000)
16351 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
16352 } __attribute__((packed));
16354 /****************************
16355 * hwrm_port_phy_mdio_write *
16356 ****************************/
16359 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
16360 struct hwrm_port_phy_mdio_write_input {
16361 /* The HWRM command request type. */
16364 * The completion ring to send the completion event on. This should
16365 * be the NQ ID returned from the `nq_alloc` HWRM command.
16367 uint16_t cmpl_ring;
16369 * The sequence ID is used by the driver for tracking multiple
16370 * commands. This ID is treated as opaque data by the firmware and
16371 * the value is returned in the `hwrm_resp_hdr` upon completion.
16375 * The target ID of the command:
16376 * * 0x0-0xFFF8 - The function ID
16377 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16378 * * 0xFFFD - Reserved for user-space HWRM interface
16381 uint16_t target_id;
16383 * A physical address pointer pointing to a host buffer that the
16384 * command's response data will be written. This can be either a host
16385 * physical address (HPA) or a guest physical address (GPA) and must
16386 * point to a physically contiguous block of memory.
16388 uint64_t resp_addr;
16389 /* Reserved for future use. */
16390 uint32_t unused_0[2];
16391 /* Port ID of port. */
16393 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16395 /* 8-bit device address. */
16397 /* 16-bit register address. */
16399 /* 16-bit register data. */
16402 * When this bit is set to 1 a Clause 45 mdio access is done.
16403 * when this bit is set to 0 a Clause 22 mdio access is done.
16407 uint8_t unused_1[7];
16408 } __attribute__((packed));
16410 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
16411 struct hwrm_port_phy_mdio_write_output {
16412 /* The specific error status for the command. */
16413 uint16_t error_code;
16414 /* The HWRM command request type. */
16416 /* The sequence ID from the original command. */
16418 /* The length of the response data in number of bytes. */
16420 uint8_t unused_0[7];
16422 * This field is used in Output records to indicate that the output
16423 * is completely written to RAM. This field should be read as '1'
16424 * to indicate that the output has been completely written.
16425 * When writing a command completion or response to an internal processor,
16426 * the order of writes has to be such that this field is written last.
16429 } __attribute__((packed));
16431 /***************************
16432 * hwrm_port_phy_mdio_read *
16433 ***************************/
16436 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
16437 struct hwrm_port_phy_mdio_read_input {
16438 /* The HWRM command request type. */
16441 * The completion ring to send the completion event on. This should
16442 * be the NQ ID returned from the `nq_alloc` HWRM command.
16444 uint16_t cmpl_ring;
16446 * The sequence ID is used by the driver for tracking multiple
16447 * commands. This ID is treated as opaque data by the firmware and
16448 * the value is returned in the `hwrm_resp_hdr` upon completion.
16452 * The target ID of the command:
16453 * * 0x0-0xFFF8 - The function ID
16454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16455 * * 0xFFFD - Reserved for user-space HWRM interface
16458 uint16_t target_id;
16460 * A physical address pointer pointing to a host buffer that the
16461 * command's response data will be written. This can be either a host
16462 * physical address (HPA) or a guest physical address (GPA) and must
16463 * point to a physically contiguous block of memory.
16465 uint64_t resp_addr;
16466 /* Reserved for future use. */
16467 uint32_t unused_0[2];
16468 /* Port ID of port. */
16470 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16472 /* 8-bit device address. */
16474 /* 16-bit register address. */
16477 * When this bit is set to 1 a Clause 45 mdio access is done.
16478 * when this bit is set to 0 a Clause 22 mdio access is done.
16483 } __attribute__((packed));
16485 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
16486 struct hwrm_port_phy_mdio_read_output {
16487 /* The specific error status for the command. */
16488 uint16_t error_code;
16489 /* The HWRM command request type. */
16491 /* The sequence ID from the original command. */
16493 /* The length of the response data in number of bytes. */
16495 /* 16-bit register data. */
16497 uint8_t unused_0[5];
16499 * This field is used in Output records to indicate that the output
16500 * is completely written to RAM. This field should be read as '1'
16501 * to indicate that the output has been completely written.
16502 * When writing a command completion or response to an internal processor,
16503 * the order of writes has to be such that this field is written last.
16506 } __attribute__((packed));
16508 /*********************
16509 * hwrm_port_led_cfg *
16510 *********************/
16513 /* hwrm_port_led_cfg_input (size:512b/64B) */
16514 struct hwrm_port_led_cfg_input {
16515 /* The HWRM command request type. */
16518 * The completion ring to send the completion event on. This should
16519 * be the NQ ID returned from the `nq_alloc` HWRM command.
16521 uint16_t cmpl_ring;
16523 * The sequence ID is used by the driver for tracking multiple
16524 * commands. This ID is treated as opaque data by the firmware and
16525 * the value is returned in the `hwrm_resp_hdr` upon completion.
16529 * The target ID of the command:
16530 * * 0x0-0xFFF8 - The function ID
16531 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16532 * * 0xFFFD - Reserved for user-space HWRM interface
16535 uint16_t target_id;
16537 * A physical address pointer pointing to a host buffer that the
16538 * command's response data will be written. This can be either a host
16539 * physical address (HPA) or a guest physical address (GPA) and must
16540 * point to a physically contiguous block of memory.
16542 uint64_t resp_addr;
16545 * This bit must be '1' for the led0_id field to be
16548 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
16551 * This bit must be '1' for the led0_state field to be
16554 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
16557 * This bit must be '1' for the led0_color field to be
16560 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
16563 * This bit must be '1' for the led0_blink_on field to be
16566 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
16569 * This bit must be '1' for the led0_blink_off field to be
16572 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
16575 * This bit must be '1' for the led0_group_id field to be
16578 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
16581 * This bit must be '1' for the led1_id field to be
16584 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
16587 * This bit must be '1' for the led1_state field to be
16590 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
16593 * This bit must be '1' for the led1_color field to be
16596 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
16599 * This bit must be '1' for the led1_blink_on field to be
16602 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
16605 * This bit must be '1' for the led1_blink_off field to be
16608 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
16611 * This bit must be '1' for the led1_group_id field to be
16614 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
16617 * This bit must be '1' for the led2_id field to be
16620 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
16623 * This bit must be '1' for the led2_state field to be
16626 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
16629 * This bit must be '1' for the led2_color field to be
16632 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
16635 * This bit must be '1' for the led2_blink_on field to be
16638 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
16641 * This bit must be '1' for the led2_blink_off field to be
16644 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
16647 * This bit must be '1' for the led2_group_id field to be
16650 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
16653 * This bit must be '1' for the led3_id field to be
16656 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
16659 * This bit must be '1' for the led3_state field to be
16662 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
16665 * This bit must be '1' for the led3_color field to be
16668 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
16671 * This bit must be '1' for the led3_blink_on field to be
16674 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
16677 * This bit must be '1' for the led3_blink_off field to be
16680 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
16683 * This bit must be '1' for the led3_group_id field to be
16686 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
16688 /* Port ID of port whose LEDs are configured. */
16691 * The number of LEDs that are being configured.
16692 * Up to 4 LEDs can be configured with this command.
16695 /* Reserved field. */
16697 /* An identifier for the LED #0. */
16699 /* The requested state of the LED #0. */
16700 uint8_t led0_state;
16701 /* Default state of the LED */
16702 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
16704 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
16706 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
16708 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
16709 /* Blink Alternately */
16710 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
16711 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
16712 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
16713 /* The requested color of LED #0. */
16714 uint8_t led0_color;
16716 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
16718 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
16720 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
16721 /* Green or Amber */
16722 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
16723 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
16724 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
16727 * If the LED #0 state is "blink" or "blinkalt", then
16728 * this field represents the requested time in milliseconds
16729 * to keep LED on between cycles.
16731 uint16_t led0_blink_on;
16733 * If the LED #0 state is "blink" or "blinkalt", then
16734 * this field represents the requested time in milliseconds
16735 * to keep LED off between cycles.
16737 uint16_t led0_blink_off;
16739 * An identifier for the group of LEDs that LED #0 belongs
16741 * If set to 0, then the LED #0 shall not be grouped and
16742 * shall be treated as an individual resource.
16743 * For all other non-zero values of this field, LED #0 shall
16744 * be grouped together with the LEDs with the same group ID
16747 uint8_t led0_group_id;
16748 /* Reserved field. */
16750 /* An identifier for the LED #1. */
16752 /* The requested state of the LED #1. */
16753 uint8_t led1_state;
16754 /* Default state of the LED */
16755 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
16757 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
16759 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
16761 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
16762 /* Blink Alternately */
16763 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
16764 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
16765 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
16766 /* The requested color of LED #1. */
16767 uint8_t led1_color;
16769 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
16771 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
16773 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
16774 /* Green or Amber */
16775 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
16776 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
16777 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
16780 * If the LED #1 state is "blink" or "blinkalt", then
16781 * this field represents the requested time in milliseconds
16782 * to keep LED on between cycles.
16784 uint16_t led1_blink_on;
16786 * If the LED #1 state is "blink" or "blinkalt", then
16787 * this field represents the requested time in milliseconds
16788 * to keep LED off between cycles.
16790 uint16_t led1_blink_off;
16792 * An identifier for the group of LEDs that LED #1 belongs
16794 * If set to 0, then the LED #1 shall not be grouped and
16795 * shall be treated as an individual resource.
16796 * For all other non-zero values of this field, LED #1 shall
16797 * be grouped together with the LEDs with the same group ID
16800 uint8_t led1_group_id;
16801 /* Reserved field. */
16803 /* An identifier for the LED #2. */
16805 /* The requested state of the LED #2. */
16806 uint8_t led2_state;
16807 /* Default state of the LED */
16808 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
16810 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
16812 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
16814 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
16815 /* Blink Alternately */
16816 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
16817 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
16818 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
16819 /* The requested color of LED #2. */
16820 uint8_t led2_color;
16822 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
16824 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
16826 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
16827 /* Green or Amber */
16828 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16829 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
16830 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
16833 * If the LED #2 state is "blink" or "blinkalt", then
16834 * this field represents the requested time in milliseconds
16835 * to keep LED on between cycles.
16837 uint16_t led2_blink_on;
16839 * If the LED #2 state is "blink" or "blinkalt", then
16840 * this field represents the requested time in milliseconds
16841 * to keep LED off between cycles.
16843 uint16_t led2_blink_off;
16845 * An identifier for the group of LEDs that LED #2 belongs
16847 * If set to 0, then the LED #2 shall not be grouped and
16848 * shall be treated as an individual resource.
16849 * For all other non-zero values of this field, LED #2 shall
16850 * be grouped together with the LEDs with the same group ID
16853 uint8_t led2_group_id;
16854 /* Reserved field. */
16856 /* An identifier for the LED #3. */
16858 /* The requested state of the LED #3. */
16859 uint8_t led3_state;
16860 /* Default state of the LED */
16861 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
16863 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
16865 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
16867 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
16868 /* Blink Alternately */
16869 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
16870 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
16871 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
16872 /* The requested color of LED #3. */
16873 uint8_t led3_color;
16875 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
16877 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
16879 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
16880 /* Green or Amber */
16881 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
16882 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
16883 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
16886 * If the LED #3 state is "blink" or "blinkalt", then
16887 * this field represents the requested time in milliseconds
16888 * to keep LED on between cycles.
16890 uint16_t led3_blink_on;
16892 * If the LED #3 state is "blink" or "blinkalt", then
16893 * this field represents the requested time in milliseconds
16894 * to keep LED off between cycles.
16896 uint16_t led3_blink_off;
16898 * An identifier for the group of LEDs that LED #3 belongs
16900 * If set to 0, then the LED #3 shall not be grouped and
16901 * shall be treated as an individual resource.
16902 * For all other non-zero values of this field, LED #3 shall
16903 * be grouped together with the LEDs with the same group ID
16906 uint8_t led3_group_id;
16907 /* Reserved field. */
16909 } __attribute__((packed));
16911 /* hwrm_port_led_cfg_output (size:128b/16B) */
16912 struct hwrm_port_led_cfg_output {
16913 /* The specific error status for the command. */
16914 uint16_t error_code;
16915 /* The HWRM command request type. */
16917 /* The sequence ID from the original command. */
16919 /* The length of the response data in number of bytes. */
16921 uint8_t unused_0[7];
16923 * This field is used in Output records to indicate that the output
16924 * is completely written to RAM. This field should be read as '1'
16925 * to indicate that the output has been completely written.
16926 * When writing a command completion or response to an internal processor,
16927 * the order of writes has to be such that this field is written last.
16930 } __attribute__((packed));
16932 /**********************
16933 * hwrm_port_led_qcfg *
16934 **********************/
16937 /* hwrm_port_led_qcfg_input (size:192b/24B) */
16938 struct hwrm_port_led_qcfg_input {
16939 /* The HWRM command request type. */
16942 * The completion ring to send the completion event on. This should
16943 * be the NQ ID returned from the `nq_alloc` HWRM command.
16945 uint16_t cmpl_ring;
16947 * The sequence ID is used by the driver for tracking multiple
16948 * commands. This ID is treated as opaque data by the firmware and
16949 * the value is returned in the `hwrm_resp_hdr` upon completion.
16953 * The target ID of the command:
16954 * * 0x0-0xFFF8 - The function ID
16955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16956 * * 0xFFFD - Reserved for user-space HWRM interface
16959 uint16_t target_id;
16961 * A physical address pointer pointing to a host buffer that the
16962 * command's response data will be written. This can be either a host
16963 * physical address (HPA) or a guest physical address (GPA) and must
16964 * point to a physically contiguous block of memory.
16966 uint64_t resp_addr;
16967 /* Port ID of port whose LED configuration is being queried. */
16969 uint8_t unused_0[6];
16970 } __attribute__((packed));
16972 /* hwrm_port_led_qcfg_output (size:448b/56B) */
16973 struct hwrm_port_led_qcfg_output {
16974 /* The specific error status for the command. */
16975 uint16_t error_code;
16976 /* The HWRM command request type. */
16978 /* The sequence ID from the original command. */
16980 /* The length of the response data in number of bytes. */
16983 * The number of LEDs that are configured on this port.
16984 * Up to 4 LEDs can be returned in the response.
16987 /* An identifier for the LED #0. */
16989 /* The type of LED #0. */
16992 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
16994 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
16996 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
16997 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
16998 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
16999 /* The current state of the LED #0. */
17000 uint8_t led0_state;
17001 /* Default state of the LED */
17002 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
17004 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
17006 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
17008 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
17009 /* Blink Alternately */
17010 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
17011 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
17012 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
17013 /* The color of LED #0. */
17014 uint8_t led0_color;
17016 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
17018 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
17020 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
17021 /* Green or Amber */
17022 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
17023 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
17024 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
17027 * If the LED #0 state is "blink" or "blinkalt", then
17028 * this field represents the requested time in milliseconds
17029 * to keep LED on between cycles.
17031 uint16_t led0_blink_on;
17033 * If the LED #0 state is "blink" or "blinkalt", then
17034 * this field represents the requested time in milliseconds
17035 * to keep LED off between cycles.
17037 uint16_t led0_blink_off;
17039 * An identifier for the group of LEDs that LED #0 belongs
17041 * If set to 0, then the LED #0 is not grouped.
17042 * For all other non-zero values of this field, LED #0 is
17043 * grouped together with the LEDs with the same group ID
17046 uint8_t led0_group_id;
17047 /* An identifier for the LED #1. */
17049 /* The type of LED #1. */
17052 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17054 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17056 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17057 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
17058 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
17059 /* The current state of the LED #1. */
17060 uint8_t led1_state;
17061 /* Default state of the LED */
17062 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
17064 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
17066 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
17068 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
17069 /* Blink Alternately */
17070 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
17071 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
17072 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
17073 /* The color of LED #1. */
17074 uint8_t led1_color;
17076 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
17078 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
17080 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
17081 /* Green or Amber */
17082 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
17083 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
17084 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
17087 * If the LED #1 state is "blink" or "blinkalt", then
17088 * this field represents the requested time in milliseconds
17089 * to keep LED on between cycles.
17091 uint16_t led1_blink_on;
17093 * If the LED #1 state is "blink" or "blinkalt", then
17094 * this field represents the requested time in milliseconds
17095 * to keep LED off between cycles.
17097 uint16_t led1_blink_off;
17099 * An identifier for the group of LEDs that LED #1 belongs
17101 * If set to 0, then the LED #1 is not grouped.
17102 * For all other non-zero values of this field, LED #1 is
17103 * grouped together with the LEDs with the same group ID
17106 uint8_t led1_group_id;
17107 /* An identifier for the LED #2. */
17109 /* The type of LED #2. */
17112 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17114 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17116 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17117 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
17118 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
17119 /* The current state of the LED #2. */
17120 uint8_t led2_state;
17121 /* Default state of the LED */
17122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
17124 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
17126 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
17128 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
17129 /* Blink Alternately */
17130 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
17131 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
17132 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
17133 /* The color of LED #2. */
17134 uint8_t led2_color;
17136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
17138 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
17140 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
17141 /* Green or Amber */
17142 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
17143 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
17144 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
17147 * If the LED #2 state is "blink" or "blinkalt", then
17148 * this field represents the requested time in milliseconds
17149 * to keep LED on between cycles.
17151 uint16_t led2_blink_on;
17153 * If the LED #2 state is "blink" or "blinkalt", then
17154 * this field represents the requested time in milliseconds
17155 * to keep LED off between cycles.
17157 uint16_t led2_blink_off;
17159 * An identifier for the group of LEDs that LED #2 belongs
17161 * If set to 0, then the LED #2 is not grouped.
17162 * For all other non-zero values of this field, LED #2 is
17163 * grouped together with the LEDs with the same group ID
17166 uint8_t led2_group_id;
17167 /* An identifier for the LED #3. */
17169 /* The type of LED #3. */
17172 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17174 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17176 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17177 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
17178 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
17179 /* The current state of the LED #3. */
17180 uint8_t led3_state;
17181 /* Default state of the LED */
17182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
17184 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
17186 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
17188 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
17189 /* Blink Alternately */
17190 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
17191 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
17192 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
17193 /* The color of LED #3. */
17194 uint8_t led3_color;
17196 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
17198 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
17200 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
17201 /* Green or Amber */
17202 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
17203 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
17204 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
17207 * If the LED #3 state is "blink" or "blinkalt", then
17208 * this field represents the requested time in milliseconds
17209 * to keep LED on between cycles.
17211 uint16_t led3_blink_on;
17213 * If the LED #3 state is "blink" or "blinkalt", then
17214 * this field represents the requested time in milliseconds
17215 * to keep LED off between cycles.
17217 uint16_t led3_blink_off;
17219 * An identifier for the group of LEDs that LED #3 belongs
17221 * If set to 0, then the LED #3 is not grouped.
17222 * For all other non-zero values of this field, LED #3 is
17223 * grouped together with the LEDs with the same group ID
17226 uint8_t led3_group_id;
17227 uint8_t unused_4[6];
17229 * This field is used in Output records to indicate that the output
17230 * is completely written to RAM. This field should be read as '1'
17231 * to indicate that the output has been completely written.
17232 * When writing a command completion or response to an internal processor,
17233 * the order of writes has to be such that this field is written last.
17236 } __attribute__((packed));
17238 /***********************
17239 * hwrm_port_led_qcaps *
17240 ***********************/
17243 /* hwrm_port_led_qcaps_input (size:192b/24B) */
17244 struct hwrm_port_led_qcaps_input {
17245 /* The HWRM command request type. */
17248 * The completion ring to send the completion event on. This should
17249 * be the NQ ID returned from the `nq_alloc` HWRM command.
17251 uint16_t cmpl_ring;
17253 * The sequence ID is used by the driver for tracking multiple
17254 * commands. This ID is treated as opaque data by the firmware and
17255 * the value is returned in the `hwrm_resp_hdr` upon completion.
17259 * The target ID of the command:
17260 * * 0x0-0xFFF8 - The function ID
17261 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17262 * * 0xFFFD - Reserved for user-space HWRM interface
17265 uint16_t target_id;
17267 * A physical address pointer pointing to a host buffer that the
17268 * command's response data will be written. This can be either a host
17269 * physical address (HPA) or a guest physical address (GPA) and must
17270 * point to a physically contiguous block of memory.
17272 uint64_t resp_addr;
17273 /* Port ID of port whose LED configuration is being queried. */
17275 uint8_t unused_0[6];
17276 } __attribute__((packed));
17278 /* hwrm_port_led_qcaps_output (size:384b/48B) */
17279 struct hwrm_port_led_qcaps_output {
17280 /* The specific error status for the command. */
17281 uint16_t error_code;
17282 /* The HWRM command request type. */
17284 /* The sequence ID from the original command. */
17286 /* The length of the response data in number of bytes. */
17289 * The number of LEDs that are configured on this port.
17290 * Up to 4 LEDs can be returned in the response.
17293 /* Reserved for future use. */
17295 /* An identifier for the LED #0. */
17297 /* The type of LED #0. */
17300 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
17302 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
17304 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
17305 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
17306 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
17308 * An identifier for the group of LEDs that LED #0 belongs
17310 * If set to 0, then the LED #0 cannot be grouped.
17311 * For all other non-zero values of this field, LED #0 is
17312 * grouped together with the LEDs with the same group ID
17315 uint8_t led0_group_id;
17317 /* The states supported by LED #0. */
17318 uint16_t led0_state_caps;
17320 * If set to 1, this LED is enabled.
17321 * If set to 0, this LED is disabled.
17323 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
17326 * If set to 1, off state is supported on this LED.
17327 * If set to 0, off state is not supported on this LED.
17329 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
17332 * If set to 1, on state is supported on this LED.
17333 * If set to 0, on state is not supported on this LED.
17335 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
17338 * If set to 1, blink state is supported on this LED.
17339 * If set to 0, blink state is not supported on this LED.
17341 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
17344 * If set to 1, blink_alt state is supported on this LED.
17345 * If set to 0, blink_alt state is not supported on this LED.
17347 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
17349 /* The colors supported by LED #0. */
17350 uint16_t led0_color_caps;
17352 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
17355 * If set to 1, Amber color is supported on this LED.
17356 * If set to 0, Amber color is not supported on this LED.
17358 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
17361 * If set to 1, Green color is supported on this LED.
17362 * If set to 0, Green color is not supported on this LED.
17364 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
17366 /* An identifier for the LED #1. */
17368 /* The type of LED #1. */
17371 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17373 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17375 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17376 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
17377 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
17379 * An identifier for the group of LEDs that LED #1 belongs
17381 * If set to 0, then the LED #0 cannot be grouped.
17382 * For all other non-zero values of this field, LED #0 is
17383 * grouped together with the LEDs with the same group ID
17386 uint8_t led1_group_id;
17388 /* The states supported by LED #1. */
17389 uint16_t led1_state_caps;
17391 * If set to 1, this LED is enabled.
17392 * If set to 0, this LED is disabled.
17394 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
17397 * If set to 1, off state is supported on this LED.
17398 * If set to 0, off state is not supported on this LED.
17400 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
17403 * If set to 1, on state is supported on this LED.
17404 * If set to 0, on state is not supported on this LED.
17406 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
17409 * If set to 1, blink state is supported on this LED.
17410 * If set to 0, blink state is not supported on this LED.
17412 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
17415 * If set to 1, blink_alt state is supported on this LED.
17416 * If set to 0, blink_alt state is not supported on this LED.
17418 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
17420 /* The colors supported by LED #1. */
17421 uint16_t led1_color_caps;
17423 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
17426 * If set to 1, Amber color is supported on this LED.
17427 * If set to 0, Amber color is not supported on this LED.
17429 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
17432 * If set to 1, Green color is supported on this LED.
17433 * If set to 0, Green color is not supported on this LED.
17435 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
17437 /* An identifier for the LED #2. */
17439 /* The type of LED #2. */
17442 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17444 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17446 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17447 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
17448 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
17450 * An identifier for the group of LEDs that LED #0 belongs
17452 * If set to 0, then the LED #0 cannot be grouped.
17453 * For all other non-zero values of this field, LED #0 is
17454 * grouped together with the LEDs with the same group ID
17457 uint8_t led2_group_id;
17459 /* The states supported by LED #2. */
17460 uint16_t led2_state_caps;
17462 * If set to 1, this LED is enabled.
17463 * If set to 0, this LED is disabled.
17465 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
17468 * If set to 1, off state is supported on this LED.
17469 * If set to 0, off state is not supported on this LED.
17471 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
17474 * If set to 1, on state is supported on this LED.
17475 * If set to 0, on state is not supported on this LED.
17477 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
17480 * If set to 1, blink state is supported on this LED.
17481 * If set to 0, blink state is not supported on this LED.
17483 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
17486 * If set to 1, blink_alt state is supported on this LED.
17487 * If set to 0, blink_alt state is not supported on this LED.
17489 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
17491 /* The colors supported by LED #2. */
17492 uint16_t led2_color_caps;
17494 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
17497 * If set to 1, Amber color is supported on this LED.
17498 * If set to 0, Amber color is not supported on this LED.
17500 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
17503 * If set to 1, Green color is supported on this LED.
17504 * If set to 0, Green color is not supported on this LED.
17506 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
17508 /* An identifier for the LED #3. */
17510 /* The type of LED #3. */
17513 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17515 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17517 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17518 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
17519 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
17521 * An identifier for the group of LEDs that LED #3 belongs
17523 * If set to 0, then the LED #0 cannot be grouped.
17524 * For all other non-zero values of this field, LED #0 is
17525 * grouped together with the LEDs with the same group ID
17528 uint8_t led3_group_id;
17530 /* The states supported by LED #3. */
17531 uint16_t led3_state_caps;
17533 * If set to 1, this LED is enabled.
17534 * If set to 0, this LED is disabled.
17536 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
17539 * If set to 1, off state is supported on this LED.
17540 * If set to 0, off state is not supported on this LED.
17542 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
17545 * If set to 1, on state is supported on this LED.
17546 * If set to 0, on state is not supported on this LED.
17548 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
17551 * If set to 1, blink state is supported on this LED.
17552 * If set to 0, blink state is not supported on this LED.
17554 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
17557 * If set to 1, blink_alt state is supported on this LED.
17558 * If set to 0, blink_alt state is not supported on this LED.
17560 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
17562 /* The colors supported by LED #3. */
17563 uint16_t led3_color_caps;
17565 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
17568 * If set to 1, Amber color is supported on this LED.
17569 * If set to 0, Amber color is not supported on this LED.
17571 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
17574 * If set to 1, Green color is supported on this LED.
17575 * If set to 0, Green color is not supported on this LED.
17577 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
17579 uint8_t unused_4[3];
17581 * This field is used in Output records to indicate that the output
17582 * is completely written to RAM. This field should be read as '1'
17583 * to indicate that the output has been completely written.
17584 * When writing a command completion or response to an internal processor,
17585 * the order of writes has to be such that this field is written last.
17588 } __attribute__((packed));
17590 /***********************
17591 * hwrm_port_prbs_test *
17592 ***********************/
17595 /* hwrm_port_prbs_test_input (size:384b/48B) */
17596 struct hwrm_port_prbs_test_input {
17597 /* The HWRM command request type. */
17600 * The completion ring to send the completion event on. This should
17601 * be the NQ ID returned from the `nq_alloc` HWRM command.
17603 uint16_t cmpl_ring;
17605 * The sequence ID is used by the driver for tracking multiple
17606 * commands. This ID is treated as opaque data by the firmware and
17607 * the value is returned in the `hwrm_resp_hdr` upon completion.
17611 * The target ID of the command:
17612 * * 0x0-0xFFF8 - The function ID
17613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17614 * * 0xFFFD - Reserved for user-space HWRM interface
17617 uint16_t target_id;
17619 * A physical address pointer pointing to a host buffer that the
17620 * command's response data will be written. This can be either a host
17621 * physical address (HPA) or a guest physical address (GPA) and must
17622 * point to a physically contiguous block of memory.
17624 uint64_t resp_addr;
17625 /* Host address data is to DMA'd to. */
17626 uint64_t resp_data_addr;
17628 * Size of the buffer pointed to by resp_data_addr. The firmware may
17629 * use this entire buffer or less than the entire buffer, but never more.
17634 /* Port ID of port where PRBS test to be run. */
17636 /* Polynomial selection for PRBS test. */
17639 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
17641 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
17643 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
17645 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
17647 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
17649 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
17651 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
17653 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
17654 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
17655 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
17657 * Configuration bits for PRBS test.
17658 * Use enable bit to start/stop test.
17659 * Use tx/rx lane map bits to run test on specific lanes,
17660 * if set to 0 test will be run on all lanes.
17662 uint16_t prbs_config;
17664 * Set 0 to stop test currently in progress
17665 * Set 1 to start test with configuration provided.
17667 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
17670 * If set to 1, tx_lane_map bitmap should have lane bits set.
17671 * If set to 0, test will be run on all lanes for this port.
17673 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
17676 * If set to 1, rx_lane_map bitmap should have lane bits set.
17677 * If set to 0, test will be run on all lanes for this port.
17679 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
17681 /* Duration in seconds to run the PRBS test. */
17684 * If tx_lane_map_valid is set to 1, this field is a bitmap
17685 * of tx lanes to run PRBS test. bit0 = lane0,
17686 * bit1 = lane1 ..bit31 = lane31
17688 uint32_t tx_lane_map;
17690 * If rx_lane_map_valid is set to 1, this field is a bitmap
17691 * of rx lanes to run PRBS test. bit0 = lane0,
17692 * bit1 = lane1 ..bit31 = lane31
17694 uint32_t rx_lane_map;
17695 } __attribute__((packed));
17697 /* hwrm_port_prbs_test_output (size:128b/16B) */
17698 struct hwrm_port_prbs_test_output {
17699 /* The specific error status for the command. */
17700 uint16_t error_code;
17701 /* The HWRM command request type. */
17703 /* The sequence ID from the original command. */
17705 /* The length of the response data in number of bytes. */
17707 /* Total length of stored data. */
17708 uint16_t total_data_len;
17710 uint8_t unused_1[3];
17712 * This field is used in Output records to indicate that the output
17713 * is completely written to RAM. This field should be read as '1'
17714 * to indicate that the output has been completely written.
17715 * When writing a command completion or response to an internal processor,
17716 * the order of writes has to be such that this field is written last.
17719 } __attribute__((packed));
17721 /***********************
17722 * hwrm_queue_qportcfg *
17723 ***********************/
17726 /* hwrm_queue_qportcfg_input (size:192b/24B) */
17727 struct hwrm_queue_qportcfg_input {
17728 /* The HWRM command request type. */
17731 * The completion ring to send the completion event on. This should
17732 * be the NQ ID returned from the `nq_alloc` HWRM command.
17734 uint16_t cmpl_ring;
17736 * The sequence ID is used by the driver for tracking multiple
17737 * commands. This ID is treated as opaque data by the firmware and
17738 * the value is returned in the `hwrm_resp_hdr` upon completion.
17742 * The target ID of the command:
17743 * * 0x0-0xFFF8 - The function ID
17744 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17745 * * 0xFFFD - Reserved for user-space HWRM interface
17748 uint16_t target_id;
17750 * A physical address pointer pointing to a host buffer that the
17751 * command's response data will be written. This can be either a host
17752 * physical address (HPA) or a guest physical address (GPA) and must
17753 * point to a physically contiguous block of memory.
17755 uint64_t resp_addr;
17758 * Enumeration denoting the RX, TX type of the resource.
17759 * This enumeration is used for resources that are similar for both
17760 * TX and RX paths of the chip.
17762 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17764 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17766 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17767 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
17768 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
17770 * Port ID of port for which the queue configuration is being
17771 * queried. This field is only required when sent by IPC.
17775 * Drivers will set this capability when it can use
17776 * queue_idx_service_profile to map the queues to application.
17778 uint8_t drv_qmap_cap;
17780 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
17782 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
17783 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
17784 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
17786 } __attribute__((packed));
17788 /* hwrm_queue_qportcfg_output (size:256b/32B) */
17789 struct hwrm_queue_qportcfg_output {
17790 /* The specific error status for the command. */
17791 uint16_t error_code;
17792 /* The HWRM command request type. */
17794 /* The sequence ID from the original command. */
17796 /* The length of the response data in number of bytes. */
17799 * The maximum number of queues that can be configured on this
17801 * Valid values range from 1 through 8.
17803 uint8_t max_configurable_queues;
17805 * The maximum number of lossless queues that can be configured
17807 * Valid values range from 0 through 8.
17809 uint8_t max_configurable_lossless_queues;
17811 * Bitmask indicating which queues can be configured by the
17812 * hwrm_queue_cfg command.
17814 * Each bit represents a specific queue where bit 0 represents
17815 * queue 0 and bit 7 represents queue 7.
17816 * # A value of 0 indicates that the queue is not configurable
17817 * by the hwrm_queue_cfg command.
17818 * # A value of 1 indicates that the queue is configurable.
17819 * # A hwrm_queue_cfg command shall return error when trying to
17820 * configure a queue not configurable.
17822 uint8_t queue_cfg_allowed;
17823 /* Information about queue configuration. */
17824 uint8_t queue_cfg_info;
17826 * If this flag is set to '1', then the queues are
17827 * configured asymmetrically on TX and RX sides.
17828 * If this flag is set to '0', then the queues are
17829 * configured symmetrically on TX and RX sides. For
17830 * symmetric configuration, the queue configuration
17831 * including queue ids and service profiles on the
17832 * TX side is the same as the corresponding queue
17833 * configuration on the RX side.
17835 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17838 * Bitmask indicating which queues can be configured by the
17839 * hwrm_queue_pfcenable_cfg command.
17841 * Each bit represents a specific priority where bit 0 represents
17842 * priority 0 and bit 7 represents priority 7.
17843 * # A value of 0 indicates that the priority is not configurable by
17844 * the hwrm_queue_pfcenable_cfg command.
17845 * # A value of 1 indicates that the priority is configurable.
17846 * # A hwrm_queue_pfcenable_cfg command shall return error when
17847 * trying to configure a priority that is not configurable.
17849 uint8_t queue_pfcenable_cfg_allowed;
17851 * Bitmask indicating which queues can be configured by the
17852 * hwrm_queue_pri2cos_cfg command.
17854 * Each bit represents a specific queue where bit 0 represents
17855 * queue 0 and bit 7 represents queue 7.
17856 * # A value of 0 indicates that the queue is not configurable
17857 * by the hwrm_queue_pri2cos_cfg command.
17858 * # A value of 1 indicates that the queue is configurable.
17859 * # A hwrm_queue_pri2cos_cfg command shall return error when
17860 * trying to configure a queue that is not configurable.
17862 uint8_t queue_pri2cos_cfg_allowed;
17864 * Bitmask indicating which queues can be configured by the
17865 * hwrm_queue_pri2cos_cfg command.
17867 * Each bit represents a specific queue where bit 0 represents
17868 * queue 0 and bit 7 represents queue 7.
17869 * # A value of 0 indicates that the queue is not configurable
17870 * by the hwrm_queue_pri2cos_cfg command.
17871 * # A value of 1 indicates that the queue is configurable.
17872 * # A hwrm_queue_pri2cos_cfg command shall return error when
17873 * trying to configure a queue not configurable.
17875 uint8_t queue_cos2bw_cfg_allowed;
17877 * ID of CoS Queue 0.
17880 * # This ID can be used on any subsequent call to an hwrm command
17881 * that takes a queue id.
17882 * # IDs must always be queried by this command before any use
17883 * by the driver or software.
17884 * # Any driver or software should not make any assumptions about
17886 * # A value of 0xff indicates that the queue is not available.
17887 * # Available queues may not be in sequential order.
17890 /* This value is applicable to CoS queues only. */
17891 uint8_t queue_id0_service_profile;
17892 /* Lossy (best-effort) */
17893 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
17895 /* Lossless (legacy) */
17896 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
17898 /* Lossless RoCE */
17899 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
17901 /* Lossy RoCE CNP */
17902 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17905 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
17907 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17908 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
17910 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
17911 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
17913 * ID of CoS Queue 1.
17916 * # This ID can be used on any subsequent call to an hwrm command
17917 * that takes a queue id.
17918 * # IDs must always be queried by this command before any use
17919 * by the driver or software.
17920 * # Any driver or software should not make any assumptions about
17922 * # A value of 0xff indicates that the queue is not available.
17923 * # Available queues may not be in sequential order.
17926 /* This value is applicable to CoS queues only. */
17927 uint8_t queue_id1_service_profile;
17928 /* Lossy (best-effort) */
17929 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
17931 /* Lossless (legacy) */
17932 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
17934 /* Lossless RoCE */
17935 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
17937 /* Lossy RoCE CNP */
17938 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17941 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
17943 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17944 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
17946 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
17947 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
17949 * ID of CoS Queue 2.
17952 * # This ID can be used on any subsequent call to an hwrm command
17953 * that takes a queue id.
17954 * # IDs must always be queried by this command before any use
17955 * by the driver or software.
17956 * # Any driver or software should not make any assumptions about
17958 * # A value of 0xff indicates that the queue is not available.
17959 * # Available queues may not be in sequential order.
17962 /* This value is applicable to CoS queues only. */
17963 uint8_t queue_id2_service_profile;
17964 /* Lossy (best-effort) */
17965 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
17967 /* Lossless (legacy) */
17968 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
17970 /* Lossless RoCE */
17971 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
17973 /* Lossy RoCE CNP */
17974 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17977 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
17979 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17980 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
17982 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
17983 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
17985 * ID of CoS Queue 3.
17988 * # This ID can be used on any subsequent call to an hwrm command
17989 * that takes a queue id.
17990 * # IDs must always be queried by this command before any use
17991 * by the driver or software.
17992 * # Any driver or software should not make any assumptions about
17994 * # A value of 0xff indicates that the queue is not available.
17995 * # Available queues may not be in sequential order.
17998 /* This value is applicable to CoS queues only. */
17999 uint8_t queue_id3_service_profile;
18000 /* Lossy (best-effort) */
18001 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
18003 /* Lossless (legacy) */
18004 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
18006 /* Lossless RoCE */
18007 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
18009 /* Lossy RoCE CNP */
18010 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18013 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
18015 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18016 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
18018 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
18019 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
18021 * ID of CoS Queue 4.
18024 * # This ID can be used on any subsequent call to an hwrm command
18025 * that takes a queue id.
18026 * # IDs must always be queried by this command before any use
18027 * by the driver or software.
18028 * # Any driver or software should not make any assumptions about
18030 * # A value of 0xff indicates that the queue is not available.
18031 * # Available queues may not be in sequential order.
18034 /* This value is applicable to CoS queues only. */
18035 uint8_t queue_id4_service_profile;
18036 /* Lossy (best-effort) */
18037 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
18039 /* Lossless (legacy) */
18040 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
18042 /* Lossless RoCE */
18043 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
18045 /* Lossy RoCE CNP */
18046 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18049 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
18051 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18052 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
18054 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
18055 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
18057 * ID of CoS Queue 5.
18060 * # This ID can be used on any subsequent call to an hwrm command
18061 * that takes a queue id.
18062 * # IDs must always be queried by this command before any use
18063 * by the driver or software.
18064 * # Any driver or software should not make any assumptions about
18066 * # A value of 0xff indicates that the queue is not available.
18067 * # Available queues may not be in sequential order.
18070 /* This value is applicable to CoS queues only. */
18071 uint8_t queue_id5_service_profile;
18072 /* Lossy (best-effort) */
18073 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
18075 /* Lossless (legacy) */
18076 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
18078 /* Lossless RoCE */
18079 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
18081 /* Lossy RoCE CNP */
18082 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18085 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
18087 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18088 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
18090 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
18091 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
18093 * ID of CoS Queue 6.
18096 * # This ID can be used on any subsequent call to an hwrm command
18097 * that takes a queue id.
18098 * # IDs must always be queried by this command before any use
18099 * by the driver or software.
18100 * # Any driver or software should not make any assumptions about
18102 * # A value of 0xff indicates that the queue is not available.
18103 * # Available queues may not be in sequential order.
18106 /* This value is applicable to CoS queues only. */
18107 uint8_t queue_id6_service_profile;
18108 /* Lossy (best-effort) */
18109 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
18111 /* Lossless (legacy) */
18112 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
18114 /* Lossless RoCE */
18115 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
18117 /* Lossy RoCE CNP */
18118 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18121 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
18123 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18124 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
18126 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
18127 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
18129 * ID of CoS Queue 7.
18132 * # This ID can be used on any subsequent call to an hwrm command
18133 * that takes a queue id.
18134 * # IDs must always be queried by this command before any use
18135 * by the driver or software.
18136 * # Any driver or software should not make any assumptions about
18138 * # A value of 0xff indicates that the queue is not available.
18139 * # Available queues may not be in sequential order.
18142 /* This value is applicable to CoS queues only. */
18143 uint8_t queue_id7_service_profile;
18144 /* Lossy (best-effort) */
18145 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
18147 /* Lossless (legacy) */
18148 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
18150 /* Lossless RoCE */
18151 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
18153 /* Lossy RoCE CNP */
18154 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18157 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
18159 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18160 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
18162 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
18163 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
18165 * This field is used in Output records to indicate that the output
18166 * is completely written to RAM. This field should be read as '1'
18167 * to indicate that the output has been completely written.
18168 * When writing a command completion or response to an internal processor,
18169 * the order of writes has to be such that this field is written last.
18172 } __attribute__((packed));
18174 /*******************
18175 * hwrm_queue_qcfg *
18176 *******************/
18179 /* hwrm_queue_qcfg_input (size:192b/24B) */
18180 struct hwrm_queue_qcfg_input {
18181 /* The HWRM command request type. */
18184 * The completion ring to send the completion event on. This should
18185 * be the NQ ID returned from the `nq_alloc` HWRM command.
18187 uint16_t cmpl_ring;
18189 * The sequence ID is used by the driver for tracking multiple
18190 * commands. This ID is treated as opaque data by the firmware and
18191 * the value is returned in the `hwrm_resp_hdr` upon completion.
18195 * The target ID of the command:
18196 * * 0x0-0xFFF8 - The function ID
18197 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18198 * * 0xFFFD - Reserved for user-space HWRM interface
18201 uint16_t target_id;
18203 * A physical address pointer pointing to a host buffer that the
18204 * command's response data will be written. This can be either a host
18205 * physical address (HPA) or a guest physical address (GPA) and must
18206 * point to a physically contiguous block of memory.
18208 uint64_t resp_addr;
18211 * Enumeration denoting the RX, TX type of the resource.
18212 * This enumeration is used for resources that are similar for both
18213 * TX and RX paths of the chip.
18215 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18217 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18219 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18220 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
18221 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
18222 /* Queue ID of the queue. */
18224 } __attribute__((packed));
18226 /* hwrm_queue_qcfg_output (size:128b/16B) */
18227 struct hwrm_queue_qcfg_output {
18228 /* The specific error status for the command. */
18229 uint16_t error_code;
18230 /* The HWRM command request type. */
18232 /* The sequence ID from the original command. */
18234 /* The length of the response data in number of bytes. */
18237 * This value is a the estimate packet length used in the
18240 uint32_t queue_len;
18241 /* This value is applicable to CoS queues only. */
18242 uint8_t service_profile;
18243 /* Lossy (best-effort) */
18244 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18246 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18247 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18248 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18249 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
18250 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
18251 /* Information about queue configuration. */
18252 uint8_t queue_cfg_info;
18254 * If this flag is set to '1', then the queue is
18255 * configured asymmetrically on TX and RX sides.
18256 * If this flag is set to '0', then this queue is
18257 * configured symmetrically on TX and RX sides.
18259 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18263 * This field is used in Output records to indicate that the output
18264 * is completely written to RAM. This field should be read as '1'
18265 * to indicate that the output has been completely written.
18266 * When writing a command completion or response to an internal processor,
18267 * the order of writes has to be such that this field is written last.
18270 } __attribute__((packed));
18272 /******************
18274 ******************/
18277 /* hwrm_queue_cfg_input (size:320b/40B) */
18278 struct hwrm_queue_cfg_input {
18279 /* The HWRM command request type. */
18282 * The completion ring to send the completion event on. This should
18283 * be the NQ ID returned from the `nq_alloc` HWRM command.
18285 uint16_t cmpl_ring;
18287 * The sequence ID is used by the driver for tracking multiple
18288 * commands. This ID is treated as opaque data by the firmware and
18289 * the value is returned in the `hwrm_resp_hdr` upon completion.
18293 * The target ID of the command:
18294 * * 0x0-0xFFF8 - The function ID
18295 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18296 * * 0xFFFD - Reserved for user-space HWRM interface
18299 uint16_t target_id;
18301 * A physical address pointer pointing to a host buffer that the
18302 * command's response data will be written. This can be either a host
18303 * physical address (HPA) or a guest physical address (GPA) and must
18304 * point to a physically contiguous block of memory.
18306 uint64_t resp_addr;
18309 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
18310 * This enumeration is used for resources that are similar for both
18311 * TX and RX paths of the chip.
18313 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
18314 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
18316 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18318 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18319 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
18320 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
18321 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
18322 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
18325 * This bit must be '1' for the dflt_len field to be
18328 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
18330 * This bit must be '1' for the service_profile field to be
18333 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
18334 /* Queue ID of queue that is to be configured by this function. */
18337 * This value is a the estimate packet length used in the
18339 * Set to 0xFF... (All Fs) to not adjust this value.
18342 /* This value is applicable to CoS queues only. */
18343 uint8_t service_profile;
18344 /* Lossy (best-effort) */
18345 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18347 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18348 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18349 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18350 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
18351 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
18352 uint8_t unused_0[7];
18353 } __attribute__((packed));
18355 /* hwrm_queue_cfg_output (size:128b/16B) */
18356 struct hwrm_queue_cfg_output {
18357 /* The specific error status for the command. */
18358 uint16_t error_code;
18359 /* The HWRM command request type. */
18361 /* The sequence ID from the original command. */
18363 /* The length of the response data in number of bytes. */
18365 uint8_t unused_0[7];
18367 * This field is used in Output records to indicate that the output
18368 * is completely written to RAM. This field should be read as '1'
18369 * to indicate that the output has been completely written.
18370 * When writing a command completion or response to an internal processor,
18371 * the order of writes has to be such that this field is written last.
18374 } __attribute__((packed));
18376 /*****************************
18377 * hwrm_queue_pfcenable_qcfg *
18378 *****************************/
18381 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
18382 struct hwrm_queue_pfcenable_qcfg_input {
18383 /* The HWRM command request type. */
18386 * The completion ring to send the completion event on. This should
18387 * be the NQ ID returned from the `nq_alloc` HWRM command.
18389 uint16_t cmpl_ring;
18391 * The sequence ID is used by the driver for tracking multiple
18392 * commands. This ID is treated as opaque data by the firmware and
18393 * the value is returned in the `hwrm_resp_hdr` upon completion.
18397 * The target ID of the command:
18398 * * 0x0-0xFFF8 - The function ID
18399 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18400 * * 0xFFFD - Reserved for user-space HWRM interface
18403 uint16_t target_id;
18405 * A physical address pointer pointing to a host buffer that the
18406 * command's response data will be written. This can be either a host
18407 * physical address (HPA) or a guest physical address (GPA) and must
18408 * point to a physically contiguous block of memory.
18410 uint64_t resp_addr;
18412 * Port ID of port for which the table is being configured.
18413 * The HWRM needs to check whether this function is allowed
18414 * to configure pri2cos mapping on this port.
18417 uint8_t unused_0[6];
18418 } __attribute__((packed));
18420 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
18421 struct hwrm_queue_pfcenable_qcfg_output {
18422 /* The specific error status for the command. */
18423 uint16_t error_code;
18424 /* The HWRM command request type. */
18426 /* The sequence ID from the original command. */
18428 /* The length of the response data in number of bytes. */
18431 /* If set to 1, then PFC is enabled on PRI 0. */
18432 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
18434 /* If set to 1, then PFC is enabled on PRI 1. */
18435 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
18437 /* If set to 1, then PFC is enabled on PRI 2. */
18438 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
18440 /* If set to 1, then PFC is enabled on PRI 3. */
18441 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
18443 /* If set to 1, then PFC is enabled on PRI 4. */
18444 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
18446 /* If set to 1, then PFC is enabled on PRI 5. */
18447 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
18449 /* If set to 1, then PFC is enabled on PRI 6. */
18450 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
18452 /* If set to 1, then PFC is enabled on PRI 7. */
18453 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
18455 uint8_t unused_0[3];
18457 * This field is used in Output records to indicate that the output
18458 * is completely written to RAM. This field should be read as '1'
18459 * to indicate that the output has been completely written.
18460 * When writing a command completion or response to an internal processor,
18461 * the order of writes has to be such that this field is written last.
18464 } __attribute__((packed));
18466 /****************************
18467 * hwrm_queue_pfcenable_cfg *
18468 ****************************/
18471 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
18472 struct hwrm_queue_pfcenable_cfg_input {
18473 /* The HWRM command request type. */
18476 * The completion ring to send the completion event on. This should
18477 * be the NQ ID returned from the `nq_alloc` HWRM command.
18479 uint16_t cmpl_ring;
18481 * The sequence ID is used by the driver for tracking multiple
18482 * commands. This ID is treated as opaque data by the firmware and
18483 * the value is returned in the `hwrm_resp_hdr` upon completion.
18487 * The target ID of the command:
18488 * * 0x0-0xFFF8 - The function ID
18489 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18490 * * 0xFFFD - Reserved for user-space HWRM interface
18493 uint16_t target_id;
18495 * A physical address pointer pointing to a host buffer that the
18496 * command's response data will be written. This can be either a host
18497 * physical address (HPA) or a guest physical address (GPA) and must
18498 * point to a physically contiguous block of memory.
18500 uint64_t resp_addr;
18502 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
18503 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
18505 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
18506 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
18508 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
18509 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
18511 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
18512 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
18514 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
18515 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
18517 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
18518 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
18520 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
18521 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
18523 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
18524 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
18527 * Port ID of port for which the table is being configured.
18528 * The HWRM needs to check whether this function is allowed
18529 * to configure pri2cos mapping on this port.
18532 uint8_t unused_0[2];
18533 } __attribute__((packed));
18535 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
18536 struct hwrm_queue_pfcenable_cfg_output {
18537 /* The specific error status for the command. */
18538 uint16_t error_code;
18539 /* The HWRM command request type. */
18541 /* The sequence ID from the original command. */
18543 /* The length of the response data in number of bytes. */
18545 uint8_t unused_0[7];
18547 * This field is used in Output records to indicate that the output
18548 * is completely written to RAM. This field should be read as '1'
18549 * to indicate that the output has been completely written.
18550 * When writing a command completion or response to an internal processor,
18551 * the order of writes has to be such that this field is written last.
18554 } __attribute__((packed));
18556 /***************************
18557 * hwrm_queue_pri2cos_qcfg *
18558 ***************************/
18561 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
18562 struct hwrm_queue_pri2cos_qcfg_input {
18563 /* The HWRM command request type. */
18566 * The completion ring to send the completion event on. This should
18567 * be the NQ ID returned from the `nq_alloc` HWRM command.
18569 uint16_t cmpl_ring;
18571 * The sequence ID is used by the driver for tracking multiple
18572 * commands. This ID is treated as opaque data by the firmware and
18573 * the value is returned in the `hwrm_resp_hdr` upon completion.
18577 * The target ID of the command:
18578 * * 0x0-0xFFF8 - The function ID
18579 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18580 * * 0xFFFD - Reserved for user-space HWRM interface
18583 uint16_t target_id;
18585 * A physical address pointer pointing to a host buffer that the
18586 * command's response data will be written. This can be either a host
18587 * physical address (HPA) or a guest physical address (GPA) and must
18588 * point to a physically contiguous block of memory.
18590 uint64_t resp_addr;
18593 * Enumeration denoting the RX, TX type of the resource.
18594 * This enumeration is used for resources that are similar for both
18595 * TX and RX paths of the chip.
18597 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18599 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18601 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18602 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
18603 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
18605 * When this bit is set to '0', the query is
18606 * for VLAN PRI field in tunnel headers.
18607 * When this bit is set to '1', the query is
18608 * for VLAN PRI field in inner packet headers.
18610 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
18612 * Port ID of port for which the table is being configured.
18613 * The HWRM needs to check whether this function is allowed
18614 * to configure pri2cos mapping on this port.
18617 uint8_t unused_0[3];
18618 } __attribute__((packed));
18620 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
18621 struct hwrm_queue_pri2cos_qcfg_output {
18622 /* The specific error status for the command. */
18623 uint16_t error_code;
18624 /* The HWRM command request type. */
18626 /* The sequence ID from the original command. */
18628 /* The length of the response data in number of bytes. */
18631 * CoS Queue assigned to priority 0. This value can only
18632 * be changed before traffic has started.
18633 * A value of 0xff indicates that no CoS queue is assigned to the
18634 * specified priority.
18636 uint8_t pri0_cos_queue_id;
18638 * CoS Queue assigned to priority 1. This value can only
18639 * be changed before traffic has started.
18640 * A value of 0xff indicates that no CoS queue is assigned to the
18641 * specified priority.
18643 uint8_t pri1_cos_queue_id;
18645 * CoS Queue assigned to priority 2 This value can only
18646 * be changed before traffic has started.
18647 * A value of 0xff indicates that no CoS queue is assigned to the
18648 * specified priority.
18650 uint8_t pri2_cos_queue_id;
18652 * CoS Queue assigned to priority 3. This value can only
18653 * be changed before traffic has started.
18654 * A value of 0xff indicates that no CoS queue is assigned to the
18655 * specified priority.
18657 uint8_t pri3_cos_queue_id;
18659 * CoS Queue assigned to priority 4. This value can only
18660 * be changed before traffic has started.
18661 * A value of 0xff indicates that no CoS queue is assigned to the
18662 * specified priority.
18664 uint8_t pri4_cos_queue_id;
18666 * CoS Queue assigned to priority 5. This value can only
18667 * be changed before traffic has started.
18668 * A value of 0xff indicates that no CoS queue is assigned to the
18669 * specified priority.
18671 uint8_t pri5_cos_queue_id;
18673 * CoS Queue assigned to priority 6. This value can only
18674 * be changed before traffic has started.
18675 * A value of 0xff indicates that no CoS queue is assigned to the
18676 * specified priority.
18678 uint8_t pri6_cos_queue_id;
18680 * CoS Queue assigned to priority 7. This value can only
18681 * be changed before traffic has started.
18682 * A value of 0xff indicates that no CoS queue is assigned to the
18683 * specified priority.
18685 uint8_t pri7_cos_queue_id;
18686 /* Information about queue configuration. */
18687 uint8_t queue_cfg_info;
18689 * If this flag is set to '1', then the PRI to CoS
18690 * configuration is asymmetric on TX and RX sides.
18691 * If this flag is set to '0', then PRI to CoS configuration
18692 * is symmetric on TX and RX sides.
18694 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18696 uint8_t unused_0[6];
18698 * This field is used in Output records to indicate that the output
18699 * is completely written to RAM. This field should be read as '1'
18700 * to indicate that the output has been completely written.
18701 * When writing a command completion or response to an internal processor,
18702 * the order of writes has to be such that this field is written last.
18705 } __attribute__((packed));
18707 /**************************
18708 * hwrm_queue_pri2cos_cfg *
18709 **************************/
18712 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
18713 struct hwrm_queue_pri2cos_cfg_input {
18714 /* The HWRM command request type. */
18717 * The completion ring to send the completion event on. This should
18718 * be the NQ ID returned from the `nq_alloc` HWRM command.
18720 uint16_t cmpl_ring;
18722 * The sequence ID is used by the driver for tracking multiple
18723 * commands. This ID is treated as opaque data by the firmware and
18724 * the value is returned in the `hwrm_resp_hdr` upon completion.
18728 * The target ID of the command:
18729 * * 0x0-0xFFF8 - The function ID
18730 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18731 * * 0xFFFD - Reserved for user-space HWRM interface
18734 uint16_t target_id;
18736 * A physical address pointer pointing to a host buffer that the
18737 * command's response data will be written. This can be either a host
18738 * physical address (HPA) or a guest physical address (GPA) and must
18739 * point to a physically contiguous block of memory.
18741 uint64_t resp_addr;
18744 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
18745 * This enumeration is used for resources that are similar for both
18746 * TX and RX paths of the chip.
18748 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
18749 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
18751 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18753 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18754 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
18755 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
18756 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
18757 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
18759 * When this bit is set to '0', the mapping is requested
18760 * for VLAN PRI field in tunnel headers.
18761 * When this bit is set to '1', the mapping is requested
18762 * for VLAN PRI field in inner packet headers.
18764 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
18767 * This bit must be '1' for the pri0_cos_queue_id field to be
18770 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
18773 * This bit must be '1' for the pri1_cos_queue_id field to be
18776 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
18779 * This bit must be '1' for the pri2_cos_queue_id field to be
18782 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
18785 * This bit must be '1' for the pri3_cos_queue_id field to be
18788 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
18791 * This bit must be '1' for the pri4_cos_queue_id field to be
18794 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
18797 * This bit must be '1' for the pri5_cos_queue_id field to be
18800 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
18803 * This bit must be '1' for the pri6_cos_queue_id field to be
18806 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
18809 * This bit must be '1' for the pri7_cos_queue_id field to be
18812 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
18815 * Port ID of port for which the table is being configured.
18816 * The HWRM needs to check whether this function is allowed
18817 * to configure pri2cos mapping on this port.
18821 * CoS Queue assigned to priority 0. This value can only
18822 * be changed before traffic has started.
18824 uint8_t pri0_cos_queue_id;
18826 * CoS Queue assigned to priority 1. This value can only
18827 * be changed before traffic has started.
18829 uint8_t pri1_cos_queue_id;
18831 * CoS Queue assigned to priority 2 This value can only
18832 * be changed before traffic has started.
18834 uint8_t pri2_cos_queue_id;
18836 * CoS Queue assigned to priority 3. This value can only
18837 * be changed before traffic has started.
18839 uint8_t pri3_cos_queue_id;
18841 * CoS Queue assigned to priority 4. This value can only
18842 * be changed before traffic has started.
18844 uint8_t pri4_cos_queue_id;
18846 * CoS Queue assigned to priority 5. This value can only
18847 * be changed before traffic has started.
18849 uint8_t pri5_cos_queue_id;
18851 * CoS Queue assigned to priority 6. This value can only
18852 * be changed before traffic has started.
18854 uint8_t pri6_cos_queue_id;
18856 * CoS Queue assigned to priority 7. This value can only
18857 * be changed before traffic has started.
18859 uint8_t pri7_cos_queue_id;
18860 uint8_t unused_0[7];
18861 } __attribute__((packed));
18863 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
18864 struct hwrm_queue_pri2cos_cfg_output {
18865 /* The specific error status for the command. */
18866 uint16_t error_code;
18867 /* The HWRM command request type. */
18869 /* The sequence ID from the original command. */
18871 /* The length of the response data in number of bytes. */
18873 uint8_t unused_0[7];
18875 * This field is used in Output records to indicate that the output
18876 * is completely written to RAM. This field should be read as '1'
18877 * to indicate that the output has been completely written.
18878 * When writing a command completion or response to an internal processor,
18879 * the order of writes has to be such that this field is written last.
18882 } __attribute__((packed));
18884 /**************************
18885 * hwrm_queue_cos2bw_qcfg *
18886 **************************/
18889 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
18890 struct hwrm_queue_cos2bw_qcfg_input {
18891 /* The HWRM command request type. */
18894 * The completion ring to send the completion event on. This should
18895 * be the NQ ID returned from the `nq_alloc` HWRM command.
18897 uint16_t cmpl_ring;
18899 * The sequence ID is used by the driver for tracking multiple
18900 * commands. This ID is treated as opaque data by the firmware and
18901 * the value is returned in the `hwrm_resp_hdr` upon completion.
18905 * The target ID of the command:
18906 * * 0x0-0xFFF8 - The function ID
18907 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18908 * * 0xFFFD - Reserved for user-space HWRM interface
18911 uint16_t target_id;
18913 * A physical address pointer pointing to a host buffer that the
18914 * command's response data will be written. This can be either a host
18915 * physical address (HPA) or a guest physical address (GPA) and must
18916 * point to a physically contiguous block of memory.
18918 uint64_t resp_addr;
18920 * Port ID of port for which the table is being configured.
18921 * The HWRM needs to check whether this function is allowed
18922 * to configure TC BW assignment on this port.
18925 uint8_t unused_0[6];
18926 } __attribute__((packed));
18928 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
18929 struct hwrm_queue_cos2bw_qcfg_output {
18930 /* The specific error status for the command. */
18931 uint16_t error_code;
18932 /* The HWRM command request type. */
18934 /* The sequence ID from the original command. */
18936 /* The length of the response data in number of bytes. */
18938 /* ID of CoS Queue 0. */
18943 * Minimum BW allocated to CoS Queue.
18944 * The HWRM will translate this value into byte counter and
18945 * time interval used for this COS inside the device.
18947 uint32_t queue_id0_min_bw;
18948 /* The bandwidth value. */
18949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
18950 UINT32_C(0xfffffff)
18951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
18953 /* The granularity of the value (bits or bytes). */
18954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
18955 UINT32_C(0x10000000)
18956 /* Value is in bits. */
18957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
18958 (UINT32_C(0x0) << 28)
18959 /* Value is in bytes. */
18960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
18961 (UINT32_C(0x1) << 28)
18962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
18963 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
18964 /* bw_value_unit is 3 b */
18965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
18966 UINT32_C(0xe0000000)
18967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
18969 /* Value is in Mb or MB (base 10). */
18970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
18971 (UINT32_C(0x0) << 29)
18972 /* Value is in Kb or KB (base 10). */
18973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
18974 (UINT32_C(0x2) << 29)
18975 /* Value is in bits or bytes. */
18976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
18977 (UINT32_C(0x4) << 29)
18978 /* Value is in Gb or GB (base 10). */
18979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
18980 (UINT32_C(0x6) << 29)
18981 /* Value is in 1/100th of a percentage of total bandwidth. */
18982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18983 (UINT32_C(0x1) << 29)
18985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
18986 (UINT32_C(0x7) << 29)
18987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
18988 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
18990 * Maximum BW allocated to CoS Queue.
18991 * The HWRM will translate this value into byte counter and
18992 * time interval used for this COS inside the device.
18994 uint32_t queue_id0_max_bw;
18995 /* The bandwidth value. */
18996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
18997 UINT32_C(0xfffffff)
18998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
19000 /* The granularity of the value (bits or bytes). */
19001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
19002 UINT32_C(0x10000000)
19003 /* Value is in bits. */
19004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
19005 (UINT32_C(0x0) << 28)
19006 /* Value is in bytes. */
19007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
19008 (UINT32_C(0x1) << 28)
19009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
19010 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
19011 /* bw_value_unit is 3 b */
19012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
19013 UINT32_C(0xe0000000)
19014 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
19016 /* Value is in Mb or MB (base 10). */
19017 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
19018 (UINT32_C(0x0) << 29)
19019 /* Value is in Kb or KB (base 10). */
19020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
19021 (UINT32_C(0x2) << 29)
19022 /* Value is in bits or bytes. */
19023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
19024 (UINT32_C(0x4) << 29)
19025 /* Value is in Gb or GB (base 10). */
19026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
19027 (UINT32_C(0x6) << 29)
19028 /* Value is in 1/100th of a percentage of total bandwidth. */
19029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19030 (UINT32_C(0x1) << 29)
19032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
19033 (UINT32_C(0x7) << 29)
19034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
19035 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
19036 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19037 uint8_t queue_id0_tsa_assign;
19038 /* Strict Priority */
19039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
19041 /* Enhanced Transmission Selection */
19042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
19045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
19048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
19051 * Priority level for strict priority. Valid only when the
19052 * tsa_assign is 0 - Strict Priority (SP)
19053 * 0..7 - Valid values.
19054 * 8..255 - Reserved.
19056 uint8_t queue_id0_pri_lvl;
19058 * Weight used to allocate remaining BW for this COS after
19059 * servicing guaranteed bandwidths for all COS.
19061 uint8_t queue_id0_bw_weight;
19062 /* ID of CoS Queue 1. */
19065 * Minimum BW allocated to CoS Queue.
19066 * The HWRM will translate this value into byte counter and
19067 * time interval used for this COS inside the device.
19069 uint32_t queue_id1_min_bw;
19070 /* The bandwidth value. */
19071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
19072 UINT32_C(0xfffffff)
19073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
19075 /* The granularity of the value (bits or bytes). */
19076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
19077 UINT32_C(0x10000000)
19078 /* Value is in bits. */
19079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
19080 (UINT32_C(0x0) << 28)
19081 /* Value is in bytes. */
19082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
19083 (UINT32_C(0x1) << 28)
19084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
19085 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
19086 /* bw_value_unit is 3 b */
19087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
19088 UINT32_C(0xe0000000)
19089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
19091 /* Value is in Mb or MB (base 10). */
19092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
19093 (UINT32_C(0x0) << 29)
19094 /* Value is in Kb or KB (base 10). */
19095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
19096 (UINT32_C(0x2) << 29)
19097 /* Value is in bits or bytes. */
19098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
19099 (UINT32_C(0x4) << 29)
19100 /* Value is in Gb or GB (base 10). */
19101 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
19102 (UINT32_C(0x6) << 29)
19103 /* Value is in 1/100th of a percentage of total bandwidth. */
19104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19105 (UINT32_C(0x1) << 29)
19107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
19108 (UINT32_C(0x7) << 29)
19109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
19110 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
19112 * Maximum BW allocated to CoS queue.
19113 * The HWRM will translate this value into byte counter and
19114 * time interval used for this COS inside the device.
19116 uint32_t queue_id1_max_bw;
19117 /* The bandwidth value. */
19118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
19119 UINT32_C(0xfffffff)
19120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
19122 /* The granularity of the value (bits or bytes). */
19123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
19124 UINT32_C(0x10000000)
19125 /* Value is in bits. */
19126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
19127 (UINT32_C(0x0) << 28)
19128 /* Value is in bytes. */
19129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
19130 (UINT32_C(0x1) << 28)
19131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
19132 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
19133 /* bw_value_unit is 3 b */
19134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
19135 UINT32_C(0xe0000000)
19136 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
19138 /* Value is in Mb or MB (base 10). */
19139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
19140 (UINT32_C(0x0) << 29)
19141 /* Value is in Kb or KB (base 10). */
19142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
19143 (UINT32_C(0x2) << 29)
19144 /* Value is in bits or bytes. */
19145 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
19146 (UINT32_C(0x4) << 29)
19147 /* Value is in Gb or GB (base 10). */
19148 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
19149 (UINT32_C(0x6) << 29)
19150 /* Value is in 1/100th of a percentage of total bandwidth. */
19151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19152 (UINT32_C(0x1) << 29)
19154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
19155 (UINT32_C(0x7) << 29)
19156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
19157 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
19158 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19159 uint8_t queue_id1_tsa_assign;
19160 /* Strict Priority */
19161 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
19163 /* Enhanced Transmission Selection */
19164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
19167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
19170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
19173 * Priority level for strict priority. Valid only when the
19174 * tsa_assign is 0 - Strict Priority (SP)
19175 * 0..7 - Valid values.
19176 * 8..255 - Reserved.
19178 uint8_t queue_id1_pri_lvl;
19180 * Weight used to allocate remaining BW for this COS after
19181 * servicing guaranteed bandwidths for all COS.
19183 uint8_t queue_id1_bw_weight;
19184 /* ID of CoS Queue 2. */
19187 * Minimum BW allocated to CoS Queue.
19188 * The HWRM will translate this value into byte counter and
19189 * time interval used for this COS inside the device.
19191 uint32_t queue_id2_min_bw;
19192 /* The bandwidth value. */
19193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
19194 UINT32_C(0xfffffff)
19195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
19197 /* The granularity of the value (bits or bytes). */
19198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
19199 UINT32_C(0x10000000)
19200 /* Value is in bits. */
19201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
19202 (UINT32_C(0x0) << 28)
19203 /* Value is in bytes. */
19204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
19205 (UINT32_C(0x1) << 28)
19206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
19207 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
19208 /* bw_value_unit is 3 b */
19209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
19210 UINT32_C(0xe0000000)
19211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
19213 /* Value is in Mb or MB (base 10). */
19214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
19215 (UINT32_C(0x0) << 29)
19216 /* Value is in Kb or KB (base 10). */
19217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
19218 (UINT32_C(0x2) << 29)
19219 /* Value is in bits or bytes. */
19220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
19221 (UINT32_C(0x4) << 29)
19222 /* Value is in Gb or GB (base 10). */
19223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
19224 (UINT32_C(0x6) << 29)
19225 /* Value is in 1/100th of a percentage of total bandwidth. */
19226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19227 (UINT32_C(0x1) << 29)
19229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
19230 (UINT32_C(0x7) << 29)
19231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
19232 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
19234 * Maximum BW allocated to CoS queue.
19235 * The HWRM will translate this value into byte counter and
19236 * time interval used for this COS inside the device.
19238 uint32_t queue_id2_max_bw;
19239 /* The bandwidth value. */
19240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
19241 UINT32_C(0xfffffff)
19242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
19244 /* The granularity of the value (bits or bytes). */
19245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
19246 UINT32_C(0x10000000)
19247 /* Value is in bits. */
19248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
19249 (UINT32_C(0x0) << 28)
19250 /* Value is in bytes. */
19251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
19252 (UINT32_C(0x1) << 28)
19253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
19254 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
19255 /* bw_value_unit is 3 b */
19256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
19257 UINT32_C(0xe0000000)
19258 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
19260 /* Value is in Mb or MB (base 10). */
19261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
19262 (UINT32_C(0x0) << 29)
19263 /* Value is in Kb or KB (base 10). */
19264 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
19265 (UINT32_C(0x2) << 29)
19266 /* Value is in bits or bytes. */
19267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
19268 (UINT32_C(0x4) << 29)
19269 /* Value is in Gb or GB (base 10). */
19270 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
19271 (UINT32_C(0x6) << 29)
19272 /* Value is in 1/100th of a percentage of total bandwidth. */
19273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19274 (UINT32_C(0x1) << 29)
19276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
19277 (UINT32_C(0x7) << 29)
19278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
19279 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
19280 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19281 uint8_t queue_id2_tsa_assign;
19282 /* Strict Priority */
19283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
19285 /* Enhanced Transmission Selection */
19286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
19289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
19292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
19295 * Priority level for strict priority. Valid only when the
19296 * tsa_assign is 0 - Strict Priority (SP)
19297 * 0..7 - Valid values.
19298 * 8..255 - Reserved.
19300 uint8_t queue_id2_pri_lvl;
19302 * Weight used to allocate remaining BW for this COS after
19303 * servicing guaranteed bandwidths for all COS.
19305 uint8_t queue_id2_bw_weight;
19306 /* ID of CoS Queue 3. */
19309 * Minimum BW allocated to CoS Queue.
19310 * The HWRM will translate this value into byte counter and
19311 * time interval used for this COS inside the device.
19313 uint32_t queue_id3_min_bw;
19314 /* The bandwidth value. */
19315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
19316 UINT32_C(0xfffffff)
19317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
19319 /* The granularity of the value (bits or bytes). */
19320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
19321 UINT32_C(0x10000000)
19322 /* Value is in bits. */
19323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
19324 (UINT32_C(0x0) << 28)
19325 /* Value is in bytes. */
19326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
19327 (UINT32_C(0x1) << 28)
19328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
19329 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
19330 /* bw_value_unit is 3 b */
19331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
19332 UINT32_C(0xe0000000)
19333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
19335 /* Value is in Mb or MB (base 10). */
19336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
19337 (UINT32_C(0x0) << 29)
19338 /* Value is in Kb or KB (base 10). */
19339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
19340 (UINT32_C(0x2) << 29)
19341 /* Value is in bits or bytes. */
19342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
19343 (UINT32_C(0x4) << 29)
19344 /* Value is in Gb or GB (base 10). */
19345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
19346 (UINT32_C(0x6) << 29)
19347 /* Value is in 1/100th of a percentage of total bandwidth. */
19348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19349 (UINT32_C(0x1) << 29)
19351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
19352 (UINT32_C(0x7) << 29)
19353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
19354 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
19356 * Maximum BW allocated to CoS queue.
19357 * The HWRM will translate this value into byte counter and
19358 * time interval used for this COS inside the device.
19360 uint32_t queue_id3_max_bw;
19361 /* The bandwidth value. */
19362 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
19363 UINT32_C(0xfffffff)
19364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
19366 /* The granularity of the value (bits or bytes). */
19367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
19368 UINT32_C(0x10000000)
19369 /* Value is in bits. */
19370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
19371 (UINT32_C(0x0) << 28)
19372 /* Value is in bytes. */
19373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
19374 (UINT32_C(0x1) << 28)
19375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
19376 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
19377 /* bw_value_unit is 3 b */
19378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
19379 UINT32_C(0xe0000000)
19380 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
19382 /* Value is in Mb or MB (base 10). */
19383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
19384 (UINT32_C(0x0) << 29)
19385 /* Value is in Kb or KB (base 10). */
19386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
19387 (UINT32_C(0x2) << 29)
19388 /* Value is in bits or bytes. */
19389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
19390 (UINT32_C(0x4) << 29)
19391 /* Value is in Gb or GB (base 10). */
19392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
19393 (UINT32_C(0x6) << 29)
19394 /* Value is in 1/100th of a percentage of total bandwidth. */
19395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19396 (UINT32_C(0x1) << 29)
19398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
19399 (UINT32_C(0x7) << 29)
19400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
19401 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
19402 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19403 uint8_t queue_id3_tsa_assign;
19404 /* Strict Priority */
19405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
19407 /* Enhanced Transmission Selection */
19408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
19411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
19414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
19417 * Priority level for strict priority. Valid only when the
19418 * tsa_assign is 0 - Strict Priority (SP)
19419 * 0..7 - Valid values.
19420 * 8..255 - Reserved.
19422 uint8_t queue_id3_pri_lvl;
19424 * Weight used to allocate remaining BW for this COS after
19425 * servicing guaranteed bandwidths for all COS.
19427 uint8_t queue_id3_bw_weight;
19428 /* ID of CoS Queue 4. */
19431 * Minimum BW allocated to CoS Queue.
19432 * The HWRM will translate this value into byte counter and
19433 * time interval used for this COS inside the device.
19435 uint32_t queue_id4_min_bw;
19436 /* The bandwidth value. */
19437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
19438 UINT32_C(0xfffffff)
19439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
19441 /* The granularity of the value (bits or bytes). */
19442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
19443 UINT32_C(0x10000000)
19444 /* Value is in bits. */
19445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
19446 (UINT32_C(0x0) << 28)
19447 /* Value is in bytes. */
19448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
19449 (UINT32_C(0x1) << 28)
19450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
19451 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
19452 /* bw_value_unit is 3 b */
19453 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
19454 UINT32_C(0xe0000000)
19455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
19457 /* Value is in Mb or MB (base 10). */
19458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
19459 (UINT32_C(0x0) << 29)
19460 /* Value is in Kb or KB (base 10). */
19461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
19462 (UINT32_C(0x2) << 29)
19463 /* Value is in bits or bytes. */
19464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
19465 (UINT32_C(0x4) << 29)
19466 /* Value is in Gb or GB (base 10). */
19467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
19468 (UINT32_C(0x6) << 29)
19469 /* Value is in 1/100th of a percentage of total bandwidth. */
19470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19471 (UINT32_C(0x1) << 29)
19473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
19474 (UINT32_C(0x7) << 29)
19475 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
19476 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
19478 * Maximum BW allocated to CoS queue.
19479 * The HWRM will translate this value into byte counter and
19480 * time interval used for this COS inside the device.
19482 uint32_t queue_id4_max_bw;
19483 /* The bandwidth value. */
19484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
19485 UINT32_C(0xfffffff)
19486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
19488 /* The granularity of the value (bits or bytes). */
19489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
19490 UINT32_C(0x10000000)
19491 /* Value is in bits. */
19492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
19493 (UINT32_C(0x0) << 28)
19494 /* Value is in bytes. */
19495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
19496 (UINT32_C(0x1) << 28)
19497 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
19498 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
19499 /* bw_value_unit is 3 b */
19500 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
19501 UINT32_C(0xe0000000)
19502 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
19504 /* Value is in Mb or MB (base 10). */
19505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
19506 (UINT32_C(0x0) << 29)
19507 /* Value is in Kb or KB (base 10). */
19508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
19509 (UINT32_C(0x2) << 29)
19510 /* Value is in bits or bytes. */
19511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
19512 (UINT32_C(0x4) << 29)
19513 /* Value is in Gb or GB (base 10). */
19514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
19515 (UINT32_C(0x6) << 29)
19516 /* Value is in 1/100th of a percentage of total bandwidth. */
19517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19518 (UINT32_C(0x1) << 29)
19520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
19521 (UINT32_C(0x7) << 29)
19522 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
19523 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
19524 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19525 uint8_t queue_id4_tsa_assign;
19526 /* Strict Priority */
19527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
19529 /* Enhanced Transmission Selection */
19530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
19533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
19536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
19539 * Priority level for strict priority. Valid only when the
19540 * tsa_assign is 0 - Strict Priority (SP)
19541 * 0..7 - Valid values.
19542 * 8..255 - Reserved.
19544 uint8_t queue_id4_pri_lvl;
19546 * Weight used to allocate remaining BW for this COS after
19547 * servicing guaranteed bandwidths for all COS.
19549 uint8_t queue_id4_bw_weight;
19550 /* ID of CoS Queue 5. */
19553 * Minimum BW allocated to CoS Queue.
19554 * The HWRM will translate this value into byte counter and
19555 * time interval used for this COS inside the device.
19557 uint32_t queue_id5_min_bw;
19558 /* The bandwidth value. */
19559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
19560 UINT32_C(0xfffffff)
19561 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
19563 /* The granularity of the value (bits or bytes). */
19564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
19565 UINT32_C(0x10000000)
19566 /* Value is in bits. */
19567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
19568 (UINT32_C(0x0) << 28)
19569 /* Value is in bytes. */
19570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
19571 (UINT32_C(0x1) << 28)
19572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
19573 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
19574 /* bw_value_unit is 3 b */
19575 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
19576 UINT32_C(0xe0000000)
19577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
19579 /* Value is in Mb or MB (base 10). */
19580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
19581 (UINT32_C(0x0) << 29)
19582 /* Value is in Kb or KB (base 10). */
19583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
19584 (UINT32_C(0x2) << 29)
19585 /* Value is in bits or bytes. */
19586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
19587 (UINT32_C(0x4) << 29)
19588 /* Value is in Gb or GB (base 10). */
19589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
19590 (UINT32_C(0x6) << 29)
19591 /* Value is in 1/100th of a percentage of total bandwidth. */
19592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19593 (UINT32_C(0x1) << 29)
19595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
19596 (UINT32_C(0x7) << 29)
19597 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
19598 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
19600 * Maximum BW allocated to CoS queue.
19601 * The HWRM will translate this value into byte counter and
19602 * time interval used for this COS inside the device.
19604 uint32_t queue_id5_max_bw;
19605 /* The bandwidth value. */
19606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
19607 UINT32_C(0xfffffff)
19608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
19610 /* The granularity of the value (bits or bytes). */
19611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
19612 UINT32_C(0x10000000)
19613 /* Value is in bits. */
19614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
19615 (UINT32_C(0x0) << 28)
19616 /* Value is in bytes. */
19617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
19618 (UINT32_C(0x1) << 28)
19619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
19620 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
19621 /* bw_value_unit is 3 b */
19622 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
19623 UINT32_C(0xe0000000)
19624 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
19626 /* Value is in Mb or MB (base 10). */
19627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
19628 (UINT32_C(0x0) << 29)
19629 /* Value is in Kb or KB (base 10). */
19630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
19631 (UINT32_C(0x2) << 29)
19632 /* Value is in bits or bytes. */
19633 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
19634 (UINT32_C(0x4) << 29)
19635 /* Value is in Gb or GB (base 10). */
19636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
19637 (UINT32_C(0x6) << 29)
19638 /* Value is in 1/100th of a percentage of total bandwidth. */
19639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19640 (UINT32_C(0x1) << 29)
19642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
19643 (UINT32_C(0x7) << 29)
19644 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
19645 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
19646 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19647 uint8_t queue_id5_tsa_assign;
19648 /* Strict Priority */
19649 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
19651 /* Enhanced Transmission Selection */
19652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
19655 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
19658 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
19661 * Priority level for strict priority. Valid only when the
19662 * tsa_assign is 0 - Strict Priority (SP)
19663 * 0..7 - Valid values.
19664 * 8..255 - Reserved.
19666 uint8_t queue_id5_pri_lvl;
19668 * Weight used to allocate remaining BW for this COS after
19669 * servicing guaranteed bandwidths for all COS.
19671 uint8_t queue_id5_bw_weight;
19672 /* ID of CoS Queue 6. */
19675 * Minimum BW allocated to CoS Queue.
19676 * The HWRM will translate this value into byte counter and
19677 * time interval used for this COS inside the device.
19679 uint32_t queue_id6_min_bw;
19680 /* The bandwidth value. */
19681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
19682 UINT32_C(0xfffffff)
19683 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
19685 /* The granularity of the value (bits or bytes). */
19686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
19687 UINT32_C(0x10000000)
19688 /* Value is in bits. */
19689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
19690 (UINT32_C(0x0) << 28)
19691 /* Value is in bytes. */
19692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
19693 (UINT32_C(0x1) << 28)
19694 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
19695 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
19696 /* bw_value_unit is 3 b */
19697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
19698 UINT32_C(0xe0000000)
19699 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
19701 /* Value is in Mb or MB (base 10). */
19702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
19703 (UINT32_C(0x0) << 29)
19704 /* Value is in Kb or KB (base 10). */
19705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
19706 (UINT32_C(0x2) << 29)
19707 /* Value is in bits or bytes. */
19708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
19709 (UINT32_C(0x4) << 29)
19710 /* Value is in Gb or GB (base 10). */
19711 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
19712 (UINT32_C(0x6) << 29)
19713 /* Value is in 1/100th of a percentage of total bandwidth. */
19714 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19715 (UINT32_C(0x1) << 29)
19717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
19718 (UINT32_C(0x7) << 29)
19719 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
19720 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
19722 * Maximum BW allocated to CoS queue.
19723 * The HWRM will translate this value into byte counter and
19724 * time interval used for this COS inside the device.
19726 uint32_t queue_id6_max_bw;
19727 /* The bandwidth value. */
19728 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
19729 UINT32_C(0xfffffff)
19730 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
19732 /* The granularity of the value (bits or bytes). */
19733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
19734 UINT32_C(0x10000000)
19735 /* Value is in bits. */
19736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
19737 (UINT32_C(0x0) << 28)
19738 /* Value is in bytes. */
19739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
19740 (UINT32_C(0x1) << 28)
19741 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
19742 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
19743 /* bw_value_unit is 3 b */
19744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
19745 UINT32_C(0xe0000000)
19746 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
19748 /* Value is in Mb or MB (base 10). */
19749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
19750 (UINT32_C(0x0) << 29)
19751 /* Value is in Kb or KB (base 10). */
19752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
19753 (UINT32_C(0x2) << 29)
19754 /* Value is in bits or bytes. */
19755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
19756 (UINT32_C(0x4) << 29)
19757 /* Value is in Gb or GB (base 10). */
19758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
19759 (UINT32_C(0x6) << 29)
19760 /* Value is in 1/100th of a percentage of total bandwidth. */
19761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19762 (UINT32_C(0x1) << 29)
19764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
19765 (UINT32_C(0x7) << 29)
19766 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
19767 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
19768 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19769 uint8_t queue_id6_tsa_assign;
19770 /* Strict Priority */
19771 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
19773 /* Enhanced Transmission Selection */
19774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
19777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
19780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
19783 * Priority level for strict priority. Valid only when the
19784 * tsa_assign is 0 - Strict Priority (SP)
19785 * 0..7 - Valid values.
19786 * 8..255 - Reserved.
19788 uint8_t queue_id6_pri_lvl;
19790 * Weight used to allocate remaining BW for this COS after
19791 * servicing guaranteed bandwidths for all COS.
19793 uint8_t queue_id6_bw_weight;
19794 /* ID of CoS Queue 7. */
19797 * Minimum BW allocated to CoS Queue.
19798 * The HWRM will translate this value into byte counter and
19799 * time interval used for this COS inside the device.
19801 uint32_t queue_id7_min_bw;
19802 /* The bandwidth value. */
19803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
19804 UINT32_C(0xfffffff)
19805 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
19807 /* The granularity of the value (bits or bytes). */
19808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
19809 UINT32_C(0x10000000)
19810 /* Value is in bits. */
19811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
19812 (UINT32_C(0x0) << 28)
19813 /* Value is in bytes. */
19814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
19815 (UINT32_C(0x1) << 28)
19816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
19817 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
19818 /* bw_value_unit is 3 b */
19819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
19820 UINT32_C(0xe0000000)
19821 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
19823 /* Value is in Mb or MB (base 10). */
19824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
19825 (UINT32_C(0x0) << 29)
19826 /* Value is in Kb or KB (base 10). */
19827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
19828 (UINT32_C(0x2) << 29)
19829 /* Value is in bits or bytes. */
19830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
19831 (UINT32_C(0x4) << 29)
19832 /* Value is in Gb or GB (base 10). */
19833 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
19834 (UINT32_C(0x6) << 29)
19835 /* Value is in 1/100th of a percentage of total bandwidth. */
19836 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19837 (UINT32_C(0x1) << 29)
19839 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
19840 (UINT32_C(0x7) << 29)
19841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
19842 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
19844 * Maximum BW allocated to CoS queue.
19845 * The HWRM will translate this value into byte counter and
19846 * time interval used for this COS inside the device.
19848 uint32_t queue_id7_max_bw;
19849 /* The bandwidth value. */
19850 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
19851 UINT32_C(0xfffffff)
19852 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
19854 /* The granularity of the value (bits or bytes). */
19855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
19856 UINT32_C(0x10000000)
19857 /* Value is in bits. */
19858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
19859 (UINT32_C(0x0) << 28)
19860 /* Value is in bytes. */
19861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
19862 (UINT32_C(0x1) << 28)
19863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
19864 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
19865 /* bw_value_unit is 3 b */
19866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
19867 UINT32_C(0xe0000000)
19868 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
19870 /* Value is in Mb or MB (base 10). */
19871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
19872 (UINT32_C(0x0) << 29)
19873 /* Value is in Kb or KB (base 10). */
19874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
19875 (UINT32_C(0x2) << 29)
19876 /* Value is in bits or bytes. */
19877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
19878 (UINT32_C(0x4) << 29)
19879 /* Value is in Gb or GB (base 10). */
19880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
19881 (UINT32_C(0x6) << 29)
19882 /* Value is in 1/100th of a percentage of total bandwidth. */
19883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19884 (UINT32_C(0x1) << 29)
19886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
19887 (UINT32_C(0x7) << 29)
19888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
19889 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
19890 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19891 uint8_t queue_id7_tsa_assign;
19892 /* Strict Priority */
19893 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
19895 /* Enhanced Transmission Selection */
19896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
19899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
19902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
19905 * Priority level for strict priority. Valid only when the
19906 * tsa_assign is 0 - Strict Priority (SP)
19907 * 0..7 - Valid values.
19908 * 8..255 - Reserved.
19910 uint8_t queue_id7_pri_lvl;
19912 * Weight used to allocate remaining BW for this COS after
19913 * servicing guaranteed bandwidths for all COS.
19915 uint8_t queue_id7_bw_weight;
19916 uint8_t unused_2[4];
19918 * This field is used in Output records to indicate that the output
19919 * is completely written to RAM. This field should be read as '1'
19920 * to indicate that the output has been completely written.
19921 * When writing a command completion or response to an internal processor,
19922 * the order of writes has to be such that this field is written last.
19925 } __attribute__((packed));
19927 /*************************
19928 * hwrm_queue_cos2bw_cfg *
19929 *************************/
19932 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
19933 struct hwrm_queue_cos2bw_cfg_input {
19934 /* The HWRM command request type. */
19937 * The completion ring to send the completion event on. This should
19938 * be the NQ ID returned from the `nq_alloc` HWRM command.
19940 uint16_t cmpl_ring;
19942 * The sequence ID is used by the driver for tracking multiple
19943 * commands. This ID is treated as opaque data by the firmware and
19944 * the value is returned in the `hwrm_resp_hdr` upon completion.
19948 * The target ID of the command:
19949 * * 0x0-0xFFF8 - The function ID
19950 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19951 * * 0xFFFD - Reserved for user-space HWRM interface
19954 uint16_t target_id;
19956 * A physical address pointer pointing to a host buffer that the
19957 * command's response data will be written. This can be either a host
19958 * physical address (HPA) or a guest physical address (GPA) and must
19959 * point to a physically contiguous block of memory.
19961 uint64_t resp_addr;
19965 * If this bit is set to 1, then all queue_id0 related
19966 * parameters in this command are valid.
19968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
19971 * If this bit is set to 1, then all queue_id1 related
19972 * parameters in this command are valid.
19974 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
19977 * If this bit is set to 1, then all queue_id2 related
19978 * parameters in this command are valid.
19980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
19983 * If this bit is set to 1, then all queue_id3 related
19984 * parameters in this command are valid.
19986 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
19989 * If this bit is set to 1, then all queue_id4 related
19990 * parameters in this command are valid.
19992 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
19995 * If this bit is set to 1, then all queue_id5 related
19996 * parameters in this command are valid.
19998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
20001 * If this bit is set to 1, then all queue_id6 related
20002 * parameters in this command are valid.
20004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
20007 * If this bit is set to 1, then all queue_id7 related
20008 * parameters in this command are valid.
20010 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
20013 * Port ID of port for which the table is being configured.
20014 * The HWRM needs to check whether this function is allowed
20015 * to configure TC BW assignment on this port.
20018 /* ID of CoS Queue 0. */
20022 * Minimum BW allocated to CoS Queue.
20023 * The HWRM will translate this value into byte counter and
20024 * time interval used for this COS inside the device.
20026 uint32_t queue_id0_min_bw;
20027 /* The bandwidth value. */
20028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
20029 UINT32_C(0xfffffff)
20030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
20032 /* The granularity of the value (bits or bytes). */
20033 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
20034 UINT32_C(0x10000000)
20035 /* Value is in bits. */
20036 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
20037 (UINT32_C(0x0) << 28)
20038 /* Value is in bytes. */
20039 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
20040 (UINT32_C(0x1) << 28)
20041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
20042 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
20043 /* bw_value_unit is 3 b */
20044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
20045 UINT32_C(0xe0000000)
20046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
20048 /* Value is in Mb or MB (base 10). */
20049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
20050 (UINT32_C(0x0) << 29)
20051 /* Value is in Kb or KB (base 10). */
20052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
20053 (UINT32_C(0x2) << 29)
20054 /* Value is in bits or bytes. */
20055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
20056 (UINT32_C(0x4) << 29)
20057 /* Value is in Gb or GB (base 10). */
20058 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
20059 (UINT32_C(0x6) << 29)
20060 /* Value is in 1/100th of a percentage of total bandwidth. */
20061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20062 (UINT32_C(0x1) << 29)
20064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
20065 (UINT32_C(0x7) << 29)
20066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
20067 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
20069 * Maximum BW allocated to CoS Queue.
20070 * The HWRM will translate this value into byte counter and
20071 * time interval used for this COS inside the device.
20073 uint32_t queue_id0_max_bw;
20074 /* The bandwidth value. */
20075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
20076 UINT32_C(0xfffffff)
20077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
20079 /* The granularity of the value (bits or bytes). */
20080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
20081 UINT32_C(0x10000000)
20082 /* Value is in bits. */
20083 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
20084 (UINT32_C(0x0) << 28)
20085 /* Value is in bytes. */
20086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
20087 (UINT32_C(0x1) << 28)
20088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
20089 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
20090 /* bw_value_unit is 3 b */
20091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
20092 UINT32_C(0xe0000000)
20093 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
20095 /* Value is in Mb or MB (base 10). */
20096 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
20097 (UINT32_C(0x0) << 29)
20098 /* Value is in Kb or KB (base 10). */
20099 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
20100 (UINT32_C(0x2) << 29)
20101 /* Value is in bits or bytes. */
20102 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
20103 (UINT32_C(0x4) << 29)
20104 /* Value is in Gb or GB (base 10). */
20105 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
20106 (UINT32_C(0x6) << 29)
20107 /* Value is in 1/100th of a percentage of total bandwidth. */
20108 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20109 (UINT32_C(0x1) << 29)
20111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
20112 (UINT32_C(0x7) << 29)
20113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
20114 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
20115 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20116 uint8_t queue_id0_tsa_assign;
20117 /* Strict Priority */
20118 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
20120 /* Enhanced Transmission Selection */
20121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
20124 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
20127 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
20130 * Priority level for strict priority. Valid only when the
20131 * tsa_assign is 0 - Strict Priority (SP)
20132 * 0..7 - Valid values.
20133 * 8..255 - Reserved.
20135 uint8_t queue_id0_pri_lvl;
20137 * Weight used to allocate remaining BW for this COS after
20138 * servicing guaranteed bandwidths for all COS.
20140 uint8_t queue_id0_bw_weight;
20141 /* ID of CoS Queue 1. */
20144 * Minimum BW allocated to CoS Queue.
20145 * The HWRM will translate this value into byte counter and
20146 * time interval used for this COS inside the device.
20148 uint32_t queue_id1_min_bw;
20149 /* The bandwidth value. */
20150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
20151 UINT32_C(0xfffffff)
20152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
20154 /* The granularity of the value (bits or bytes). */
20155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
20156 UINT32_C(0x10000000)
20157 /* Value is in bits. */
20158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
20159 (UINT32_C(0x0) << 28)
20160 /* Value is in bytes. */
20161 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
20162 (UINT32_C(0x1) << 28)
20163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
20164 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
20165 /* bw_value_unit is 3 b */
20166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
20167 UINT32_C(0xe0000000)
20168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
20170 /* Value is in Mb or MB (base 10). */
20171 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
20172 (UINT32_C(0x0) << 29)
20173 /* Value is in Kb or KB (base 10). */
20174 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
20175 (UINT32_C(0x2) << 29)
20176 /* Value is in bits or bytes. */
20177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
20178 (UINT32_C(0x4) << 29)
20179 /* Value is in Gb or GB (base 10). */
20180 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
20181 (UINT32_C(0x6) << 29)
20182 /* Value is in 1/100th of a percentage of total bandwidth. */
20183 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20184 (UINT32_C(0x1) << 29)
20186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
20187 (UINT32_C(0x7) << 29)
20188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
20189 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
20191 * Maximum BW allocated to CoS queue.
20192 * The HWRM will translate this value into byte counter and
20193 * time interval used for this COS inside the device.
20195 uint32_t queue_id1_max_bw;
20196 /* The bandwidth value. */
20197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
20198 UINT32_C(0xfffffff)
20199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
20201 /* The granularity of the value (bits or bytes). */
20202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
20203 UINT32_C(0x10000000)
20204 /* Value is in bits. */
20205 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
20206 (UINT32_C(0x0) << 28)
20207 /* Value is in bytes. */
20208 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
20209 (UINT32_C(0x1) << 28)
20210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
20211 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
20212 /* bw_value_unit is 3 b */
20213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
20214 UINT32_C(0xe0000000)
20215 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
20217 /* Value is in Mb or MB (base 10). */
20218 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
20219 (UINT32_C(0x0) << 29)
20220 /* Value is in Kb or KB (base 10). */
20221 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
20222 (UINT32_C(0x2) << 29)
20223 /* Value is in bits or bytes. */
20224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
20225 (UINT32_C(0x4) << 29)
20226 /* Value is in Gb or GB (base 10). */
20227 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
20228 (UINT32_C(0x6) << 29)
20229 /* Value is in 1/100th of a percentage of total bandwidth. */
20230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20231 (UINT32_C(0x1) << 29)
20233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
20234 (UINT32_C(0x7) << 29)
20235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
20236 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
20237 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20238 uint8_t queue_id1_tsa_assign;
20239 /* Strict Priority */
20240 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
20242 /* Enhanced Transmission Selection */
20243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
20246 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
20249 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
20252 * Priority level for strict priority. Valid only when the
20253 * tsa_assign is 0 - Strict Priority (SP)
20254 * 0..7 - Valid values.
20255 * 8..255 - Reserved.
20257 uint8_t queue_id1_pri_lvl;
20259 * Weight used to allocate remaining BW for this COS after
20260 * servicing guaranteed bandwidths for all COS.
20262 uint8_t queue_id1_bw_weight;
20263 /* ID of CoS Queue 2. */
20266 * Minimum BW allocated to CoS Queue.
20267 * The HWRM will translate this value into byte counter and
20268 * time interval used for this COS inside the device.
20270 uint32_t queue_id2_min_bw;
20271 /* The bandwidth value. */
20272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
20273 UINT32_C(0xfffffff)
20274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
20276 /* The granularity of the value (bits or bytes). */
20277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
20278 UINT32_C(0x10000000)
20279 /* Value is in bits. */
20280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
20281 (UINT32_C(0x0) << 28)
20282 /* Value is in bytes. */
20283 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
20284 (UINT32_C(0x1) << 28)
20285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
20286 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
20287 /* bw_value_unit is 3 b */
20288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
20289 UINT32_C(0xe0000000)
20290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
20292 /* Value is in Mb or MB (base 10). */
20293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
20294 (UINT32_C(0x0) << 29)
20295 /* Value is in Kb or KB (base 10). */
20296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
20297 (UINT32_C(0x2) << 29)
20298 /* Value is in bits or bytes. */
20299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
20300 (UINT32_C(0x4) << 29)
20301 /* Value is in Gb or GB (base 10). */
20302 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
20303 (UINT32_C(0x6) << 29)
20304 /* Value is in 1/100th of a percentage of total bandwidth. */
20305 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20306 (UINT32_C(0x1) << 29)
20308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
20309 (UINT32_C(0x7) << 29)
20310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
20311 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
20313 * Maximum BW allocated to CoS queue.
20314 * The HWRM will translate this value into byte counter and
20315 * time interval used for this COS inside the device.
20317 uint32_t queue_id2_max_bw;
20318 /* The bandwidth value. */
20319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
20320 UINT32_C(0xfffffff)
20321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
20323 /* The granularity of the value (bits or bytes). */
20324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
20325 UINT32_C(0x10000000)
20326 /* Value is in bits. */
20327 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
20328 (UINT32_C(0x0) << 28)
20329 /* Value is in bytes. */
20330 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
20331 (UINT32_C(0x1) << 28)
20332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
20333 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
20334 /* bw_value_unit is 3 b */
20335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
20336 UINT32_C(0xe0000000)
20337 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
20339 /* Value is in Mb or MB (base 10). */
20340 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
20341 (UINT32_C(0x0) << 29)
20342 /* Value is in Kb or KB (base 10). */
20343 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
20344 (UINT32_C(0x2) << 29)
20345 /* Value is in bits or bytes. */
20346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
20347 (UINT32_C(0x4) << 29)
20348 /* Value is in Gb or GB (base 10). */
20349 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
20350 (UINT32_C(0x6) << 29)
20351 /* Value is in 1/100th of a percentage of total bandwidth. */
20352 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20353 (UINT32_C(0x1) << 29)
20355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
20356 (UINT32_C(0x7) << 29)
20357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
20358 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
20359 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20360 uint8_t queue_id2_tsa_assign;
20361 /* Strict Priority */
20362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
20364 /* Enhanced Transmission Selection */
20365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
20368 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
20371 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
20374 * Priority level for strict priority. Valid only when the
20375 * tsa_assign is 0 - Strict Priority (SP)
20376 * 0..7 - Valid values.
20377 * 8..255 - Reserved.
20379 uint8_t queue_id2_pri_lvl;
20381 * Weight used to allocate remaining BW for this COS after
20382 * servicing guaranteed bandwidths for all COS.
20384 uint8_t queue_id2_bw_weight;
20385 /* ID of CoS Queue 3. */
20388 * Minimum BW allocated to CoS Queue.
20389 * The HWRM will translate this value into byte counter and
20390 * time interval used for this COS inside the device.
20392 uint32_t queue_id3_min_bw;
20393 /* The bandwidth value. */
20394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
20395 UINT32_C(0xfffffff)
20396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
20398 /* The granularity of the value (bits or bytes). */
20399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
20400 UINT32_C(0x10000000)
20401 /* Value is in bits. */
20402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
20403 (UINT32_C(0x0) << 28)
20404 /* Value is in bytes. */
20405 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
20406 (UINT32_C(0x1) << 28)
20407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
20408 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
20409 /* bw_value_unit is 3 b */
20410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
20411 UINT32_C(0xe0000000)
20412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
20414 /* Value is in Mb or MB (base 10). */
20415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
20416 (UINT32_C(0x0) << 29)
20417 /* Value is in Kb or KB (base 10). */
20418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
20419 (UINT32_C(0x2) << 29)
20420 /* Value is in bits or bytes. */
20421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
20422 (UINT32_C(0x4) << 29)
20423 /* Value is in Gb or GB (base 10). */
20424 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
20425 (UINT32_C(0x6) << 29)
20426 /* Value is in 1/100th of a percentage of total bandwidth. */
20427 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20428 (UINT32_C(0x1) << 29)
20430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
20431 (UINT32_C(0x7) << 29)
20432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
20433 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
20435 * Maximum BW allocated to CoS queue.
20436 * The HWRM will translate this value into byte counter and
20437 * time interval used for this COS inside the device.
20439 uint32_t queue_id3_max_bw;
20440 /* The bandwidth value. */
20441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
20442 UINT32_C(0xfffffff)
20443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
20445 /* The granularity of the value (bits or bytes). */
20446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
20447 UINT32_C(0x10000000)
20448 /* Value is in bits. */
20449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
20450 (UINT32_C(0x0) << 28)
20451 /* Value is in bytes. */
20452 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
20453 (UINT32_C(0x1) << 28)
20454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
20455 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
20456 /* bw_value_unit is 3 b */
20457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
20458 UINT32_C(0xe0000000)
20459 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
20461 /* Value is in Mb or MB (base 10). */
20462 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
20463 (UINT32_C(0x0) << 29)
20464 /* Value is in Kb or KB (base 10). */
20465 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
20466 (UINT32_C(0x2) << 29)
20467 /* Value is in bits or bytes. */
20468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
20469 (UINT32_C(0x4) << 29)
20470 /* Value is in Gb or GB (base 10). */
20471 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
20472 (UINT32_C(0x6) << 29)
20473 /* Value is in 1/100th of a percentage of total bandwidth. */
20474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20475 (UINT32_C(0x1) << 29)
20477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
20478 (UINT32_C(0x7) << 29)
20479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
20480 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
20481 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20482 uint8_t queue_id3_tsa_assign;
20483 /* Strict Priority */
20484 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
20486 /* Enhanced Transmission Selection */
20487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
20490 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
20493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
20496 * Priority level for strict priority. Valid only when the
20497 * tsa_assign is 0 - Strict Priority (SP)
20498 * 0..7 - Valid values.
20499 * 8..255 - Reserved.
20501 uint8_t queue_id3_pri_lvl;
20503 * Weight used to allocate remaining BW for this COS after
20504 * servicing guaranteed bandwidths for all COS.
20506 uint8_t queue_id3_bw_weight;
20507 /* ID of CoS Queue 4. */
20510 * Minimum BW allocated to CoS Queue.
20511 * The HWRM will translate this value into byte counter and
20512 * time interval used for this COS inside the device.
20514 uint32_t queue_id4_min_bw;
20515 /* The bandwidth value. */
20516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
20517 UINT32_C(0xfffffff)
20518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
20520 /* The granularity of the value (bits or bytes). */
20521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
20522 UINT32_C(0x10000000)
20523 /* Value is in bits. */
20524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
20525 (UINT32_C(0x0) << 28)
20526 /* Value is in bytes. */
20527 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
20528 (UINT32_C(0x1) << 28)
20529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
20530 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
20531 /* bw_value_unit is 3 b */
20532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
20533 UINT32_C(0xe0000000)
20534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
20536 /* Value is in Mb or MB (base 10). */
20537 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
20538 (UINT32_C(0x0) << 29)
20539 /* Value is in Kb or KB (base 10). */
20540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
20541 (UINT32_C(0x2) << 29)
20542 /* Value is in bits or bytes. */
20543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
20544 (UINT32_C(0x4) << 29)
20545 /* Value is in Gb or GB (base 10). */
20546 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
20547 (UINT32_C(0x6) << 29)
20548 /* Value is in 1/100th of a percentage of total bandwidth. */
20549 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20550 (UINT32_C(0x1) << 29)
20552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
20553 (UINT32_C(0x7) << 29)
20554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
20555 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
20557 * Maximum BW allocated to CoS queue.
20558 * The HWRM will translate this value into byte counter and
20559 * time interval used for this COS inside the device.
20561 uint32_t queue_id4_max_bw;
20562 /* The bandwidth value. */
20563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
20564 UINT32_C(0xfffffff)
20565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
20567 /* The granularity of the value (bits or bytes). */
20568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
20569 UINT32_C(0x10000000)
20570 /* Value is in bits. */
20571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
20572 (UINT32_C(0x0) << 28)
20573 /* Value is in bytes. */
20574 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
20575 (UINT32_C(0x1) << 28)
20576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
20577 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
20578 /* bw_value_unit is 3 b */
20579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
20580 UINT32_C(0xe0000000)
20581 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
20583 /* Value is in Mb or MB (base 10). */
20584 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
20585 (UINT32_C(0x0) << 29)
20586 /* Value is in Kb or KB (base 10). */
20587 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
20588 (UINT32_C(0x2) << 29)
20589 /* Value is in bits or bytes. */
20590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
20591 (UINT32_C(0x4) << 29)
20592 /* Value is in Gb or GB (base 10). */
20593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
20594 (UINT32_C(0x6) << 29)
20595 /* Value is in 1/100th of a percentage of total bandwidth. */
20596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20597 (UINT32_C(0x1) << 29)
20599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
20600 (UINT32_C(0x7) << 29)
20601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
20602 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
20603 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20604 uint8_t queue_id4_tsa_assign;
20605 /* Strict Priority */
20606 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
20608 /* Enhanced Transmission Selection */
20609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
20612 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
20615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
20618 * Priority level for strict priority. Valid only when the
20619 * tsa_assign is 0 - Strict Priority (SP)
20620 * 0..7 - Valid values.
20621 * 8..255 - Reserved.
20623 uint8_t queue_id4_pri_lvl;
20625 * Weight used to allocate remaining BW for this COS after
20626 * servicing guaranteed bandwidths for all COS.
20628 uint8_t queue_id4_bw_weight;
20629 /* ID of CoS Queue 5. */
20632 * Minimum BW allocated to CoS Queue.
20633 * The HWRM will translate this value into byte counter and
20634 * time interval used for this COS inside the device.
20636 uint32_t queue_id5_min_bw;
20637 /* The bandwidth value. */
20638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
20639 UINT32_C(0xfffffff)
20640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
20642 /* The granularity of the value (bits or bytes). */
20643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
20644 UINT32_C(0x10000000)
20645 /* Value is in bits. */
20646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
20647 (UINT32_C(0x0) << 28)
20648 /* Value is in bytes. */
20649 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
20650 (UINT32_C(0x1) << 28)
20651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
20652 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
20653 /* bw_value_unit is 3 b */
20654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
20655 UINT32_C(0xe0000000)
20656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
20658 /* Value is in Mb or MB (base 10). */
20659 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
20660 (UINT32_C(0x0) << 29)
20661 /* Value is in Kb or KB (base 10). */
20662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
20663 (UINT32_C(0x2) << 29)
20664 /* Value is in bits or bytes. */
20665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
20666 (UINT32_C(0x4) << 29)
20667 /* Value is in Gb or GB (base 10). */
20668 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
20669 (UINT32_C(0x6) << 29)
20670 /* Value is in 1/100th of a percentage of total bandwidth. */
20671 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20672 (UINT32_C(0x1) << 29)
20674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
20675 (UINT32_C(0x7) << 29)
20676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
20677 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
20679 * Maximum BW allocated to CoS queue.
20680 * The HWRM will translate this value into byte counter and
20681 * time interval used for this COS inside the device.
20683 uint32_t queue_id5_max_bw;
20684 /* The bandwidth value. */
20685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
20686 UINT32_C(0xfffffff)
20687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
20689 /* The granularity of the value (bits or bytes). */
20690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
20691 UINT32_C(0x10000000)
20692 /* Value is in bits. */
20693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
20694 (UINT32_C(0x0) << 28)
20695 /* Value is in bytes. */
20696 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
20697 (UINT32_C(0x1) << 28)
20698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
20699 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
20700 /* bw_value_unit is 3 b */
20701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
20702 UINT32_C(0xe0000000)
20703 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
20705 /* Value is in Mb or MB (base 10). */
20706 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
20707 (UINT32_C(0x0) << 29)
20708 /* Value is in Kb or KB (base 10). */
20709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
20710 (UINT32_C(0x2) << 29)
20711 /* Value is in bits or bytes. */
20712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
20713 (UINT32_C(0x4) << 29)
20714 /* Value is in Gb or GB (base 10). */
20715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
20716 (UINT32_C(0x6) << 29)
20717 /* Value is in 1/100th of a percentage of total bandwidth. */
20718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20719 (UINT32_C(0x1) << 29)
20721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
20722 (UINT32_C(0x7) << 29)
20723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
20724 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
20725 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20726 uint8_t queue_id5_tsa_assign;
20727 /* Strict Priority */
20728 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
20730 /* Enhanced Transmission Selection */
20731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
20734 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
20737 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
20740 * Priority level for strict priority. Valid only when the
20741 * tsa_assign is 0 - Strict Priority (SP)
20742 * 0..7 - Valid values.
20743 * 8..255 - Reserved.
20745 uint8_t queue_id5_pri_lvl;
20747 * Weight used to allocate remaining BW for this COS after
20748 * servicing guaranteed bandwidths for all COS.
20750 uint8_t queue_id5_bw_weight;
20751 /* ID of CoS Queue 6. */
20754 * Minimum BW allocated to CoS Queue.
20755 * The HWRM will translate this value into byte counter and
20756 * time interval used for this COS inside the device.
20758 uint32_t queue_id6_min_bw;
20759 /* The bandwidth value. */
20760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
20761 UINT32_C(0xfffffff)
20762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
20764 /* The granularity of the value (bits or bytes). */
20765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
20766 UINT32_C(0x10000000)
20767 /* Value is in bits. */
20768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
20769 (UINT32_C(0x0) << 28)
20770 /* Value is in bytes. */
20771 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
20772 (UINT32_C(0x1) << 28)
20773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
20774 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
20775 /* bw_value_unit is 3 b */
20776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
20777 UINT32_C(0xe0000000)
20778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
20780 /* Value is in Mb or MB (base 10). */
20781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
20782 (UINT32_C(0x0) << 29)
20783 /* Value is in Kb or KB (base 10). */
20784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
20785 (UINT32_C(0x2) << 29)
20786 /* Value is in bits or bytes. */
20787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
20788 (UINT32_C(0x4) << 29)
20789 /* Value is in Gb or GB (base 10). */
20790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
20791 (UINT32_C(0x6) << 29)
20792 /* Value is in 1/100th of a percentage of total bandwidth. */
20793 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20794 (UINT32_C(0x1) << 29)
20796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
20797 (UINT32_C(0x7) << 29)
20798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
20799 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
20801 * Maximum BW allocated to CoS queue.
20802 * The HWRM will translate this value into byte counter and
20803 * time interval used for this COS inside the device.
20805 uint32_t queue_id6_max_bw;
20806 /* The bandwidth value. */
20807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
20808 UINT32_C(0xfffffff)
20809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
20811 /* The granularity of the value (bits or bytes). */
20812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
20813 UINT32_C(0x10000000)
20814 /* Value is in bits. */
20815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
20816 (UINT32_C(0x0) << 28)
20817 /* Value is in bytes. */
20818 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
20819 (UINT32_C(0x1) << 28)
20820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
20821 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
20822 /* bw_value_unit is 3 b */
20823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
20824 UINT32_C(0xe0000000)
20825 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
20827 /* Value is in Mb or MB (base 10). */
20828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
20829 (UINT32_C(0x0) << 29)
20830 /* Value is in Kb or KB (base 10). */
20831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
20832 (UINT32_C(0x2) << 29)
20833 /* Value is in bits or bytes. */
20834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
20835 (UINT32_C(0x4) << 29)
20836 /* Value is in Gb or GB (base 10). */
20837 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
20838 (UINT32_C(0x6) << 29)
20839 /* Value is in 1/100th of a percentage of total bandwidth. */
20840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20841 (UINT32_C(0x1) << 29)
20843 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
20844 (UINT32_C(0x7) << 29)
20845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
20846 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
20847 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20848 uint8_t queue_id6_tsa_assign;
20849 /* Strict Priority */
20850 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
20852 /* Enhanced Transmission Selection */
20853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
20856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
20859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
20862 * Priority level for strict priority. Valid only when the
20863 * tsa_assign is 0 - Strict Priority (SP)
20864 * 0..7 - Valid values.
20865 * 8..255 - Reserved.
20867 uint8_t queue_id6_pri_lvl;
20869 * Weight used to allocate remaining BW for this COS after
20870 * servicing guaranteed bandwidths for all COS.
20872 uint8_t queue_id6_bw_weight;
20873 /* ID of CoS Queue 7. */
20876 * Minimum BW allocated to CoS Queue.
20877 * The HWRM will translate this value into byte counter and
20878 * time interval used for this COS inside the device.
20880 uint32_t queue_id7_min_bw;
20881 /* The bandwidth value. */
20882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
20883 UINT32_C(0xfffffff)
20884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
20886 /* The granularity of the value (bits or bytes). */
20887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
20888 UINT32_C(0x10000000)
20889 /* Value is in bits. */
20890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
20891 (UINT32_C(0x0) << 28)
20892 /* Value is in bytes. */
20893 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
20894 (UINT32_C(0x1) << 28)
20895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
20896 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
20897 /* bw_value_unit is 3 b */
20898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
20899 UINT32_C(0xe0000000)
20900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
20902 /* Value is in Mb or MB (base 10). */
20903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
20904 (UINT32_C(0x0) << 29)
20905 /* Value is in Kb or KB (base 10). */
20906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
20907 (UINT32_C(0x2) << 29)
20908 /* Value is in bits or bytes. */
20909 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
20910 (UINT32_C(0x4) << 29)
20911 /* Value is in Gb or GB (base 10). */
20912 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
20913 (UINT32_C(0x6) << 29)
20914 /* Value is in 1/100th of a percentage of total bandwidth. */
20915 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20916 (UINT32_C(0x1) << 29)
20918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
20919 (UINT32_C(0x7) << 29)
20920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
20921 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
20923 * Maximum BW allocated to CoS queue.
20924 * The HWRM will translate this value into byte counter and
20925 * time interval used for this COS inside the device.
20927 uint32_t queue_id7_max_bw;
20928 /* The bandwidth value. */
20929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
20930 UINT32_C(0xfffffff)
20931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
20933 /* The granularity of the value (bits or bytes). */
20934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
20935 UINT32_C(0x10000000)
20936 /* Value is in bits. */
20937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
20938 (UINT32_C(0x0) << 28)
20939 /* Value is in bytes. */
20940 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
20941 (UINT32_C(0x1) << 28)
20942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
20943 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
20944 /* bw_value_unit is 3 b */
20945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
20946 UINT32_C(0xe0000000)
20947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
20949 /* Value is in Mb or MB (base 10). */
20950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
20951 (UINT32_C(0x0) << 29)
20952 /* Value is in Kb or KB (base 10). */
20953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
20954 (UINT32_C(0x2) << 29)
20955 /* Value is in bits or bytes. */
20956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
20957 (UINT32_C(0x4) << 29)
20958 /* Value is in Gb or GB (base 10). */
20959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
20960 (UINT32_C(0x6) << 29)
20961 /* Value is in 1/100th of a percentage of total bandwidth. */
20962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20963 (UINT32_C(0x1) << 29)
20965 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
20966 (UINT32_C(0x7) << 29)
20967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
20968 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
20969 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20970 uint8_t queue_id7_tsa_assign;
20971 /* Strict Priority */
20972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
20974 /* Enhanced Transmission Selection */
20975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
20978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
20981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
20984 * Priority level for strict priority. Valid only when the
20985 * tsa_assign is 0 - Strict Priority (SP)
20986 * 0..7 - Valid values.
20987 * 8..255 - Reserved.
20989 uint8_t queue_id7_pri_lvl;
20991 * Weight used to allocate remaining BW for this COS after
20992 * servicing guaranteed bandwidths for all COS.
20994 uint8_t queue_id7_bw_weight;
20995 uint8_t unused_1[5];
20996 } __attribute__((packed));
20998 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
20999 struct hwrm_queue_cos2bw_cfg_output {
21000 /* The specific error status for the command. */
21001 uint16_t error_code;
21002 /* The HWRM command request type. */
21004 /* The sequence ID from the original command. */
21006 /* The length of the response data in number of bytes. */
21008 uint8_t unused_0[7];
21010 * This field is used in Output records to indicate that the output
21011 * is completely written to RAM. This field should be read as '1'
21012 * to indicate that the output has been completely written.
21013 * When writing a command completion or response to an internal processor,
21014 * the order of writes has to be such that this field is written last.
21017 } __attribute__((packed));
21019 /*******************
21020 * hwrm_vnic_alloc *
21021 *******************/
21024 /* hwrm_vnic_alloc_input (size:192b/24B) */
21025 struct hwrm_vnic_alloc_input {
21026 /* The HWRM command request type. */
21029 * The completion ring to send the completion event on. This should
21030 * be the NQ ID returned from the `nq_alloc` HWRM command.
21032 uint16_t cmpl_ring;
21034 * The sequence ID is used by the driver for tracking multiple
21035 * commands. This ID is treated as opaque data by the firmware and
21036 * the value is returned in the `hwrm_resp_hdr` upon completion.
21040 * The target ID of the command:
21041 * * 0x0-0xFFF8 - The function ID
21042 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21043 * * 0xFFFD - Reserved for user-space HWRM interface
21046 uint16_t target_id;
21048 * A physical address pointer pointing to a host buffer that the
21049 * command's response data will be written. This can be either a host
21050 * physical address (HPA) or a guest physical address (GPA) and must
21051 * point to a physically contiguous block of memory.
21053 uint64_t resp_addr;
21056 * When this bit is '1', this VNIC is requested to
21057 * be the default VNIC for this function.
21059 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
21060 uint8_t unused_0[4];
21061 } __attribute__((packed));
21063 /* hwrm_vnic_alloc_output (size:128b/16B) */
21064 struct hwrm_vnic_alloc_output {
21065 /* The specific error status for the command. */
21066 uint16_t error_code;
21067 /* The HWRM command request type. */
21069 /* The sequence ID from the original command. */
21071 /* The length of the response data in number of bytes. */
21073 /* Logical vnic ID */
21075 uint8_t unused_0[3];
21077 * This field is used in Output records to indicate that the output
21078 * is completely written to RAM. This field should be read as '1'
21079 * to indicate that the output has been completely written.
21080 * When writing a command completion or response to an internal processor,
21081 * the order of writes has to be such that this field is written last.
21084 } __attribute__((packed));
21086 /******************
21088 ******************/
21091 /* hwrm_vnic_free_input (size:192b/24B) */
21092 struct hwrm_vnic_free_input {
21093 /* The HWRM command request type. */
21096 * The completion ring to send the completion event on. This should
21097 * be the NQ ID returned from the `nq_alloc` HWRM command.
21099 uint16_t cmpl_ring;
21101 * The sequence ID is used by the driver for tracking multiple
21102 * commands. This ID is treated as opaque data by the firmware and
21103 * the value is returned in the `hwrm_resp_hdr` upon completion.
21107 * The target ID of the command:
21108 * * 0x0-0xFFF8 - The function ID
21109 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21110 * * 0xFFFD - Reserved for user-space HWRM interface
21113 uint16_t target_id;
21115 * A physical address pointer pointing to a host buffer that the
21116 * command's response data will be written. This can be either a host
21117 * physical address (HPA) or a guest physical address (GPA) and must
21118 * point to a physically contiguous block of memory.
21120 uint64_t resp_addr;
21121 /* Logical vnic ID */
21123 uint8_t unused_0[4];
21124 } __attribute__((packed));
21126 /* hwrm_vnic_free_output (size:128b/16B) */
21127 struct hwrm_vnic_free_output {
21128 /* The specific error status for the command. */
21129 uint16_t error_code;
21130 /* The HWRM command request type. */
21132 /* The sequence ID from the original command. */
21134 /* The length of the response data in number of bytes. */
21136 uint8_t unused_0[7];
21138 * This field is used in Output records to indicate that the output
21139 * is completely written to RAM. This field should be read as '1'
21140 * to indicate that the output has been completely written.
21141 * When writing a command completion or response to an internal processor,
21142 * the order of writes has to be such that this field is written last.
21145 } __attribute__((packed));
21152 /* hwrm_vnic_cfg_input (size:320b/40B) */
21153 struct hwrm_vnic_cfg_input {
21154 /* The HWRM command request type. */
21157 * The completion ring to send the completion event on. This should
21158 * be the NQ ID returned from the `nq_alloc` HWRM command.
21160 uint16_t cmpl_ring;
21162 * The sequence ID is used by the driver for tracking multiple
21163 * commands. This ID is treated as opaque data by the firmware and
21164 * the value is returned in the `hwrm_resp_hdr` upon completion.
21168 * The target ID of the command:
21169 * * 0x0-0xFFF8 - The function ID
21170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21171 * * 0xFFFD - Reserved for user-space HWRM interface
21174 uint16_t target_id;
21176 * A physical address pointer pointing to a host buffer that the
21177 * command's response data will be written. This can be either a host
21178 * physical address (HPA) or a guest physical address (GPA) and must
21179 * point to a physically contiguous block of memory.
21181 uint64_t resp_addr;
21184 * When this bit is '1', the VNIC is requested to
21185 * be the default VNIC for the function.
21187 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
21190 * When this bit is '1', the VNIC is being configured to
21191 * strip VLAN in the RX path.
21192 * If set to '0', then VLAN stripping is disabled on
21195 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
21198 * When this bit is '1', the VNIC is being configured to
21199 * buffer receive packets in the hardware until the host
21200 * posts new receive buffers.
21201 * If set to '0', then bd_stall is being configured to be
21202 * disabled on this VNIC.
21204 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
21207 * When this bit is '1', the VNIC is being configured to
21208 * receive both RoCE and non-RoCE traffic.
21209 * If set to '0', then this VNIC is not configured to be
21210 * operating in dual VNIC mode.
21212 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
21215 * When this flag is set to '1', the VNIC is requested to
21216 * be configured to receive only RoCE traffic.
21217 * If this flag is set to '0', then this flag shall be
21218 * ignored by the HWRM.
21219 * If roce_dual_vnic_mode flag is set to '1'
21220 * or roce_mirroring_capable_vnic_mode flag to 1,
21221 * then the HWRM client shall not set this flag to '1'.
21223 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
21226 * When a VNIC uses one destination ring group for certain
21227 * application (e.g. Receive Flow Steering) where
21228 * exact match is used to direct packets to a VNIC with one
21229 * destination ring group only, there is no need to configure
21230 * RSS indirection table for that VNIC as only one destination
21231 * ring group is used.
21233 * This flag is used to enable a mode where
21234 * RSS is enabled in the VNIC using a RSS context
21235 * for computing RSS hash but the RSS indirection table is
21236 * not configured using hwrm_vnic_rss_cfg.
21238 * If this mode is enabled, then the driver should not program
21239 * RSS indirection table for the RSS context that is used for
21240 * computing RSS hash only.
21242 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
21245 * When this bit is '1', the VNIC is being configured to
21246 * receive both RoCE and non-RoCE traffic, but forward only the
21247 * RoCE traffic further. Also, RoCE traffic can be mirrored to
21250 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
21254 * This bit must be '1' for the dflt_ring_grp field to be
21257 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
21260 * This bit must be '1' for the rss_rule field to be
21263 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
21266 * This bit must be '1' for the cos_rule field to be
21269 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
21272 * This bit must be '1' for the lb_rule field to be
21275 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
21278 * This bit must be '1' for the mru field to be
21281 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
21284 * This bit must be '1' for the default_rx_ring_id field to be
21287 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
21290 * This bit must be '1' for the default_cmpl_ring_id field to be
21293 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
21295 /* Logical vnic ID */
21298 * Default Completion ring for the VNIC. This ring will
21299 * be chosen if packet does not match any RSS rules and if
21300 * there is no COS rule.
21302 uint16_t dflt_ring_grp;
21304 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
21305 * there is no RSS rule.
21309 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
21310 * there is no COS rule.
21314 * RSS ID for load balancing rule/table structure.
21315 * 0xFF... (All Fs) if there is no LB rule.
21319 * The maximum receive unit of the vnic.
21320 * Each vnic is associated with a function.
21321 * The vnic mru value overwrites the mru setting of the
21322 * associated function.
21323 * The HWRM shall make sure that vnic mru does not exceed
21324 * the mru of the port the function is associated with.
21328 * Default Rx ring for the VNIC. This ring will
21329 * be chosen if packet does not match any RSS rules.
21330 * The aggregation ring associated with the Rx ring is
21331 * implied based on the Rx ring specified when the
21332 * aggregation ring was allocated.
21334 uint16_t default_rx_ring_id;
21336 * Default completion ring for the VNIC. This ring will
21337 * be chosen if packet does not match any RSS rules.
21339 uint16_t default_cmpl_ring_id;
21340 } __attribute__((packed));
21342 /* hwrm_vnic_cfg_output (size:128b/16B) */
21343 struct hwrm_vnic_cfg_output {
21344 /* The specific error status for the command. */
21345 uint16_t error_code;
21346 /* The HWRM command request type. */
21348 /* The sequence ID from the original command. */
21350 /* The length of the response data in number of bytes. */
21352 uint8_t unused_0[7];
21354 * This field is used in Output records to indicate that the output
21355 * is completely written to RAM. This field should be read as '1'
21356 * to indicate that the output has been completely written.
21357 * When writing a command completion or response to an internal processor,
21358 * the order of writes has to be such that this field is written last.
21361 } __attribute__((packed));
21363 /******************
21365 ******************/
21368 /* hwrm_vnic_qcfg_input (size:256b/32B) */
21369 struct hwrm_vnic_qcfg_input {
21370 /* The HWRM command request type. */
21373 * The completion ring to send the completion event on. This should
21374 * be the NQ ID returned from the `nq_alloc` HWRM command.
21376 uint16_t cmpl_ring;
21378 * The sequence ID is used by the driver for tracking multiple
21379 * commands. This ID is treated as opaque data by the firmware and
21380 * the value is returned in the `hwrm_resp_hdr` upon completion.
21384 * The target ID of the command:
21385 * * 0x0-0xFFF8 - The function ID
21386 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21387 * * 0xFFFD - Reserved for user-space HWRM interface
21390 uint16_t target_id;
21392 * A physical address pointer pointing to a host buffer that the
21393 * command's response data will be written. This can be either a host
21394 * physical address (HPA) or a guest physical address (GPA) and must
21395 * point to a physically contiguous block of memory.
21397 uint64_t resp_addr;
21400 * This bit must be '1' for the vf_id_valid field to be
21403 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
21404 /* Logical vnic ID */
21406 /* ID of Virtual Function whose VNIC resource is being queried. */
21408 uint8_t unused_0[6];
21409 } __attribute__((packed));
21411 /* hwrm_vnic_qcfg_output (size:256b/32B) */
21412 struct hwrm_vnic_qcfg_output {
21413 /* The specific error status for the command. */
21414 uint16_t error_code;
21415 /* The HWRM command request type. */
21417 /* The sequence ID from the original command. */
21419 /* The length of the response data in number of bytes. */
21421 /* Default Completion ring for the VNIC. */
21422 uint16_t dflt_ring_grp;
21424 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
21425 * there is no RSS rule.
21429 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
21430 * there is no COS rule.
21434 * RSS ID for load balancing rule/table structure.
21435 * 0xFF... (All Fs) if there is no LB rule.
21438 /* The maximum receive unit of the vnic. */
21440 uint8_t unused_0[2];
21443 * When this bit is '1', the VNIC is the default VNIC for
21446 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
21449 * When this bit is '1', the VNIC is configured to
21450 * strip VLAN in the RX path.
21451 * If set to '0', then VLAN stripping is disabled on
21454 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
21457 * When this bit is '1', the VNIC is configured to
21458 * buffer receive packets in the hardware until the host
21459 * posts new receive buffers.
21460 * If set to '0', then bd_stall is disabled on
21463 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
21466 * When this bit is '1', the VNIC is configured to
21467 * receive both RoCE and non-RoCE traffic.
21468 * If set to '0', then this VNIC is not configured to
21469 * operate in dual VNIC mode.
21471 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
21474 * When this flag is set to '1', the VNIC is configured to
21475 * receive only RoCE traffic.
21476 * When this flag is set to '0', the VNIC is not configured
21477 * to receive only RoCE traffic.
21478 * If roce_dual_vnic_mode flag and this flag both are set
21479 * to '1', then it is an invalid configuration of the
21480 * VNIC. The HWRM should not allow that type of
21481 * mis-configuration by HWRM clients.
21483 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
21486 * When a VNIC uses one destination ring group for certain
21487 * application (e.g. Receive Flow Steering) where
21488 * exact match is used to direct packets to a VNIC with one
21489 * destination ring group only, there is no need to configure
21490 * RSS indirection table for that VNIC as only one destination
21491 * ring group is used.
21493 * When this bit is set to '1', then the VNIC is enabled in a
21494 * mode where RSS is enabled in the VNIC using a RSS context
21495 * for computing RSS hash but the RSS indirection table is
21498 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
21501 * When this bit is '1', the VNIC is configured to
21502 * receive both RoCE and non-RoCE traffic, but forward only
21503 * RoCE traffic further. Also RoCE traffic can be mirrored to
21506 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
21508 uint8_t unused_1[7];
21510 * This field is used in Output records to indicate that the output
21511 * is completely written to RAM. This field should be read as '1'
21512 * to indicate that the output has been completely written.
21513 * When writing a command completion or response to an internal processor,
21514 * the order of writes has to be such that this field is written last.
21517 } __attribute__((packed));
21519 /*******************
21520 * hwrm_vnic_qcaps *
21521 *******************/
21524 /* hwrm_vnic_qcaps_input (size:192b/24B) */
21525 struct hwrm_vnic_qcaps_input {
21526 /* The HWRM command request type. */
21529 * The completion ring to send the completion event on. This should
21530 * be the NQ ID returned from the `nq_alloc` HWRM command.
21532 uint16_t cmpl_ring;
21534 * The sequence ID is used by the driver for tracking multiple
21535 * commands. This ID is treated as opaque data by the firmware and
21536 * the value is returned in the `hwrm_resp_hdr` upon completion.
21540 * The target ID of the command:
21541 * * 0x0-0xFFF8 - The function ID
21542 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21543 * * 0xFFFD - Reserved for user-space HWRM interface
21546 uint16_t target_id;
21548 * A physical address pointer pointing to a host buffer that the
21549 * command's response data will be written. This can be either a host
21550 * physical address (HPA) or a guest physical address (GPA) and must
21551 * point to a physically contiguous block of memory.
21553 uint64_t resp_addr;
21555 uint8_t unused_0[4];
21556 } __attribute__((packed));
21558 /* hwrm_vnic_qcaps_output (size:192b/24B) */
21559 struct hwrm_vnic_qcaps_output {
21560 /* The specific error status for the command. */
21561 uint16_t error_code;
21562 /* The HWRM command request type. */
21564 /* The sequence ID from the original command. */
21566 /* The length of the response data in number of bytes. */
21568 /* The maximum receive unit that is settable on a vnic. */
21570 uint8_t unused_0[2];
21573 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
21576 * When this bit is '1', the capability of stripping VLAN in
21577 * the RX path is supported on VNIC(s).
21578 * If set to '0', then VLAN stripping capability is
21579 * not supported on VNIC(s).
21581 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
21584 * When this bit is '1', the capability to buffer receive
21585 * packets in the hardware until the host posts new receive buffers
21586 * is supported on VNIC(s).
21587 * If set to '0', then bd_stall capability is not supported
21590 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
21593 * When this bit is '1', the capability to
21594 * receive both RoCE and non-RoCE traffic on VNIC(s) is
21596 * If set to '0', then the capability to receive
21597 * both RoCE and non-RoCE traffic on VNIC(s) is
21600 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
21603 * When this bit is set to '1', the capability to configure
21604 * a VNIC to receive only RoCE traffic is supported.
21605 * When this flag is set to '0', the VNIC capability to
21606 * configure to receive only RoCE traffic is not supported.
21608 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
21611 * When this bit is set to '1', then the capability to enable
21612 * a VNIC in a mode where RSS context without configuring
21613 * RSS indirection table is supported (for RSS hash computation).
21614 * When this bit is set to '0', then a VNIC can not be configured
21615 * with a mode to enable RSS context without configuring RSS
21616 * indirection table.
21618 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
21621 * When this bit is '1', the capability to
21622 * mirror the the RoCE traffic is supported.
21623 * If set to '0', then the capability to mirror the
21624 * RoCE traffic is not supported.
21626 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
21629 * When this bit is '1', the outermost RSS hashing capability
21630 * is supported. If set to '0', then the outermost RSS hashing
21631 * capability is not supported.
21633 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
21636 * This field advertises the maximum concurrent TPA aggregations
21637 * supported by the VNIC on new devices that support TPA v2.
21638 * '0' means that TPA v2 is not supported.
21640 uint16_t max_aggs_supported;
21641 uint8_t unused_1[5];
21643 * This field is used in Output records to indicate that the output
21644 * is completely written to RAM. This field should be read as '1'
21645 * to indicate that the output has been completely written.
21646 * When writing a command completion or response to an internal processor,
21647 * the order of writes has to be such that this field is written last.
21650 } __attribute__((packed));
21652 /*********************
21653 * hwrm_vnic_tpa_cfg *
21654 *********************/
21657 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
21658 struct hwrm_vnic_tpa_cfg_input {
21659 /* The HWRM command request type. */
21662 * The completion ring to send the completion event on. This should
21663 * be the NQ ID returned from the `nq_alloc` HWRM command.
21665 uint16_t cmpl_ring;
21667 * The sequence ID is used by the driver for tracking multiple
21668 * commands. This ID is treated as opaque data by the firmware and
21669 * the value is returned in the `hwrm_resp_hdr` upon completion.
21673 * The target ID of the command:
21674 * * 0x0-0xFFF8 - The function ID
21675 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21676 * * 0xFFFD - Reserved for user-space HWRM interface
21679 uint16_t target_id;
21681 * A physical address pointer pointing to a host buffer that the
21682 * command's response data will be written. This can be either a host
21683 * physical address (HPA) or a guest physical address (GPA) and must
21684 * point to a physically contiguous block of memory.
21686 uint64_t resp_addr;
21689 * When this bit is '1', the VNIC shall be configured to
21690 * perform transparent packet aggregation (TPA) of
21691 * non-tunneled TCP packets.
21693 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
21696 * When this bit is '1', the VNIC shall be configured to
21697 * perform transparent packet aggregation (TPA) of
21698 * tunneled TCP packets.
21700 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
21703 * When this bit is '1', the VNIC shall be configured to
21704 * perform transparent packet aggregation (TPA) according
21705 * to Windows Receive Segment Coalescing (RSC) rules.
21707 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
21710 * When this bit is '1', the VNIC shall be configured to
21711 * perform transparent packet aggregation (TPA) according
21712 * to Linux Generic Receive Offload (GRO) rules.
21714 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
21717 * When this bit is '1', the VNIC shall be configured to
21718 * perform transparent packet aggregation (TPA) for TCP
21719 * packets with IP ECN set to non-zero.
21721 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
21724 * When this bit is '1', the VNIC shall be configured to
21725 * perform transparent packet aggregation (TPA) for
21726 * GRE tunneled TCP packets only if all packets have the
21727 * same GRE sequence.
21729 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
21732 * When this bit is '1' and the GRO mode is enabled,
21733 * the VNIC shall be configured to
21734 * perform transparent packet aggregation (TPA) for
21735 * TCP/IPv4 packets with consecutively increasing IPIDs.
21736 * In other words, the last packet that is being
21737 * aggregated to an already existing aggregation context
21738 * shall have IPID 1 more than the IPID of the last packet
21739 * that was aggregated in that aggregation context.
21741 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
21744 * When this bit is '1' and the GRO mode is enabled,
21745 * the VNIC shall be configured to
21746 * perform transparent packet aggregation (TPA) for
21747 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
21750 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
21753 * When this bit is '1' and the GRO mode is enabled,
21754 * the VNIC shall DMA payload data using GRO rules.
21755 * When this bit is '0', the VNIC shall DMA payload data
21756 * using the more efficient LRO rules of filling all
21757 * aggregation buffers.
21759 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
21763 * This bit must be '1' for the max_agg_segs field to be
21766 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
21768 * This bit must be '1' for the max_aggs field to be
21771 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
21773 * This bit must be '1' for the max_agg_timer field to be
21776 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
21777 /* deprecated bit. Do not use!!! */
21778 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
21779 /* Logical vnic ID */
21782 * This is the maximum number of TCP segments that can
21783 * be aggregated (unit is Log2). Max value is 31. On new
21784 * devices supporting TPA v2, the unit is multiples of 4 and
21785 * valid values are > 0 and <= 63.
21787 uint16_t max_agg_segs;
21789 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
21791 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
21793 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
21795 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
21796 /* Any segment size larger than this is not valid */
21797 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
21798 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
21799 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
21801 * This is the maximum number of aggregations this VNIC is
21802 * allowed (unit is Log2). Max value is 7. On new devices
21803 * supporting TPA v2, this is in unit of 1 and must be > 0
21804 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
21805 * to enable TPA v2.
21808 /* 1 aggregation */
21809 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
21810 /* 2 aggregations */
21811 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
21812 /* 4 aggregations */
21813 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
21814 /* 8 aggregations */
21815 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
21816 /* 16 aggregations */
21817 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
21818 /* Any aggregation size larger than this is not valid */
21819 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
21820 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
21821 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
21822 uint8_t unused_0[2];
21824 * This is the maximum amount of time allowed for
21825 * an aggregation context to complete after it was initiated.
21827 uint32_t max_agg_timer;
21829 * This is the minimum amount of payload length required to
21830 * start an aggregation context. This field is deprecated and
21831 * should be set to 0. The minimum length is set by firmware
21832 * and can be queried using hwrm_vnic_tpa_qcfg.
21834 uint32_t min_agg_len;
21835 } __attribute__((packed));
21837 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
21838 struct hwrm_vnic_tpa_cfg_output {
21839 /* The specific error status for the command. */
21840 uint16_t error_code;
21841 /* The HWRM command request type. */
21843 /* The sequence ID from the original command. */
21845 /* The length of the response data in number of bytes. */
21847 uint8_t unused_0[7];
21849 * This field is used in Output records to indicate that the output
21850 * is completely written to RAM. This field should be read as '1'
21851 * to indicate that the output has been completely written.
21852 * When writing a command completion or response to an internal processor,
21853 * the order of writes has to be such that this field is written last.
21856 } __attribute__((packed));
21858 /*********************
21859 * hwrm_vnic_rss_cfg *
21860 *********************/
21863 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
21864 struct hwrm_vnic_rss_cfg_input {
21865 /* The HWRM command request type. */
21868 * The completion ring to send the completion event on. This should
21869 * be the NQ ID returned from the `nq_alloc` HWRM command.
21871 uint16_t cmpl_ring;
21873 * The sequence ID is used by the driver for tracking multiple
21874 * commands. This ID is treated as opaque data by the firmware and
21875 * the value is returned in the `hwrm_resp_hdr` upon completion.
21879 * The target ID of the command:
21880 * * 0x0-0xFFF8 - The function ID
21881 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21882 * * 0xFFFD - Reserved for user-space HWRM interface
21885 uint16_t target_id;
21887 * A physical address pointer pointing to a host buffer that the
21888 * command's response data will be written. This can be either a host
21889 * physical address (HPA) or a guest physical address (GPA) and must
21890 * point to a physically contiguous block of memory.
21892 uint64_t resp_addr;
21893 uint32_t hash_type;
21895 * When this bit is '1', the RSS hash shall be computed
21896 * over source and destination IPv4 addresses of IPv4
21899 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
21901 * When this bit is '1', the RSS hash shall be computed
21902 * over source/destination IPv4 addresses and
21903 * source/destination ports of TCP/IPv4 packets.
21905 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
21907 * When this bit is '1', the RSS hash shall be computed
21908 * over source/destination IPv4 addresses and
21909 * source/destination ports of UDP/IPv4 packets.
21911 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
21913 * When this bit is '1', the RSS hash shall be computed
21914 * over source and destination IPv4 addresses of IPv6
21917 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
21919 * When this bit is '1', the RSS hash shall be computed
21920 * over source/destination IPv6 addresses and
21921 * source/destination ports of TCP/IPv6 packets.
21923 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
21925 * When this bit is '1', the RSS hash shall be computed
21926 * over source/destination IPv6 addresses and
21927 * source/destination ports of UDP/IPv6 packets.
21929 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
21930 /* VNIC ID of VNIC associated with RSS table being configured. */
21933 * Specifies which VNIC ring table pair to configure.
21934 * Valid values range from 0 to 7.
21936 uint8_t ring_table_pair_index;
21937 /* Flags to specify different RSS hash modes. */
21938 uint8_t hash_mode_flags;
21940 * When this bit is '1', it indicates using current RSS
21941 * hash mode setting configured in the device.
21943 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
21946 * When this bit is '1', it indicates requesting support of
21947 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
21948 * l4.src, l4.dest} for tunnel packets. For none-tunnel
21949 * packets, the RSS hash is computed over the normal
21950 * src/dest l3 and src/dest l4 headers.
21952 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
21955 * When this bit is '1', it indicates requesting support of
21956 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
21957 * tunnel packets. For none-tunnel packets, the RSS hash is
21958 * computed over the normal src/dest l3 headers.
21960 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
21963 * When this bit is '1', it indicates requesting support of
21964 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
21965 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
21966 * packets, the RSS hash is computed over the normal
21967 * src/dest l3 and src/dest l4 headers.
21969 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
21972 * When this bit is '1', it indicates requesting support of
21973 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
21974 * tunnel packets. For none-tunnel packets, the RSS hash is
21975 * computed over the normal src/dest l3 headers.
21977 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
21979 /* This is the address for rss ring group table */
21980 uint64_t ring_grp_tbl_addr;
21981 /* This is the address for rss hash key table */
21982 uint64_t hash_key_tbl_addr;
21983 /* Index to the rss indirection table. */
21984 uint16_t rss_ctx_idx;
21985 uint8_t unused_1[6];
21986 } __attribute__((packed));
21988 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
21989 struct hwrm_vnic_rss_cfg_output {
21990 /* The specific error status for the command. */
21991 uint16_t error_code;
21992 /* The HWRM command request type. */
21994 /* The sequence ID from the original command. */
21996 /* The length of the response data in number of bytes. */
21998 uint8_t unused_0[7];
22000 * This field is used in Output records to indicate that the output
22001 * is completely written to RAM. This field should be read as '1'
22002 * to indicate that the output has been completely written.
22003 * When writing a command completion or response to an internal processor,
22004 * the order of writes has to be such that this field is written last.
22007 } __attribute__((packed));
22009 /**********************
22010 * hwrm_vnic_rss_qcfg *
22011 **********************/
22014 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
22015 struct hwrm_vnic_rss_qcfg_input {
22016 /* The HWRM command request type. */
22019 * The completion ring to send the completion event on. This should
22020 * be the NQ ID returned from the `nq_alloc` HWRM command.
22022 uint16_t cmpl_ring;
22024 * The sequence ID is used by the driver for tracking multiple
22025 * commands. This ID is treated as opaque data by the firmware and
22026 * the value is returned in the `hwrm_resp_hdr` upon completion.
22030 * The target ID of the command:
22031 * * 0x0-0xFFF8 - The function ID
22032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22033 * * 0xFFFD - Reserved for user-space HWRM interface
22036 uint16_t target_id;
22038 * A physical address pointer pointing to a host buffer that the
22039 * command's response data will be written. This can be either a host
22040 * physical address (HPA) or a guest physical address (GPA) and must
22041 * point to a physically contiguous block of memory.
22043 uint64_t resp_addr;
22044 /* Index to the rss indirection table. */
22045 uint16_t rss_ctx_idx;
22046 uint8_t unused_0[6];
22047 } __attribute__((packed));
22049 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
22050 struct hwrm_vnic_rss_qcfg_output {
22051 /* The specific error status for the command. */
22052 uint16_t error_code;
22053 /* The HWRM command request type. */
22055 /* The sequence ID from the original command. */
22057 /* The length of the response data in number of bytes. */
22059 uint32_t hash_type;
22061 * When this bit is '1', the RSS hash shall be computed
22062 * over source and destination IPv4 addresses of IPv4
22065 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
22067 * When this bit is '1', the RSS hash shall be computed
22068 * over source/destination IPv4 addresses and
22069 * source/destination ports of TCP/IPv4 packets.
22071 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
22073 * When this bit is '1', the RSS hash shall be computed
22074 * over source/destination IPv4 addresses and
22075 * source/destination ports of UDP/IPv4 packets.
22077 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
22079 * When this bit is '1', the RSS hash shall be computed
22080 * over source and destination IPv4 addresses of IPv6
22083 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
22085 * When this bit is '1', the RSS hash shall be computed
22086 * over source/destination IPv6 addresses and
22087 * source/destination ports of TCP/IPv6 packets.
22089 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
22091 * When this bit is '1', the RSS hash shall be computed
22092 * over source/destination IPv6 addresses and
22093 * source/destination ports of UDP/IPv6 packets.
22095 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
22096 uint8_t unused_0[4];
22097 /* This is the value of rss hash key */
22098 uint32_t hash_key[10];
22099 /* Flags to specify different RSS hash modes. */
22100 uint8_t hash_mode_flags;
22102 * When this bit is '1', it indicates using current RSS
22103 * hash mode setting configured in the device.
22105 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
22108 * When this bit is '1', it indicates requesting support of
22109 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
22110 * l4.src, l4.dest} for tunnel packets. For none-tunnel
22111 * packets, the RSS hash is computed over the normal
22112 * src/dest l3 and src/dest l4 headers.
22114 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
22117 * When this bit is '1', it indicates requesting support of
22118 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
22119 * tunnel packets. For none-tunnel packets, the RSS hash is
22120 * computed over the normal src/dest l3 headers.
22122 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
22125 * When this bit is '1', it indicates requesting support of
22126 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
22127 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
22128 * packets, the RSS hash is computed over the normal
22129 * src/dest l3 and src/dest l4 headers.
22131 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
22134 * When this bit is '1', it indicates requesting support of
22135 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
22136 * tunnel packets. For none-tunnel packets, the RSS hash is
22137 * computed over the normal src/dest l3 headers.
22139 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
22141 uint8_t unused_1[6];
22143 * This field is used in Output records to indicate that the output
22144 * is completely written to RAM. This field should be read as '1'
22145 * to indicate that the output has been completely written.
22146 * When writing a command completion or response to an internal processor,
22147 * the order of writes has to be such that this field is written last.
22150 } __attribute__((packed));
22152 /**************************
22153 * hwrm_vnic_plcmodes_cfg *
22154 **************************/
22157 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
22158 struct hwrm_vnic_plcmodes_cfg_input {
22159 /* The HWRM command request type. */
22162 * The completion ring to send the completion event on. This should
22163 * be the NQ ID returned from the `nq_alloc` HWRM command.
22165 uint16_t cmpl_ring;
22167 * The sequence ID is used by the driver for tracking multiple
22168 * commands. This ID is treated as opaque data by the firmware and
22169 * the value is returned in the `hwrm_resp_hdr` upon completion.
22173 * The target ID of the command:
22174 * * 0x0-0xFFF8 - The function ID
22175 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22176 * * 0xFFFD - Reserved for user-space HWRM interface
22179 uint16_t target_id;
22181 * A physical address pointer pointing to a host buffer that the
22182 * command's response data will be written. This can be either a host
22183 * physical address (HPA) or a guest physical address (GPA) and must
22184 * point to a physically contiguous block of memory.
22186 uint64_t resp_addr;
22189 * When this bit is '1', the VNIC shall be configured to
22190 * use regular placement algorithm.
22191 * By default, the regular placement algorithm shall be
22192 * enabled on the VNIC.
22194 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
22197 * When this bit is '1', the VNIC shall be configured
22198 * use the jumbo placement algorithm.
22200 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
22203 * When this bit is '1', the VNIC shall be configured
22204 * to enable Header-Data split for IPv4 packets according
22205 * to the following rules:
22206 * # If the packet is identified as TCP/IPv4, then the
22207 * packet is split at the beginning of the TCP payload.
22208 * # If the packet is identified as UDP/IPv4, then the
22209 * packet is split at the beginning of UDP payload.
22210 * # If the packet is identified as non-TCP and non-UDP
22211 * IPv4 packet, then the packet is split at the beginning
22212 * of the upper layer protocol header carried in the IPv4
22215 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
22218 * When this bit is '1', the VNIC shall be configured
22219 * to enable Header-Data split for IPv6 packets according
22220 * to the following rules:
22221 * # If the packet is identified as TCP/IPv6, then the
22222 * packet is split at the beginning of the TCP payload.
22223 * # If the packet is identified as UDP/IPv6, then the
22224 * packet is split at the beginning of UDP payload.
22225 * # If the packet is identified as non-TCP and non-UDP
22226 * IPv6 packet, then the packet is split at the beginning
22227 * of the upper layer protocol header carried in the IPv6
22230 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
22233 * When this bit is '1', the VNIC shall be configured
22234 * to enable Header-Data split for FCoE packets at the
22235 * beginning of FC payload.
22237 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
22240 * When this bit is '1', the VNIC shall be configured
22241 * to enable Header-Data split for RoCE packets at the
22242 * beginning of RoCE payload (after BTH/GRH headers).
22244 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
22248 * This bit must be '1' for the jumbo_thresh_valid field to be
22251 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
22254 * This bit must be '1' for the hds_offset_valid field to be
22257 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
22260 * This bit must be '1' for the hds_threshold_valid field to be
22263 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
22265 /* Logical vnic ID */
22268 * When jumbo placement algorithm is enabled, this value
22269 * is used to determine the threshold for jumbo placement.
22270 * Packets with length larger than this value will be
22271 * placed according to the jumbo placement algorithm.
22273 uint16_t jumbo_thresh;
22275 * This value is used to determine the offset into
22276 * packet buffer where the split data (payload) will be
22277 * placed according to one of of HDS placement algorithm.
22279 * The lengths of packet buffers provided for split data
22280 * shall be larger than this value.
22282 uint16_t hds_offset;
22284 * When one of the HDS placement algorithm is enabled, this
22285 * value is used to determine the threshold for HDS
22287 * Packets with length larger than this value will be
22288 * placed according to the HDS placement algorithm.
22289 * This value shall be in multiple of 4 bytes.
22291 uint16_t hds_threshold;
22292 uint8_t unused_0[6];
22293 } __attribute__((packed));
22295 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
22296 struct hwrm_vnic_plcmodes_cfg_output {
22297 /* The specific error status for the command. */
22298 uint16_t error_code;
22299 /* The HWRM command request type. */
22301 /* The sequence ID from the original command. */
22303 /* The length of the response data in number of bytes. */
22305 uint8_t unused_0[7];
22307 * This field is used in Output records to indicate that the output
22308 * is completely written to RAM. This field should be read as '1'
22309 * to indicate that the output has been completely written.
22310 * When writing a command completion or response to an internal processor,
22311 * the order of writes has to be such that this field is written last.
22314 } __attribute__((packed));
22316 /***************************
22317 * hwrm_vnic_plcmodes_qcfg *
22318 ***************************/
22321 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
22322 struct hwrm_vnic_plcmodes_qcfg_input {
22323 /* The HWRM command request type. */
22326 * The completion ring to send the completion event on. This should
22327 * be the NQ ID returned from the `nq_alloc` HWRM command.
22329 uint16_t cmpl_ring;
22331 * The sequence ID is used by the driver for tracking multiple
22332 * commands. This ID is treated as opaque data by the firmware and
22333 * the value is returned in the `hwrm_resp_hdr` upon completion.
22337 * The target ID of the command:
22338 * * 0x0-0xFFF8 - The function ID
22339 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22340 * * 0xFFFD - Reserved for user-space HWRM interface
22343 uint16_t target_id;
22345 * A physical address pointer pointing to a host buffer that the
22346 * command's response data will be written. This can be either a host
22347 * physical address (HPA) or a guest physical address (GPA) and must
22348 * point to a physically contiguous block of memory.
22350 uint64_t resp_addr;
22351 /* Logical vnic ID */
22353 uint8_t unused_0[4];
22354 } __attribute__((packed));
22356 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
22357 struct hwrm_vnic_plcmodes_qcfg_output {
22358 /* The specific error status for the command. */
22359 uint16_t error_code;
22360 /* The HWRM command request type. */
22362 /* The sequence ID from the original command. */
22364 /* The length of the response data in number of bytes. */
22368 * When this bit is '1', the VNIC is configured to
22369 * use regular placement algorithm.
22371 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
22374 * When this bit is '1', the VNIC is configured to
22375 * use the jumbo placement algorithm.
22377 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
22380 * When this bit is '1', the VNIC is configured
22381 * to enable Header-Data split for IPv4 packets.
22383 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
22386 * When this bit is '1', the VNIC is configured
22387 * to enable Header-Data split for IPv6 packets.
22389 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
22392 * When this bit is '1', the VNIC is configured
22393 * to enable Header-Data split for FCoE packets.
22395 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
22398 * When this bit is '1', the VNIC is configured
22399 * to enable Header-Data split for RoCE packets.
22401 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
22404 * When this bit is '1', the VNIC is configured
22405 * to be the default VNIC of the requesting function.
22407 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
22410 * When jumbo placement algorithm is enabled, this value
22411 * is used to determine the threshold for jumbo placement.
22412 * Packets with length larger than this value will be
22413 * placed according to the jumbo placement algorithm.
22415 uint16_t jumbo_thresh;
22417 * This value is used to determine the offset into
22418 * packet buffer where the split data (payload) will be
22419 * placed according to one of of HDS placement algorithm.
22421 * The lengths of packet buffers provided for split data
22422 * shall be larger than this value.
22424 uint16_t hds_offset;
22426 * When one of the HDS placement algorithm is enabled, this
22427 * value is used to determine the threshold for HDS
22429 * Packets with length larger than this value will be
22430 * placed according to the HDS placement algorithm.
22431 * This value shall be in multiple of 4 bytes.
22433 uint16_t hds_threshold;
22434 uint8_t unused_0[5];
22436 * This field is used in Output records to indicate that the output
22437 * is completely written to RAM. This field should be read as '1'
22438 * to indicate that the output has been completely written.
22439 * When writing a command completion or response to an internal processor,
22440 * the order of writes has to be such that this field is written last.
22443 } __attribute__((packed));
22445 /**********************************
22446 * hwrm_vnic_rss_cos_lb_ctx_alloc *
22447 **********************************/
22450 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
22451 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
22452 /* The HWRM command request type. */
22455 * The completion ring to send the completion event on. This should
22456 * be the NQ ID returned from the `nq_alloc` HWRM command.
22458 uint16_t cmpl_ring;
22460 * The sequence ID is used by the driver for tracking multiple
22461 * commands. This ID is treated as opaque data by the firmware and
22462 * the value is returned in the `hwrm_resp_hdr` upon completion.
22466 * The target ID of the command:
22467 * * 0x0-0xFFF8 - The function ID
22468 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22469 * * 0xFFFD - Reserved for user-space HWRM interface
22472 uint16_t target_id;
22474 * A physical address pointer pointing to a host buffer that the
22475 * command's response data will be written. This can be either a host
22476 * physical address (HPA) or a guest physical address (GPA) and must
22477 * point to a physically contiguous block of memory.
22479 uint64_t resp_addr;
22480 } __attribute__((packed));
22482 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
22483 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
22484 /* The specific error status for the command. */
22485 uint16_t error_code;
22486 /* The HWRM command request type. */
22488 /* The sequence ID from the original command. */
22490 /* The length of the response data in number of bytes. */
22492 /* rss_cos_lb_ctx_id is 16 b */
22493 uint16_t rss_cos_lb_ctx_id;
22494 uint8_t unused_0[5];
22496 * This field is used in Output records to indicate that the output
22497 * is completely written to RAM. This field should be read as '1'
22498 * to indicate that the output has been completely written.
22499 * When writing a command completion or response to an internal processor,
22500 * the order of writes has to be such that this field is written last.
22503 } __attribute__((packed));
22505 /*********************************
22506 * hwrm_vnic_rss_cos_lb_ctx_free *
22507 *********************************/
22510 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
22511 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
22512 /* The HWRM command request type. */
22515 * The completion ring to send the completion event on. This should
22516 * be the NQ ID returned from the `nq_alloc` HWRM command.
22518 uint16_t cmpl_ring;
22520 * The sequence ID is used by the driver for tracking multiple
22521 * commands. This ID is treated as opaque data by the firmware and
22522 * the value is returned in the `hwrm_resp_hdr` upon completion.
22526 * The target ID of the command:
22527 * * 0x0-0xFFF8 - The function ID
22528 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22529 * * 0xFFFD - Reserved for user-space HWRM interface
22532 uint16_t target_id;
22534 * A physical address pointer pointing to a host buffer that the
22535 * command's response data will be written. This can be either a host
22536 * physical address (HPA) or a guest physical address (GPA) and must
22537 * point to a physically contiguous block of memory.
22539 uint64_t resp_addr;
22540 /* rss_cos_lb_ctx_id is 16 b */
22541 uint16_t rss_cos_lb_ctx_id;
22542 uint8_t unused_0[6];
22543 } __attribute__((packed));
22545 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
22546 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
22547 /* The specific error status for the command. */
22548 uint16_t error_code;
22549 /* The HWRM command request type. */
22551 /* The sequence ID from the original command. */
22553 /* The length of the response data in number of bytes. */
22555 uint8_t unused_0[7];
22557 * This field is used in Output records to indicate that the output
22558 * is completely written to RAM. This field should be read as '1'
22559 * to indicate that the output has been completely written.
22560 * When writing a command completion or response to an internal processor,
22561 * the order of writes has to be such that this field is written last.
22564 } __attribute__((packed));
22566 /*******************
22567 * hwrm_ring_alloc *
22568 *******************/
22571 /* hwrm_ring_alloc_input (size:704b/88B) */
22572 struct hwrm_ring_alloc_input {
22573 /* The HWRM command request type. */
22576 * The completion ring to send the completion event on. This should
22577 * be the NQ ID returned from the `nq_alloc` HWRM command.
22579 uint16_t cmpl_ring;
22581 * The sequence ID is used by the driver for tracking multiple
22582 * commands. This ID is treated as opaque data by the firmware and
22583 * the value is returned in the `hwrm_resp_hdr` upon completion.
22587 * The target ID of the command:
22588 * * 0x0-0xFFF8 - The function ID
22589 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22590 * * 0xFFFD - Reserved for user-space HWRM interface
22593 uint16_t target_id;
22595 * A physical address pointer pointing to a host buffer that the
22596 * command's response data will be written. This can be either a host
22597 * physical address (HPA) or a guest physical address (GPA) and must
22598 * point to a physically contiguous block of memory.
22600 uint64_t resp_addr;
22603 * This bit must be '1' for the ring_arb_cfg field to be
22606 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
22609 * This bit must be '1' for the stat_ctx_id_valid field to be
22612 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
22615 * This bit must be '1' for the max_bw_valid field to be
22618 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
22621 * This bit must be '1' for the rx_ring_id field to be
22624 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
22627 * This bit must be '1' for the nq_ring_id field to be
22630 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
22633 * This bit must be '1' for the rx_buf_size field to be
22636 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
22640 /* L2 Completion Ring (CR) */
22641 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22643 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
22645 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
22646 /* RoCE Notification Completion Ring (ROCE_CR) */
22647 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22648 /* RX Aggregation Ring */
22649 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22650 /* Notification Queue */
22651 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22652 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
22653 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
22655 /* Ring allocation flags. */
22658 * For Rx rings, the incoming packet data can be placed at either
22659 * a 0B or 2B offset from the start of the Rx packet buffer. When
22660 * '1', the received packet will be padded with 2B of zeros at the
22661 * front of the packet. Note that this flag is only used for
22662 * Rx rings and is ignored for all other rings included Rx
22663 * Aggregation rings.
22665 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
22667 * This value is a pointer to the page table for the
22670 uint64_t page_tbl_addr;
22671 /* First Byte Offset of the first entry in the first page. */
22674 * Actual page size in 2^page_size. The supported range is increments
22675 * in powers of 2 from 16 bytes to 1GB.
22677 * Page size is 16 B.
22679 * Page size is 4 KB.
22681 * Page size is 8 KB.
22683 * Page size is 64 KB.
22685 * Page size is 2 MB.
22687 * Page size is 4 MB.
22689 * Page size is 1 GB.
22693 * This value indicates the depth of page table.
22694 * For this version of the specification, value other than 0 or
22695 * 1 shall be considered as an invalid value.
22696 * When the page_tbl_depth = 0, then it is treated as a
22697 * special case with the following.
22698 * 1. FBO and page size fields are not valid.
22699 * 2. page_tbl_addr is the physical address of the first
22700 * element of the ring.
22702 uint8_t page_tbl_depth;
22703 uint8_t unused_1[2];
22705 * Number of 16B units in the ring. Minimum size for
22706 * a ring is 16 16B entries.
22710 * Logical ring number for the ring to be allocated.
22711 * This value determines the position in the doorbell
22712 * area where the update to the ring will be made.
22714 * For completion rings, this value is also the MSI-X
22715 * vector number for the function the completion ring is
22718 uint16_t logical_id;
22720 * This field is used only when ring_type is a TX ring.
22721 * This value indicates what completion ring the TX ring
22722 * is associated with.
22724 uint16_t cmpl_ring_id;
22726 * This field is used only when ring_type is a TX ring.
22727 * This value indicates what CoS queue the TX ring
22728 * is associated with.
22732 * When allocating a Rx ring or Rx aggregation ring, this field
22733 * specifies the size of the buffer descriptors posted to the ring.
22735 uint16_t rx_buf_size;
22737 * When allocating an Rx aggregation ring, this field
22738 * specifies the associated Rx ring ID.
22740 uint16_t rx_ring_id;
22742 * When allocating a completion ring, this field
22743 * specifies the associated NQ ring ID.
22745 uint16_t nq_ring_id;
22747 * This field is used only when ring_type is a TX ring.
22748 * This field is used to configure arbitration related
22749 * parameters for a TX ring.
22751 uint16_t ring_arb_cfg;
22752 /* Arbitration policy used for the ring. */
22753 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
22755 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
22757 * Use strict priority for the TX ring.
22758 * Priority value is specified in arb_policy_param
22760 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
22763 * Use weighted fair queue arbitration for the TX ring.
22764 * Weight is specified in arb_policy_param
22766 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
22768 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
22769 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
22770 /* Reserved field. */
22771 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
22773 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
22775 * Arbitration policy specific parameter.
22776 * # For strict priority arbitration policy, this field
22777 * represents a priority value. If set to 0, then the priority
22778 * is not specified and the HWRM is allowed to select
22779 * any priority for this TX ring.
22780 * # For weighted fair queue arbitration policy, this field
22781 * represents a weight value. If set to 0, then the weight
22782 * is not specified and the HWRM is allowed to select
22783 * any weight for this TX ring.
22785 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
22787 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
22790 * This field is reserved for the future use.
22791 * It shall be set to 0.
22793 uint32_t reserved3;
22795 * This field is used only when ring_type is a TX ring.
22796 * This input indicates what statistics context this ring
22797 * should be associated with.
22799 uint32_t stat_ctx_id;
22801 * This field is reserved for the future use.
22802 * It shall be set to 0.
22804 uint32_t reserved4;
22806 * This field is used only when ring_type is a TX ring
22807 * to specify maximum BW allocated to the TX ring.
22808 * The HWRM will translate this value into byte counter and
22809 * time interval used for this ring inside the device.
22812 /* The bandwidth value. */
22813 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
22814 UINT32_C(0xfffffff)
22815 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
22816 /* The granularity of the value (bits or bytes). */
22817 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
22818 UINT32_C(0x10000000)
22819 /* Value is in bits. */
22820 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
22821 (UINT32_C(0x0) << 28)
22822 /* Value is in bytes. */
22823 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
22824 (UINT32_C(0x1) << 28)
22825 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
22826 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
22827 /* bw_value_unit is 3 b */
22828 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
22829 UINT32_C(0xe0000000)
22830 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
22831 /* Value is in Mb or MB (base 10). */
22832 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
22833 (UINT32_C(0x0) << 29)
22834 /* Value is in Kb or KB (base 10). */
22835 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
22836 (UINT32_C(0x2) << 29)
22837 /* Value is in bits or bytes. */
22838 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
22839 (UINT32_C(0x4) << 29)
22840 /* Value is in Gb or GB (base 10). */
22841 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
22842 (UINT32_C(0x6) << 29)
22843 /* Value is in 1/100th of a percentage of total bandwidth. */
22844 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22845 (UINT32_C(0x1) << 29)
22847 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
22848 (UINT32_C(0x7) << 29)
22849 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
22850 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
22852 * This field is used only when ring_type is a Completion ring.
22853 * This value indicates what interrupt mode should be used
22854 * on this completion ring.
22855 * Note: In the legacy interrupt mode, no more than 16
22856 * completion rings are allowed.
22860 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
22862 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
22864 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
22865 /* No Interrupt - Polled mode */
22866 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
22867 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
22868 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
22869 uint8_t unused_4[3];
22871 * The cq_handle is specified when allocating a completion ring. For
22872 * devices that support NQs, this cq_handle will be included in the
22873 * NQE to specify which CQ should be read to retrieve the completion
22876 uint64_t cq_handle;
22877 } __attribute__((packed));
22879 /* hwrm_ring_alloc_output (size:128b/16B) */
22880 struct hwrm_ring_alloc_output {
22881 /* The specific error status for the command. */
22882 uint16_t error_code;
22883 /* The HWRM command request type. */
22885 /* The sequence ID from the original command. */
22887 /* The length of the response data in number of bytes. */
22890 * Physical number of ring allocated.
22891 * This value shall be unique for a ring type.
22894 /* Logical number of ring allocated. */
22895 uint16_t logical_ring_id;
22896 uint8_t unused_0[3];
22898 * This field is used in Output records to indicate that the output
22899 * is completely written to RAM. This field should be read as '1'
22900 * to indicate that the output has been completely written.
22901 * When writing a command completion or response to an internal processor,
22902 * the order of writes has to be such that this field is written last.
22905 } __attribute__((packed));
22907 /******************
22909 ******************/
22912 /* hwrm_ring_free_input (size:192b/24B) */
22913 struct hwrm_ring_free_input {
22914 /* The HWRM command request type. */
22917 * The completion ring to send the completion event on. This should
22918 * be the NQ ID returned from the `nq_alloc` HWRM command.
22920 uint16_t cmpl_ring;
22922 * The sequence ID is used by the driver for tracking multiple
22923 * commands. This ID is treated as opaque data by the firmware and
22924 * the value is returned in the `hwrm_resp_hdr` upon completion.
22928 * The target ID of the command:
22929 * * 0x0-0xFFF8 - The function ID
22930 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22931 * * 0xFFFD - Reserved for user-space HWRM interface
22934 uint16_t target_id;
22936 * A physical address pointer pointing to a host buffer that the
22937 * command's response data will be written. This can be either a host
22938 * physical address (HPA) or a guest physical address (GPA) and must
22939 * point to a physically contiguous block of memory.
22941 uint64_t resp_addr;
22944 /* L2 Completion Ring (CR) */
22945 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22947 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
22949 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
22950 /* RoCE Notification Completion Ring (ROCE_CR) */
22951 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22952 /* RX Aggregation Ring */
22953 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22954 /* Notification Queue */
22955 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22956 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
22957 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
22959 /* Physical number of ring allocated. */
22961 uint8_t unused_1[4];
22962 } __attribute__((packed));
22964 /* hwrm_ring_free_output (size:128b/16B) */
22965 struct hwrm_ring_free_output {
22966 /* The specific error status for the command. */
22967 uint16_t error_code;
22968 /* The HWRM command request type. */
22970 /* The sequence ID from the original command. */
22972 /* The length of the response data in number of bytes. */
22974 uint8_t unused_0[7];
22976 * This field is used in Output records to indicate that the output
22977 * is completely written to RAM. This field should be read as '1'
22978 * to indicate that the output has been completely written.
22979 * When writing a command completion or response to an internal processor,
22980 * the order of writes has to be such that this field is written last.
22983 } __attribute__((packed));
22985 /*******************
22986 * hwrm_ring_reset *
22987 *******************/
22990 /* hwrm_ring_reset_input (size:192b/24B) */
22991 struct hwrm_ring_reset_input {
22992 /* The HWRM command request type. */
22995 * The completion ring to send the completion event on. This should
22996 * be the NQ ID returned from the `nq_alloc` HWRM command.
22998 uint16_t cmpl_ring;
23000 * The sequence ID is used by the driver for tracking multiple
23001 * commands. This ID is treated as opaque data by the firmware and
23002 * the value is returned in the `hwrm_resp_hdr` upon completion.
23006 * The target ID of the command:
23007 * * 0x0-0xFFF8 - The function ID
23008 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23009 * * 0xFFFD - Reserved for user-space HWRM interface
23012 uint16_t target_id;
23014 * A physical address pointer pointing to a host buffer that the
23015 * command's response data will be written. This can be either a host
23016 * physical address (HPA) or a guest physical address (GPA) and must
23017 * point to a physically contiguous block of memory.
23019 uint64_t resp_addr;
23022 /* L2 Completion Ring (CR) */
23023 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
23025 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
23027 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
23028 /* RoCE Notification Completion Ring (ROCE_CR) */
23029 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
23030 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
23031 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
23033 /* Physical number of the ring. */
23035 uint8_t unused_1[4];
23036 } __attribute__((packed));
23038 /* hwrm_ring_reset_output (size:128b/16B) */
23039 struct hwrm_ring_reset_output {
23040 /* The specific error status for the command. */
23041 uint16_t error_code;
23042 /* The HWRM command request type. */
23044 /* The sequence ID from the original command. */
23046 /* The length of the response data in number of bytes. */
23048 uint8_t unused_0[4];
23049 /* Position of consumer index after ring reset completes. */
23050 uint8_t consumer_idx[3];
23052 * This field is used in Output records to indicate that the output
23053 * is completely written to RAM. This field should be read as '1'
23054 * to indicate that the output has been completely written.
23055 * When writing a command completion or response to an internal processor,
23056 * the order of writes has to be such that this field is written last.
23059 } __attribute__((packed));
23061 /**************************
23062 * hwrm_ring_aggint_qcaps *
23063 **************************/
23066 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
23067 struct hwrm_ring_aggint_qcaps_input {
23068 /* The HWRM command request type. */
23071 * The completion ring to send the completion event on. This should
23072 * be the NQ ID returned from the `nq_alloc` HWRM command.
23074 uint16_t cmpl_ring;
23076 * The sequence ID is used by the driver for tracking multiple
23077 * commands. This ID is treated as opaque data by the firmware and
23078 * the value is returned in the `hwrm_resp_hdr` upon completion.
23082 * The target ID of the command:
23083 * * 0x0-0xFFF8 - The function ID
23084 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23085 * * 0xFFFD - Reserved for user-space HWRM interface
23088 uint16_t target_id;
23090 * A physical address pointer pointing to a host buffer that the
23091 * command's response data will be written. This can be either a host
23092 * physical address (HPA) or a guest physical address (GPA) and must
23093 * point to a physically contiguous block of memory.
23095 uint64_t resp_addr;
23096 } __attribute__((packed));
23098 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
23099 struct hwrm_ring_aggint_qcaps_output {
23100 /* The specific error status for the command. */
23101 uint16_t error_code;
23102 /* The HWRM command request type. */
23104 /* The sequence ID from the original command. */
23106 /* The length of the response data in number of bytes. */
23108 uint32_t cmpl_params;
23110 * When this bit is set to '1', int_lat_tmr_min can be configured
23111 * on completion rings.
23113 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
23116 * When this bit is set to '1', int_lat_tmr_max can be configured
23117 * on completion rings.
23119 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
23122 * When this bit is set to '1', timer_reset can be enabled
23123 * on completion rings.
23125 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
23128 * When this bit is set to '1', ring_idle can be enabled
23129 * on completion rings.
23131 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
23134 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
23135 * on completion rings.
23137 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
23140 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
23141 * on completion rings.
23143 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
23146 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
23147 * on completion rings.
23149 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
23152 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
23153 * on completion rings.
23155 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
23158 * When this bit is set to '1', num_cmpl_aggr_int can be configured
23159 * on completion rings.
23161 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
23163 uint32_t nq_params;
23165 * When this bit is set to '1', int_lat_tmr_min can be configured
23166 * on notification queues.
23168 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
23170 /* Minimum value for num_cmpl_dma_aggr */
23171 uint16_t num_cmpl_dma_aggr_min;
23172 /* Maximum value for num_cmpl_dma_aggr */
23173 uint16_t num_cmpl_dma_aggr_max;
23174 /* Minimum value for num_cmpl_dma_aggr_during_int */
23175 uint16_t num_cmpl_dma_aggr_during_int_min;
23176 /* Maximum value for num_cmpl_dma_aggr_during_int */
23177 uint16_t num_cmpl_dma_aggr_during_int_max;
23178 /* Minimum value for cmpl_aggr_dma_tmr */
23179 uint16_t cmpl_aggr_dma_tmr_min;
23180 /* Maximum value for cmpl_aggr_dma_tmr */
23181 uint16_t cmpl_aggr_dma_tmr_max;
23182 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
23183 uint16_t cmpl_aggr_dma_tmr_during_int_min;
23184 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
23185 uint16_t cmpl_aggr_dma_tmr_during_int_max;
23186 /* Minimum value for int_lat_tmr_min */
23187 uint16_t int_lat_tmr_min_min;
23188 /* Maximum value for int_lat_tmr_min */
23189 uint16_t int_lat_tmr_min_max;
23190 /* Minimum value for int_lat_tmr_max */
23191 uint16_t int_lat_tmr_max_min;
23192 /* Maximum value for int_lat_tmr_max */
23193 uint16_t int_lat_tmr_max_max;
23194 /* Minimum value for num_cmpl_aggr_int */
23195 uint16_t num_cmpl_aggr_int_min;
23196 /* Maximum value for num_cmpl_aggr_int */
23197 uint16_t num_cmpl_aggr_int_max;
23198 /* The units for timer parameters, in nanoseconds. */
23199 uint16_t timer_units;
23200 uint8_t unused_0[1];
23202 * This field is used in Output records to indicate that the output
23203 * is completely written to RAM. This field should be read as '1'
23204 * to indicate that the output has been completely written.
23205 * When writing a command completion or response to an internal processor,
23206 * the order of writes has to be such that this field is written last.
23209 } __attribute__((packed));
23211 /**************************************
23212 * hwrm_ring_cmpl_ring_qaggint_params *
23213 **************************************/
23216 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
23217 struct hwrm_ring_cmpl_ring_qaggint_params_input {
23218 /* The HWRM command request type. */
23221 * The completion ring to send the completion event on. This should
23222 * be the NQ ID returned from the `nq_alloc` HWRM command.
23224 uint16_t cmpl_ring;
23226 * The sequence ID is used by the driver for tracking multiple
23227 * commands. This ID is treated as opaque data by the firmware and
23228 * the value is returned in the `hwrm_resp_hdr` upon completion.
23232 * The target ID of the command:
23233 * * 0x0-0xFFF8 - The function ID
23234 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23235 * * 0xFFFD - Reserved for user-space HWRM interface
23238 uint16_t target_id;
23240 * A physical address pointer pointing to a host buffer that the
23241 * command's response data will be written. This can be either a host
23242 * physical address (HPA) or a guest physical address (GPA) and must
23243 * point to a physically contiguous block of memory.
23245 uint64_t resp_addr;
23246 /* Physical number of completion ring. */
23248 uint8_t unused_0[6];
23249 } __attribute__((packed));
23251 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
23252 struct hwrm_ring_cmpl_ring_qaggint_params_output {
23253 /* The specific error status for the command. */
23254 uint16_t error_code;
23255 /* The HWRM command request type. */
23257 /* The sequence ID from the original command. */
23259 /* The length of the response data in number of bytes. */
23263 * When this bit is set to '1', interrupt max
23264 * timer is reset whenever a completion is received.
23266 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
23269 * When this bit is set to '1', ring idle mode
23270 * aggregation will be enabled.
23272 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
23275 * Number of completions to aggregate before DMA
23276 * during the normal mode.
23278 uint16_t num_cmpl_dma_aggr;
23280 * Number of completions to aggregate before DMA
23281 * during the interrupt mode.
23283 uint16_t num_cmpl_dma_aggr_during_int;
23285 * Timer in unit of 80-nsec used to aggregate completions before
23286 * DMA during the normal mode (not in interrupt mode).
23288 uint16_t cmpl_aggr_dma_tmr;
23290 * Timer in unit of 80-nsec used to aggregate completions before
23291 * DMA during the interrupt mode.
23293 uint16_t cmpl_aggr_dma_tmr_during_int;
23294 /* Minimum time (in unit of 80-nsec) between two interrupts. */
23295 uint16_t int_lat_tmr_min;
23297 * Maximum wait time (in unit of 80-nsec) spent aggregating
23298 * completions before signaling the interrupt after the
23299 * interrupt is enabled.
23301 uint16_t int_lat_tmr_max;
23303 * Minimum number of completions aggregated before signaling
23306 uint16_t num_cmpl_aggr_int;
23307 uint8_t unused_0[7];
23309 * This field is used in Output records to indicate that the output
23310 * is completely written to RAM. This field should be read as '1'
23311 * to indicate that the output has been completely written.
23312 * When writing a command completion or response to an internal processor,
23313 * the order of writes has to be such that this field is written last.
23316 } __attribute__((packed));
23318 /*****************************************
23319 * hwrm_ring_cmpl_ring_cfg_aggint_params *
23320 *****************************************/
23323 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
23324 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
23325 /* The HWRM command request type. */
23328 * The completion ring to send the completion event on. This should
23329 * be the NQ ID returned from the `nq_alloc` HWRM command.
23331 uint16_t cmpl_ring;
23333 * The sequence ID is used by the driver for tracking multiple
23334 * commands. This ID is treated as opaque data by the firmware and
23335 * the value is returned in the `hwrm_resp_hdr` upon completion.
23339 * The target ID of the command:
23340 * * 0x0-0xFFF8 - The function ID
23341 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23342 * * 0xFFFD - Reserved for user-space HWRM interface
23345 uint16_t target_id;
23347 * A physical address pointer pointing to a host buffer that the
23348 * command's response data will be written. This can be either a host
23349 * physical address (HPA) or a guest physical address (GPA) and must
23350 * point to a physically contiguous block of memory.
23352 uint64_t resp_addr;
23353 /* Physical number of completion ring. */
23357 * When this bit is set to '1', interrupt latency max
23358 * timer is reset whenever a completion is received.
23360 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
23363 * When this bit is set to '1', ring idle mode
23364 * aggregation will be enabled.
23366 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
23369 * Set this flag to 1 when configuring parameters on a
23370 * notification queue. Set this flag to 0 when configuring
23371 * parameters on a completion queue.
23373 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
23376 * Number of completions to aggregate before DMA
23377 * during the normal mode.
23379 uint16_t num_cmpl_dma_aggr;
23381 * Number of completions to aggregate before DMA
23382 * during the interrupt mode.
23384 uint16_t num_cmpl_dma_aggr_during_int;
23386 * Timer in unit of 80-nsec used to aggregate completions before
23387 * DMA during the normal mode (not in interrupt mode).
23389 uint16_t cmpl_aggr_dma_tmr;
23391 * Timer in unit of 80-nsec used to aggregate completions before
23392 * DMA during the interrupt mode.
23394 uint16_t cmpl_aggr_dma_tmr_during_int;
23395 /* Minimum time (in unit of 80-nsec) between two interrupts. */
23396 uint16_t int_lat_tmr_min;
23398 * Maximum wait time (in unit of 80-nsec) spent aggregating
23399 * cmpls before signaling the interrupt after the
23400 * interrupt is enabled.
23402 uint16_t int_lat_tmr_max;
23404 * Minimum number of completions aggregated before signaling
23407 uint16_t num_cmpl_aggr_int;
23409 * Bitfield that indicates which parameters are to be applied. Only
23410 * required when configuring devices with notification queues, and
23411 * used in that case to set certain parameters on completion queues
23412 * and others on notification queues.
23416 * This bit must be '1' for the num_cmpl_dma_aggr field to be
23419 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
23422 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
23425 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
23428 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
23431 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
23434 * This bit must be '1' for the int_lat_tmr_min field to be
23437 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
23440 * This bit must be '1' for the int_lat_tmr_max field to be
23443 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
23446 * This bit must be '1' for the num_cmpl_aggr_int field to be
23449 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
23451 uint8_t unused_0[4];
23452 } __attribute__((packed));
23454 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
23455 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
23456 /* The specific error status for the command. */
23457 uint16_t error_code;
23458 /* The HWRM command request type. */
23460 /* The sequence ID from the original command. */
23462 /* The length of the response data in number of bytes. */
23464 uint8_t unused_0[7];
23466 * This field is used in Output records to indicate that the output
23467 * is completely written to RAM. This field should be read as '1'
23468 * to indicate that the output has been completely written.
23469 * When writing a command completion or response to an internal processor,
23470 * the order of writes has to be such that this field is written last.
23473 } __attribute__((packed));
23475 /***********************
23476 * hwrm_ring_grp_alloc *
23477 ***********************/
23480 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
23481 struct hwrm_ring_grp_alloc_input {
23482 /* The HWRM command request type. */
23485 * The completion ring to send the completion event on. This should
23486 * be the NQ ID returned from the `nq_alloc` HWRM command.
23488 uint16_t cmpl_ring;
23490 * The sequence ID is used by the driver for tracking multiple
23491 * commands. This ID is treated as opaque data by the firmware and
23492 * the value is returned in the `hwrm_resp_hdr` upon completion.
23496 * The target ID of the command:
23497 * * 0x0-0xFFF8 - The function ID
23498 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23499 * * 0xFFFD - Reserved for user-space HWRM interface
23502 uint16_t target_id;
23504 * A physical address pointer pointing to a host buffer that the
23505 * command's response data will be written. This can be either a host
23506 * physical address (HPA) or a guest physical address (GPA) and must
23507 * point to a physically contiguous block of memory.
23509 uint64_t resp_addr;
23511 * This value identifies the CR associated with the ring
23516 * This value identifies the main RR associated with the ring
23521 * This value identifies the aggregation RR associated with
23522 * the ring group. If this value is 0xFF... (All Fs), then no
23523 * Aggregation ring will be set.
23527 * This value identifies the statistics context associated
23528 * with the ring group.
23531 } __attribute__((packed));
23533 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
23534 struct hwrm_ring_grp_alloc_output {
23535 /* The specific error status for the command. */
23536 uint16_t error_code;
23537 /* The HWRM command request type. */
23539 /* The sequence ID from the original command. */
23541 /* The length of the response data in number of bytes. */
23544 * This is the ring group ID value. Use this value to program
23545 * the default ring group for the VNIC or as table entries
23546 * in an RSS/COS context.
23548 uint32_t ring_group_id;
23549 uint8_t unused_0[3];
23551 * This field is used in Output records to indicate that the output
23552 * is completely written to RAM. This field should be read as '1'
23553 * to indicate that the output has been completely written.
23554 * When writing a command completion or response to an internal processor,
23555 * the order of writes has to be such that this field is written last.
23558 } __attribute__((packed));
23560 /**********************
23561 * hwrm_ring_grp_free *
23562 **********************/
23565 /* hwrm_ring_grp_free_input (size:192b/24B) */
23566 struct hwrm_ring_grp_free_input {
23567 /* The HWRM command request type. */
23570 * The completion ring to send the completion event on. This should
23571 * be the NQ ID returned from the `nq_alloc` HWRM command.
23573 uint16_t cmpl_ring;
23575 * The sequence ID is used by the driver for tracking multiple
23576 * commands. This ID is treated as opaque data by the firmware and
23577 * the value is returned in the `hwrm_resp_hdr` upon completion.
23581 * The target ID of the command:
23582 * * 0x0-0xFFF8 - The function ID
23583 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23584 * * 0xFFFD - Reserved for user-space HWRM interface
23587 uint16_t target_id;
23589 * A physical address pointer pointing to a host buffer that the
23590 * command's response data will be written. This can be either a host
23591 * physical address (HPA) or a guest physical address (GPA) and must
23592 * point to a physically contiguous block of memory.
23594 uint64_t resp_addr;
23595 /* This is the ring group ID value. */
23596 uint32_t ring_group_id;
23597 uint8_t unused_0[4];
23598 } __attribute__((packed));
23600 /* hwrm_ring_grp_free_output (size:128b/16B) */
23601 struct hwrm_ring_grp_free_output {
23602 /* The specific error status for the command. */
23603 uint16_t error_code;
23604 /* The HWRM command request type. */
23606 /* The sequence ID from the original command. */
23608 /* The length of the response data in number of bytes. */
23610 uint8_t unused_0[7];
23612 * This field is used in Output records to indicate that the output
23613 * is completely written to RAM. This field should be read as '1'
23614 * to indicate that the output has been completely written.
23615 * When writing a command completion or response to an internal processor,
23616 * the order of writes has to be such that this field is written last.
23619 } __attribute__((packed));
23621 * special reserved flow ID to identify per function default
23622 * flows for vSwitch offload
23624 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
23626 * special reserved flow ID to identify per function RoCEv1
23629 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
23631 * special reserved flow ID to identify per function RoCEv2
23634 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
23636 * special reserved flow ID to identify per function RoCEv2
23639 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
23641 /****************************
23642 * hwrm_cfa_l2_filter_alloc *
23643 ****************************/
23646 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
23647 struct hwrm_cfa_l2_filter_alloc_input {
23648 /* The HWRM command request type. */
23651 * The completion ring to send the completion event on. This should
23652 * be the NQ ID returned from the `nq_alloc` HWRM command.
23654 uint16_t cmpl_ring;
23656 * The sequence ID is used by the driver for tracking multiple
23657 * commands. This ID is treated as opaque data by the firmware and
23658 * the value is returned in the `hwrm_resp_hdr` upon completion.
23662 * The target ID of the command:
23663 * * 0x0-0xFFF8 - The function ID
23664 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23665 * * 0xFFFD - Reserved for user-space HWRM interface
23668 uint16_t target_id;
23670 * A physical address pointer pointing to a host buffer that the
23671 * command's response data will be written. This can be either a host
23672 * physical address (HPA) or a guest physical address (GPA) and must
23673 * point to a physically contiguous block of memory.
23675 uint64_t resp_addr;
23678 * Enumeration denoting the RX, TX type of the resource.
23679 * This enumeration is used for resources that are similar for both
23680 * TX and RX paths of the chip.
23682 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
23685 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
23688 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
23690 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
23691 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
23692 /* Setting of this flag indicates the applicability to the loopback path. */
23693 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
23696 * Setting of this flag indicates drop action. If this flag is not set,
23697 * then it should be considered accept action.
23699 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
23702 * If this flag is set, all t_l2_* fields are invalid
23703 * and they should not be specified.
23704 * If this flag is set, then l2_* fields refer to
23705 * fields of outermost L2 header.
23707 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
23710 * Enumeration denoting NO_ROCE_L2 to support old drivers.
23711 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
23713 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
23715 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
23716 /* To support old drivers */
23717 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
23718 (UINT32_C(0x0) << 4)
23719 /* Only L2 traffic */
23720 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
23721 (UINT32_C(0x1) << 4)
23722 /* Roce & L2 traffic */
23723 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
23724 (UINT32_C(0x2) << 4)
23725 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
23726 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
23728 * Setting of this flag indicates that no XDP filter is created with
23730 * 0 - legacy behavior, XDP filter is created with L2 filter
23731 * 1 - XDP filter won't be created with L2 filter
23733 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
23736 * Setting this flag to 1 indicate the L2 fields in this command
23737 * pertain to source fields. Setting this flag to 0 indicate the
23738 * L2 fields in this command pertain to the destination fields
23739 * and this is the default/legacy behavior.
23741 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
23745 * This bit must be '1' for the l2_addr field to be
23748 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
23751 * This bit must be '1' for the l2_addr_mask field to be
23754 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
23757 * This bit must be '1' for the l2_ovlan field to be
23760 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
23763 * This bit must be '1' for the l2_ovlan_mask field to be
23766 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
23769 * This bit must be '1' for the l2_ivlan field to be
23772 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
23775 * This bit must be '1' for the l2_ivlan_mask field to be
23778 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
23781 * This bit must be '1' for the t_l2_addr field to be
23784 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
23787 * This bit must be '1' for the t_l2_addr_mask field to be
23790 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
23793 * This bit must be '1' for the t_l2_ovlan field to be
23796 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
23799 * This bit must be '1' for the t_l2_ovlan_mask field to be
23802 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
23805 * This bit must be '1' for the t_l2_ivlan field to be
23808 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
23811 * This bit must be '1' for the t_l2_ivlan_mask field to be
23814 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
23817 * This bit must be '1' for the src_type field to be
23820 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
23823 * This bit must be '1' for the src_id field to be
23826 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
23829 * This bit must be '1' for the tunnel_type field to be
23832 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23835 * This bit must be '1' for the dst_id field to be
23838 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23841 * This bit must be '1' for the mirror_vnic_id field to be
23844 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23847 * This bit must be '1' for the num_vlans field to be
23850 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
23853 * This bit must be '1' for the t_num_vlans field to be
23856 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
23859 * This value sets the match value for the L2 MAC address.
23860 * Destination MAC address for RX path.
23861 * Source MAC address for TX path.
23863 uint8_t l2_addr[6];
23864 /* This value sets the match value for the number of VLANs. */
23867 * This value sets the match value for the number of VLANs
23868 * in the tunnel headers.
23870 uint8_t t_num_vlans;
23872 * This value sets the mask value for the L2 address.
23873 * A value of 0 will mask the corresponding bit from
23876 uint8_t l2_addr_mask[6];
23877 /* This value sets VLAN ID value for outer VLAN. */
23880 * This value sets the mask value for the ovlan id.
23881 * A value of 0 will mask the corresponding bit from
23884 uint16_t l2_ovlan_mask;
23885 /* This value sets VLAN ID value for inner VLAN. */
23888 * This value sets the mask value for the ivlan id.
23889 * A value of 0 will mask the corresponding bit from
23892 uint16_t l2_ivlan_mask;
23893 uint8_t unused_1[2];
23895 * This value sets the match value for the tunnel
23897 * Destination MAC address for RX path.
23898 * Source MAC address for TX path.
23900 uint8_t t_l2_addr[6];
23901 uint8_t unused_2[2];
23903 * This value sets the mask value for the tunnel L2
23905 * A value of 0 will mask the corresponding bit from
23908 uint8_t t_l2_addr_mask[6];
23909 /* This value sets VLAN ID value for tunnel outer VLAN. */
23910 uint16_t t_l2_ovlan;
23912 * This value sets the mask value for the tunnel ovlan id.
23913 * A value of 0 will mask the corresponding bit from
23916 uint16_t t_l2_ovlan_mask;
23917 /* This value sets VLAN ID value for tunnel inner VLAN. */
23918 uint16_t t_l2_ivlan;
23920 * This value sets the mask value for the tunnel ivlan id.
23921 * A value of 0 will mask the corresponding bit from
23924 uint16_t t_l2_ivlan_mask;
23925 /* This value identifies the type of source of the packet. */
23928 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
23929 /* Physical function */
23930 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
23931 /* Virtual function */
23932 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
23933 /* Virtual NIC of a function */
23934 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
23935 /* Embedded processor for CFA management */
23936 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
23937 /* Embedded processor for OOB management */
23938 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
23939 /* Embedded processor for RoCE */
23940 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
23941 /* Embedded processor for network proxy functions */
23942 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
23943 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
23944 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
23947 * This value is the id of the source.
23948 * For a network port, it represents port_id.
23949 * For a physical function, it represents fid.
23950 * For a virtual function, it represents vf_id.
23951 * For a vnic, it represents vnic_id.
23952 * For embedded processors, this id is not valid.
23955 * 1. The function ID is implied if it src_id is
23956 * not provided for a src_type that is either
23960 uint8_t tunnel_type;
23962 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23964 /* Virtual eXtensible Local Area Network (VXLAN) */
23965 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23967 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23968 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23970 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23971 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23974 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23976 /* Generic Network Virtualization Encapsulation (Geneve) */
23977 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23979 /* Multi-Protocol Lable Switching (MPLS) */
23980 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23982 /* Stateless Transport Tunnel (STT) */
23983 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23985 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23986 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23988 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23989 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23991 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23992 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23994 /* Use fixed layer 2 ether type of 0xFFFF */
23995 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23997 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23998 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24000 /* Any tunneled traffic */
24001 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24003 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24004 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24007 * If set, this value shall represent the
24008 * Logical VNIC ID of the destination VNIC for the RX
24009 * path and network port id of the destination port for
24014 * Logical VNIC ID of the VNIC where traffic is
24017 uint16_t mirror_vnic_id;
24019 * This hint is provided to help in placing
24020 * the filter in the filter table.
24023 /* No preference */
24024 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
24026 /* Above the given filter */
24027 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
24029 /* Below the given filter */
24030 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
24032 /* As high as possible */
24033 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
24035 /* As low as possible */
24036 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
24038 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
24039 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
24043 * This is the ID of the filter that goes along with
24046 * This field is valid only for the following values.
24047 * 1 - Above the given filter
24048 * 2 - Below the given filter
24050 uint64_t l2_filter_id_hint;
24051 } __attribute__((packed));
24053 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
24054 struct hwrm_cfa_l2_filter_alloc_output {
24055 /* The specific error status for the command. */
24056 uint16_t error_code;
24057 /* The HWRM command request type. */
24059 /* The sequence ID from the original command. */
24061 /* The length of the response data in number of bytes. */
24064 * This value identifies a set of CFA data structures used for an L2
24067 uint64_t l2_filter_id;
24069 * The flow id value in bit 0-29 is the actual ID of the flow
24070 * associated with this filter and it shall be used to match
24071 * and associate the flow identifier returned in completion
24072 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24073 * shall indicate no valid flow id.
24076 /* Indicate the flow id value. */
24077 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24078 UINT32_C(0x3fffffff)
24079 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24080 /* Indicate type of the flow. */
24081 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24082 UINT32_C(0x40000000)
24084 * If this bit set to 0, then it indicates that the flow is
24087 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24088 (UINT32_C(0x0) << 30)
24090 * If this bit is set to 1, then it indicates that the flow is
24093 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24094 (UINT32_C(0x1) << 30)
24095 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24096 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24097 /* Indicate the flow direction. */
24098 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24099 UINT32_C(0x80000000)
24100 /* If this bit set to 0, then it indicates rx flow. */
24101 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24102 (UINT32_C(0x0) << 31)
24103 /* If this bit is set to 1, then it indicates that tx flow. */
24104 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24105 (UINT32_C(0x1) << 31)
24106 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24107 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24108 uint8_t unused_0[3];
24110 * This field is used in Output records to indicate that the output
24111 * is completely written to RAM. This field should be read as '1'
24112 * to indicate that the output has been completely written.
24113 * When writing a command completion or response to an internal processor,
24114 * the order of writes has to be such that this field is written last.
24117 } __attribute__((packed));
24119 /***************************
24120 * hwrm_cfa_l2_filter_free *
24121 ***************************/
24124 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
24125 struct hwrm_cfa_l2_filter_free_input {
24126 /* The HWRM command request type. */
24129 * The completion ring to send the completion event on. This should
24130 * be the NQ ID returned from the `nq_alloc` HWRM command.
24132 uint16_t cmpl_ring;
24134 * The sequence ID is used by the driver for tracking multiple
24135 * commands. This ID is treated as opaque data by the firmware and
24136 * the value is returned in the `hwrm_resp_hdr` upon completion.
24140 * The target ID of the command:
24141 * * 0x0-0xFFF8 - The function ID
24142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24143 * * 0xFFFD - Reserved for user-space HWRM interface
24146 uint16_t target_id;
24148 * A physical address pointer pointing to a host buffer that the
24149 * command's response data will be written. This can be either a host
24150 * physical address (HPA) or a guest physical address (GPA) and must
24151 * point to a physically contiguous block of memory.
24153 uint64_t resp_addr;
24155 * This value identifies a set of CFA data structures used for an L2
24158 uint64_t l2_filter_id;
24159 } __attribute__((packed));
24161 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
24162 struct hwrm_cfa_l2_filter_free_output {
24163 /* The specific error status for the command. */
24164 uint16_t error_code;
24165 /* The HWRM command request type. */
24167 /* The sequence ID from the original command. */
24169 /* The length of the response data in number of bytes. */
24171 uint8_t unused_0[7];
24173 * This field is used in Output records to indicate that the output
24174 * is completely written to RAM. This field should be read as '1'
24175 * to indicate that the output has been completely written.
24176 * When writing a command completion or response to an internal processor,
24177 * the order of writes has to be such that this field is written last.
24180 } __attribute__((packed));
24182 /**************************
24183 * hwrm_cfa_l2_filter_cfg *
24184 **************************/
24187 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
24188 struct hwrm_cfa_l2_filter_cfg_input {
24189 /* The HWRM command request type. */
24192 * The completion ring to send the completion event on. This should
24193 * be the NQ ID returned from the `nq_alloc` HWRM command.
24195 uint16_t cmpl_ring;
24197 * The sequence ID is used by the driver for tracking multiple
24198 * commands. This ID is treated as opaque data by the firmware and
24199 * the value is returned in the `hwrm_resp_hdr` upon completion.
24203 * The target ID of the command:
24204 * * 0x0-0xFFF8 - The function ID
24205 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24206 * * 0xFFFD - Reserved for user-space HWRM interface
24209 uint16_t target_id;
24211 * A physical address pointer pointing to a host buffer that the
24212 * command's response data will be written. This can be either a host
24213 * physical address (HPA) or a guest physical address (GPA) and must
24214 * point to a physically contiguous block of memory.
24216 uint64_t resp_addr;
24219 * Enumeration denoting the RX, TX type of the resource.
24220 * This enumeration is used for resources that are similar for both
24221 * TX and RX paths of the chip.
24223 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
24226 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
24229 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
24231 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
24232 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
24234 * Setting of this flag indicates drop action. If this flag is not set,
24235 * then it should be considered accept action.
24237 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
24240 * Enumeration denoting NO_ROCE_L2 to support old drivers.
24241 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
24243 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
24245 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
24246 /* To support old drivers */
24247 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
24248 (UINT32_C(0x0) << 2)
24249 /* Only L2 traffic */
24250 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
24251 (UINT32_C(0x1) << 2)
24252 /* Roce & L2 traffic */
24253 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
24254 (UINT32_C(0x2) << 2)
24255 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
24256 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
24259 * This bit must be '1' for the dst_id field to be
24262 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
24265 * This bit must be '1' for the new_mirror_vnic_id field to be
24268 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
24271 * This value identifies a set of CFA data structures used for an L2
24274 uint64_t l2_filter_id;
24276 * If set, this value shall represent the
24277 * Logical VNIC ID of the destination VNIC for the RX
24278 * path and network port id of the destination port for
24283 * New Logical VNIC ID of the VNIC where traffic is
24286 uint32_t new_mirror_vnic_id;
24287 } __attribute__((packed));
24289 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
24290 struct hwrm_cfa_l2_filter_cfg_output {
24291 /* The specific error status for the command. */
24292 uint16_t error_code;
24293 /* The HWRM command request type. */
24295 /* The sequence ID from the original command. */
24297 /* The length of the response data in number of bytes. */
24299 uint8_t unused_0[7];
24301 * This field is used in Output records to indicate that the output
24302 * is completely written to RAM. This field should be read as '1'
24303 * to indicate that the output has been completely written.
24304 * When writing a command completion or response to an internal processor,
24305 * the order of writes has to be such that this field is written last.
24308 } __attribute__((packed));
24310 /***************************
24311 * hwrm_cfa_l2_set_rx_mask *
24312 ***************************/
24315 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
24316 struct hwrm_cfa_l2_set_rx_mask_input {
24317 /* The HWRM command request type. */
24320 * The completion ring to send the completion event on. This should
24321 * be the NQ ID returned from the `nq_alloc` HWRM command.
24323 uint16_t cmpl_ring;
24325 * The sequence ID is used by the driver for tracking multiple
24326 * commands. This ID is treated as opaque data by the firmware and
24327 * the value is returned in the `hwrm_resp_hdr` upon completion.
24331 * The target ID of the command:
24332 * * 0x0-0xFFF8 - The function ID
24333 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24334 * * 0xFFFD - Reserved for user-space HWRM interface
24337 uint16_t target_id;
24339 * A physical address pointer pointing to a host buffer that the
24340 * command's response data will be written. This can be either a host
24341 * physical address (HPA) or a guest physical address (GPA) and must
24342 * point to a physically contiguous block of memory.
24344 uint64_t resp_addr;
24349 * When this bit is '1', the function is requested to accept
24350 * multi-cast packets specified by the multicast addr table.
24352 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
24355 * When this bit is '1', the function is requested to accept
24356 * all multi-cast packets.
24358 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
24361 * When this bit is '1', the function is requested to accept
24362 * broadcast packets.
24364 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
24367 * When this bit is '1', the function is requested to be
24368 * put in the promiscuous mode.
24370 * The HWRM should accept any function to set up
24371 * promiscuous mode.
24373 * The HWRM shall follow the semantics below for the
24374 * promiscuous mode support.
24375 * # When partitioning is not enabled on a port
24376 * (i.e. single PF on the port), then the PF shall
24377 * be allowed to be in the promiscuous mode. When the
24378 * PF is in the promiscuous mode, then it shall
24379 * receive all host bound traffic on that port.
24380 * # When partitioning is enabled on a port
24381 * (i.e. multiple PFs per port) and a PF on that
24382 * port is in the promiscuous mode, then the PF
24383 * receives all traffic within that partition as
24384 * identified by a unique identifier for the
24385 * PF (e.g. S-Tag). If a unique outer VLAN
24386 * for the PF is specified, then the setting of
24387 * promiscuous mode on that PF shall result in the
24388 * PF receiving all host bound traffic with matching
24390 * # A VF shall can be set in the promiscuous mode.
24391 * In the promiscuous mode, the VF does not receive any
24392 * traffic unless a unique outer VLAN for the
24393 * VF is specified. If a unique outer VLAN
24394 * for the VF is specified, then the setting of
24395 * promiscuous mode on that VF shall result in the
24396 * VF receiving all host bound traffic with the
24397 * matching outer VLAN.
24398 * # The HWRM shall allow the setting of promiscuous
24399 * mode on a function independently from the
24400 * promiscuous mode settings on other functions.
24402 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
24405 * If this flag is set, the corresponding RX
24406 * filters shall be set up to cover multicast/broadcast
24407 * filters for the outermost Layer 2 destination MAC
24410 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
24413 * If this flag is set, the corresponding RX
24414 * filters shall be set up to cover multicast/broadcast
24415 * filters for the VLAN-tagged packets that match the
24416 * TPID and VID fields of VLAN tags in the VLAN tag
24417 * table specified in this command.
24419 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
24422 * If this flag is set, the corresponding RX
24423 * filters shall be set up to cover multicast/broadcast
24424 * filters for non-VLAN tagged packets and VLAN-tagged
24425 * packets that match the TPID and VID fields of VLAN
24426 * tags in the VLAN tag table specified in this command.
24428 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
24431 * If this flag is set, the corresponding RX
24432 * filters shall be set up to cover multicast/broadcast
24433 * filters for non-VLAN tagged packets and VLAN-tagged
24434 * packets matching any VLAN tag.
24436 * If this flag is set, then the HWRM shall ignore
24437 * VLAN tags specified in vlan_tag_tbl.
24439 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
24440 * flags is set, then the HWRM shall ignore
24441 * VLAN tags specified in vlan_tag_tbl.
24443 * The HWRM client shall set at most one flag out of
24444 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
24446 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
24448 /* This is the address for mcast address tbl. */
24449 uint64_t mc_tbl_addr;
24451 * This value indicates how many entries in mc_tbl are valid.
24452 * Each entry is 6 bytes.
24454 uint32_t num_mc_entries;
24455 uint8_t unused_0[4];
24457 * This is the address for VLAN tag table.
24458 * Each VLAN entry in the table is 4 bytes of a VLAN tag
24459 * including TPID, PCP, DEI, and VID fields in network byte
24462 uint64_t vlan_tag_tbl_addr;
24464 * This value indicates how many entries in vlan_tag_tbl are
24465 * valid. Each entry is 4 bytes.
24467 uint32_t num_vlan_tags;
24468 uint8_t unused_1[4];
24469 } __attribute__((packed));
24471 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
24472 struct hwrm_cfa_l2_set_rx_mask_output {
24473 /* The specific error status for the command. */
24474 uint16_t error_code;
24475 /* The HWRM command request type. */
24477 /* The sequence ID from the original command. */
24479 /* The length of the response data in number of bytes. */
24481 uint8_t unused_0[7];
24483 * This field is used in Output records to indicate that the output
24484 * is completely written to RAM. This field should be read as '1'
24485 * to indicate that the output has been completely written.
24486 * When writing a command completion or response to an internal processor,
24487 * the order of writes has to be such that this field is written last.
24490 } __attribute__((packed));
24492 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
24493 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
24495 * command specific error codes that goes to
24496 * the cmd_err field in Common HWRM Error Response.
24499 /* Unknown error */
24500 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
24502 /* Unable to complete operation due to conflict with Ntuple Filter */
24503 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
24505 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
24506 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
24507 uint8_t unused_0[7];
24508 } __attribute__((packed));
24510 /*******************************
24511 * hwrm_cfa_vlan_antispoof_cfg *
24512 *******************************/
24515 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
24516 struct hwrm_cfa_vlan_antispoof_cfg_input {
24517 /* The HWRM command request type. */
24520 * The completion ring to send the completion event on. This should
24521 * be the NQ ID returned from the `nq_alloc` HWRM command.
24523 uint16_t cmpl_ring;
24525 * The sequence ID is used by the driver for tracking multiple
24526 * commands. This ID is treated as opaque data by the firmware and
24527 * the value is returned in the `hwrm_resp_hdr` upon completion.
24531 * The target ID of the command:
24532 * * 0x0-0xFFF8 - The function ID
24533 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24534 * * 0xFFFD - Reserved for user-space HWRM interface
24537 uint16_t target_id;
24539 * A physical address pointer pointing to a host buffer that the
24540 * command's response data will be written. This can be either a host
24541 * physical address (HPA) or a guest physical address (GPA) and must
24542 * point to a physically contiguous block of memory.
24544 uint64_t resp_addr;
24546 * Function ID of the function that is being configured.
24547 * Only valid for a VF FID configured by the PF.
24550 uint8_t unused_0[2];
24551 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
24552 uint32_t num_vlan_entries;
24554 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
24555 * antispoof table. Each table entry contains the 16-bit TPID
24556 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
24557 * all in network order to match hwrm_cfa_l2_set_rx_mask.
24558 * For an individual VLAN entry, the mask value should be 0xfff
24559 * for the 12-bit VLAN ID.
24561 uint64_t vlan_tag_mask_tbl_addr;
24562 } __attribute__((packed));
24564 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
24565 struct hwrm_cfa_vlan_antispoof_cfg_output {
24566 /* The specific error status for the command. */
24567 uint16_t error_code;
24568 /* The HWRM command request type. */
24570 /* The sequence ID from the original command. */
24572 /* The length of the response data in number of bytes. */
24574 uint8_t unused_0[7];
24576 * This field is used in Output records to indicate that the output
24577 * is completely written to RAM. This field should be read as '1'
24578 * to indicate that the output has been completely written.
24579 * When writing a command completion or response to an internal processor,
24580 * the order of writes has to be such that this field is written last.
24583 } __attribute__((packed));
24585 /********************************
24586 * hwrm_cfa_vlan_antispoof_qcfg *
24587 ********************************/
24590 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
24591 struct hwrm_cfa_vlan_antispoof_qcfg_input {
24592 /* The HWRM command request type. */
24595 * The completion ring to send the completion event on. This should
24596 * be the NQ ID returned from the `nq_alloc` HWRM command.
24598 uint16_t cmpl_ring;
24600 * The sequence ID is used by the driver for tracking multiple
24601 * commands. This ID is treated as opaque data by the firmware and
24602 * the value is returned in the `hwrm_resp_hdr` upon completion.
24606 * The target ID of the command:
24607 * * 0x0-0xFFF8 - The function ID
24608 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24609 * * 0xFFFD - Reserved for user-space HWRM interface
24612 uint16_t target_id;
24614 * A physical address pointer pointing to a host buffer that the
24615 * command's response data will be written. This can be either a host
24616 * physical address (HPA) or a guest physical address (GPA) and must
24617 * point to a physically contiguous block of memory.
24619 uint64_t resp_addr;
24621 * Function ID of the function that is being queried.
24622 * Only valid for a VF FID queried by the PF.
24625 uint8_t unused_0[2];
24627 * Maximum number of VLAN entries the firmware is allowed to DMA
24628 * to vlan_tag_mask_tbl.
24630 uint32_t max_vlan_entries;
24632 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
24633 * antispoof table to which firmware will DMA to. Each table
24634 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
24635 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
24636 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
24637 * the mask value should be 0xfff for the 12-bit VLAN ID.
24639 uint64_t vlan_tag_mask_tbl_addr;
24640 } __attribute__((packed));
24642 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
24643 struct hwrm_cfa_vlan_antispoof_qcfg_output {
24644 /* The specific error status for the command. */
24645 uint16_t error_code;
24646 /* The HWRM command request type. */
24648 /* The sequence ID from the original command. */
24650 /* The length of the response data in number of bytes. */
24652 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
24653 uint32_t num_vlan_entries;
24654 uint8_t unused_0[3];
24656 * This field is used in Output records to indicate that the output
24657 * is completely written to RAM. This field should be read as '1'
24658 * to indicate that the output has been completely written.
24659 * When writing a command completion or response to an internal processor,
24660 * the order of writes has to be such that this field is written last.
24663 } __attribute__((packed));
24665 /********************************
24666 * hwrm_cfa_tunnel_filter_alloc *
24667 ********************************/
24670 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
24671 struct hwrm_cfa_tunnel_filter_alloc_input {
24672 /* The HWRM command request type. */
24675 * The completion ring to send the completion event on. This should
24676 * be the NQ ID returned from the `nq_alloc` HWRM command.
24678 uint16_t cmpl_ring;
24680 * The sequence ID is used by the driver for tracking multiple
24681 * commands. This ID is treated as opaque data by the firmware and
24682 * the value is returned in the `hwrm_resp_hdr` upon completion.
24686 * The target ID of the command:
24687 * * 0x0-0xFFF8 - The function ID
24688 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24689 * * 0xFFFD - Reserved for user-space HWRM interface
24692 uint16_t target_id;
24694 * A physical address pointer pointing to a host buffer that the
24695 * command's response data will be written. This can be either a host
24696 * physical address (HPA) or a guest physical address (GPA) and must
24697 * point to a physically contiguous block of memory.
24699 uint64_t resp_addr;
24701 /* Setting of this flag indicates the applicability to the loopback path. */
24702 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
24706 * This bit must be '1' for the l2_filter_id field to be
24709 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
24712 * This bit must be '1' for the l2_addr field to be
24715 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
24718 * This bit must be '1' for the l2_ivlan field to be
24721 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
24724 * This bit must be '1' for the l3_addr field to be
24727 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
24730 * This bit must be '1' for the l3_addr_type field to be
24733 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
24736 * This bit must be '1' for the t_l3_addr_type field to be
24739 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
24742 * This bit must be '1' for the t_l3_addr field to be
24745 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
24748 * This bit must be '1' for the tunnel_type field to be
24751 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24754 * This bit must be '1' for the vni field to be
24757 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
24760 * This bit must be '1' for the dst_vnic_id field to be
24763 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
24766 * This bit must be '1' for the mirror_vnic_id field to be
24769 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
24772 * This value identifies a set of CFA data structures used for an L2
24775 uint64_t l2_filter_id;
24777 * This value sets the match value for the inner L2
24779 * Destination MAC address for RX path.
24780 * Source MAC address for TX path.
24782 uint8_t l2_addr[6];
24784 * This value sets VLAN ID value for inner VLAN.
24785 * Only 12-bits of VLAN ID are used in setting the filter.
24789 * The value of inner destination IP address to be used in filtering.
24790 * For IPv4, first four bytes represent the IP address.
24792 uint32_t l3_addr[4];
24794 * The value of tunnel destination IP address to be used in filtering.
24795 * For IPv4, first four bytes represent the IP address.
24797 uint32_t t_l3_addr[4];
24799 * This value indicates the type of inner IP address.
24802 * All others are invalid.
24804 uint8_t l3_addr_type;
24806 * This value indicates the type of tunnel IP address.
24809 * All others are invalid.
24811 uint8_t t_l3_addr_type;
24813 uint8_t tunnel_type;
24815 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
24817 /* Virtual eXtensible Local Area Network (VXLAN) */
24818 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
24820 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24821 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
24823 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24824 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
24827 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
24829 /* Generic Network Virtualization Encapsulation (Geneve) */
24830 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24832 /* Multi-Protocol Lable Switching (MPLS) */
24833 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
24835 /* Stateless Transport Tunnel (STT) */
24836 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
24838 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24839 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
24841 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24842 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24844 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24845 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24847 /* Use fixed layer 2 ether type of 0xFFFF */
24848 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24850 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24851 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24853 /* Any tunneled traffic */
24854 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24856 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24857 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24859 * tunnel_flags allows the user to indicate the tunnel tag detection
24860 * for the tunnel type specified in tunnel_type.
24862 uint8_t tunnel_flags;
24864 * If the tunnel_type is geneve, then this bit indicates if we
24865 * need to match the geneve OAM packet.
24866 * If the tunnel_type is nvgre or gre, then this bit indicates if
24867 * we need to detect checksum present bit in geneve header.
24868 * If the tunnel_type is mpls, then this bit indicates if we need
24869 * to match mpls packet with explicit IPV4/IPV6 null header.
24871 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
24874 * If the tunnel_type is geneve, then this bit indicates if we
24875 * need to detect the critical option bit set in the oam packet.
24876 * If the tunnel_type is nvgre or gre, then this bit indicates
24877 * if we need to match nvgre packets with key present bit set in
24879 * If the tunnel_type is mpls, then this bit indicates if we
24880 * need to match mpls packet with S bit from inner/second label.
24882 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
24885 * If the tunnel_type is geneve, then this bit indicates if we
24886 * need to match geneve packet with extended header bit set in
24888 * If the tunnel_type is nvgre or gre, then this bit indicates
24889 * if we need to match nvgre packets with sequence number
24890 * present bit set in gre header.
24891 * If the tunnel_type is mpls, then this bit indicates if we
24892 * need to match mpls packet with S bit from out/first label.
24894 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
24897 * Virtual Network Identifier (VNI). Only valid with
24898 * tunnel_types VXLAN, NVGRE, and Geneve.
24899 * Only lower 24-bits of VNI field are used
24900 * in setting up the filter.
24903 /* Logical VNIC ID of the destination VNIC. */
24904 uint32_t dst_vnic_id;
24906 * Logical VNIC ID of the VNIC where traffic is
24909 uint32_t mirror_vnic_id;
24910 } __attribute__((packed));
24912 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
24913 struct hwrm_cfa_tunnel_filter_alloc_output {
24914 /* The specific error status for the command. */
24915 uint16_t error_code;
24916 /* The HWRM command request type. */
24918 /* The sequence ID from the original command. */
24920 /* The length of the response data in number of bytes. */
24922 /* This value is an opaque id into CFA data structures. */
24923 uint64_t tunnel_filter_id;
24925 * The flow id value in bit 0-29 is the actual ID of the flow
24926 * associated with this filter and it shall be used to match
24927 * and associate the flow identifier returned in completion
24928 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24929 * shall indicate no valid flow id.
24932 /* Indicate the flow id value. */
24933 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24934 UINT32_C(0x3fffffff)
24935 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24936 /* Indicate type of the flow. */
24937 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24938 UINT32_C(0x40000000)
24940 * If this bit set to 0, then it indicates that the flow is
24943 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24944 (UINT32_C(0x0) << 30)
24946 * If this bit is set to 1, then it indicates that the flow is
24949 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24950 (UINT32_C(0x1) << 30)
24951 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24952 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24953 /* Indicate the flow direction. */
24954 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24955 UINT32_C(0x80000000)
24956 /* If this bit set to 0, then it indicates rx flow. */
24957 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24958 (UINT32_C(0x0) << 31)
24959 /* If this bit is set to 1, then it indicates that tx flow. */
24960 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24961 (UINT32_C(0x1) << 31)
24962 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24963 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24964 uint8_t unused_0[3];
24966 * This field is used in Output records to indicate that the output
24967 * is completely written to RAM. This field should be read as '1'
24968 * to indicate that the output has been completely written.
24969 * When writing a command completion or response to an internal processor,
24970 * the order of writes has to be such that this field is written last.
24973 } __attribute__((packed));
24975 /*******************************
24976 * hwrm_cfa_tunnel_filter_free *
24977 *******************************/
24980 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
24981 struct hwrm_cfa_tunnel_filter_free_input {
24982 /* The HWRM command request type. */
24985 * The completion ring to send the completion event on. This should
24986 * be the NQ ID returned from the `nq_alloc` HWRM command.
24988 uint16_t cmpl_ring;
24990 * The sequence ID is used by the driver for tracking multiple
24991 * commands. This ID is treated as opaque data by the firmware and
24992 * the value is returned in the `hwrm_resp_hdr` upon completion.
24996 * The target ID of the command:
24997 * * 0x0-0xFFF8 - The function ID
24998 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24999 * * 0xFFFD - Reserved for user-space HWRM interface
25002 uint16_t target_id;
25004 * A physical address pointer pointing to a host buffer that the
25005 * command's response data will be written. This can be either a host
25006 * physical address (HPA) or a guest physical address (GPA) and must
25007 * point to a physically contiguous block of memory.
25009 uint64_t resp_addr;
25010 /* This value is an opaque id into CFA data structures. */
25011 uint64_t tunnel_filter_id;
25012 } __attribute__((packed));
25014 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
25015 struct hwrm_cfa_tunnel_filter_free_output {
25016 /* The specific error status for the command. */
25017 uint16_t error_code;
25018 /* The HWRM command request type. */
25020 /* The sequence ID from the original command. */
25022 /* The length of the response data in number of bytes. */
25024 uint8_t unused_0[7];
25026 * This field is used in Output records to indicate that the output
25027 * is completely written to RAM. This field should be read as '1'
25028 * to indicate that the output has been completely written.
25029 * When writing a command completion or response to an internal processor,
25030 * the order of writes has to be such that this field is written last.
25033 } __attribute__((packed));
25035 /***************************************
25036 * hwrm_cfa_redirect_tunnel_type_alloc *
25037 ***************************************/
25040 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
25041 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
25042 /* The HWRM command request type. */
25045 * The completion ring to send the completion event on. This should
25046 * be the NQ ID returned from the `nq_alloc` HWRM command.
25048 uint16_t cmpl_ring;
25050 * The sequence ID is used by the driver for tracking multiple
25051 * commands. This ID is treated as opaque data by the firmware and
25052 * the value is returned in the `hwrm_resp_hdr` upon completion.
25056 * The target ID of the command:
25057 * * 0x0-0xFFF8 - The function ID
25058 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25059 * * 0xFFFD - Reserved for user-space HWRM interface
25062 uint16_t target_id;
25064 * A physical address pointer pointing to a host buffer that the
25065 * command's response data will be written. This can be either a host
25066 * physical address (HPA) or a guest physical address (GPA) and must
25067 * point to a physically contiguous block of memory.
25069 uint64_t resp_addr;
25070 /* The destination function id, to whom the traffic is redirected. */
25073 uint8_t tunnel_type;
25075 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25077 /* Virtual eXtensible Local Area Network (VXLAN) */
25078 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25080 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25081 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25083 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25084 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25087 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25089 /* Generic Network Virtualization Encapsulation (Geneve) */
25090 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25092 /* Multi-Protocol Lable Switching (MPLS) */
25093 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25095 /* Stateless Transport Tunnel (STT) */
25096 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
25098 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25099 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25101 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25102 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25104 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25107 /* Use fixed layer 2 ether type of 0xFFFF */
25108 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25110 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25111 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25113 /* Any tunneled traffic */
25114 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25116 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25117 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25118 /* Tunnel alloc flags. */
25120 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
25121 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
25123 uint8_t unused_0[4];
25124 } __attribute__((packed));
25126 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
25127 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
25128 /* The specific error status for the command. */
25129 uint16_t error_code;
25130 /* The HWRM command request type. */
25132 /* The sequence ID from the original command. */
25134 /* The length of the response data in number of bytes. */
25136 uint8_t unused_0[7];
25138 * This field is used in Output records to indicate that the output
25139 * is completely written to RAM. This field should be read as '1'
25140 * to indicate that the output has been completely written.
25141 * When writing a command completion or response to an internal processor,
25142 * the order of writes has to be such that this field is written last.
25145 } __attribute__((packed));
25147 /**************************************
25148 * hwrm_cfa_redirect_tunnel_type_free *
25149 **************************************/
25152 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
25153 struct hwrm_cfa_redirect_tunnel_type_free_input {
25154 /* The HWRM command request type. */
25157 * The completion ring to send the completion event on. This should
25158 * be the NQ ID returned from the `nq_alloc` HWRM command.
25160 uint16_t cmpl_ring;
25162 * The sequence ID is used by the driver for tracking multiple
25163 * commands. This ID is treated as opaque data by the firmware and
25164 * the value is returned in the `hwrm_resp_hdr` upon completion.
25168 * The target ID of the command:
25169 * * 0x0-0xFFF8 - The function ID
25170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25171 * * 0xFFFD - Reserved for user-space HWRM interface
25174 uint16_t target_id;
25176 * A physical address pointer pointing to a host buffer that the
25177 * command's response data will be written. This can be either a host
25178 * physical address (HPA) or a guest physical address (GPA) and must
25179 * point to a physically contiguous block of memory.
25181 uint64_t resp_addr;
25182 /* The destination function id, to whom the traffic is redirected. */
25185 uint8_t tunnel_type;
25187 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
25189 /* Virtual eXtensible Local Area Network (VXLAN) */
25190 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
25192 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25193 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
25195 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25196 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
25199 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
25201 /* Generic Network Virtualization Encapsulation (Geneve) */
25202 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
25204 /* Multi-Protocol Lable Switching (MPLS) */
25205 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
25207 /* Stateless Transport Tunnel (STT) */
25208 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
25210 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25211 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
25213 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25214 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25216 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25217 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25219 /* Use fixed layer 2 ether type of 0xFFFF */
25220 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
25222 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25223 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25225 /* Any tunneled traffic */
25226 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25228 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
25229 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
25230 uint8_t unused_0[5];
25231 } __attribute__((packed));
25233 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
25234 struct hwrm_cfa_redirect_tunnel_type_free_output {
25235 /* The specific error status for the command. */
25236 uint16_t error_code;
25237 /* The HWRM command request type. */
25239 /* The sequence ID from the original command. */
25241 /* The length of the response data in number of bytes. */
25243 uint8_t unused_0[7];
25245 * This field is used in Output records to indicate that the output
25246 * is completely written to RAM. This field should be read as '1'
25247 * to indicate that the output has been completely written.
25248 * When writing a command completion or response to an internal processor,
25249 * the order of writes has to be such that this field is written last.
25252 } __attribute__((packed));
25254 /**************************************
25255 * hwrm_cfa_redirect_tunnel_type_info *
25256 **************************************/
25259 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
25260 struct hwrm_cfa_redirect_tunnel_type_info_input {
25261 /* The HWRM command request type. */
25264 * The completion ring to send the completion event on. This should
25265 * be the NQ ID returned from the `nq_alloc` HWRM command.
25267 uint16_t cmpl_ring;
25269 * The sequence ID is used by the driver for tracking multiple
25270 * commands. This ID is treated as opaque data by the firmware and
25271 * the value is returned in the `hwrm_resp_hdr` upon completion.
25275 * The target ID of the command:
25276 * * 0x0-0xFFF8 - The function ID
25277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25278 * * 0xFFFD - Reserved for user-space HWRM interface
25281 uint16_t target_id;
25283 * A physical address pointer pointing to a host buffer that the
25284 * command's response data will be written. This can be either a host
25285 * physical address (HPA) or a guest physical address (GPA) and must
25286 * point to a physically contiguous block of memory.
25288 uint64_t resp_addr;
25289 /* The source function id. */
25292 uint8_t tunnel_type;
25294 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
25296 /* Virtual eXtensible Local Area Network (VXLAN) */
25297 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
25299 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25300 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
25302 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25303 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
25306 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
25308 /* Generic Network Virtualization Encapsulation (Geneve) */
25309 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
25311 /* Multi-Protocol Lable Switching (MPLS) */
25312 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
25314 /* Stateless Transport Tunnel (STT) */
25315 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
25317 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25318 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
25320 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25321 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25323 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25324 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25326 /* Use fixed layer 2 ether type of 0xFFFF */
25327 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
25329 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25330 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25332 /* Any tunneled traffic */
25333 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25335 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
25336 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
25337 uint8_t unused_0[5];
25338 } __attribute__((packed));
25340 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
25341 struct hwrm_cfa_redirect_tunnel_type_info_output {
25342 /* The specific error status for the command. */
25343 uint16_t error_code;
25344 /* The HWRM command request type. */
25346 /* The sequence ID from the original command. */
25348 /* The length of the response data in number of bytes. */
25350 /* The destination function id, to whom the traffic is redirected. */
25352 uint8_t unused_0[5];
25354 * This field is used in Output records to indicate that the output
25355 * is completely written to RAM. This field should be read as '1'
25356 * to indicate that the output has been completely written.
25357 * When writing a command completion or response to an internal processor,
25358 * the order of writes has to be such that this field is written last.
25361 } __attribute__((packed));
25363 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
25364 struct hwrm_vxlan_ipv4_hdr {
25365 /* IPv4 version and header length. */
25367 /* IPv4 header length */
25368 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
25369 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
25371 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
25372 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
25373 /* IPv4 type of service. */
25375 /* IPv4 identification. */
25377 /* IPv4 flags and offset. */
25378 uint16_t flags_frag_offset;
25381 /* IPv4 protocol. */
25383 /* IPv4 source address. */
25384 uint32_t src_ip_addr;
25385 /* IPv4 destination address. */
25386 uint32_t dest_ip_addr;
25387 } __attribute__((packed));
25389 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
25390 struct hwrm_vxlan_ipv6_hdr {
25391 /* IPv6 version, traffic class and flow label. */
25392 uint32_t ver_tc_flow_label;
25393 /* IPv6 version shift */
25394 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
25396 /* IPv6 version mask */
25397 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
25398 UINT32_C(0xf0000000)
25399 /* IPv6 TC shift */
25400 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
25403 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
25404 UINT32_C(0xff00000)
25405 /* IPv6 flow label shift */
25406 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
25408 /* IPv6 flow label mask */
25409 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
25411 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
25412 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
25413 /* IPv6 payload length. */
25414 uint16_t payload_len;
25415 /* IPv6 next header. */
25419 /* IPv6 source address. */
25420 uint32_t src_ip_addr[4];
25421 /* IPv6 destination address. */
25422 uint32_t dest_ip_addr[4];
25423 } __attribute__((packed));
25425 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
25426 struct hwrm_cfa_encap_data_vxlan {
25427 /* Source MAC address. */
25428 uint8_t src_mac_addr[6];
25431 /* Destination MAC address. */
25432 uint8_t dst_mac_addr[6];
25433 /* Number of VLAN tags. */
25434 uint8_t num_vlan_tags;
25437 /* Outer VLAN TPID. */
25438 uint16_t ovlan_tpid;
25439 /* Outer VLAN TCI. */
25440 uint16_t ovlan_tci;
25441 /* Inner VLAN TPID. */
25442 uint16_t ivlan_tpid;
25443 /* Inner VLAN TCI. */
25444 uint16_t ivlan_tci;
25445 /* L3 header fields. */
25447 /* IP version mask. */
25448 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
25449 /* IP version 4. */
25450 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
25451 /* IP version 6. */
25452 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
25453 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
25454 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
25455 /* UDP source port. */
25457 /* UDP destination port. */
25459 /* VXLAN Network Identifier. */
25461 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
25462 uint8_t hdr_rsvd0[3];
25463 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
25465 /* VXLAN header flags field. */
25468 } __attribute__((packed));
25470 /*******************************
25471 * hwrm_cfa_encap_record_alloc *
25472 *******************************/
25475 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
25476 struct hwrm_cfa_encap_record_alloc_input {
25477 /* The HWRM command request type. */
25480 * The completion ring to send the completion event on. This should
25481 * be the NQ ID returned from the `nq_alloc` HWRM command.
25483 uint16_t cmpl_ring;
25485 * The sequence ID is used by the driver for tracking multiple
25486 * commands. This ID is treated as opaque data by the firmware and
25487 * the value is returned in the `hwrm_resp_hdr` upon completion.
25491 * The target ID of the command:
25492 * * 0x0-0xFFF8 - The function ID
25493 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25494 * * 0xFFFD - Reserved for user-space HWRM interface
25497 uint16_t target_id;
25499 * A physical address pointer pointing to a host buffer that the
25500 * command's response data will be written. This can be either a host
25501 * physical address (HPA) or a guest physical address (GPA) and must
25502 * point to a physically contiguous block of memory.
25504 uint64_t resp_addr;
25506 /* Setting of this flag indicates the applicability to the loopback path. */
25507 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
25510 * Setting of this flag indicates this encap record is external encap record.
25511 * Resetting of this flag indicates this flag is internal encap record and
25512 * this is the default setting.
25514 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
25516 /* Encapsulation Type. */
25517 uint8_t encap_type;
25518 /* Virtual eXtensible Local Area Network (VXLAN) */
25519 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
25521 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25522 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
25524 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
25525 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
25528 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
25530 /* Generic Network Virtualization Encapsulation (Geneve) */
25531 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
25533 /* Multi-Protocol Lable Switching (MPLS) */
25534 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
25537 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
25539 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25540 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
25542 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25543 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
25545 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25546 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
25548 /* Use fixed layer 2 ether type of 0xFFFF */
25549 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
25551 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25552 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
25554 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
25555 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
25556 uint8_t unused_0[3];
25557 /* This value is encap data used for the given encap type. */
25558 uint32_t encap_data[20];
25559 } __attribute__((packed));
25561 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
25562 struct hwrm_cfa_encap_record_alloc_output {
25563 /* The specific error status for the command. */
25564 uint16_t error_code;
25565 /* The HWRM command request type. */
25567 /* The sequence ID from the original command. */
25569 /* The length of the response data in number of bytes. */
25571 /* This value is an opaque id into CFA data structures. */
25572 uint32_t encap_record_id;
25573 uint8_t unused_0[3];
25575 * This field is used in Output records to indicate that the output
25576 * is completely written to RAM. This field should be read as '1'
25577 * to indicate that the output has been completely written.
25578 * When writing a command completion or response to an internal processor,
25579 * the order of writes has to be such that this field is written last.
25582 } __attribute__((packed));
25584 /******************************
25585 * hwrm_cfa_encap_record_free *
25586 ******************************/
25589 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
25590 struct hwrm_cfa_encap_record_free_input {
25591 /* The HWRM command request type. */
25594 * The completion ring to send the completion event on. This should
25595 * be the NQ ID returned from the `nq_alloc` HWRM command.
25597 uint16_t cmpl_ring;
25599 * The sequence ID is used by the driver for tracking multiple
25600 * commands. This ID is treated as opaque data by the firmware and
25601 * the value is returned in the `hwrm_resp_hdr` upon completion.
25605 * The target ID of the command:
25606 * * 0x0-0xFFF8 - The function ID
25607 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25608 * * 0xFFFD - Reserved for user-space HWRM interface
25611 uint16_t target_id;
25613 * A physical address pointer pointing to a host buffer that the
25614 * command's response data will be written. This can be either a host
25615 * physical address (HPA) or a guest physical address (GPA) and must
25616 * point to a physically contiguous block of memory.
25618 uint64_t resp_addr;
25619 /* This value is an opaque id into CFA data structures. */
25620 uint32_t encap_record_id;
25621 uint8_t unused_0[4];
25622 } __attribute__((packed));
25624 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
25625 struct hwrm_cfa_encap_record_free_output {
25626 /* The specific error status for the command. */
25627 uint16_t error_code;
25628 /* The HWRM command request type. */
25630 /* The sequence ID from the original command. */
25632 /* The length of the response data in number of bytes. */
25634 uint8_t unused_0[7];
25636 * This field is used in Output records to indicate that the output
25637 * is completely written to RAM. This field should be read as '1'
25638 * to indicate that the output has been completely written.
25639 * When writing a command completion or response to an internal processor,
25640 * the order of writes has to be such that this field is written last.
25643 } __attribute__((packed));
25645 /********************************
25646 * hwrm_cfa_ntuple_filter_alloc *
25647 ********************************/
25650 /* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
25651 struct hwrm_cfa_ntuple_filter_alloc_input {
25652 /* The HWRM command request type. */
25655 * The completion ring to send the completion event on. This should
25656 * be the NQ ID returned from the `nq_alloc` HWRM command.
25658 uint16_t cmpl_ring;
25660 * The sequence ID is used by the driver for tracking multiple
25661 * commands. This ID is treated as opaque data by the firmware and
25662 * the value is returned in the `hwrm_resp_hdr` upon completion.
25666 * The target ID of the command:
25667 * * 0x0-0xFFF8 - The function ID
25668 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25669 * * 0xFFFD - Reserved for user-space HWRM interface
25672 uint16_t target_id;
25674 * A physical address pointer pointing to a host buffer that the
25675 * command's response data will be written. This can be either a host
25676 * physical address (HPA) or a guest physical address (GPA) and must
25677 * point to a physically contiguous block of memory.
25679 uint64_t resp_addr;
25681 /* Setting of this flag indicates the applicability to the loopback path. */
25682 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
25685 * Setting of this flag indicates drop action. If this flag is not set,
25686 * then it should be considered accept action.
25688 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
25691 * Setting of this flag indicates that a meter is expected to be attached
25692 * to this flow. This hint can be used when choosing the action record
25693 * format required for the flow.
25695 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
25698 * Setting of this flag indicates that the dest_id field contains function ID.
25699 * If this is not set it indicates dest_id is VNIC or VPORT.
25701 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
25705 * This bit must be '1' for the l2_filter_id field to be
25708 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
25711 * This bit must be '1' for the ethertype field to be
25714 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
25717 * This bit must be '1' for the tunnel_type field to be
25720 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
25723 * This bit must be '1' for the src_macaddr field to be
25726 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
25729 * This bit must be '1' for the ipaddr_type field to be
25732 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
25735 * This bit must be '1' for the src_ipaddr field to be
25738 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
25741 * This bit must be '1' for the src_ipaddr_mask field to be
25744 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
25747 * This bit must be '1' for the dst_ipaddr field to be
25750 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
25753 * This bit must be '1' for the dst_ipaddr_mask field to be
25756 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
25759 * This bit must be '1' for the ip_protocol field to be
25762 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
25765 * This bit must be '1' for the src_port field to be
25768 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
25771 * This bit must be '1' for the src_port_mask field to be
25774 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
25777 * This bit must be '1' for the dst_port field to be
25780 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
25783 * This bit must be '1' for the dst_port_mask field to be
25786 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
25789 * This bit must be '1' for the pri_hint field to be
25792 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
25795 * This bit must be '1' for the ntuple_filter_id field to be
25798 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
25801 * This bit must be '1' for the dst_id field to be
25804 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
25807 * This bit must be '1' for the mirror_vnic_id field to be
25810 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25813 * This bit must be '1' for the dst_macaddr field to be
25816 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
25819 * This bit must be '1' for the rfs_ring_tbl_idx field to be
25822 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
25825 * This value identifies a set of CFA data structures used for an L2
25828 uint64_t l2_filter_id;
25830 * This value indicates the source MAC address in
25831 * the Ethernet header.
25833 uint8_t src_macaddr[6];
25834 /* This value indicates the ethertype in the Ethernet header. */
25835 uint16_t ethertype;
25837 * This value indicates the type of IP address.
25840 * All others are invalid.
25842 uint8_t ip_addr_type;
25844 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
25847 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
25850 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
25852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25853 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25855 * The value of protocol filed in IP header.
25856 * Applies to UDP and TCP traffic.
25860 uint8_t ip_protocol;
25862 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
25865 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
25868 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
25870 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
25871 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
25873 * If set, this value shall represent the
25874 * Logical VNIC ID of the destination VNIC for the RX
25875 * path and network port id of the destination port for
25880 * Logical VNIC ID of the VNIC where traffic is
25883 uint16_t mirror_vnic_id;
25885 * This value indicates the tunnel type for this filter.
25886 * If this field is not specified, then the filter shall
25887 * apply to both non-tunneled and tunneled packets.
25888 * If this field conflicts with the tunnel_type specified
25889 * in the l2_filter_id, then the HWRM shall return an
25890 * error for this command.
25892 uint8_t tunnel_type;
25894 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25896 /* Virtual eXtensible Local Area Network (VXLAN) */
25897 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25899 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25900 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25902 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25903 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25906 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25908 /* Generic Network Virtualization Encapsulation (Geneve) */
25909 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25911 /* Multi-Protocol Lable Switching (MPLS) */
25912 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25914 /* Stateless Transport Tunnel (STT) */
25915 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
25917 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25918 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25920 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25921 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25923 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25924 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25926 /* Use fixed layer 2 ether type of 0xFFFF */
25927 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25929 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25930 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25932 /* Any tunneled traffic */
25933 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25935 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25936 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25938 * This hint is provided to help in placing
25939 * the filter in the filter table.
25942 /* No preference */
25943 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
25945 /* Above the given filter */
25946 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
25948 /* Below the given filter */
25949 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
25951 /* As high as possible */
25952 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
25954 /* As low as possible */
25955 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
25957 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
25958 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
25960 * The value of source IP address to be used in filtering.
25961 * For IPv4, first four bytes represent the IP address.
25963 uint32_t src_ipaddr[4];
25965 * The value of source IP address mask to be used in
25967 * For IPv4, first four bytes represent the IP address mask.
25969 uint32_t src_ipaddr_mask[4];
25971 * The value of destination IP address to be used in filtering.
25972 * For IPv4, first four bytes represent the IP address.
25974 uint32_t dst_ipaddr[4];
25976 * The value of destination IP address mask to be used in
25978 * For IPv4, first four bytes represent the IP address mask.
25980 uint32_t dst_ipaddr_mask[4];
25982 * The value of source port to be used in filtering.
25983 * Applies to UDP and TCP traffic.
25987 * The value of source port mask to be used in filtering.
25988 * Applies to UDP and TCP traffic.
25990 uint16_t src_port_mask;
25992 * The value of destination port to be used in filtering.
25993 * Applies to UDP and TCP traffic.
25997 * The value of destination port mask to be used in
25999 * Applies to UDP and TCP traffic.
26001 uint16_t dst_port_mask;
26003 * This is the ID of the filter that goes along with
26006 uint64_t ntuple_filter_id_hint;
26008 * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
26009 * This index is used in lieu of the RSS hash when selecting the
26010 * index into the RSS table to determine the rx ring.
26012 uint16_t rfs_ring_tbl_idx;
26013 uint8_t unused_0[6];
26014 } __attribute__((packed));
26016 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
26017 struct hwrm_cfa_ntuple_filter_alloc_output {
26018 /* The specific error status for the command. */
26019 uint16_t error_code;
26020 /* The HWRM command request type. */
26022 /* The sequence ID from the original command. */
26024 /* The length of the response data in number of bytes. */
26026 /* This value is an opaque id into CFA data structures. */
26027 uint64_t ntuple_filter_id;
26029 * The flow id value in bit 0-29 is the actual ID of the flow
26030 * associated with this filter and it shall be used to match
26031 * and associate the flow identifier returned in completion
26032 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26033 * shall indicate no valid flow id.
26036 /* Indicate the flow id value. */
26037 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26038 UINT32_C(0x3fffffff)
26039 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26040 /* Indicate type of the flow. */
26041 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
26042 UINT32_C(0x40000000)
26044 * If this bit set to 0, then it indicates that the flow is
26047 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26048 (UINT32_C(0x0) << 30)
26050 * If this bit is set to 1, then it indicates that the flow is
26053 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26054 (UINT32_C(0x1) << 30)
26055 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26056 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26057 /* Indicate the flow direction. */
26058 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
26059 UINT32_C(0x80000000)
26060 /* If this bit set to 0, then it indicates rx flow. */
26061 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26062 (UINT32_C(0x0) << 31)
26063 /* If this bit is set to 1, then it indicates that tx flow. */
26064 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26065 (UINT32_C(0x1) << 31)
26066 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26067 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26068 uint8_t unused_0[3];
26070 * This field is used in Output records to indicate that the output
26071 * is completely written to RAM. This field should be read as '1'
26072 * to indicate that the output has been completely written.
26073 * When writing a command completion or response to an internal processor,
26074 * the order of writes has to be such that this field is written last.
26077 } __attribute__((packed));
26079 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
26080 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
26082 * command specific error codes that goes to
26083 * the cmd_err field in Common HWRM Error Response.
26086 /* Unknown error */
26087 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
26089 /* Unable to complete operation due to conflict with Rx Mask VLAN */
26090 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
26092 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
26093 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
26094 uint8_t unused_0[7];
26095 } __attribute__((packed));
26097 /*******************************
26098 * hwrm_cfa_ntuple_filter_free *
26099 *******************************/
26102 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
26103 struct hwrm_cfa_ntuple_filter_free_input {
26104 /* The HWRM command request type. */
26107 * The completion ring to send the completion event on. This should
26108 * be the NQ ID returned from the `nq_alloc` HWRM command.
26110 uint16_t cmpl_ring;
26112 * The sequence ID is used by the driver for tracking multiple
26113 * commands. This ID is treated as opaque data by the firmware and
26114 * the value is returned in the `hwrm_resp_hdr` upon completion.
26118 * The target ID of the command:
26119 * * 0x0-0xFFF8 - The function ID
26120 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26121 * * 0xFFFD - Reserved for user-space HWRM interface
26124 uint16_t target_id;
26126 * A physical address pointer pointing to a host buffer that the
26127 * command's response data will be written. This can be either a host
26128 * physical address (HPA) or a guest physical address (GPA) and must
26129 * point to a physically contiguous block of memory.
26131 uint64_t resp_addr;
26132 /* This value is an opaque id into CFA data structures. */
26133 uint64_t ntuple_filter_id;
26134 } __attribute__((packed));
26136 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
26137 struct hwrm_cfa_ntuple_filter_free_output {
26138 /* The specific error status for the command. */
26139 uint16_t error_code;
26140 /* The HWRM command request type. */
26142 /* The sequence ID from the original command. */
26144 /* The length of the response data in number of bytes. */
26146 uint8_t unused_0[7];
26148 * This field is used in Output records to indicate that the output
26149 * is completely written to RAM. This field should be read as '1'
26150 * to indicate that the output has been completely written.
26151 * When writing a command completion or response to an internal processor,
26152 * the order of writes has to be such that this field is written last.
26155 } __attribute__((packed));
26157 /******************************
26158 * hwrm_cfa_ntuple_filter_cfg *
26159 ******************************/
26162 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
26163 struct hwrm_cfa_ntuple_filter_cfg_input {
26164 /* The HWRM command request type. */
26167 * The completion ring to send the completion event on. This should
26168 * be the NQ ID returned from the `nq_alloc` HWRM command.
26170 uint16_t cmpl_ring;
26172 * The sequence ID is used by the driver for tracking multiple
26173 * commands. This ID is treated as opaque data by the firmware and
26174 * the value is returned in the `hwrm_resp_hdr` upon completion.
26178 * The target ID of the command:
26179 * * 0x0-0xFFF8 - The function ID
26180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26181 * * 0xFFFD - Reserved for user-space HWRM interface
26184 uint16_t target_id;
26186 * A physical address pointer pointing to a host buffer that the
26187 * command's response data will be written. This can be either a host
26188 * physical address (HPA) or a guest physical address (GPA) and must
26189 * point to a physically contiguous block of memory.
26191 uint64_t resp_addr;
26194 * This bit must be '1' for the new_dst_id field to be
26197 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
26200 * This bit must be '1' for the new_mirror_vnic_id field to be
26203 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
26206 * This bit must be '1' for the new_meter_instance_id field to be
26209 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
26213 * Setting this bit to 1 indicates that dest_id field contains FID.
26214 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
26216 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
26218 /* This value is an opaque id into CFA data structures. */
26219 uint64_t ntuple_filter_id;
26221 * If set, this value shall represent the new
26222 * Logical VNIC ID of the destination VNIC for the RX
26223 * path and new network port id of the destination port for
26226 uint32_t new_dst_id;
26228 * New Logical VNIC ID of the VNIC where traffic is
26231 uint32_t new_mirror_vnic_id;
26233 * New meter to attach to the flow. Specifying the
26234 * invalid instance ID is used to remove any existing
26235 * meter from the flow.
26237 uint16_t new_meter_instance_id;
26239 * A value of 0xfff is considered invalid and implies the
26240 * instance is not configured.
26242 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
26244 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
26245 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
26246 uint8_t unused_1[6];
26247 } __attribute__((packed));
26249 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
26250 struct hwrm_cfa_ntuple_filter_cfg_output {
26251 /* The specific error status for the command. */
26252 uint16_t error_code;
26253 /* The HWRM command request type. */
26255 /* The sequence ID from the original command. */
26257 /* The length of the response data in number of bytes. */
26259 uint8_t unused_0[7];
26261 * This field is used in Output records to indicate that the output
26262 * is completely written to RAM. This field should be read as '1'
26263 * to indicate that the output has been completely written.
26264 * When writing a command completion or response to an internal processor,
26265 * the order of writes has to be such that this field is written last.
26268 } __attribute__((packed));
26270 /**************************
26271 * hwrm_cfa_em_flow_alloc *
26272 **************************/
26275 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
26276 struct hwrm_cfa_em_flow_alloc_input {
26277 /* The HWRM command request type. */
26280 * The completion ring to send the completion event on. This should
26281 * be the NQ ID returned from the `nq_alloc` HWRM command.
26283 uint16_t cmpl_ring;
26285 * The sequence ID is used by the driver for tracking multiple
26286 * commands. This ID is treated as opaque data by the firmware and
26287 * the value is returned in the `hwrm_resp_hdr` upon completion.
26291 * The target ID of the command:
26292 * * 0x0-0xFFF8 - The function ID
26293 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26294 * * 0xFFFD - Reserved for user-space HWRM interface
26297 uint16_t target_id;
26299 * A physical address pointer pointing to a host buffer that the
26300 * command's response data will be written. This can be either a host
26301 * physical address (HPA) or a guest physical address (GPA) and must
26302 * point to a physically contiguous block of memory.
26304 uint64_t resp_addr;
26307 * Enumeration denoting the RX, TX type of the resource.
26308 * This enumeration is used for resources that are similar for both
26309 * TX and RX paths of the chip.
26311 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26313 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26315 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26316 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
26317 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
26319 * Setting of this flag indicates enabling of a byte counter for a given
26322 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
26324 * Setting of this flag indicates enabling of a packet counter for a given
26327 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
26328 /* Setting of this flag indicates de-capsulation action for the given flow. */
26329 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
26330 /* Setting of this flag indicates encapsulation action for the given flow. */
26331 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
26333 * Setting of this flag indicates drop action. If this flag is not set,
26334 * then it should be considered accept action.
26336 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
26338 * Setting of this flag indicates that a meter is expected to be attached
26339 * to this flow. This hint can be used when choosing the action record
26340 * format required for the flow.
26342 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
26345 * This bit must be '1' for the l2_filter_id field to be
26348 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
26351 * This bit must be '1' for the tunnel_type field to be
26354 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26357 * This bit must be '1' for the tunnel_id field to be
26360 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
26363 * This bit must be '1' for the src_macaddr field to be
26366 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
26369 * This bit must be '1' for the dst_macaddr field to be
26372 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
26375 * This bit must be '1' for the ovlan_vid field to be
26378 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
26381 * This bit must be '1' for the ivlan_vid field to be
26384 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
26387 * This bit must be '1' for the ethertype field to be
26390 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
26393 * This bit must be '1' for the src_ipaddr field to be
26396 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
26399 * This bit must be '1' for the dst_ipaddr field to be
26402 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
26405 * This bit must be '1' for the ipaddr_type field to be
26408 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
26411 * This bit must be '1' for the ip_protocol field to be
26414 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
26417 * This bit must be '1' for the src_port field to be
26420 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
26423 * This bit must be '1' for the dst_port field to be
26426 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
26429 * This bit must be '1' for the dst_id field to be
26432 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
26435 * This bit must be '1' for the mirror_vnic_id field to be
26438 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
26441 * This bit must be '1' for the encap_record_id field to be
26444 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
26447 * This bit must be '1' for the meter_instance_id field to be
26450 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
26453 * This value identifies a set of CFA data structures used for an L2
26456 uint64_t l2_filter_id;
26458 uint8_t tunnel_type;
26460 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26462 /* Virtual eXtensible Local Area Network (VXLAN) */
26463 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26465 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26466 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26468 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26469 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26472 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26474 /* Generic Network Virtualization Encapsulation (Geneve) */
26475 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26477 /* Multi-Protocol Lable Switching (MPLS) */
26478 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26480 /* Stateless Transport Tunnel (STT) */
26481 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
26483 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26484 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26486 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26487 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26489 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26490 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26492 /* Use fixed layer 2 ether type of 0xFFFF */
26493 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26495 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26496 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26498 /* Any tunneled traffic */
26499 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26501 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26502 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26503 uint8_t unused_0[3];
26505 * Tunnel identifier.
26506 * Virtual Network Identifier (VNI). Only valid with
26507 * tunnel_types VXLAN, NVGRE, and Geneve.
26508 * Only lower 24-bits of VNI field are used
26509 * in setting up the filter.
26511 uint32_t tunnel_id;
26513 * This value indicates the source MAC address in
26514 * the Ethernet header.
26516 uint8_t src_macaddr[6];
26517 /* The meter instance to attach to the flow. */
26518 uint16_t meter_instance_id;
26520 * A value of 0xfff is considered invalid and implies the
26521 * instance is not configured.
26523 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
26525 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
26526 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
26528 * This value indicates the destination MAC address in
26529 * the Ethernet header.
26531 uint8_t dst_macaddr[6];
26533 * This value indicates the VLAN ID of the outer VLAN tag
26534 * in the Ethernet header.
26536 uint16_t ovlan_vid;
26538 * This value indicates the VLAN ID of the inner VLAN tag
26539 * in the Ethernet header.
26541 uint16_t ivlan_vid;
26542 /* This value indicates the ethertype in the Ethernet header. */
26543 uint16_t ethertype;
26545 * This value indicates the type of IP address.
26548 * All others are invalid.
26550 uint8_t ip_addr_type;
26552 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
26554 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
26556 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
26557 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
26558 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
26560 * The value of protocol filed in IP header.
26561 * Applies to UDP and TCP traffic.
26565 uint8_t ip_protocol;
26567 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
26569 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
26571 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
26572 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
26573 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
26574 uint8_t unused_1[2];
26576 * The value of source IP address to be used in filtering.
26577 * For IPv4, first four bytes represent the IP address.
26579 uint32_t src_ipaddr[4];
26581 * big_endian = True
26582 * The value of destination IP address to be used in filtering.
26583 * For IPv4, first four bytes represent the IP address.
26585 uint32_t dst_ipaddr[4];
26587 * The value of source port to be used in filtering.
26588 * Applies to UDP and TCP traffic.
26592 * The value of destination port to be used in filtering.
26593 * Applies to UDP and TCP traffic.
26597 * If set, this value shall represent the
26598 * Logical VNIC ID of the destination VNIC for the RX
26599 * path and network port id of the destination port for
26604 * Logical VNIC ID of the VNIC where traffic is
26607 uint16_t mirror_vnic_id;
26608 /* Logical ID of the encapsulation record. */
26609 uint32_t encap_record_id;
26610 uint8_t unused_2[4];
26611 } __attribute__((packed));
26613 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
26614 struct hwrm_cfa_em_flow_alloc_output {
26615 /* The specific error status for the command. */
26616 uint16_t error_code;
26617 /* The HWRM command request type. */
26619 /* The sequence ID from the original command. */
26621 /* The length of the response data in number of bytes. */
26623 /* This value is an opaque id into CFA data structures. */
26624 uint64_t em_filter_id;
26626 * The flow id value in bit 0-29 is the actual ID of the flow
26627 * associated with this filter and it shall be used to match
26628 * and associate the flow identifier returned in completion
26629 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26630 * shall indicate no valid flow id.
26633 /* Indicate the flow id value. */
26634 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26635 UINT32_C(0x3fffffff)
26636 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26637 /* Indicate type of the flow. */
26638 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
26639 UINT32_C(0x40000000)
26641 * If this bit set to 0, then it indicates that the flow is
26644 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26645 (UINT32_C(0x0) << 30)
26647 * If this bit is set to 1, then it indicates that the flow is
26650 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26651 (UINT32_C(0x1) << 30)
26652 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26653 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26654 /* Indicate the flow direction. */
26655 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
26656 UINT32_C(0x80000000)
26657 /* If this bit set to 0, then it indicates rx flow. */
26658 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26659 (UINT32_C(0x0) << 31)
26660 /* If this bit is set to 1, then it indicates that tx flow. */
26661 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26662 (UINT32_C(0x1) << 31)
26663 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26664 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26665 uint8_t unused_0[3];
26667 * This field is used in Output records to indicate that the output
26668 * is completely written to RAM. This field should be read as '1'
26669 * to indicate that the output has been completely written.
26670 * When writing a command completion or response to an internal processor,
26671 * the order of writes has to be such that this field is written last.
26674 } __attribute__((packed));
26676 /*************************
26677 * hwrm_cfa_em_flow_free *
26678 *************************/
26681 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
26682 struct hwrm_cfa_em_flow_free_input {
26683 /* The HWRM command request type. */
26686 * The completion ring to send the completion event on. This should
26687 * be the NQ ID returned from the `nq_alloc` HWRM command.
26689 uint16_t cmpl_ring;
26691 * The sequence ID is used by the driver for tracking multiple
26692 * commands. This ID is treated as opaque data by the firmware and
26693 * the value is returned in the `hwrm_resp_hdr` upon completion.
26697 * The target ID of the command:
26698 * * 0x0-0xFFF8 - The function ID
26699 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26700 * * 0xFFFD - Reserved for user-space HWRM interface
26703 uint16_t target_id;
26705 * A physical address pointer pointing to a host buffer that the
26706 * command's response data will be written. This can be either a host
26707 * physical address (HPA) or a guest physical address (GPA) and must
26708 * point to a physically contiguous block of memory.
26710 uint64_t resp_addr;
26711 /* This value is an opaque id into CFA data structures. */
26712 uint64_t em_filter_id;
26713 } __attribute__((packed));
26715 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
26716 struct hwrm_cfa_em_flow_free_output {
26717 /* The specific error status for the command. */
26718 uint16_t error_code;
26719 /* The HWRM command request type. */
26721 /* The sequence ID from the original command. */
26723 /* The length of the response data in number of bytes. */
26725 uint8_t unused_0[7];
26727 * This field is used in Output records to indicate that the output
26728 * is completely written to RAM. This field should be read as '1'
26729 * to indicate that the output has been completely written.
26730 * When writing a command completion or response to an internal processor,
26731 * the order of writes has to be such that this field is written last.
26734 } __attribute__((packed));
26736 /************************
26737 * hwrm_cfa_meter_qcaps *
26738 ************************/
26741 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
26742 struct hwrm_cfa_meter_qcaps_input {
26743 /* The HWRM command request type. */
26746 * The completion ring to send the completion event on. This should
26747 * be the NQ ID returned from the `nq_alloc` HWRM command.
26749 uint16_t cmpl_ring;
26751 * The sequence ID is used by the driver for tracking multiple
26752 * commands. This ID is treated as opaque data by the firmware and
26753 * the value is returned in the `hwrm_resp_hdr` upon completion.
26757 * The target ID of the command:
26758 * * 0x0-0xFFF8 - The function ID
26759 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26760 * * 0xFFFD - Reserved for user-space HWRM interface
26763 uint16_t target_id;
26765 * A physical address pointer pointing to a host buffer that the
26766 * command's response data will be written. This can be either a host
26767 * physical address (HPA) or a guest physical address (GPA) and must
26768 * point to a physically contiguous block of memory.
26770 uint64_t resp_addr;
26771 } __attribute__((packed));
26773 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
26774 struct hwrm_cfa_meter_qcaps_output {
26775 /* The specific error status for the command. */
26776 uint16_t error_code;
26777 /* The HWRM command request type. */
26779 /* The sequence ID from the original command. */
26781 /* The length of the response data in number of bytes. */
26785 * Enumeration denoting the clock at which the Meter is running with.
26786 * This enumeration is used for resources that are similar for both
26787 * TX and RX paths of the chip.
26789 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
26790 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
26792 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
26794 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
26795 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
26796 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
26797 uint8_t unused_0[4];
26799 * The minimum guaranteed number of tx meter profiles supported
26800 * for this function.
26802 uint16_t min_tx_profile;
26804 * The maximum non-guaranteed number of tx meter profiles supported
26805 * for this function.
26807 uint16_t max_tx_profile;
26809 * The minimum guaranteed number of rx meter profiles supported
26810 * for this function.
26812 uint16_t min_rx_profile;
26814 * The maximum non-guaranteed number of rx meter profiles supported
26815 * for this function.
26817 uint16_t max_rx_profile;
26819 * The minimum guaranteed number of tx meter instances supported
26820 * for this function.
26822 uint16_t min_tx_instance;
26824 * The maximum non-guaranteed number of tx meter instances supported
26825 * for this function.
26827 uint16_t max_tx_instance;
26829 * The minimum guaranteed number of rx meter instances supported
26830 * for this function.
26832 uint16_t min_rx_instance;
26834 * The maximum non-guaranteed number of rx meter instances supported
26835 * for this function.
26837 uint16_t max_rx_instance;
26838 uint8_t unused_1[7];
26840 * This field is used in Output records to indicate that the output
26841 * is completely written to RAM. This field should be read as '1'
26842 * to indicate that the output has been completely written.
26843 * When writing a command completion or response to an internal processor,
26844 * the order of writes has to be such that this field is written last.
26847 } __attribute__((packed));
26849 /********************************
26850 * hwrm_cfa_meter_profile_alloc *
26851 ********************************/
26854 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
26855 struct hwrm_cfa_meter_profile_alloc_input {
26856 /* The HWRM command request type. */
26859 * The completion ring to send the completion event on. This should
26860 * be the NQ ID returned from the `nq_alloc` HWRM command.
26862 uint16_t cmpl_ring;
26864 * The sequence ID is used by the driver for tracking multiple
26865 * commands. This ID is treated as opaque data by the firmware and
26866 * the value is returned in the `hwrm_resp_hdr` upon completion.
26870 * The target ID of the command:
26871 * * 0x0-0xFFF8 - The function ID
26872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26873 * * 0xFFFD - Reserved for user-space HWRM interface
26876 uint16_t target_id;
26878 * A physical address pointer pointing to a host buffer that the
26879 * command's response data will be written. This can be either a host
26880 * physical address (HPA) or a guest physical address (GPA) and must
26881 * point to a physically contiguous block of memory.
26883 uint64_t resp_addr;
26886 * Enumeration denoting the RX, TX type of the resource.
26887 * This enumeration is used for resources that are similar for both
26888 * TX and RX paths of the chip.
26890 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26892 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
26895 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
26897 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
26898 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
26899 /* The meter algorithm type. */
26900 uint8_t meter_type;
26901 /* RFC 2697 (srTCM) */
26902 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
26904 /* RFC 2698 (trTCM) */
26905 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
26907 /* RFC 4115 (trTCM) */
26908 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
26910 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
26911 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
26913 * This field is reserved for the future use.
26914 * It shall be set to 0.
26916 uint16_t reserved1;
26918 * This field is reserved for the future use.
26919 * It shall be set to 0.
26921 uint32_t reserved2;
26922 /* A meter rate specified in bytes-per-second. */
26923 uint32_t commit_rate;
26924 /* The bandwidth value. */
26925 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
26926 UINT32_C(0xfffffff)
26927 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
26929 /* The granularity of the value (bits or bytes). */
26930 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
26931 UINT32_C(0x10000000)
26932 /* Value is in bits. */
26933 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
26934 (UINT32_C(0x0) << 28)
26935 /* Value is in bytes. */
26936 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
26937 (UINT32_C(0x1) << 28)
26938 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
26939 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
26940 /* bw_value_unit is 3 b */
26941 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
26942 UINT32_C(0xe0000000)
26943 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
26945 /* Value is in Mb or MB (base 10). */
26946 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
26947 (UINT32_C(0x0) << 29)
26948 /* Value is in Kb or KB (base 10). */
26949 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
26950 (UINT32_C(0x2) << 29)
26951 /* Value is in bits or bytes. */
26952 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
26953 (UINT32_C(0x4) << 29)
26954 /* Value is in Gb or GB (base 10). */
26955 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
26956 (UINT32_C(0x6) << 29)
26957 /* Value is in 1/100th of a percentage of total bandwidth. */
26958 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26959 (UINT32_C(0x1) << 29)
26961 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
26962 (UINT32_C(0x7) << 29)
26963 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
26964 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
26965 /* A meter burst size specified in bytes. */
26966 uint32_t commit_burst;
26967 /* The bandwidth value. */
26968 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
26969 UINT32_C(0xfffffff)
26970 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
26972 /* The granularity of the value (bits or bytes). */
26973 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
26974 UINT32_C(0x10000000)
26975 /* Value is in bits. */
26976 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
26977 (UINT32_C(0x0) << 28)
26978 /* Value is in bytes. */
26979 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
26980 (UINT32_C(0x1) << 28)
26981 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
26982 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
26983 /* bw_value_unit is 3 b */
26984 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
26985 UINT32_C(0xe0000000)
26986 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
26988 /* Value is in Mb or MB (base 10). */
26989 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
26990 (UINT32_C(0x0) << 29)
26991 /* Value is in Kb or KB (base 10). */
26992 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
26993 (UINT32_C(0x2) << 29)
26994 /* Value is in bits or bytes. */
26995 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
26996 (UINT32_C(0x4) << 29)
26997 /* Value is in Gb or GB (base 10). */
26998 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
26999 (UINT32_C(0x6) << 29)
27000 /* Value is in 1/100th of a percentage of total bandwidth. */
27001 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27002 (UINT32_C(0x1) << 29)
27003 /* Invalid value */
27004 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
27005 (UINT32_C(0x7) << 29)
27006 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
27007 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
27008 /* A meter rate specified in bytes-per-second. */
27009 uint32_t excess_peak_rate;
27010 /* The bandwidth value. */
27011 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
27012 UINT32_C(0xfffffff)
27013 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
27015 /* The granularity of the value (bits or bytes). */
27016 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
27017 UINT32_C(0x10000000)
27018 /* Value is in bits. */
27019 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
27020 (UINT32_C(0x0) << 28)
27021 /* Value is in bytes. */
27022 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
27023 (UINT32_C(0x1) << 28)
27024 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
27025 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
27026 /* bw_value_unit is 3 b */
27027 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
27028 UINT32_C(0xe0000000)
27029 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
27031 /* Value is in Mb or MB (base 10). */
27032 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
27033 (UINT32_C(0x0) << 29)
27034 /* Value is in Kb or KB (base 10). */
27035 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
27036 (UINT32_C(0x2) << 29)
27037 /* Value is in bits or bytes. */
27038 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
27039 (UINT32_C(0x4) << 29)
27040 /* Value is in Gb or GB (base 10). */
27041 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
27042 (UINT32_C(0x6) << 29)
27043 /* Value is in 1/100th of a percentage of total bandwidth. */
27044 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27045 (UINT32_C(0x1) << 29)
27047 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
27048 (UINT32_C(0x7) << 29)
27049 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
27050 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
27051 /* A meter burst size specified in bytes. */
27052 uint32_t excess_peak_burst;
27053 /* The bandwidth value. */
27054 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
27055 UINT32_C(0xfffffff)
27056 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
27058 /* The granularity of the value (bits or bytes). */
27059 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
27060 UINT32_C(0x10000000)
27061 /* Value is in bits. */
27062 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
27063 (UINT32_C(0x0) << 28)
27064 /* Value is in bytes. */
27065 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
27066 (UINT32_C(0x1) << 28)
27067 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
27068 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
27069 /* bw_value_unit is 3 b */
27070 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
27071 UINT32_C(0xe0000000)
27072 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
27074 /* Value is in Mb or MB (base 10). */
27075 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
27076 (UINT32_C(0x0) << 29)
27077 /* Value is in Kb or KB (base 10). */
27078 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
27079 (UINT32_C(0x2) << 29)
27080 /* Value is in bits or bytes. */
27081 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
27082 (UINT32_C(0x4) << 29)
27083 /* Value is in Gb or GB (base 10). */
27084 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
27085 (UINT32_C(0x6) << 29)
27086 /* Value is in 1/100th of a percentage of total bandwidth. */
27087 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27088 (UINT32_C(0x1) << 29)
27090 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
27091 (UINT32_C(0x7) << 29)
27092 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
27093 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
27094 } __attribute__((packed));
27096 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
27097 struct hwrm_cfa_meter_profile_alloc_output {
27098 /* The specific error status for the command. */
27099 uint16_t error_code;
27100 /* The HWRM command request type. */
27102 /* The sequence ID from the original command. */
27104 /* The length of the response data in number of bytes. */
27106 /* This value identifies a meter profile in CFA. */
27107 uint16_t meter_profile_id;
27109 * A value of 0xfff is considered invalid and implies the
27110 * profile is not configured.
27112 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
27114 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
27115 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
27116 uint8_t unused_0[5];
27118 * This field is used in Output records to indicate that the output
27119 * is completely written to RAM. This field should be read as '1'
27120 * to indicate that the output has been completely written.
27121 * When writing a command completion or response to an internal processor,
27122 * the order of writes has to be such that this field is written last.
27125 } __attribute__((packed));
27127 /*******************************
27128 * hwrm_cfa_meter_profile_free *
27129 *******************************/
27132 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
27133 struct hwrm_cfa_meter_profile_free_input {
27134 /* The HWRM command request type. */
27137 * The completion ring to send the completion event on. This should
27138 * be the NQ ID returned from the `nq_alloc` HWRM command.
27140 uint16_t cmpl_ring;
27142 * The sequence ID is used by the driver for tracking multiple
27143 * commands. This ID is treated as opaque data by the firmware and
27144 * the value is returned in the `hwrm_resp_hdr` upon completion.
27148 * The target ID of the command:
27149 * * 0x0-0xFFF8 - The function ID
27150 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27151 * * 0xFFFD - Reserved for user-space HWRM interface
27154 uint16_t target_id;
27156 * A physical address pointer pointing to a host buffer that the
27157 * command's response data will be written. This can be either a host
27158 * physical address (HPA) or a guest physical address (GPA) and must
27159 * point to a physically contiguous block of memory.
27161 uint64_t resp_addr;
27164 * Enumeration denoting the RX, TX type of the resource.
27165 * This enumeration is used for resources that are similar for both
27166 * TX and RX paths of the chip.
27168 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
27170 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
27173 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
27175 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
27176 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
27178 /* This value identifies a meter profile in CFA. */
27179 uint16_t meter_profile_id;
27181 * A value of 0xfff is considered invalid and implies the
27182 * profile is not configured.
27184 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
27186 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
27187 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
27188 uint8_t unused_1[4];
27189 } __attribute__((packed));
27191 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
27192 struct hwrm_cfa_meter_profile_free_output {
27193 /* The specific error status for the command. */
27194 uint16_t error_code;
27195 /* The HWRM command request type. */
27197 /* The sequence ID from the original command. */
27199 /* The length of the response data in number of bytes. */
27201 uint8_t unused_0[7];
27203 * This field is used in Output records to indicate that the output
27204 * is completely written to RAM. This field should be read as '1'
27205 * to indicate that the output has been completely written.
27206 * When writing a command completion or response to an internal processor,
27207 * the order of writes has to be such that this field is written last.
27210 } __attribute__((packed));
27212 /******************************
27213 * hwrm_cfa_meter_profile_cfg *
27214 ******************************/
27217 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
27218 struct hwrm_cfa_meter_profile_cfg_input {
27219 /* The HWRM command request type. */
27222 * The completion ring to send the completion event on. This should
27223 * be the NQ ID returned from the `nq_alloc` HWRM command.
27225 uint16_t cmpl_ring;
27227 * The sequence ID is used by the driver for tracking multiple
27228 * commands. This ID is treated as opaque data by the firmware and
27229 * the value is returned in the `hwrm_resp_hdr` upon completion.
27233 * The target ID of the command:
27234 * * 0x0-0xFFF8 - The function ID
27235 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27236 * * 0xFFFD - Reserved for user-space HWRM interface
27239 uint16_t target_id;
27241 * A physical address pointer pointing to a host buffer that the
27242 * command's response data will be written. This can be either a host
27243 * physical address (HPA) or a guest physical address (GPA) and must
27244 * point to a physically contiguous block of memory.
27246 uint64_t resp_addr;
27249 * Enumeration denoting the RX, TX type of the resource.
27250 * This enumeration is used for resources that are similar for both
27251 * TX and RX paths of the chip.
27253 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27255 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27257 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27258 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
27259 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
27260 /* The meter algorithm type. */
27261 uint8_t meter_type;
27262 /* RFC 2697 (srTCM) */
27263 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
27265 /* RFC 2698 (trTCM) */
27266 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
27268 /* RFC 4115 (trTCM) */
27269 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
27271 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
27272 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
27273 /* This value identifies a meter profile in CFA. */
27274 uint16_t meter_profile_id;
27276 * A value of 0xfff is considered invalid and implies the
27277 * profile is not configured.
27279 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
27281 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
27282 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
27284 * This field is reserved for the future use.
27285 * It shall be set to 0.
27288 /* A meter rate specified in bytes-per-second. */
27289 uint32_t commit_rate;
27290 /* The bandwidth value. */
27291 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
27292 UINT32_C(0xfffffff)
27293 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
27295 /* The granularity of the value (bits or bytes). */
27296 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
27297 UINT32_C(0x10000000)
27298 /* Value is in bits. */
27299 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
27300 (UINT32_C(0x0) << 28)
27301 /* Value is in bytes. */
27302 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
27303 (UINT32_C(0x1) << 28)
27304 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
27305 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
27306 /* bw_value_unit is 3 b */
27307 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
27308 UINT32_C(0xe0000000)
27309 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
27311 /* Value is in Mb or MB (base 10). */
27312 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
27313 (UINT32_C(0x0) << 29)
27314 /* Value is in Kb or KB (base 10). */
27315 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
27316 (UINT32_C(0x2) << 29)
27317 /* Value is in bits or bytes. */
27318 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
27319 (UINT32_C(0x4) << 29)
27320 /* Value is in Gb or GB (base 10). */
27321 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
27322 (UINT32_C(0x6) << 29)
27323 /* Value is in 1/100th of a percentage of total bandwidth. */
27324 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27325 (UINT32_C(0x1) << 29)
27327 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
27328 (UINT32_C(0x7) << 29)
27329 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
27330 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
27331 /* A meter burst size specified in bytes. */
27332 uint32_t commit_burst;
27333 /* The bandwidth value. */
27334 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
27335 UINT32_C(0xfffffff)
27336 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
27338 /* The granularity of the value (bits or bytes). */
27339 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
27340 UINT32_C(0x10000000)
27341 /* Value is in bits. */
27342 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
27343 (UINT32_C(0x0) << 28)
27344 /* Value is in bytes. */
27345 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
27346 (UINT32_C(0x1) << 28)
27347 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
27348 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
27349 /* bw_value_unit is 3 b */
27350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
27351 UINT32_C(0xe0000000)
27352 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
27354 /* Value is in Mb or MB (base 10). */
27355 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
27356 (UINT32_C(0x0) << 29)
27357 /* Value is in Kb or KB (base 10). */
27358 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
27359 (UINT32_C(0x2) << 29)
27360 /* Value is in bits or bytes. */
27361 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
27362 (UINT32_C(0x4) << 29)
27363 /* Value is in Gb or GB (base 10). */
27364 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
27365 (UINT32_C(0x6) << 29)
27366 /* Value is in 1/100th of a percentage of total bandwidth. */
27367 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27368 (UINT32_C(0x1) << 29)
27369 /* Invalid value */
27370 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
27371 (UINT32_C(0x7) << 29)
27372 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
27373 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
27374 /* A meter rate specified in bytes-per-second. */
27375 uint32_t excess_peak_rate;
27376 /* The bandwidth value. */
27377 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
27378 UINT32_C(0xfffffff)
27379 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
27381 /* The granularity of the value (bits or bytes). */
27382 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
27383 UINT32_C(0x10000000)
27384 /* Value is in bits. */
27385 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
27386 (UINT32_C(0x0) << 28)
27387 /* Value is in bytes. */
27388 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
27389 (UINT32_C(0x1) << 28)
27390 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
27391 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
27392 /* bw_value_unit is 3 b */
27393 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
27394 UINT32_C(0xe0000000)
27395 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
27397 /* Value is in Mb or MB (base 10). */
27398 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
27399 (UINT32_C(0x0) << 29)
27400 /* Value is in Kb or KB (base 10). */
27401 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
27402 (UINT32_C(0x2) << 29)
27403 /* Value is in bits or bytes. */
27404 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
27405 (UINT32_C(0x4) << 29)
27406 /* Value is in Gb or GB (base 10). */
27407 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
27408 (UINT32_C(0x6) << 29)
27409 /* Value is in 1/100th of a percentage of total bandwidth. */
27410 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
27411 (UINT32_C(0x1) << 29)
27413 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
27414 (UINT32_C(0x7) << 29)
27415 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
27416 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
27417 /* A meter burst size specified in bytes. */
27418 uint32_t excess_peak_burst;
27419 /* The bandwidth value. */
27420 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
27421 UINT32_C(0xfffffff)
27422 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
27424 /* The granularity of the value (bits or bytes). */
27425 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
27426 UINT32_C(0x10000000)
27427 /* Value is in bits. */
27428 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
27429 (UINT32_C(0x0) << 28)
27430 /* Value is in bytes. */
27431 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
27432 (UINT32_C(0x1) << 28)
27433 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
27434 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
27435 /* bw_value_unit is 3 b */
27436 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
27437 UINT32_C(0xe0000000)
27438 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
27440 /* Value is in Mb or MB (base 10). */
27441 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
27442 (UINT32_C(0x0) << 29)
27443 /* Value is in Kb or KB (base 10). */
27444 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
27445 (UINT32_C(0x2) << 29)
27446 /* Value is in bits or bytes. */
27447 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
27448 (UINT32_C(0x4) << 29)
27449 /* Value is in Gb or GB (base 10). */
27450 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
27451 (UINT32_C(0x6) << 29)
27452 /* Value is in 1/100th of a percentage of total bandwidth. */
27453 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
27454 (UINT32_C(0x1) << 29)
27456 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
27457 (UINT32_C(0x7) << 29)
27458 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
27459 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
27460 } __attribute__((packed));
27462 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
27463 struct hwrm_cfa_meter_profile_cfg_output {
27464 /* The specific error status for the command. */
27465 uint16_t error_code;
27466 /* The HWRM command request type. */
27468 /* The sequence ID from the original command. */
27470 /* The length of the response data in number of bytes. */
27472 uint8_t unused_0[7];
27474 * This field is used in Output records to indicate that the output
27475 * is completely written to RAM. This field should be read as '1'
27476 * to indicate that the output has been completely written.
27477 * When writing a command completion or response to an internal processor,
27478 * the order of writes has to be such that this field is written last.
27481 } __attribute__((packed));
27483 /*********************************
27484 * hwrm_cfa_meter_instance_alloc *
27485 *********************************/
27488 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
27489 struct hwrm_cfa_meter_instance_alloc_input {
27490 /* The HWRM command request type. */
27493 * The completion ring to send the completion event on. This should
27494 * be the NQ ID returned from the `nq_alloc` HWRM command.
27496 uint16_t cmpl_ring;
27498 * The sequence ID is used by the driver for tracking multiple
27499 * commands. This ID is treated as opaque data by the firmware and
27500 * the value is returned in the `hwrm_resp_hdr` upon completion.
27504 * The target ID of the command:
27505 * * 0x0-0xFFF8 - The function ID
27506 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27507 * * 0xFFFD - Reserved for user-space HWRM interface
27510 uint16_t target_id;
27512 * A physical address pointer pointing to a host buffer that the
27513 * command's response data will be written. This can be either a host
27514 * physical address (HPA) or a guest physical address (GPA) and must
27515 * point to a physically contiguous block of memory.
27517 uint64_t resp_addr;
27520 * Enumeration denoting the RX, TX type of the resource.
27521 * This enumeration is used for resources that are similar for both
27522 * TX and RX paths of the chip.
27524 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
27527 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
27530 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
27532 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
27533 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
27535 /* This value identifies a meter profile in CFA. */
27536 uint16_t meter_profile_id;
27538 * A value of 0xffff is considered invalid and implies the
27539 * profile is not configured.
27541 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
27543 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
27544 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
27545 uint8_t unused_1[4];
27546 } __attribute__((packed));
27548 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
27549 struct hwrm_cfa_meter_instance_alloc_output {
27550 /* The specific error status for the command. */
27551 uint16_t error_code;
27552 /* The HWRM command request type. */
27554 /* The sequence ID from the original command. */
27556 /* The length of the response data in number of bytes. */
27558 /* This value identifies a meter instance in CFA. */
27559 uint16_t meter_instance_id;
27561 * A value of 0xffff is considered invalid and implies the
27562 * instance is not configured.
27564 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
27566 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
27567 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
27568 uint8_t unused_0[5];
27570 * This field is used in Output records to indicate that the output
27571 * is completely written to RAM. This field should be read as '1'
27572 * to indicate that the output has been completely written.
27573 * When writing a command completion or response to an internal processor,
27574 * the order of writes has to be such that this field is written last.
27577 } __attribute__((packed));
27579 /*******************************
27580 * hwrm_cfa_meter_instance_cfg *
27581 *******************************/
27584 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
27585 struct hwrm_cfa_meter_instance_cfg_input {
27586 /* The HWRM command request type. */
27589 * The completion ring to send the completion event on. This should
27590 * be the NQ ID returned from the `nq_alloc` HWRM command.
27592 uint16_t cmpl_ring;
27594 * The sequence ID is used by the driver for tracking multiple
27595 * commands. This ID is treated as opaque data by the firmware and
27596 * the value is returned in the `hwrm_resp_hdr` upon completion.
27600 * The target ID of the command:
27601 * * 0x0-0xFFF8 - The function ID
27602 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27603 * * 0xFFFD - Reserved for user-space HWRM interface
27606 uint16_t target_id;
27608 * A physical address pointer pointing to a host buffer that the
27609 * command's response data will be written. This can be either a host
27610 * physical address (HPA) or a guest physical address (GPA) and must
27611 * point to a physically contiguous block of memory.
27613 uint64_t resp_addr;
27616 * Enumeration denoting the RX, TX type of the resource.
27617 * This enumeration is used for resources that are similar for both
27618 * TX and RX paths of the chip.
27620 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27622 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
27625 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
27627 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
27628 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
27631 * This value identifies a new meter profile to be associated with
27632 * the meter instance specified in this command.
27634 uint16_t meter_profile_id;
27636 * A value of 0xffff is considered invalid and implies the
27637 * profile is not configured.
27639 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
27641 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
27642 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
27644 * This value identifies the ID of a meter instance that needs to be updated with
27645 * a new meter profile specified in this command.
27647 uint16_t meter_instance_id;
27648 uint8_t unused_1[2];
27649 } __attribute__((packed));
27651 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
27652 struct hwrm_cfa_meter_instance_cfg_output {
27653 /* The specific error status for the command. */
27654 uint16_t error_code;
27655 /* The HWRM command request type. */
27657 /* The sequence ID from the original command. */
27659 /* The length of the response data in number of bytes. */
27661 uint8_t unused_0[7];
27663 * This field is used in Output records to indicate that the output
27664 * is completely written to RAM. This field should be read as '1'
27665 * to indicate that the output has been completely written.
27666 * When writing a command completion or response to an internal processor,
27667 * the order of writes has to be such that this field is written last.
27670 } __attribute__((packed));
27672 /********************************
27673 * hwrm_cfa_meter_instance_free *
27674 ********************************/
27677 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
27678 struct hwrm_cfa_meter_instance_free_input {
27679 /* The HWRM command request type. */
27682 * The completion ring to send the completion event on. This should
27683 * be the NQ ID returned from the `nq_alloc` HWRM command.
27685 uint16_t cmpl_ring;
27687 * The sequence ID is used by the driver for tracking multiple
27688 * commands. This ID is treated as opaque data by the firmware and
27689 * the value is returned in the `hwrm_resp_hdr` upon completion.
27693 * The target ID of the command:
27694 * * 0x0-0xFFF8 - The function ID
27695 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27696 * * 0xFFFD - Reserved for user-space HWRM interface
27699 uint16_t target_id;
27701 * A physical address pointer pointing to a host buffer that the
27702 * command's response data will be written. This can be either a host
27703 * physical address (HPA) or a guest physical address (GPA) and must
27704 * point to a physically contiguous block of memory.
27706 uint64_t resp_addr;
27709 * Enumeration denoting the RX, TX type of the resource.
27710 * This enumeration is used for resources that are similar for both
27711 * TX and RX paths of the chip.
27713 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
27715 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
27718 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
27720 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
27721 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
27723 /* This value identifies a meter instance in CFA. */
27724 uint16_t meter_instance_id;
27726 * A value of 0xfff is considered invalid and implies the
27727 * instance is not configured.
27729 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
27731 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
27732 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
27733 uint8_t unused_1[4];
27734 } __attribute__((packed));
27736 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
27737 struct hwrm_cfa_meter_instance_free_output {
27738 /* The specific error status for the command. */
27739 uint16_t error_code;
27740 /* The HWRM command request type. */
27742 /* The sequence ID from the original command. */
27744 /* The length of the response data in number of bytes. */
27746 uint8_t unused_0[7];
27748 * This field is used in Output records to indicate that the output
27749 * is completely written to RAM. This field should be read as '1'
27750 * to indicate that the output has been completely written.
27751 * When writing a command completion or response to an internal processor,
27752 * the order of writes has to be such that this field is written last.
27755 } __attribute__((packed));
27757 /*******************************
27758 * hwrm_cfa_decap_filter_alloc *
27759 *******************************/
27762 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
27763 struct hwrm_cfa_decap_filter_alloc_input {
27764 /* The HWRM command request type. */
27767 * The completion ring to send the completion event on. This should
27768 * be the NQ ID returned from the `nq_alloc` HWRM command.
27770 uint16_t cmpl_ring;
27772 * The sequence ID is used by the driver for tracking multiple
27773 * commands. This ID is treated as opaque data by the firmware and
27774 * the value is returned in the `hwrm_resp_hdr` upon completion.
27778 * The target ID of the command:
27779 * * 0x0-0xFFF8 - The function ID
27780 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27781 * * 0xFFFD - Reserved for user-space HWRM interface
27784 uint16_t target_id;
27786 * A physical address pointer pointing to a host buffer that the
27787 * command's response data will be written. This can be either a host
27788 * physical address (HPA) or a guest physical address (GPA) and must
27789 * point to a physically contiguous block of memory.
27791 uint64_t resp_addr;
27793 /* ovs_tunnel is 1 b */
27794 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
27798 * This bit must be '1' for the tunnel_type field to be
27801 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27804 * This bit must be '1' for the tunnel_id field to be
27807 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
27810 * This bit must be '1' for the src_macaddr field to be
27813 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
27816 * This bit must be '1' for the dst_macaddr field to be
27819 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
27822 * This bit must be '1' for the ovlan_vid field to be
27825 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
27828 * This bit must be '1' for the ivlan_vid field to be
27831 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
27834 * This bit must be '1' for the t_ovlan_vid field to be
27837 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
27840 * This bit must be '1' for the t_ivlan_vid field to be
27843 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
27846 * This bit must be '1' for the ethertype field to be
27849 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
27852 * This bit must be '1' for the src_ipaddr field to be
27855 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
27858 * This bit must be '1' for the dst_ipaddr field to be
27861 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
27864 * This bit must be '1' for the ipaddr_type field to be
27867 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
27870 * This bit must be '1' for the ip_protocol field to be
27873 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
27876 * This bit must be '1' for the src_port field to be
27879 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
27882 * This bit must be '1' for the dst_port field to be
27885 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
27888 * This bit must be '1' for the dst_id field to be
27891 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
27894 * This bit must be '1' for the mirror_vnic_id field to be
27897 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27900 * Tunnel identifier.
27901 * Virtual Network Identifier (VNI). Only valid with
27902 * tunnel_types VXLAN, NVGRE, and Geneve.
27903 * Only lower 24-bits of VNI field are used
27904 * in setting up the filter.
27906 uint32_t tunnel_id;
27908 uint8_t tunnel_type;
27910 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27912 /* Virtual eXtensible Local Area Network (VXLAN) */
27913 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27915 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27916 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27918 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27919 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27922 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27924 /* Generic Network Virtualization Encapsulation (Geneve) */
27925 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27927 /* Multi-Protocol Lable Switching (MPLS) */
27928 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27930 /* Stateless Transport Tunnel (STT) */
27931 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
27933 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27934 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27936 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27937 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27939 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27940 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27942 /* Use fixed layer 2 ether type of 0xFFFF */
27943 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27945 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27946 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27948 /* Any tunneled traffic */
27949 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27951 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27952 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27956 * This value indicates the source MAC address in
27957 * the Ethernet header.
27959 uint8_t src_macaddr[6];
27960 uint8_t unused_2[2];
27962 * This value indicates the destination MAC address in
27963 * the Ethernet header.
27965 uint8_t dst_macaddr[6];
27967 * This value indicates the VLAN ID of the outer VLAN tag
27968 * in the Ethernet header.
27970 uint16_t ovlan_vid;
27972 * This value indicates the VLAN ID of the inner VLAN tag
27973 * in the Ethernet header.
27975 uint16_t ivlan_vid;
27977 * This value indicates the VLAN ID of the outer VLAN tag
27978 * in the tunnel Ethernet header.
27980 uint16_t t_ovlan_vid;
27982 * This value indicates the VLAN ID of the inner VLAN tag
27983 * in the tunnel Ethernet header.
27985 uint16_t t_ivlan_vid;
27986 /* This value indicates the ethertype in the Ethernet header. */
27987 uint16_t ethertype;
27989 * This value indicates the type of IP address.
27992 * All others are invalid.
27994 uint8_t ip_addr_type;
27996 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
27999 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
28002 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
28004 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
28005 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
28007 * The value of protocol filed in IP header.
28008 * Applies to UDP and TCP traffic.
28012 uint8_t ip_protocol;
28014 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
28017 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
28020 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
28022 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
28023 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
28027 * The value of source IP address to be used in filtering.
28028 * For IPv4, first four bytes represent the IP address.
28030 uint32_t src_ipaddr[4];
28032 * The value of destination IP address to be used in filtering.
28033 * For IPv4, first four bytes represent the IP address.
28035 uint32_t dst_ipaddr[4];
28037 * The value of source port to be used in filtering.
28038 * Applies to UDP and TCP traffic.
28042 * The value of destination port to be used in filtering.
28043 * Applies to UDP and TCP traffic.
28047 * If set, this value shall represent the
28048 * Logical VNIC ID of the destination VNIC for the RX
28053 * If set, this value shall represent the L2 context that matches the L2
28054 * information of the decap filter.
28056 uint16_t l2_ctxt_ref_id;
28057 } __attribute__((packed));
28059 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
28060 struct hwrm_cfa_decap_filter_alloc_output {
28061 /* The specific error status for the command. */
28062 uint16_t error_code;
28063 /* The HWRM command request type. */
28065 /* The sequence ID from the original command. */
28067 /* The length of the response data in number of bytes. */
28069 /* This value is an opaque id into CFA data structures. */
28070 uint32_t decap_filter_id;
28071 uint8_t unused_0[3];
28073 * This field is used in Output records to indicate that the output
28074 * is completely written to RAM. This field should be read as '1'
28075 * to indicate that the output has been completely written.
28076 * When writing a command completion or response to an internal processor,
28077 * the order of writes has to be such that this field is written last.
28080 } __attribute__((packed));
28082 /******************************
28083 * hwrm_cfa_decap_filter_free *
28084 ******************************/
28087 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
28088 struct hwrm_cfa_decap_filter_free_input {
28089 /* The HWRM command request type. */
28092 * The completion ring to send the completion event on. This should
28093 * be the NQ ID returned from the `nq_alloc` HWRM command.
28095 uint16_t cmpl_ring;
28097 * The sequence ID is used by the driver for tracking multiple
28098 * commands. This ID is treated as opaque data by the firmware and
28099 * the value is returned in the `hwrm_resp_hdr` upon completion.
28103 * The target ID of the command:
28104 * * 0x0-0xFFF8 - The function ID
28105 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28106 * * 0xFFFD - Reserved for user-space HWRM interface
28109 uint16_t target_id;
28111 * A physical address pointer pointing to a host buffer that the
28112 * command's response data will be written. This can be either a host
28113 * physical address (HPA) or a guest physical address (GPA) and must
28114 * point to a physically contiguous block of memory.
28116 uint64_t resp_addr;
28117 /* This value is an opaque id into CFA data structures. */
28118 uint32_t decap_filter_id;
28119 uint8_t unused_0[4];
28120 } __attribute__((packed));
28122 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
28123 struct hwrm_cfa_decap_filter_free_output {
28124 /* The specific error status for the command. */
28125 uint16_t error_code;
28126 /* The HWRM command request type. */
28128 /* The sequence ID from the original command. */
28130 /* The length of the response data in number of bytes. */
28132 uint8_t unused_0[7];
28134 * This field is used in Output records to indicate that the output
28135 * is completely written to RAM. This field should be read as '1'
28136 * to indicate that the output has been completely written.
28137 * When writing a command completion or response to an internal processor,
28138 * the order of writes has to be such that this field is written last.
28141 } __attribute__((packed));
28143 /***********************
28144 * hwrm_cfa_flow_alloc *
28145 ***********************/
28148 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
28149 struct hwrm_cfa_flow_alloc_input {
28150 /* The HWRM command request type. */
28153 * The completion ring to send the completion event on. This should
28154 * be the NQ ID returned from the `nq_alloc` HWRM command.
28156 uint16_t cmpl_ring;
28158 * The sequence ID is used by the driver for tracking multiple
28159 * commands. This ID is treated as opaque data by the firmware and
28160 * the value is returned in the `hwrm_resp_hdr` upon completion.
28164 * The target ID of the command:
28165 * * 0x0-0xFFF8 - The function ID
28166 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28167 * * 0xFFFD - Reserved for user-space HWRM interface
28170 uint16_t target_id;
28172 * A physical address pointer pointing to a host buffer that the
28173 * command's response data will be written. This can be either a host
28174 * physical address (HPA) or a guest physical address (GPA) and must
28175 * point to a physically contiguous block of memory.
28177 uint64_t resp_addr;
28179 /* tunnel is 1 b */
28180 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
28182 /* num_vlan is 2 b */
28183 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
28185 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
28187 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
28188 (UINT32_C(0x0) << 1)
28190 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
28191 (UINT32_C(0x1) << 1)
28193 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
28194 (UINT32_C(0x2) << 1)
28195 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
28196 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
28197 /* Enumeration denoting the Flow Type. */
28198 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
28200 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
28202 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
28203 (UINT32_C(0x0) << 3)
28205 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
28206 (UINT32_C(0x1) << 3)
28208 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
28209 (UINT32_C(0x2) << 3)
28210 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
28211 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
28213 * when set to 1, indicates TX flow offload for function specified in src_fid and
28214 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
28215 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
28216 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
28217 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
28218 * belong to the children VFs of the same PF to indicate VM to VM flow.
28220 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
28223 * when set to 1, indicates RX flow offload for function specified in dst_fid and
28224 * the src_fid should be set to invalid value.
28226 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
28229 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
28230 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
28231 * This flag is only valid when the flow direction is RX.
28233 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
28235 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
28236 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
28243 /* Tunnel handle valid when tunnel flag is set. */
28244 uint32_t tunnel_handle;
28245 uint16_t action_flags;
28247 * Setting of this flag indicates drop action. If this flag is not set,
28248 * then it should be considered accept action.
28250 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
28252 /* recycle is 1 b */
28253 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
28256 * Setting of this flag indicates drop action. If this flag is not set,
28257 * then it should be considered accept action.
28259 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
28262 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
28264 /* tunnel is 1 b */
28265 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
28267 /* nat_src is 1 b */
28268 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
28270 /* nat_dest is 1 b */
28271 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
28273 /* nat_ipv4_address is 1 b */
28274 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
28276 /* l2_header_rewrite is 1 b */
28277 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
28279 /* ttl_decrement is 1 b */
28280 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
28283 * If set to 1 and flow direction is TX, it indicates decap of L2 header
28284 * and encap of tunnel header. If set to 1 and flow direction is RX, it
28285 * indicates decap of tunnel header and encap L2 header. The type of tunnel
28286 * is specified in the tunnel_type field.
28288 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
28290 /* If set to 1, flow aging is enabled for this flow. */
28291 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
28294 * If set to 1 an attempt will be made to try to offload this flow to the
28295 * most optimal flow table resource. If set to 0, the flow will be
28296 * placed to the default flow table resource.
28298 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
28301 * If set to 1 there will be no attempt to allocate an on-chip try to
28302 * offload this flow. If set to 0, which will keep compatibility with the
28303 * older drivers, will cause the FW to attempt to allocate an on-chip flow
28304 * counter for the newly created flow. This will keep the existing behavior
28305 * with EM flows which always had an associated flow counter.
28307 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
28310 * Tx Flow: pf or vf fid.
28314 /* VLAN tpid, valid when push_vlan flag is set. */
28315 uint16_t l2_rewrite_vlan_tpid;
28316 /* VLAN tci, valid when push_vlan flag is set. */
28317 uint16_t l2_rewrite_vlan_tci;
28318 /* Meter id, valid when meter flag is set. */
28319 uint16_t act_meter_id;
28320 /* Flow with the same l2 context tcam key. */
28321 uint16_t ref_flow_handle;
28322 /* This value sets the match value for the ethertype. */
28323 uint16_t ethertype;
28324 /* valid when num tags is 1 or 2. */
28325 uint16_t outer_vlan_tci;
28326 /* This value sets the match value for the Destination MAC address. */
28328 /* valid when num tags is 2. */
28329 uint16_t inner_vlan_tci;
28330 /* This value sets the match value for the Source MAC address. */
28332 /* The bit length of destination IP address mask. */
28333 uint8_t ip_dst_mask_len;
28334 /* The bit length of source IP address mask. */
28335 uint8_t ip_src_mask_len;
28336 /* The value of destination IPv4/IPv6 address. */
28337 uint32_t ip_dst[4];
28338 /* The source IPv4/IPv6 address. */
28339 uint32_t ip_src[4];
28341 * The value of source port.
28342 * Applies to UDP and TCP traffic.
28344 uint16_t l4_src_port;
28346 * The value of source port mask.
28347 * Applies to UDP and TCP traffic.
28349 uint16_t l4_src_port_mask;
28351 * The value of destination port.
28352 * Applies to UDP and TCP traffic.
28354 uint16_t l4_dst_port;
28356 * The value of destination port mask.
28357 * Applies to UDP and TCP traffic.
28359 uint16_t l4_dst_port_mask;
28361 * NAT IPv4/6 address based on address type flag.
28362 * 0 values are ignored.
28364 uint32_t nat_ip_address[4];
28365 /* L2 header re-write Destination MAC address. */
28366 uint16_t l2_rewrite_dmac[3];
28368 * The NAT source/destination port based on direction flag.
28369 * Applies to UDP and TCP traffic.
28370 * 0 values are ignored.
28373 /* L2 header re-write Source MAC address. */
28374 uint16_t l2_rewrite_smac[3];
28375 /* The value of ip protocol. */
28378 uint8_t tunnel_type;
28380 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
28382 /* Virtual eXtensible Local Area Network (VXLAN) */
28383 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
28385 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28386 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
28388 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28389 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
28392 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
28394 /* Generic Network Virtualization Encapsulation (Geneve) */
28395 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
28397 /* Multi-Protocol Lable Switching (MPLS) */
28398 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
28400 /* Stateless Transport Tunnel (STT) */
28401 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
28403 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28404 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
28406 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28407 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
28409 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28410 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
28412 /* Use fixed layer 2 ether type of 0xFFFF */
28413 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
28415 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28416 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
28418 /* Any tunneled traffic */
28419 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
28421 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
28422 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
28423 } __attribute__((packed));
28425 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
28426 struct hwrm_cfa_flow_alloc_output {
28427 /* The specific error status for the command. */
28428 uint16_t error_code;
28429 /* The HWRM command request type. */
28431 /* The sequence ID from the original command. */
28433 /* The length of the response data in number of bytes. */
28435 /* Flow record index. */
28436 uint16_t flow_handle;
28437 uint8_t unused_0[2];
28439 * The flow id value in bit 0-29 is the actual ID of the flow
28440 * associated with this filter and it shall be used to match
28441 * and associate the flow identifier returned in completion
28442 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
28443 * shall indicate no valid flow id.
28446 /* Indicate the flow id value. */
28447 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
28448 UINT32_C(0x3fffffff)
28449 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
28450 /* Indicate type of the flow. */
28451 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
28452 UINT32_C(0x40000000)
28454 * If this bit set to 0, then it indicates that the flow is
28457 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
28458 (UINT32_C(0x0) << 30)
28460 * If this bit is set to 1, then it indicates that the flow is
28463 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
28464 (UINT32_C(0x1) << 30)
28465 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
28466 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
28467 /* Indicate the flow direction. */
28468 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
28469 UINT32_C(0x80000000)
28470 /* If this bit set to 0, then it indicates rx flow. */
28471 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
28472 (UINT32_C(0x0) << 31)
28473 /* If this bit is set to 1, then it indicates that tx flow. */
28474 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
28475 (UINT32_C(0x1) << 31)
28476 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
28477 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
28478 /* This value identifies a set of CFA data structures used for a flow. */
28479 uint64_t ext_flow_handle;
28480 uint32_t flow_counter_id;
28481 uint8_t unused_1[3];
28483 * This field is used in Output records to indicate that the output
28484 * is completely written to RAM. This field should be read as '1'
28485 * to indicate that the output has been completely written.
28486 * When writing a command completion or response to an internal processor,
28487 * the order of writes has to be such that this field is written last.
28490 } __attribute__((packed));
28492 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
28493 struct hwrm_cfa_flow_alloc_cmd_err {
28495 * command specific error codes that goes to
28496 * the cmd_err field in Common HWRM Error Response.
28499 /* Unknown error */
28500 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28501 /* No more L2 Context TCAM */
28502 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
28503 /* No more action records */
28504 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
28505 /* No more flow counters */
28506 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
28507 /* No more wild-card TCAM */
28508 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
28509 /* Hash collsion in exact match tables */
28510 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
28511 /* Key is already installed */
28512 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
28513 /* Flow Context DB is out of resource */
28514 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
28515 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
28516 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
28517 uint8_t unused_0[7];
28518 } __attribute__((packed));
28520 /**********************
28521 * hwrm_cfa_flow_free *
28522 **********************/
28525 /* hwrm_cfa_flow_free_input (size:256b/32B) */
28526 struct hwrm_cfa_flow_free_input {
28527 /* The HWRM command request type. */
28530 * The completion ring to send the completion event on. This should
28531 * be the NQ ID returned from the `nq_alloc` HWRM command.
28533 uint16_t cmpl_ring;
28535 * The sequence ID is used by the driver for tracking multiple
28536 * commands. This ID is treated as opaque data by the firmware and
28537 * the value is returned in the `hwrm_resp_hdr` upon completion.
28541 * The target ID of the command:
28542 * * 0x0-0xFFF8 - The function ID
28543 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28544 * * 0xFFFD - Reserved for user-space HWRM interface
28547 uint16_t target_id;
28549 * A physical address pointer pointing to a host buffer that the
28550 * command's response data will be written. This can be either a host
28551 * physical address (HPA) or a guest physical address (GPA) and must
28552 * point to a physically contiguous block of memory.
28554 uint64_t resp_addr;
28555 /* Flow record index. */
28556 uint16_t flow_handle;
28558 /* Flow counter id to be freed. */
28559 uint32_t flow_counter_id;
28560 /* This value identifies a set of CFA data structures used for a flow. */
28561 uint64_t ext_flow_handle;
28562 } __attribute__((packed));
28564 /* hwrm_cfa_flow_free_output (size:256b/32B) */
28565 struct hwrm_cfa_flow_free_output {
28566 /* The specific error status for the command. */
28567 uint16_t error_code;
28568 /* The HWRM command request type. */
28570 /* The sequence ID from the original command. */
28572 /* The length of the response data in number of bytes. */
28574 /* packet is 64 b */
28578 uint8_t unused_0[7];
28580 * This field is used in Output records to indicate that the output
28581 * is completely written to RAM. This field should be read as '1'
28582 * to indicate that the output has been completely written.
28583 * When writing a command completion or response to an internal processor,
28584 * the order of writes has to be such that this field is written last.
28587 } __attribute__((packed));
28589 /* hwrm_cfa_flow_action_data (size:960b/120B) */
28590 struct hwrm_cfa_flow_action_data {
28591 uint16_t action_flags;
28592 /* Setting of this flag indicates accept action. */
28593 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
28595 /* Setting of this flag indicates recycle action. */
28596 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
28598 /* Setting of this flag indicates drop action. */
28599 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
28601 /* Setting of this flag indicates meter action. */
28602 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
28604 /* Setting of this flag indicates tunnel action. */
28605 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
28608 * If set to 1 and flow direction is TX, it indicates decap of L2 header
28609 * and encap of tunnel header. If set to 1 and flow direction is RX, it
28610 * indicates decap of tunnel header and encap L2 header.
28612 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
28614 /* Setting of this flag indicates ttl decrement action. */
28615 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
28617 /* If set to 1, flow aging is enabled for this flow. */
28618 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
28620 /* Setting of this flag indicates encap action.. */
28621 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
28623 /* Setting of this flag indicates decap action.. */
28624 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
28627 uint16_t act_meter_id;
28630 /* vport number. */
28632 /* The NAT source/destination. */
28634 uint16_t unused_0[3];
28635 /* NAT IPv4/IPv6 address. */
28636 uint32_t nat_ip_address[4];
28637 /* Encapsulation Type. */
28638 uint8_t encap_type;
28639 /* Virtual eXtensible Local Area Network (VXLAN) */
28640 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
28641 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28642 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
28643 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
28644 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
28646 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
28647 /* Generic Network Virtualization Encapsulation (Geneve) */
28648 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
28649 /* Multi-Protocol Lable Switching (MPLS) */
28650 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
28652 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
28653 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28654 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
28655 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28656 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
28657 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28658 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
28659 /* Use fixed layer 2 ether type of 0xFFFF */
28660 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
28661 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28662 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
28663 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
28664 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
28666 /* This value is encap data for the associated encap type. */
28667 uint32_t encap_data[20];
28668 } __attribute__((packed));
28670 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
28671 struct hwrm_cfa_flow_tunnel_hdr_data {
28673 uint8_t tunnel_type;
28675 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
28677 /* Virtual eXtensible Local Area Network (VXLAN) */
28678 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
28680 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28681 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
28683 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28684 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
28687 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
28689 /* Generic Network Virtualization Encapsulation (Geneve) */
28690 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
28692 /* Multi-Protocol Lable Switching (MPLS) */
28693 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
28695 /* Stateless Transport Tunnel (STT) */
28696 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
28698 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28699 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
28701 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28702 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
28704 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28705 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
28707 /* Use fixed layer 2 ether type of 0xFFFF */
28708 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
28710 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28711 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
28713 /* Any tunneled traffic */
28714 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
28716 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
28717 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
28720 * Tunnel identifier.
28721 * Virtual Network Identifier (VNI).
28723 uint32_t tunnel_id;
28724 } __attribute__((packed));
28726 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
28727 struct hwrm_cfa_flow_l4_key_data {
28728 /* The value of source port. */
28729 uint16_t l4_src_port;
28730 /* The value of destination port. */
28731 uint16_t l4_dst_port;
28733 } __attribute__((packed));
28735 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
28736 struct hwrm_cfa_flow_l3_key_data {
28737 /* The value of ip protocol. */
28738 uint8_t ip_protocol;
28739 uint8_t unused_0[7];
28740 /* The value of destination IPv4/IPv6 address. */
28741 uint32_t ip_dst[4];
28742 /* The source IPv4/IPv6 address. */
28743 uint32_t ip_src[4];
28744 /* NAT IPv4/IPv6 address. */
28745 uint32_t nat_ip_address[4];
28746 uint32_t unused[2];
28747 } __attribute__((packed));
28749 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
28750 struct hwrm_cfa_flow_l2_key_data {
28751 /* Destination MAC address. */
28754 /* Source MAC address. */
28757 /* L2 header re-write Destination MAC address. */
28758 uint16_t l2_rewrite_dmac[3];
28760 /* L2 header re-write Source MAC address. */
28761 uint16_t l2_rewrite_smac[3];
28763 uint16_t ethertype;
28764 /* Number of VLAN tags. */
28765 uint16_t num_vlan_tags;
28767 uint16_t l2_rewrite_vlan_tpid;
28769 uint16_t l2_rewrite_vlan_tci;
28770 uint8_t unused_3[2];
28771 /* Outer VLAN TPID. */
28772 uint16_t ovlan_tpid;
28773 /* Outer VLAN TCI. */
28774 uint16_t ovlan_tci;
28775 /* Inner VLAN TPID. */
28776 uint16_t ivlan_tpid;
28777 /* Inner VLAN TCI. */
28778 uint16_t ivlan_tci;
28780 } __attribute__((packed));
28782 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
28783 struct hwrm_cfa_flow_key_data {
28784 /* Flow associated tunnel L2 header key info. */
28785 uint32_t t_l2_key_data[14];
28786 /* Flow associated tunnel L2 header mask info. */
28787 uint32_t t_l2_key_mask[14];
28788 /* Flow associated tunnel L3 header key info. */
28789 uint32_t t_l3_key_data[16];
28790 /* Flow associated tunnel L3 header mask info. */
28791 uint32_t t_l3_key_mask[16];
28792 /* Flow associated tunnel L4 header key info. */
28793 uint32_t t_l4_key_data[2];
28794 /* Flow associated tunnel L4 header mask info. */
28795 uint32_t t_l4_key_mask[2];
28796 /* Flow associated tunnel header info. */
28797 uint32_t tunnel_hdr[2];
28798 /* Flow associated L2 header key info. */
28799 uint32_t l2_key_data[14];
28800 /* Flow associated L2 header mask info. */
28801 uint32_t l2_key_mask[14];
28802 /* Flow associated L3 header key info. */
28803 uint32_t l3_key_data[16];
28804 /* Flow associated L3 header mask info. */
28805 uint32_t l3_key_mask[16];
28806 /* Flow associated L4 header key info. */
28807 uint32_t l4_key_data[2];
28808 /* Flow associated L4 header mask info. */
28809 uint32_t l4_key_mask[2];
28810 } __attribute__((packed));
28812 /**********************
28813 * hwrm_cfa_flow_info *
28814 **********************/
28817 /* hwrm_cfa_flow_info_input (size:256b/32B) */
28818 struct hwrm_cfa_flow_info_input {
28819 /* The HWRM command request type. */
28822 * The completion ring to send the completion event on. This should
28823 * be the NQ ID returned from the `nq_alloc` HWRM command.
28825 uint16_t cmpl_ring;
28827 * The sequence ID is used by the driver for tracking multiple
28828 * commands. This ID is treated as opaque data by the firmware and
28829 * the value is returned in the `hwrm_resp_hdr` upon completion.
28833 * The target ID of the command:
28834 * * 0x0-0xFFF8 - The function ID
28835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28836 * * 0xFFFD - Reserved for user-space HWRM interface
28839 uint16_t target_id;
28841 * A physical address pointer pointing to a host buffer that the
28842 * command's response data will be written. This can be either a host
28843 * physical address (HPA) or a guest physical address (GPA) and must
28844 * point to a physically contiguous block of memory.
28846 uint64_t resp_addr;
28847 /* Flow record index. */
28848 uint16_t flow_handle;
28849 /* Max flow handle */
28850 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
28852 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
28853 /* CNP flow handle */
28854 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
28856 /* RoCEv1 flow handle */
28857 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
28859 /* RoCEv2 flow handle */
28860 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
28862 /* Direction rx = 1 */
28863 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
28865 uint8_t unused_0[6];
28866 /* This value identifies a set of CFA data structures used for a flow. */
28867 uint64_t ext_flow_handle;
28868 } __attribute__((packed));
28870 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
28871 struct hwrm_cfa_flow_info_output {
28872 /* The specific error status for the command. */
28873 uint16_t error_code;
28874 /* The HWRM command request type. */
28876 /* The sequence ID from the original command. */
28878 /* The length of the response data in number of bytes. */
28881 /* When set to 1, indicates the configuration is the TX flow. */
28882 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
28883 /* When set to 1, indicates the configuration is the RX flow. */
28884 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
28885 /* profile is 8 b */
28887 /* src_fid is 16 b */
28889 /* dst_fid is 16 b */
28891 /* l2_ctxt_id is 16 b */
28892 uint16_t l2_ctxt_id;
28893 /* em_info is 64 b */
28895 /* tcam_info is 64 b */
28896 uint64_t tcam_info;
28897 /* vfp_tcam_info is 64 b */
28898 uint64_t vfp_tcam_info;
28899 /* ar_id is 16 b */
28901 /* flow_handle is 16 b */
28902 uint16_t flow_handle;
28903 /* tunnel_handle is 32 b */
28904 uint32_t tunnel_handle;
28905 /* The flow aging timer for the flow, the unit is 100 milliseconds */
28906 uint16_t flow_timer;
28907 uint8_t unused_0[6];
28908 /* Flow associated L2, L3 and L4 headers info. */
28909 uint32_t flow_key_data[130];
28910 /* Flow associated action record info. */
28911 uint32_t flow_action_info[30];
28912 uint8_t unused_1[7];
28914 * This field is used in Output records to indicate that the output
28915 * is completely written to RAM. This field should be read as '1'
28916 * to indicate that the output has been completely written.
28917 * When writing a command completion or response to an internal processor,
28918 * the order of writes has to be such that this field is written last.
28921 } __attribute__((packed));
28923 /***********************
28924 * hwrm_cfa_flow_flush *
28925 ***********************/
28928 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
28929 struct hwrm_cfa_flow_flush_input {
28930 /* The HWRM command request type. */
28933 * The completion ring to send the completion event on. This should
28934 * be the NQ ID returned from the `nq_alloc` HWRM command.
28936 uint16_t cmpl_ring;
28938 * The sequence ID is used by the driver for tracking multiple
28939 * commands. This ID is treated as opaque data by the firmware and
28940 * the value is returned in the `hwrm_resp_hdr` upon completion.
28944 * The target ID of the command:
28945 * * 0x0-0xFFF8 - The function ID
28946 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28947 * * 0xFFFD - Reserved for user-space HWRM interface
28950 uint16_t target_id;
28952 * A physical address pointer pointing to a host buffer that the
28953 * command's response data will be written. This can be either a host
28954 * physical address (HPA) or a guest physical address (GPA) and must
28955 * point to a physically contiguous block of memory.
28957 uint64_t resp_addr;
28958 /* flags is 32 b */
28961 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
28962 * fields are valid. The flow flush operation should only flush the flows from the
28963 * flow table specified. This flag is set to 0 by older driver. For older firmware,
28964 * setting this flag has no effect.
28966 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
28969 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
28970 * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
28971 * setting this flag has no effect.
28973 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
28976 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
28977 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
28979 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
28981 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
28982 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
28983 UINT32_C(0x8000000)
28985 * This specifies the size of flow handle entries provided by the driver
28986 * in the flow table specified below. Only two flow handle size enums are defined.
28988 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
28989 UINT32_C(0xc0000000)
28990 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
28992 /* The flow handle is 16bit */
28993 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
28994 (UINT32_C(0x0) << 30)
28995 /* The flow handle is 64bit */
28996 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
28997 (UINT32_C(0x1) << 30)
28998 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
28999 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
29000 /* Specify page size of the flow table memory. */
29002 /* The page size is 4K */
29003 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
29004 /* The page size is 8K */
29005 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
29006 /* The page size is 64K */
29007 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
29008 /* The page size is 256K */
29009 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
29010 /* The page size is 1M */
29011 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29012 /* The page size is 2M */
29013 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29014 /* The page size is 4M */
29015 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29016 /* The page size is 1G */
29017 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29018 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
29019 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
29020 /* FLow table memory indirect levels. */
29021 uint8_t page_level;
29022 /* PBL pointer is physical start address. */
29023 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29024 /* PBL pointer points to PTE table. */
29025 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29026 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29027 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29028 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
29029 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
29030 /* number of flows in the flow table */
29031 uint16_t num_flows;
29032 /* Pointer to the PBL, or PDL depending on number of levels */
29034 } __attribute__((packed));
29036 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
29037 struct hwrm_cfa_flow_flush_output {
29038 /* The specific error status for the command. */
29039 uint16_t error_code;
29040 /* The HWRM command request type. */
29042 /* The sequence ID from the original command. */
29044 /* The length of the response data in number of bytes. */
29046 uint8_t unused_0[7];
29048 * This field is used in Output records to indicate that the output
29049 * is completely written to RAM. This field should be read as '1'
29050 * to indicate that the output has been completely written.
29051 * When writing a command completion or response to an internal processor,
29052 * the order of writes has to be such that this field is written last.
29055 } __attribute__((packed));
29057 /***********************
29058 * hwrm_cfa_flow_stats *
29059 ***********************/
29062 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
29063 struct hwrm_cfa_flow_stats_input {
29064 /* The HWRM command request type. */
29067 * The completion ring to send the completion event on. This should
29068 * be the NQ ID returned from the `nq_alloc` HWRM command.
29070 uint16_t cmpl_ring;
29072 * The sequence ID is used by the driver for tracking multiple
29073 * commands. This ID is treated as opaque data by the firmware and
29074 * the value is returned in the `hwrm_resp_hdr` upon completion.
29078 * The target ID of the command:
29079 * * 0x0-0xFFF8 - The function ID
29080 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29081 * * 0xFFFD - Reserved for user-space HWRM interface
29084 uint16_t target_id;
29086 * A physical address pointer pointing to a host buffer that the
29087 * command's response data will be written. This can be either a host
29088 * physical address (HPA) or a guest physical address (GPA) and must
29089 * point to a physically contiguous block of memory.
29091 uint64_t resp_addr;
29093 uint16_t num_flows;
29095 uint16_t flow_handle_0;
29097 uint16_t flow_handle_1;
29099 uint16_t flow_handle_2;
29101 uint16_t flow_handle_3;
29103 uint16_t flow_handle_4;
29105 uint16_t flow_handle_5;
29107 uint16_t flow_handle_6;
29109 uint16_t flow_handle_7;
29111 uint16_t flow_handle_8;
29113 uint16_t flow_handle_9;
29114 uint8_t unused_0[2];
29115 /* Flow ID of a flow. */
29116 uint32_t flow_id_0;
29117 /* Flow ID of a flow. */
29118 uint32_t flow_id_1;
29119 /* Flow ID of a flow. */
29120 uint32_t flow_id_2;
29121 /* Flow ID of a flow. */
29122 uint32_t flow_id_3;
29123 /* Flow ID of a flow. */
29124 uint32_t flow_id_4;
29125 /* Flow ID of a flow. */
29126 uint32_t flow_id_5;
29127 /* Flow ID of a flow. */
29128 uint32_t flow_id_6;
29129 /* Flow ID of a flow. */
29130 uint32_t flow_id_7;
29131 /* Flow ID of a flow. */
29132 uint32_t flow_id_8;
29133 /* Flow ID of a flow. */
29134 uint32_t flow_id_9;
29135 } __attribute__((packed));
29137 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
29138 struct hwrm_cfa_flow_stats_output {
29139 /* The specific error status for the command. */
29140 uint16_t error_code;
29141 /* The HWRM command request type. */
29143 /* The sequence ID from the original command. */
29145 /* The length of the response data in number of bytes. */
29147 /* packet_0 is 64 b */
29149 /* packet_1 is 64 b */
29151 /* packet_2 is 64 b */
29153 /* packet_3 is 64 b */
29155 /* packet_4 is 64 b */
29157 /* packet_5 is 64 b */
29159 /* packet_6 is 64 b */
29161 /* packet_7 is 64 b */
29163 /* packet_8 is 64 b */
29165 /* packet_9 is 64 b */
29167 /* byte_0 is 64 b */
29169 /* byte_1 is 64 b */
29171 /* byte_2 is 64 b */
29173 /* byte_3 is 64 b */
29175 /* byte_4 is 64 b */
29177 /* byte_5 is 64 b */
29179 /* byte_6 is 64 b */
29181 /* byte_7 is 64 b */
29183 /* byte_8 is 64 b */
29185 /* byte_9 is 64 b */
29187 uint8_t unused_0[7];
29189 * This field is used in Output records to indicate that the output
29190 * is completely written to RAM. This field should be read as '1'
29191 * to indicate that the output has been completely written.
29192 * When writing a command completion or response to an internal processor,
29193 * the order of writes has to be such that this field is written last.
29196 } __attribute__((packed));
29198 /***********************************
29199 * hwrm_cfa_flow_aging_timer_reset *
29200 ***********************************/
29203 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
29204 struct hwrm_cfa_flow_aging_timer_reset_input {
29205 /* The HWRM command request type. */
29208 * The completion ring to send the completion event on. This should
29209 * be the NQ ID returned from the `nq_alloc` HWRM command.
29211 uint16_t cmpl_ring;
29213 * The sequence ID is used by the driver for tracking multiple
29214 * commands. This ID is treated as opaque data by the firmware and
29215 * the value is returned in the `hwrm_resp_hdr` upon completion.
29219 * The target ID of the command:
29220 * * 0x0-0xFFF8 - The function ID
29221 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29222 * * 0xFFFD - Reserved for user-space HWRM interface
29225 uint16_t target_id;
29227 * A physical address pointer pointing to a host buffer that the
29228 * command's response data will be written. This can be either a host
29229 * physical address (HPA) or a guest physical address (GPA) and must
29230 * point to a physically contiguous block of memory.
29232 uint64_t resp_addr;
29233 /* Flow record index. */
29234 uint16_t flow_handle;
29235 uint8_t unused_0[2];
29237 * New flow timer value for the flow specified in the ext_flow_handle.
29238 * The flow timer unit is 100ms.
29240 uint32_t flow_timer;
29241 /* This value identifies a set of CFA data structures used for a flow. */
29242 uint64_t ext_flow_handle;
29243 } __attribute__((packed));
29245 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
29246 struct hwrm_cfa_flow_aging_timer_reset_output {
29247 /* The specific error status for the command. */
29248 uint16_t error_code;
29249 /* The HWRM command request type. */
29251 /* The sequence ID from the original command. */
29253 /* The length of the response data in number of bytes. */
29255 uint8_t unused_0[7];
29257 * This field is used in Output records to indicate that the output
29258 * is completely written to RAM. This field should be read as '1'
29259 * to indicate that the output has been completely written.
29260 * When writing a command completion or response to an internal processor,
29261 * the order of writes has to be such that this field is written last.
29264 } __attribute__((packed));
29266 /***************************
29267 * hwrm_cfa_flow_aging_cfg *
29268 ***************************/
29271 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
29272 struct hwrm_cfa_flow_aging_cfg_input {
29273 /* The HWRM command request type. */
29276 * The completion ring to send the completion event on. This should
29277 * be the NQ ID returned from the `nq_alloc` HWRM command.
29279 uint16_t cmpl_ring;
29281 * The sequence ID is used by the driver for tracking multiple
29282 * commands. This ID is treated as opaque data by the firmware and
29283 * the value is returned in the `hwrm_resp_hdr` upon completion.
29287 * The target ID of the command:
29288 * * 0x0-0xFFF8 - The function ID
29289 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29290 * * 0xFFFD - Reserved for user-space HWRM interface
29293 uint16_t target_id;
29295 * A physical address pointer pointing to a host buffer that the
29296 * command's response data will be written. This can be either a host
29297 * physical address (HPA) or a guest physical address (GPA) and must
29298 * point to a physically contiguous block of memory.
29300 uint64_t resp_addr;
29301 /* The bit field to enable per flow aging configuration. */
29303 /* This bit must be '1' for the tcp flow timer field to be configured */
29304 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
29306 /* This bit must be '1' for the tcp finish timer field to be configured */
29307 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
29309 /* This bit must be '1' for the udp flow timer field to be configured */
29310 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
29312 /* This bit must be '1' for the eem dma interval field to be configured */
29313 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
29315 /* This bit must be '1' for the eem notice interval field to be configured */
29316 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
29318 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
29319 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
29321 /* This bit must be '1' for the eem context memory ID field to be configured */
29322 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
29324 /* This bit must be '1' for the eem context memory type field to be configured */
29325 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
29328 /* Enumeration denoting the RX, TX type of the resource. */
29329 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29331 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29333 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29334 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
29335 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
29336 /* Enumeration denoting the enable, disable eem flow aging configuration. */
29337 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
29339 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
29340 (UINT32_C(0x0) << 1)
29342 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
29343 (UINT32_C(0x1) << 1)
29344 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
29345 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
29347 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
29348 uint32_t tcp_flow_timer;
29349 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
29350 uint32_t tcp_fin_timer;
29351 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
29352 uint32_t udp_flow_timer;
29353 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
29354 uint16_t eem_dma_interval;
29355 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
29356 uint16_t eem_notice_interval;
29357 /* The maximum entries number in the eem context memory. */
29358 uint32_t eem_ctx_max_entries;
29359 /* The context memory ID for eem flow aging. */
29360 uint16_t eem_ctx_id;
29361 uint16_t eem_ctx_mem_type;
29362 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
29363 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
29365 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
29366 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
29367 uint8_t unused_1[4];
29368 } __attribute__((packed));
29370 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
29371 struct hwrm_cfa_flow_aging_cfg_output {
29372 /* The specific error status for the command. */
29373 uint16_t error_code;
29374 /* The HWRM command request type. */
29376 /* The sequence ID from the original command. */
29378 /* The length of the response data in number of bytes. */
29380 uint8_t unused_0[7];
29382 * This field is used in Output records to indicate that the output
29383 * is completely written to RAM. This field should be read as '1'
29384 * to indicate that the output has been completely written.
29385 * When writing a command completion or response to an internal processor,
29386 * the order of writes has to be such that this field is written last.
29389 } __attribute__((packed));
29391 /****************************
29392 * hwrm_cfa_flow_aging_qcfg *
29393 ****************************/
29396 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
29397 struct hwrm_cfa_flow_aging_qcfg_input {
29398 /* The HWRM command request type. */
29401 * The completion ring to send the completion event on. This should
29402 * be the NQ ID returned from the `nq_alloc` HWRM command.
29404 uint16_t cmpl_ring;
29406 * The sequence ID is used by the driver for tracking multiple
29407 * commands. This ID is treated as opaque data by the firmware and
29408 * the value is returned in the `hwrm_resp_hdr` upon completion.
29412 * The target ID of the command:
29413 * * 0x0-0xFFF8 - The function ID
29414 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29415 * * 0xFFFD - Reserved for user-space HWRM interface
29418 uint16_t target_id;
29420 * A physical address pointer pointing to a host buffer that the
29421 * command's response data will be written. This can be either a host
29422 * physical address (HPA) or a guest physical address (GPA) and must
29423 * point to a physically contiguous block of memory.
29425 uint64_t resp_addr;
29426 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
29428 /* Enumeration denoting the RX, TX type of the resource. */
29429 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
29431 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29433 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29434 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
29435 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
29436 uint8_t unused_0[7];
29437 } __attribute__((packed));
29439 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
29440 struct hwrm_cfa_flow_aging_qcfg_output {
29441 /* The specific error status for the command. */
29442 uint16_t error_code;
29443 /* The HWRM command request type. */
29445 /* The sequence ID from the original command. */
29447 /* The length of the response data in number of bytes. */
29449 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
29450 uint32_t tcp_flow_timer;
29451 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
29452 uint32_t tcp_fin_timer;
29453 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
29454 uint32_t udp_flow_timer;
29455 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
29456 uint16_t eem_dma_interval;
29457 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
29458 uint16_t eem_notice_interval;
29459 /* The maximum entries number in the eem context memory. */
29460 uint32_t eem_ctx_max_entries;
29461 /* The context memory ID for eem flow aging. */
29462 uint16_t eem_ctx_id;
29463 /* The context memory type for eem flow aging. */
29464 uint16_t eem_ctx_mem_type;
29465 uint8_t unused_0[7];
29467 * This field is used in Output records to indicate that the output
29468 * is completely written to RAM. This field should be read as '1'
29469 * to indicate that the output has been completely written.
29470 * When writing a command completion or response to an internal processor,
29471 * the order of writes has to be such that this field is written last.
29474 } __attribute__((packed));
29476 /*****************************
29477 * hwrm_cfa_flow_aging_qcaps *
29478 *****************************/
29481 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
29482 struct hwrm_cfa_flow_aging_qcaps_input {
29483 /* The HWRM command request type. */
29486 * The completion ring to send the completion event on. This should
29487 * be the NQ ID returned from the `nq_alloc` HWRM command.
29489 uint16_t cmpl_ring;
29491 * The sequence ID is used by the driver for tracking multiple
29492 * commands. This ID is treated as opaque data by the firmware and
29493 * the value is returned in the `hwrm_resp_hdr` upon completion.
29497 * The target ID of the command:
29498 * * 0x0-0xFFF8 - The function ID
29499 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29500 * * 0xFFFD - Reserved for user-space HWRM interface
29503 uint16_t target_id;
29505 * A physical address pointer pointing to a host buffer that the
29506 * command's response data will be written. This can be either a host
29507 * physical address (HPA) or a guest physical address (GPA) and must
29508 * point to a physically contiguous block of memory.
29510 uint64_t resp_addr;
29511 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
29513 /* Enumeration denoting the RX, TX type of the resource. */
29514 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
29516 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
29518 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
29519 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
29520 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
29521 uint8_t unused_0[7];
29522 } __attribute__((packed));
29524 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
29525 struct hwrm_cfa_flow_aging_qcaps_output {
29526 /* The specific error status for the command. */
29527 uint16_t error_code;
29528 /* The HWRM command request type. */
29530 /* The sequence ID from the original command. */
29532 /* The length of the response data in number of bytes. */
29534 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
29535 uint32_t max_tcp_flow_timer;
29536 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
29537 uint32_t max_tcp_fin_timer;
29538 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
29539 uint32_t max_udp_flow_timer;
29540 /* The maximum aging flows that HW can support. */
29541 uint32_t max_aging_flows;
29542 uint8_t unused_0[7];
29544 * This field is used in Output records to indicate that the output
29545 * is completely written to RAM. This field should be read as '1'
29546 * to indicate that the output has been completely written.
29547 * When writing a command completion or response to an internal processor,
29548 * the order of writes has to be such that this field is written last.
29551 } __attribute__((packed));
29553 /**********************************
29554 * hwrm_cfa_tcp_flag_process_qcfg *
29555 **********************************/
29558 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
29559 struct hwrm_cfa_tcp_flag_process_qcfg_input {
29560 /* The HWRM command request type. */
29563 * The completion ring to send the completion event on. This should
29564 * be the NQ ID returned from the `nq_alloc` HWRM command.
29566 uint16_t cmpl_ring;
29568 * The sequence ID is used by the driver for tracking multiple
29569 * commands. This ID is treated as opaque data by the firmware and
29570 * the value is returned in the `hwrm_resp_hdr` upon completion.
29574 * The target ID of the command:
29575 * * 0x0-0xFFF8 - The function ID
29576 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29577 * * 0xFFFD - Reserved for user-space HWRM interface
29580 uint16_t target_id;
29582 * A physical address pointer pointing to a host buffer that the
29583 * command's response data will be written. This can be either a host
29584 * physical address (HPA) or a guest physical address (GPA) and must
29585 * point to a physically contiguous block of memory.
29587 uint64_t resp_addr;
29588 } __attribute__((packed));
29590 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
29591 struct hwrm_cfa_tcp_flag_process_qcfg_output {
29592 /* The specific error status for the command. */
29593 uint16_t error_code;
29594 /* The HWRM command request type. */
29596 /* The sequence ID from the original command. */
29598 /* The length of the response data in number of bytes. */
29600 /* The port 0 RX mirror action record ID. */
29601 uint16_t rx_ar_id_port0;
29602 /* The port 1 RX mirror action record ID. */
29603 uint16_t rx_ar_id_port1;
29604 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
29605 uint16_t tx_ar_id_port0;
29606 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
29607 uint16_t tx_ar_id_port1;
29608 uint8_t unused_0[7];
29610 * This field is used in Output records to indicate that the output
29611 * is completely written to RAM. This field should be read as '1'
29612 * to indicate that the output has been completely written.
29613 * When writing a command completion or response to an internal processor,
29614 * the order of writes has to be such that this field is written last.
29617 } __attribute__((packed));
29619 /**********************
29620 * hwrm_cfa_pair_info *
29621 **********************/
29624 /* hwrm_cfa_pair_info_input (size:448b/56B) */
29625 struct hwrm_cfa_pair_info_input {
29626 /* The HWRM command request type. */
29629 * The completion ring to send the completion event on. This should
29630 * be the NQ ID returned from the `nq_alloc` HWRM command.
29632 uint16_t cmpl_ring;
29634 * The sequence ID is used by the driver for tracking multiple
29635 * commands. This ID is treated as opaque data by the firmware and
29636 * the value is returned in the `hwrm_resp_hdr` upon completion.
29640 * The target ID of the command:
29641 * * 0x0-0xFFF8 - The function ID
29642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29643 * * 0xFFFD - Reserved for user-space HWRM interface
29646 uint16_t target_id;
29648 * A physical address pointer pointing to a host buffer that the
29649 * command's response data will be written. This can be either a host
29650 * physical address (HPA) or a guest physical address (GPA) and must
29651 * point to a physically contiguous block of memory.
29653 uint64_t resp_addr;
29655 /* If this flag is set, lookup by name else lookup by index. */
29656 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
29657 /* If this flag is set, lookup by PF id and VF id. */
29658 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
29659 /* Pair table index. */
29660 uint16_t pair_index;
29661 /* Pair pf index. */
29663 /* Pair vf index. */
29665 /* Pair name (32 byte string). */
29666 char pair_name[32];
29667 } __attribute__((packed));
29669 /* hwrm_cfa_pair_info_output (size:576b/72B) */
29670 struct hwrm_cfa_pair_info_output {
29671 /* The specific error status for the command. */
29672 uint16_t error_code;
29673 /* The HWRM command request type. */
29675 /* The sequence ID from the original command. */
29677 /* The length of the response data in number of bytes. */
29679 /* Pair table index. */
29680 uint16_t next_pair_index;
29681 /* Pair member a's fid. */
29683 /* Logical host number. */
29684 uint8_t host_a_index;
29685 /* Logical PF number. */
29686 uint8_t pf_a_index;
29687 /* Pair member a's Linux logical VF number. */
29688 uint16_t vf_a_index;
29690 uint16_t rx_cfa_code_a;
29691 /* Tx CFA action. */
29692 uint16_t tx_cfa_action_a;
29693 /* Pair member b's fid. */
29695 /* Logical host number. */
29696 uint8_t host_b_index;
29697 /* Logical PF number. */
29698 uint8_t pf_b_index;
29699 /* Pair member a's Linux logical VF number. */
29700 uint16_t vf_b_index;
29702 uint16_t rx_cfa_code_b;
29703 /* Tx CFA action. */
29704 uint16_t tx_cfa_action_b;
29705 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
29707 /* Pair between VF on local host with PF or VF on specified host. */
29708 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
29709 /* Pair between REP on local host with PF or VF on specified host. */
29710 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
29711 /* Pair between REP on local host with REP on specified host. */
29712 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
29713 /* Pair for the proxy interface. */
29714 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
29715 /* Pair for the PF interface. */
29716 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
29717 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
29718 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
29720 uint8_t pair_state;
29721 /* Pair has been allocated */
29722 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
29723 /* Both pair members are active */
29724 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
29725 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
29726 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
29727 /* Pair name (32 byte string). */
29728 char pair_name[32];
29729 uint8_t unused_0[7];
29731 * This field is used in Output records to indicate that the output
29732 * is completely written to RAM. This field should be read as '1'
29733 * to indicate that the output has been completely written.
29734 * When writing a command completion or response to an internal processor,
29735 * the order of writes has to be such that this field is written last.
29738 } __attribute__((packed));
29740 /***************************************
29741 * hwrm_cfa_redirect_query_tunnel_type *
29742 ***************************************/
29745 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
29746 struct hwrm_cfa_redirect_query_tunnel_type_input {
29747 /* The HWRM command request type. */
29750 * The completion ring to send the completion event on. This should
29751 * be the NQ ID returned from the `nq_alloc` HWRM command.
29753 uint16_t cmpl_ring;
29755 * The sequence ID is used by the driver for tracking multiple
29756 * commands. This ID is treated as opaque data by the firmware and
29757 * the value is returned in the `hwrm_resp_hdr` upon completion.
29761 * The target ID of the command:
29762 * * 0x0-0xFFF8 - The function ID
29763 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29764 * * 0xFFFD - Reserved for user-space HWRM interface
29767 uint16_t target_id;
29769 * A physical address pointer pointing to a host buffer that the
29770 * command's response data will be written. This can be either a host
29771 * physical address (HPA) or a guest physical address (GPA) and must
29772 * point to a physically contiguous block of memory.
29774 uint64_t resp_addr;
29775 /* The source function id. */
29777 uint8_t unused_0[6];
29778 } __attribute__((packed));
29780 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
29781 struct hwrm_cfa_redirect_query_tunnel_type_output {
29782 /* The specific error status for the command. */
29783 uint16_t error_code;
29784 /* The HWRM command request type. */
29786 /* The sequence ID from the original command. */
29788 /* The length of the response data in number of bytes. */
29791 uint32_t tunnel_mask;
29793 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
29795 /* Virtual eXtensible Local Area Network (VXLAN) */
29796 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
29798 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29799 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
29801 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29802 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
29805 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
29807 /* Generic Network Virtualization Encapsulation (Geneve) */
29808 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
29810 /* Multi-Protocol Lable Switching (MPLS) */
29811 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
29813 /* Stateless Transport Tunnel (STT) */
29814 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
29816 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29817 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
29819 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29820 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
29822 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29823 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
29825 /* Any tunneled traffic */
29826 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
29828 /* Use fixed layer 2 ether type of 0xFFFF */
29829 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
29831 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29832 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
29834 uint8_t unused_0[3];
29836 * This field is used in Output records to indicate that the output
29837 * is completely written to RAM. This field should be read as '1'
29838 * to indicate that the output has been completely written.
29839 * When writing a command completion or response to an internal processor,
29840 * the order of writes has to be such that this field is written last.
29843 } __attribute__((packed));
29845 /*************************
29846 * hwrm_cfa_ctx_mem_rgtr *
29847 *************************/
29850 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
29851 struct hwrm_cfa_ctx_mem_rgtr_input {
29852 /* The HWRM command request type. */
29855 * The completion ring to send the completion event on. This should
29856 * be the NQ ID returned from the `nq_alloc` HWRM command.
29858 uint16_t cmpl_ring;
29860 * The sequence ID is used by the driver for tracking multiple
29861 * commands. This ID is treated as opaque data by the firmware and
29862 * the value is returned in the `hwrm_resp_hdr` upon completion.
29866 * The target ID of the command:
29867 * * 0x0-0xFFF8 - The function ID
29868 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29869 * * 0xFFFD - Reserved for user-space HWRM interface
29872 uint16_t target_id;
29874 * A physical address pointer pointing to a host buffer that the
29875 * command's response data will be written. This can be either a host
29876 * physical address (HPA) or a guest physical address (GPA) and must
29877 * point to a physically contiguous block of memory.
29879 uint64_t resp_addr;
29881 /* Counter PBL indirect levels. */
29882 uint8_t page_level;
29883 /* PBL pointer is physical start address. */
29884 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29885 /* PBL pointer points to PTE table. */
29886 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29887 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29888 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29889 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
29890 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
29893 /* 4KB page size. */
29894 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
29895 /* 8KB page size. */
29896 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
29897 /* 64KB page size. */
29898 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
29899 /* 256KB page size. */
29900 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
29901 /* 1MB page size. */
29902 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29903 /* 2MB page size. */
29904 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29905 /* 4MB page size. */
29906 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29907 /* 1GB page size. */
29908 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29909 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
29910 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
29912 /* Pointer to the PBL, or PDL depending on number of levels */
29914 } __attribute__((packed));
29916 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
29917 struct hwrm_cfa_ctx_mem_rgtr_output {
29918 /* The specific error status for the command. */
29919 uint16_t error_code;
29920 /* The HWRM command request type. */
29922 /* The sequence ID from the original command. */
29924 /* The length of the response data in number of bytes. */
29927 * Id/Handle to the recently register context memory. This handle is passed
29928 * to the CFA feature.
29931 uint8_t unused_0[5];
29933 * This field is used in Output records to indicate that the output
29934 * is completely written to RAM. This field should be read as '1'
29935 * to indicate that the output has been completely written.
29936 * When writing a command completion or response to an internal processor,
29937 * the order of writes has to be such that this field is written last.
29940 } __attribute__((packed));
29942 /***************************
29943 * hwrm_cfa_ctx_mem_unrgtr *
29944 ***************************/
29947 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
29948 struct hwrm_cfa_ctx_mem_unrgtr_input {
29949 /* The HWRM command request type. */
29952 * The completion ring to send the completion event on. This should
29953 * be the NQ ID returned from the `nq_alloc` HWRM command.
29955 uint16_t cmpl_ring;
29957 * The sequence ID is used by the driver for tracking multiple
29958 * commands. This ID is treated as opaque data by the firmware and
29959 * the value is returned in the `hwrm_resp_hdr` upon completion.
29963 * The target ID of the command:
29964 * * 0x0-0xFFF8 - The function ID
29965 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29966 * * 0xFFFD - Reserved for user-space HWRM interface
29969 uint16_t target_id;
29971 * A physical address pointer pointing to a host buffer that the
29972 * command's response data will be written. This can be either a host
29973 * physical address (HPA) or a guest physical address (GPA) and must
29974 * point to a physically contiguous block of memory.
29976 uint64_t resp_addr;
29978 * Id/Handle to the recently register context memory. This handle is passed
29979 * to the CFA feature.
29982 uint8_t unused_0[6];
29983 } __attribute__((packed));
29985 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
29986 struct hwrm_cfa_ctx_mem_unrgtr_output {
29987 /* The specific error status for the command. */
29988 uint16_t error_code;
29989 /* The HWRM command request type. */
29991 /* The sequence ID from the original command. */
29993 /* The length of the response data in number of bytes. */
29995 uint8_t unused_0[7];
29997 * This field is used in Output records to indicate that the output
29998 * is completely written to RAM. This field should be read as '1'
29999 * to indicate that the output has been completely written.
30000 * When writing a command completion or response to an internal processor,
30001 * the order of writes has to be such that this field is written last.
30004 } __attribute__((packed));
30006 /*************************
30007 * hwrm_cfa_ctx_mem_qctx *
30008 *************************/
30011 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
30012 struct hwrm_cfa_ctx_mem_qctx_input {
30013 /* The HWRM command request type. */
30016 * The completion ring to send the completion event on. This should
30017 * be the NQ ID returned from the `nq_alloc` HWRM command.
30019 uint16_t cmpl_ring;
30021 * The sequence ID is used by the driver for tracking multiple
30022 * commands. This ID is treated as opaque data by the firmware and
30023 * the value is returned in the `hwrm_resp_hdr` upon completion.
30027 * The target ID of the command:
30028 * * 0x0-0xFFF8 - The function ID
30029 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30030 * * 0xFFFD - Reserved for user-space HWRM interface
30033 uint16_t target_id;
30035 * A physical address pointer pointing to a host buffer that the
30036 * command's response data will be written. This can be either a host
30037 * physical address (HPA) or a guest physical address (GPA) and must
30038 * point to a physically contiguous block of memory.
30040 uint64_t resp_addr;
30042 * Id/Handle to the recently register context memory. This handle is passed
30043 * to the CFA feature.
30046 uint8_t unused_0[6];
30047 } __attribute__((packed));
30049 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
30050 struct hwrm_cfa_ctx_mem_qctx_output {
30051 /* The specific error status for the command. */
30052 uint16_t error_code;
30053 /* The HWRM command request type. */
30055 /* The sequence ID from the original command. */
30057 /* The length of the response data in number of bytes. */
30060 /* Counter PBL indirect levels. */
30061 uint8_t page_level;
30062 /* PBL pointer is physical start address. */
30063 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
30064 /* PBL pointer points to PTE table. */
30065 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
30066 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
30067 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
30068 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
30069 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
30072 /* 4KB page size. */
30073 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
30074 /* 8KB page size. */
30075 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
30076 /* 64KB page size. */
30077 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
30078 /* 256KB page size. */
30079 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
30080 /* 1MB page size. */
30081 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
30082 /* 2MB page size. */
30083 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
30084 /* 4MB page size. */
30085 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
30086 /* 1GB page size. */
30087 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
30088 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
30089 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
30090 uint8_t unused_0[4];
30091 /* Pointer to the PBL, or PDL depending on number of levels */
30093 uint8_t unused_1[7];
30095 * This field is used in Output records to indicate that the output
30096 * is completely written to RAM. This field should be read as '1'
30097 * to indicate that the output has been completely written.
30098 * When writing a command completion or response to an internal processor,
30099 * the order of writes has to be such that this field is written last.
30102 } __attribute__((packed));
30104 /**************************
30105 * hwrm_cfa_ctx_mem_qcaps *
30106 **************************/
30109 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
30110 struct hwrm_cfa_ctx_mem_qcaps_input {
30111 /* The HWRM command request type. */
30114 * The completion ring to send the completion event on. This should
30115 * be the NQ ID returned from the `nq_alloc` HWRM command.
30117 uint16_t cmpl_ring;
30119 * The sequence ID is used by the driver for tracking multiple
30120 * commands. This ID is treated as opaque data by the firmware and
30121 * the value is returned in the `hwrm_resp_hdr` upon completion.
30125 * The target ID of the command:
30126 * * 0x0-0xFFF8 - The function ID
30127 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30128 * * 0xFFFD - Reserved for user-space HWRM interface
30131 uint16_t target_id;
30133 * A physical address pointer pointing to a host buffer that the
30134 * command's response data will be written. This can be either a host
30135 * physical address (HPA) or a guest physical address (GPA) and must
30136 * point to a physically contiguous block of memory.
30138 uint64_t resp_addr;
30139 } __attribute__((packed));
30141 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
30142 struct hwrm_cfa_ctx_mem_qcaps_output {
30143 /* The specific error status for the command. */
30144 uint16_t error_code;
30145 /* The HWRM command request type. */
30147 /* The sequence ID from the original command. */
30149 /* The length of the response data in number of bytes. */
30151 /* Indicates the maximum number of context memory which can be registered. */
30152 uint16_t max_entries;
30153 uint8_t unused_0[5];
30155 * This field is used in Output records to indicate that the output
30156 * is completely written to RAM. This field should be read as '1'
30157 * to indicate that the output has been completely written.
30158 * When writing a command completion or response to an internal processor,
30159 * the order of writes has to be such that this field is written last.
30162 } __attribute__((packed));
30164 /**********************
30165 * hwrm_cfa_eem_qcaps *
30166 **********************/
30169 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
30170 struct hwrm_cfa_eem_qcaps_input {
30171 /* The HWRM command request type. */
30174 * The completion ring to send the completion event on. This should
30175 * be the NQ ID returned from the `nq_alloc` HWRM command.
30177 uint16_t cmpl_ring;
30179 * The sequence ID is used by the driver for tracking multiple
30180 * commands. This ID is treated as opaque data by the firmware and
30181 * the value is returned in the `hwrm_resp_hdr` upon completion.
30185 * The target ID of the command:
30186 * * 0x0-0xFFF8 - The function ID
30187 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30188 * * 0xFFFD - Reserved for user-space HWRM interface
30191 uint16_t target_id;
30193 * A physical address pointer pointing to a host buffer that the
30194 * command's response data will be written. This can be either a host
30195 * physical address (HPA) or a guest physical address (GPA) and must
30196 * point to a physically contiguous block of memory.
30198 uint64_t resp_addr;
30201 * When set to 1, indicates the configuration will apply to TX flows
30202 * which are to be offloaded.
30203 * Note if this bit is set then the path_rx bit can't be set.
30205 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
30208 * When set to 1, indicates the configuration will apply to RX flows
30209 * which are to be offloaded.
30210 * Note if this bit is set then the path_tx bit can't be set.
30212 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
30214 /* When set to 1, all offloaded flows will be sent to EEM. */
30215 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
30218 } __attribute__((packed));
30220 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
30221 struct hwrm_cfa_eem_qcaps_output {
30222 /* The specific error status for the command. */
30223 uint16_t error_code;
30224 /* The HWRM command request type. */
30226 /* The sequence ID from the original command. */
30228 /* The length of the response data in number of bytes. */
30232 * When set to 1, indicates the configuration will apply to TX flows
30233 * which are to be offloaded.
30234 * Note if this bit is set then the path_rx bit can't be set.
30236 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
30239 * When set to 1, indicates the configuration will apply to RX flows
30240 * which are to be offloaded.
30241 * Note if this bit is set then the path_tx bit can't be set.
30243 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
30246 * When set to 1, indicates the the FW supports the Centralized
30247 * Memory Model. The concept designates one entity for the
30248 * memory allocation while all others ‘subscribe’ to it.
30250 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
30253 * When set to 1, indicates the the FW supports the Detached
30254 * Centralized Memory Model. The memory is allocated and managed
30255 * as a separate entity. All PFs and VFs will be granted direct
30256 * or semi-direct access to the allocated memory while none of
30257 * which can interfere with the management of the memory.
30259 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
30262 uint32_t supported;
30264 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
30265 * If set to 0, EEM KEY0 table is not supported.
30267 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
30270 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
30271 * If set to 0, EEM KEY1 table is not supported.
30273 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
30276 * If set to 1, then EEM External Record table is supported.
30277 * If set to 0, EEM External Record table is not supported.
30278 * (This table includes action record, EFC pointers, encap pointers)
30280 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
30283 * If set to 1, then EEM External Flow Counters table is supported.
30284 * If set to 0, EEM External Flow Counters table is not supported.
30286 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
30289 * If set to 1, then FID table used for implicit flow flush is supported.
30290 * If set to 0, then FID table used for implicit flow flush is not supported.
30292 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
30295 * The maximum number of entries supported by EEM. When configuring the host memory
30296 * the number of numbers of entries that can supported are -
30297 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
30298 * Any value that are not these values, the FW will round down to the closest support
30299 * number of entries.
30301 uint32_t max_entries_supported;
30302 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
30303 uint16_t key_entry_size;
30304 /* The entry size in bytes of each entry in the EEM RECORD tables. */
30305 uint16_t record_entry_size;
30306 /* The entry size in bytes of each entry in the EEM EFC tables. */
30307 uint16_t efc_entry_size;
30308 /* The FID size in bytes of each entry in the EEM FID tables. */
30309 uint16_t fid_entry_size;
30310 uint8_t unused_1[7];
30312 * This field is used in Output records to indicate that the output
30313 * is completely written to RAM. This field should be read as '1'
30314 * to indicate that the output has been completely written.
30315 * When writing a command completion or response to an internal processor,
30316 * the order of writes has to be such that this field is written last.
30319 } __attribute__((packed));
30321 /********************
30322 * hwrm_cfa_eem_cfg *
30323 ********************/
30326 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
30327 struct hwrm_cfa_eem_cfg_input {
30328 /* The HWRM command request type. */
30331 * The completion ring to send the completion event on. This should
30332 * be the NQ ID returned from the `nq_alloc` HWRM command.
30334 uint16_t cmpl_ring;
30336 * The sequence ID is used by the driver for tracking multiple
30337 * commands. This ID is treated as opaque data by the firmware and
30338 * the value is returned in the `hwrm_resp_hdr` upon completion.
30342 * The target ID of the command:
30343 * * 0x0-0xFFF8 - The function ID
30344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30345 * * 0xFFFD - Reserved for user-space HWRM interface
30348 uint16_t target_id;
30350 * A physical address pointer pointing to a host buffer that the
30351 * command's response data will be written. This can be either a host
30352 * physical address (HPA) or a guest physical address (GPA) and must
30353 * point to a physically contiguous block of memory.
30355 uint64_t resp_addr;
30358 * When set to 1, indicates the configuration will apply to TX flows
30359 * which are to be offloaded.
30360 * Note if this bit is set then the path_rx bit can't be set.
30362 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
30365 * When set to 1, indicates the configuration will apply to RX flows
30366 * which are to be offloaded.
30367 * Note if this bit is set then the path_tx bit can't be set.
30369 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
30371 /* When set to 1, all offloaded flows will be sent to EEM. */
30372 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
30374 /* When set to 1, secondary, 0 means primary. */
30375 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
30378 * Group_id which used by Firmware to identify memory pools belonging
30379 * to certain group.
30384 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
30385 * RECORD, EFC all have the same number of entries and all tables will be configured
30386 * using this value. Current minimum value is 32k. Current maximum value is 128M.
30388 uint32_t num_entries;
30390 /* Configured EEM with the given context if for KEY0 table. */
30391 uint16_t key0_ctx_id;
30392 /* Configured EEM with the given context if for KEY1 table. */
30393 uint16_t key1_ctx_id;
30394 /* Configured EEM with the given context if for RECORD table. */
30395 uint16_t record_ctx_id;
30396 /* Configured EEM with the given context if for EFC table. */
30397 uint16_t efc_ctx_id;
30398 /* Configured EEM with the given context if for EFC table. */
30399 uint16_t fid_ctx_id;
30402 } __attribute__((packed));
30404 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
30405 struct hwrm_cfa_eem_cfg_output {
30406 /* The specific error status for the command. */
30407 uint16_t error_code;
30408 /* The HWRM command request type. */
30410 /* The sequence ID from the original command. */
30412 /* The length of the response data in number of bytes. */
30414 uint8_t unused_0[7];
30416 * This field is used in Output records to indicate that the output
30417 * is completely written to RAM. This field should be read as '1'
30418 * to indicate that the output has been completely written.
30419 * When writing a command completion or response to an internal processor,
30420 * the order of writes has to be such that this field is written last.
30423 } __attribute__((packed));
30425 /*********************
30426 * hwrm_cfa_eem_qcfg *
30427 *********************/
30430 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
30431 struct hwrm_cfa_eem_qcfg_input {
30432 /* The HWRM command request type. */
30435 * The completion ring to send the completion event on. This should
30436 * be the NQ ID returned from the `nq_alloc` HWRM command.
30438 uint16_t cmpl_ring;
30440 * The sequence ID is used by the driver for tracking multiple
30441 * commands. This ID is treated as opaque data by the firmware and
30442 * the value is returned in the `hwrm_resp_hdr` upon completion.
30446 * The target ID of the command:
30447 * * 0x0-0xFFF8 - The function ID
30448 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30449 * * 0xFFFD - Reserved for user-space HWRM interface
30452 uint16_t target_id;
30454 * A physical address pointer pointing to a host buffer that the
30455 * command's response data will be written. This can be either a host
30456 * physical address (HPA) or a guest physical address (GPA) and must
30457 * point to a physically contiguous block of memory.
30459 uint64_t resp_addr;
30461 /* When set to 1, indicates the configuration is the TX flow. */
30462 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
30463 /* When set to 1, indicates the configuration is the RX flow. */
30464 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
30466 } __attribute__((packed));
30468 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
30469 struct hwrm_cfa_eem_qcfg_output {
30470 /* The specific error status for the command. */
30471 uint16_t error_code;
30472 /* The HWRM command request type. */
30474 /* The sequence ID from the original command. */
30476 /* The length of the response data in number of bytes. */
30479 /* When set to 1, indicates the configuration is the TX flow. */
30480 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
30482 /* When set to 1, indicates the configuration is the RX flow. */
30483 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
30485 /* When set to 1, all offloaded flows will be sent to EEM. */
30486 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
30488 /* The number of entries the FW has configured for EEM. */
30489 uint32_t num_entries;
30490 /* Configured EEM with the given context if for KEY0 table. */
30491 uint16_t key0_ctx_id;
30492 /* Configured EEM with the given context if for KEY1 table. */
30493 uint16_t key1_ctx_id;
30494 /* Configured EEM with the given context if for RECORD table. */
30495 uint16_t record_ctx_id;
30496 /* Configured EEM with the given context if for EFC table. */
30497 uint16_t efc_ctx_id;
30498 /* Configured EEM with the given context if for EFC table. */
30499 uint16_t fid_ctx_id;
30500 uint8_t unused_2[5];
30502 * This field is used in Output records to indicate that the output
30503 * is completely written to RAM. This field should be read as '1'
30504 * to indicate that the output has been completely written.
30505 * When writing a command completion or response to an internal processor,
30506 * the order of writes has to be such that this field is written last.
30509 } __attribute__((packed));
30511 /*******************
30512 * hwrm_cfa_eem_op *
30513 *******************/
30516 /* hwrm_cfa_eem_op_input (size:192b/24B) */
30517 struct hwrm_cfa_eem_op_input {
30518 /* The HWRM command request type. */
30521 * The completion ring to send the completion event on. This should
30522 * be the NQ ID returned from the `nq_alloc` HWRM command.
30524 uint16_t cmpl_ring;
30526 * The sequence ID is used by the driver for tracking multiple
30527 * commands. This ID is treated as opaque data by the firmware and
30528 * the value is returned in the `hwrm_resp_hdr` upon completion.
30532 * The target ID of the command:
30533 * * 0x0-0xFFF8 - The function ID
30534 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30535 * * 0xFFFD - Reserved for user-space HWRM interface
30538 uint16_t target_id;
30540 * A physical address pointer pointing to a host buffer that the
30541 * command's response data will be written. This can be either a host
30542 * physical address (HPA) or a guest physical address (GPA) and must
30543 * point to a physically contiguous block of memory.
30545 uint64_t resp_addr;
30548 * When set to 1, indicates the host memory which is passed will be
30549 * used for the TX flow offload function specified in fid.
30550 * Note if this bit is set then the path_rx bit can't be set.
30552 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
30554 * When set to 1, indicates the host memory which is passed will be
30555 * used for the RX flow offload function specified in fid.
30556 * Note if this bit is set then the path_tx bit can't be set.
30558 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
30560 /* The number of EEM key table entries to be configured. */
30562 /* This value is reserved and should not be used. */
30563 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
30565 * To properly stop EEM and ensure there are no DMA's, the caller
30566 * must disable EEM for the given PF, using this call. This will
30567 * safely disable EEM and ensure that all DMA'ed to the
30568 * keys/records/efc have been completed.
30570 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
30572 * Once the EEM host memory has been configured, EEM options have
30573 * been configured. Then the caller should enable EEM for the given
30574 * PF. Note once this call has been made, then the EEM mechanism
30575 * will be active and DMA's will occur as packets are processed.
30577 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
30579 * Clear EEM settings for the given PF so that the register values
30580 * are reset back to there initial state.
30582 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
30583 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
30584 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
30585 } __attribute__((packed));
30587 /* hwrm_cfa_eem_op_output (size:128b/16B) */
30588 struct hwrm_cfa_eem_op_output {
30589 /* The specific error status for the command. */
30590 uint16_t error_code;
30591 /* The HWRM command request type. */
30593 /* The sequence ID from the original command. */
30595 /* The length of the response data in number of bytes. */
30597 uint8_t unused_0[7];
30599 * This field is used in Output records to indicate that the output
30600 * is completely written to RAM. This field should be read as '1'
30601 * to indicate that the output has been completely written.
30602 * When writing a command completion or response to an internal processor,
30603 * the order of writes has to be such that this field is written last.
30606 } __attribute__((packed));
30608 /********************************
30609 * hwrm_cfa_adv_flow_mgnt_qcaps *
30610 ********************************/
30613 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
30614 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
30615 /* The HWRM command request type. */
30618 * The completion ring to send the completion event on. This should
30619 * be the NQ ID returned from the `nq_alloc` HWRM command.
30621 uint16_t cmpl_ring;
30623 * The sequence ID is used by the driver for tracking multiple
30624 * commands. This ID is treated as opaque data by the firmware and
30625 * the value is returned in the `hwrm_resp_hdr` upon completion.
30629 * The target ID of the command:
30630 * * 0x0-0xFFF8 - The function ID
30631 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30632 * * 0xFFFD - Reserved for user-space HWRM interface
30635 uint16_t target_id;
30637 * A physical address pointer pointing to a host buffer that the
30638 * command's response data will be written. This can be either a host
30639 * physical address (HPA) or a guest physical address (GPA) and must
30640 * point to a physically contiguous block of memory.
30642 uint64_t resp_addr;
30643 uint32_t unused_0[4];
30644 } __attribute__((packed));
30646 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
30647 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
30648 /* The specific error status for the command. */
30649 uint16_t error_code;
30650 /* The HWRM command request type. */
30652 /* The sequence ID from the original command. */
30654 /* The length of the response data in number of bytes. */
30658 * Value of 1 to indicate firmware support 16-bit flow handle.
30659 * Value of 0 to indicate firmware not support 16-bit flow handle.
30661 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
30664 * Value of 1 to indicate firmware support 64-bit flow handle.
30665 * Value of 0 to indicate firmware not support 64-bit flow handle.
30667 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
30670 * Value of 1 to indicate firmware support flow batch delete operation through
30671 * HWRM_CFA_FLOW_FLUSH command.
30672 * Value of 0 to indicate that the firmware does not support flow batch delete
30675 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
30678 * Value of 1 to indicate that the firmware support flow reset all operation through
30679 * HWRM_CFA_FLOW_FLUSH command.
30680 * Value of 0 indicates firmware does not support flow reset all operation.
30682 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
30685 * Value of 1 to indicate that firmware supports use of FID as dest_id in
30686 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
30687 * Value of 0 indicates firmware does not support use of FID as dest_id.
30689 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
30692 * Value of 1 to indicate that firmware supports TX EEM flows.
30693 * Value of 0 indicates firmware does not support TX EEM flows.
30695 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
30698 * Value of 1 to indicate that firmware supports RX EEM flows.
30699 * Value of 0 indicates firmware does not support RX EEM flows.
30701 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
30704 * Value of 1 to indicate that firmware supports the dynamic allocation of an
30705 * on-chip flow counter which can be used for EEM flows.
30706 * Value of 0 indicates firmware does not support the dynamic allocation of an
30707 * on-chip flow counter.
30709 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
30712 * Value of 1 to indicate that firmware supports setting of
30713 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
30714 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
30716 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
30719 * Value of 1 to indicate that firmware supports untagged matching
30720 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
30721 * indicates firmware does not support untagged matching.
30723 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
30726 * Value of 1 to indicate that firmware supports XDP filter. Value
30727 * of 0 indicates firmware does not support XDP filter.
30729 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
30732 * Value of 1 to indicate that the firmware support L2 header source
30733 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
30734 * Value of 0 indicates firmware does not support L2 header source
30737 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
30739 uint8_t unused_0[3];
30741 * This field is used in Output records to indicate that the output
30742 * is completely written to RAM. This field should be read as '1'
30743 * to indicate that the output has been completely written.
30744 * When writing a command completion or response to an internal processor,
30745 * the order of writes has to be such that this field is written last.
30748 } __attribute__((packed));
30750 /******************
30752 ******************/
30755 /* hwrm_cfa_tflib_input (size:1024b/128B) */
30756 struct hwrm_cfa_tflib_input {
30757 /* The HWRM command request type. */
30760 * The completion ring to send the completion event on. This should
30761 * be the NQ ID returned from the `nq_alloc` HWRM command.
30763 uint16_t cmpl_ring;
30765 * The sequence ID is used by the driver for tracking multiple
30766 * commands. This ID is treated as opaque data by the firmware and
30767 * the value is returned in the `hwrm_resp_hdr` upon completion.
30771 * The target ID of the command:
30772 * * 0x0-0xFFF8 - The function ID
30773 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30774 * * 0xFFFD - Reserved for user-space HWRM interface
30777 uint16_t target_id;
30779 * A physical address pointer pointing to a host buffer that the
30780 * command's response data will be written. This can be either a host
30781 * physical address (HPA) or a guest physical address (GPA) and must
30782 * point to a physically contiguous block of memory.
30784 uint64_t resp_addr;
30785 /* TFLIB message type. */
30787 /* TFLIB message subtype. */
30788 uint16_t tf_subtype;
30790 uint8_t unused0[4];
30791 /* TFLIB request data. */
30792 uint32_t tf_req[26];
30793 } __attribute__((packed));
30795 /* hwrm_cfa_tflib_output (size:5632b/704B) */
30796 struct hwrm_cfa_tflib_output {
30797 /* The specific error status for the command. */
30798 uint16_t error_code;
30799 /* The HWRM command request type. */
30801 /* The sequence ID from the original command. */
30803 /* The length of the response data in number of bytes. */
30805 /* TFLIB message type. */
30807 /* TFLIB message subtype. */
30808 uint16_t tf_subtype;
30809 /* TFLIB response code */
30810 uint32_t tf_resp_code;
30811 /* TFLIB response data. */
30812 uint32_t tf_resp[170];
30814 uint8_t unused1[7];
30816 * This field is used in Output records to indicate that the output
30817 * is completely written to RAM. This field should be read as '1'
30818 * to indicate that the output has been completely written.
30819 * When writing a command completion or response to an internal processor,
30820 * the order of writes has to be such that this field is written last.
30823 } __attribute__((packed));
30825 /******************************
30826 * hwrm_tunnel_dst_port_query *
30827 ******************************/
30830 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
30831 struct hwrm_tunnel_dst_port_query_input {
30832 /* The HWRM command request type. */
30835 * The completion ring to send the completion event on. This should
30836 * be the NQ ID returned from the `nq_alloc` HWRM command.
30838 uint16_t cmpl_ring;
30840 * The sequence ID is used by the driver for tracking multiple
30841 * commands. This ID is treated as opaque data by the firmware and
30842 * the value is returned in the `hwrm_resp_hdr` upon completion.
30846 * The target ID of the command:
30847 * * 0x0-0xFFF8 - The function ID
30848 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30849 * * 0xFFFD - Reserved for user-space HWRM interface
30852 uint16_t target_id;
30854 * A physical address pointer pointing to a host buffer that the
30855 * command's response data will be written. This can be either a host
30856 * physical address (HPA) or a guest physical address (GPA) and must
30857 * point to a physically contiguous block of memory.
30859 uint64_t resp_addr;
30861 uint8_t tunnel_type;
30862 /* Virtual eXtensible Local Area Network (VXLAN) */
30863 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
30865 /* Generic Network Virtualization Encapsulation (Geneve) */
30866 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
30868 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30869 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30871 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30872 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30874 /* Use fixed layer 2 ether type of 0xFFFF */
30875 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
30877 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30878 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30880 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
30881 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30882 uint8_t unused_0[7];
30883 } __attribute__((packed));
30885 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
30886 struct hwrm_tunnel_dst_port_query_output {
30887 /* The specific error status for the command. */
30888 uint16_t error_code;
30889 /* The HWRM command request type. */
30891 /* The sequence ID from the original command. */
30893 /* The length of the response data in number of bytes. */
30896 * This field represents the identifier of L4 destination port
30897 * used for the given tunnel type. This field is valid for
30898 * specific tunnel types that use layer 4 (e.g. UDP)
30899 * transports for tunneling.
30901 uint16_t tunnel_dst_port_id;
30903 * This field represents the value of L4 destination port
30904 * identified by tunnel_dst_port_id. This field is valid for
30905 * specific tunnel types that use layer 4 (e.g. UDP)
30906 * transports for tunneling.
30907 * This field is in network byte order.
30909 * A value of 0 means that the destination port is not
30912 uint16_t tunnel_dst_port_val;
30913 uint8_t unused_0[3];
30915 * This field is used in Output records to indicate that the output
30916 * is completely written to RAM. This field should be read as '1'
30917 * to indicate that the output has been completely written.
30918 * When writing a command completion or response to an internal processor,
30919 * the order of writes has to be such that this field is written last.
30922 } __attribute__((packed));
30924 /******************************
30925 * hwrm_tunnel_dst_port_alloc *
30926 ******************************/
30929 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
30930 struct hwrm_tunnel_dst_port_alloc_input {
30931 /* The HWRM command request type. */
30934 * The completion ring to send the completion event on. This should
30935 * be the NQ ID returned from the `nq_alloc` HWRM command.
30937 uint16_t cmpl_ring;
30939 * The sequence ID is used by the driver for tracking multiple
30940 * commands. This ID is treated as opaque data by the firmware and
30941 * the value is returned in the `hwrm_resp_hdr` upon completion.
30945 * The target ID of the command:
30946 * * 0x0-0xFFF8 - The function ID
30947 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30948 * * 0xFFFD - Reserved for user-space HWRM interface
30951 uint16_t target_id;
30953 * A physical address pointer pointing to a host buffer that the
30954 * command's response data will be written. This can be either a host
30955 * physical address (HPA) or a guest physical address (GPA) and must
30956 * point to a physically contiguous block of memory.
30958 uint64_t resp_addr;
30960 uint8_t tunnel_type;
30961 /* Virtual eXtensible Local Area Network (VXLAN) */
30962 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30964 /* Generic Network Virtualization Encapsulation (Geneve) */
30965 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30967 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30968 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30970 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30971 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30973 /* Use fixed layer 2 ether type of 0xFFFF */
30974 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30976 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30977 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30979 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30980 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30983 * This field represents the value of L4 destination port used
30984 * for the given tunnel type. This field is valid for
30985 * specific tunnel types that use layer 4 (e.g. UDP)
30986 * transports for tunneling.
30988 * This field is in network byte order.
30990 * A value of 0 shall fail the command.
30992 uint16_t tunnel_dst_port_val;
30993 uint8_t unused_1[4];
30994 } __attribute__((packed));
30996 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
30997 struct hwrm_tunnel_dst_port_alloc_output {
30998 /* The specific error status for the command. */
30999 uint16_t error_code;
31000 /* The HWRM command request type. */
31002 /* The sequence ID from the original command. */
31004 /* The length of the response data in number of bytes. */
31007 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
31008 * types that has l4 destination port parameters.
31010 uint16_t tunnel_dst_port_id;
31011 uint8_t unused_0[5];
31013 * This field is used in Output records to indicate that the output
31014 * is completely written to RAM. This field should be read as '1'
31015 * to indicate that the output has been completely written.
31016 * When writing a command completion or response to an internal processor,
31017 * the order of writes has to be such that this field is written last.
31020 } __attribute__((packed));
31022 /*****************************
31023 * hwrm_tunnel_dst_port_free *
31024 *****************************/
31027 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
31028 struct hwrm_tunnel_dst_port_free_input {
31029 /* The HWRM command request type. */
31032 * The completion ring to send the completion event on. This should
31033 * be the NQ ID returned from the `nq_alloc` HWRM command.
31035 uint16_t cmpl_ring;
31037 * The sequence ID is used by the driver for tracking multiple
31038 * commands. This ID is treated as opaque data by the firmware and
31039 * the value is returned in the `hwrm_resp_hdr` upon completion.
31043 * The target ID of the command:
31044 * * 0x0-0xFFF8 - The function ID
31045 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31046 * * 0xFFFD - Reserved for user-space HWRM interface
31049 uint16_t target_id;
31051 * A physical address pointer pointing to a host buffer that the
31052 * command's response data will be written. This can be either a host
31053 * physical address (HPA) or a guest physical address (GPA) and must
31054 * point to a physically contiguous block of memory.
31056 uint64_t resp_addr;
31058 uint8_t tunnel_type;
31059 /* Virtual eXtensible Local Area Network (VXLAN) */
31060 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
31062 /* Generic Network Virtualization Encapsulation (Geneve) */
31063 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
31065 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31066 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31068 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31069 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31071 /* Use fixed layer 2 ether type of 0xFFFF */
31072 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
31074 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31075 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31077 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
31078 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
31081 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
31082 * types that has l4 destination port parameters.
31084 uint16_t tunnel_dst_port_id;
31085 uint8_t unused_1[4];
31086 } __attribute__((packed));
31088 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
31089 struct hwrm_tunnel_dst_port_free_output {
31090 /* The specific error status for the command. */
31091 uint16_t error_code;
31092 /* The HWRM command request type. */
31094 /* The sequence ID from the original command. */
31096 /* The length of the response data in number of bytes. */
31098 uint8_t unused_1[7];
31100 * This field is used in Output records to indicate that the output
31101 * is completely written to RAM. This field should be read as '1'
31102 * to indicate that the output has been completely written.
31103 * When writing a command completion or response to an internal processor,
31104 * the order of writes has to be such that this field is written last.
31107 } __attribute__((packed));
31109 /* Periodic statistics context DMA to host. */
31110 /* ctx_hw_stats (size:1280b/160B) */
31111 struct ctx_hw_stats {
31112 /* Number of received unicast packets */
31113 uint64_t rx_ucast_pkts;
31114 /* Number of received multicast packets */
31115 uint64_t rx_mcast_pkts;
31116 /* Number of received broadcast packets */
31117 uint64_t rx_bcast_pkts;
31118 /* Number of discarded packets on received path */
31119 uint64_t rx_discard_pkts;
31120 /* Number of dropped packets on received path */
31121 uint64_t rx_drop_pkts;
31122 /* Number of received bytes for unicast traffic */
31123 uint64_t rx_ucast_bytes;
31124 /* Number of received bytes for multicast traffic */
31125 uint64_t rx_mcast_bytes;
31126 /* Number of received bytes for broadcast traffic */
31127 uint64_t rx_bcast_bytes;
31128 /* Number of transmitted unicast packets */
31129 uint64_t tx_ucast_pkts;
31130 /* Number of transmitted multicast packets */
31131 uint64_t tx_mcast_pkts;
31132 /* Number of transmitted broadcast packets */
31133 uint64_t tx_bcast_pkts;
31134 /* Number of discarded packets on transmit path */
31135 uint64_t tx_discard_pkts;
31136 /* Number of dropped packets on transmit path */
31137 uint64_t tx_drop_pkts;
31138 /* Number of transmitted bytes for unicast traffic */
31139 uint64_t tx_ucast_bytes;
31140 /* Number of transmitted bytes for multicast traffic */
31141 uint64_t tx_mcast_bytes;
31142 /* Number of transmitted bytes for broadcast traffic */
31143 uint64_t tx_bcast_bytes;
31144 /* Number of TPA packets */
31146 /* Number of TPA bytes */
31147 uint64_t tpa_bytes;
31148 /* Number of TPA events */
31149 uint64_t tpa_events;
31150 /* Number of TPA aborts */
31151 uint64_t tpa_aborts;
31152 } __attribute__((packed));
31154 /* Periodic statistics context DMA to host. */
31155 /* ctx_hw_stats_ext (size:1344b/168B) */
31156 struct ctx_hw_stats_ext {
31157 /* Number of received unicast packets */
31158 uint64_t rx_ucast_pkts;
31159 /* Number of received multicast packets */
31160 uint64_t rx_mcast_pkts;
31161 /* Number of received broadcast packets */
31162 uint64_t rx_bcast_pkts;
31163 /* Number of discarded packets on received path */
31164 uint64_t rx_discard_pkts;
31165 /* Number of dropped packets on received path */
31166 uint64_t rx_drop_pkts;
31167 /* Number of received bytes for unicast traffic */
31168 uint64_t rx_ucast_bytes;
31169 /* Number of received bytes for multicast traffic */
31170 uint64_t rx_mcast_bytes;
31171 /* Number of received bytes for broadcast traffic */
31172 uint64_t rx_bcast_bytes;
31173 /* Number of transmitted unicast packets */
31174 uint64_t tx_ucast_pkts;
31175 /* Number of transmitted multicast packets */
31176 uint64_t tx_mcast_pkts;
31177 /* Number of transmitted broadcast packets */
31178 uint64_t tx_bcast_pkts;
31179 /* Number of discarded packets on transmit path */
31180 uint64_t tx_discard_pkts;
31181 /* Number of dropped packets on transmit path */
31182 uint64_t tx_drop_pkts;
31183 /* Number of transmitted bytes for unicast traffic */
31184 uint64_t tx_ucast_bytes;
31185 /* Number of transmitted bytes for multicast traffic */
31186 uint64_t tx_mcast_bytes;
31187 /* Number of transmitted bytes for broadcast traffic */
31188 uint64_t tx_bcast_bytes;
31189 /* Number of TPA eligible packets */
31190 uint64_t rx_tpa_eligible_pkt;
31191 /* Number of TPA eligible bytes */
31192 uint64_t rx_tpa_eligible_bytes;
31193 /* Number of TPA packets */
31194 uint64_t rx_tpa_pkt;
31195 /* Number of TPA bytes */
31196 uint64_t rx_tpa_bytes;
31197 /* Number of TPA errors */
31198 uint64_t rx_tpa_errors;
31199 } __attribute__((packed));
31201 /* Periodic Engine statistics context DMA to host. */
31202 /* ctx_eng_stats (size:512b/64B) */
31203 struct ctx_eng_stats {
31205 * Count of data bytes into the Engine.
31206 * This includes any user supplied prefix,
31207 * but does not include any predefined
31210 uint64_t eng_bytes_in;
31211 /* Count of data bytes out of the Engine. */
31212 uint64_t eng_bytes_out;
31214 * Count, in 4-byte (dword) units, of bytes
31215 * that are input as auxiliary data.
31216 * This includes the aux_cmd data.
31218 uint64_t aux_bytes_in;
31220 * Count, in 4-byte (dword) units, of bytes
31221 * that are output as auxiliary data.
31222 * This count is the buffer space for aux_data
31223 * output provided in the RQE, not the actual
31226 uint64_t aux_bytes_out;
31227 /* Count of number of commands executed. */
31230 * Count of number of error commands.
31231 * These are the commands with a
31232 * non-zero status value.
31234 uint64_t error_commands;
31236 * Compression/Encryption Engine usage,
31237 * the unit is count of clock cycles
31239 uint64_t cce_engine_usage;
31241 * De-Compression/De-cryption Engine usage,
31242 * the unit is count of clock cycles
31244 uint64_t cdd_engine_usage;
31245 } __attribute__((packed));
31247 /***********************
31248 * hwrm_stat_ctx_alloc *
31249 ***********************/
31252 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
31253 struct hwrm_stat_ctx_alloc_input {
31254 /* The HWRM command request type. */
31257 * The completion ring to send the completion event on. This should
31258 * be the NQ ID returned from the `nq_alloc` HWRM command.
31260 uint16_t cmpl_ring;
31262 * The sequence ID is used by the driver for tracking multiple
31263 * commands. This ID is treated as opaque data by the firmware and
31264 * the value is returned in the `hwrm_resp_hdr` upon completion.
31268 * The target ID of the command:
31269 * * 0x0-0xFFF8 - The function ID
31270 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31271 * * 0xFFFD - Reserved for user-space HWRM interface
31274 uint16_t target_id;
31276 * A physical address pointer pointing to a host buffer that the
31277 * command's response data will be written. This can be either a host
31278 * physical address (HPA) or a guest physical address (GPA) and must
31279 * point to a physically contiguous block of memory.
31281 uint64_t resp_addr;
31283 * This is the address for statistic block.
31284 * > For new versions of the chip, this address should be 128B
31287 uint64_t stats_dma_addr;
31289 * The statistic block update period in ms.
31290 * e.g. 250ms, 500ms, 750ms, 1000ms.
31291 * If update_period_ms is 0, then the stats update
31292 * shall be never done and the DMA address shall not be used.
31293 * In this case, the stat block can only be read by
31294 * hwrm_stat_ctx_query command.
31295 * On Ethernet/L2 based devices:
31296 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
31297 * ctx_hw_stats_ext is used for DMA,
31299 * ctx_hw_stats is used for DMA.
31301 uint32_t update_period_ms;
31303 * This field is used to specify statistics context specific
31304 * configuration flags.
31306 uint8_t stat_ctx_flags;
31308 * When this bit is set to '1', the statistics context shall be
31309 * allocated for RoCE traffic only. In this case, traffic other
31310 * than offloaded RoCE traffic shall not be included in this
31311 * statistic context.
31312 * When this bit is set to '0', the statistics context shall be
31313 * used for network traffic or engine traffic.
31315 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
31318 * This is the size of the structure (ctx_hw_stats or
31319 * ctx_hw_stats_ext) that the driver has allocated to be used
31320 * for the periodic DMA updates.
31322 uint16_t stats_dma_length;
31323 } __attribute__((packed));
31325 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
31326 struct hwrm_stat_ctx_alloc_output {
31327 /* The specific error status for the command. */
31328 uint16_t error_code;
31329 /* The HWRM command request type. */
31331 /* The sequence ID from the original command. */
31333 /* The length of the response data in number of bytes. */
31335 /* This is the statistics context ID value. */
31336 uint32_t stat_ctx_id;
31337 uint8_t unused_0[3];
31339 * This field is used in Output records to indicate that the output
31340 * is completely written to RAM. This field should be read as '1'
31341 * to indicate that the output has been completely written.
31342 * When writing a command completion or response to an internal processor,
31343 * the order of writes has to be such that this field is written last.
31346 } __attribute__((packed));
31348 /**********************
31349 * hwrm_stat_ctx_free *
31350 **********************/
31353 /* hwrm_stat_ctx_free_input (size:192b/24B) */
31354 struct hwrm_stat_ctx_free_input {
31355 /* The HWRM command request type. */
31358 * The completion ring to send the completion event on. This should
31359 * be the NQ ID returned from the `nq_alloc` HWRM command.
31361 uint16_t cmpl_ring;
31363 * The sequence ID is used by the driver for tracking multiple
31364 * commands. This ID is treated as opaque data by the firmware and
31365 * the value is returned in the `hwrm_resp_hdr` upon completion.
31369 * The target ID of the command:
31370 * * 0x0-0xFFF8 - The function ID
31371 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31372 * * 0xFFFD - Reserved for user-space HWRM interface
31375 uint16_t target_id;
31377 * A physical address pointer pointing to a host buffer that the
31378 * command's response data will be written. This can be either a host
31379 * physical address (HPA) or a guest physical address (GPA) and must
31380 * point to a physically contiguous block of memory.
31382 uint64_t resp_addr;
31383 /* ID of the statistics context that is being queried. */
31384 uint32_t stat_ctx_id;
31385 uint8_t unused_0[4];
31386 } __attribute__((packed));
31388 /* hwrm_stat_ctx_free_output (size:128b/16B) */
31389 struct hwrm_stat_ctx_free_output {
31390 /* The specific error status for the command. */
31391 uint16_t error_code;
31392 /* The HWRM command request type. */
31394 /* The sequence ID from the original command. */
31396 /* The length of the response data in number of bytes. */
31398 /* This is the statistics context ID value. */
31399 uint32_t stat_ctx_id;
31400 uint8_t unused_0[3];
31402 * This field is used in Output records to indicate that the output
31403 * is completely written to RAM. This field should be read as '1'
31404 * to indicate that the output has been completely written.
31405 * When writing a command completion or response to an internal processor,
31406 * the order of writes has to be such that this field is written last.
31409 } __attribute__((packed));
31411 /***********************
31412 * hwrm_stat_ctx_query *
31413 ***********************/
31416 /* hwrm_stat_ctx_query_input (size:192b/24B) */
31417 struct hwrm_stat_ctx_query_input {
31418 /* The HWRM command request type. */
31421 * The completion ring to send the completion event on. This should
31422 * be the NQ ID returned from the `nq_alloc` HWRM command.
31424 uint16_t cmpl_ring;
31426 * The sequence ID is used by the driver for tracking multiple
31427 * commands. This ID is treated as opaque data by the firmware and
31428 * the value is returned in the `hwrm_resp_hdr` upon completion.
31432 * The target ID of the command:
31433 * * 0x0-0xFFF8 - The function ID
31434 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31435 * * 0xFFFD - Reserved for user-space HWRM interface
31438 uint16_t target_id;
31440 * A physical address pointer pointing to a host buffer that the
31441 * command's response data will be written. This can be either a host
31442 * physical address (HPA) or a guest physical address (GPA) and must
31443 * point to a physically contiguous block of memory.
31445 uint64_t resp_addr;
31446 /* ID of the statistics context that is being queried. */
31447 uint32_t stat_ctx_id;
31448 uint8_t unused_0[4];
31449 } __attribute__((packed));
31451 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
31452 struct hwrm_stat_ctx_query_output {
31453 /* The specific error status for the command. */
31454 uint16_t error_code;
31455 /* The HWRM command request type. */
31457 /* The sequence ID from the original command. */
31459 /* The length of the response data in number of bytes. */
31461 /* Number of transmitted unicast packets */
31462 uint64_t tx_ucast_pkts;
31463 /* Number of transmitted multicast packets */
31464 uint64_t tx_mcast_pkts;
31465 /* Number of transmitted broadcast packets */
31466 uint64_t tx_bcast_pkts;
31467 /* Number of transmitted packets with error */
31468 uint64_t tx_err_pkts;
31469 /* Number of dropped packets on transmit path */
31470 uint64_t tx_drop_pkts;
31471 /* Number of transmitted bytes for unicast traffic */
31472 uint64_t tx_ucast_bytes;
31473 /* Number of transmitted bytes for multicast traffic */
31474 uint64_t tx_mcast_bytes;
31475 /* Number of transmitted bytes for broadcast traffic */
31476 uint64_t tx_bcast_bytes;
31477 /* Number of received unicast packets */
31478 uint64_t rx_ucast_pkts;
31479 /* Number of received multicast packets */
31480 uint64_t rx_mcast_pkts;
31481 /* Number of received broadcast packets */
31482 uint64_t rx_bcast_pkts;
31483 /* Number of received packets with error */
31484 uint64_t rx_err_pkts;
31485 /* Number of dropped packets on received path */
31486 uint64_t rx_drop_pkts;
31487 /* Number of received bytes for unicast traffic */
31488 uint64_t rx_ucast_bytes;
31489 /* Number of received bytes for multicast traffic */
31490 uint64_t rx_mcast_bytes;
31491 /* Number of received bytes for broadcast traffic */
31492 uint64_t rx_bcast_bytes;
31493 /* Number of aggregated unicast packets */
31494 uint64_t rx_agg_pkts;
31495 /* Number of aggregated unicast bytes */
31496 uint64_t rx_agg_bytes;
31497 /* Number of aggregation events */
31498 uint64_t rx_agg_events;
31499 /* Number of aborted aggregations */
31500 uint64_t rx_agg_aborts;
31501 uint8_t unused_0[7];
31503 * This field is used in Output records to indicate that the output
31504 * is completely written to RAM. This field should be read as '1'
31505 * to indicate that the output has been completely written.
31506 * When writing a command completion or response to an internal processor,
31507 * the order of writes has to be such that this field is written last.
31510 } __attribute__((packed));
31512 /***************************
31513 * hwrm_stat_ctx_eng_query *
31514 ***************************/
31517 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
31518 struct hwrm_stat_ctx_eng_query_input {
31519 /* The HWRM command request type. */
31522 * The completion ring to send the completion event on. This should
31523 * be the NQ ID returned from the `nq_alloc` HWRM command.
31525 uint16_t cmpl_ring;
31527 * The sequence ID is used by the driver for tracking multiple
31528 * commands. This ID is treated as opaque data by the firmware and
31529 * the value is returned in the `hwrm_resp_hdr` upon completion.
31533 * The target ID of the command:
31534 * * 0x0-0xFFF8 - The function ID
31535 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31536 * * 0xFFFD - Reserved for user-space HWRM interface
31539 uint16_t target_id;
31541 * A physical address pointer pointing to a host buffer that the
31542 * command's response data will be written. This can be either a host
31543 * physical address (HPA) or a guest physical address (GPA) and must
31544 * point to a physically contiguous block of memory.
31546 uint64_t resp_addr;
31547 /* ID of the statistics context that is being queried. */
31548 uint32_t stat_ctx_id;
31549 uint8_t unused_0[4];
31550 } __attribute__((packed));
31552 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
31553 struct hwrm_stat_ctx_eng_query_output {
31554 /* The specific error status for the command. */
31555 uint16_t error_code;
31556 /* The HWRM command request type. */
31558 /* The sequence ID from the original command. */
31560 /* The length of the response data in number of bytes. */
31563 * Count of data bytes into the Engine.
31564 * This includes any user supplied prefix,
31565 * but does not include any predefined
31568 uint64_t eng_bytes_in;
31569 /* Count of data bytes out of the Engine. */
31570 uint64_t eng_bytes_out;
31572 * Count, in 4-byte (dword) units, of bytes
31573 * that are input as auxiliary data.
31574 * This includes the aux_cmd data.
31576 uint64_t aux_bytes_in;
31578 * Count, in 4-byte (dword) units, of bytes
31579 * that are output as auxiliary data.
31580 * This count is the buffer space for aux_data
31581 * output provided in the RQE, not the actual
31584 uint64_t aux_bytes_out;
31585 /* Count of number of commands executed. */
31588 * Count of number of error commands.
31589 * These are the commands with a
31590 * non-zero status value.
31592 uint64_t error_commands;
31594 * Compression/Encryption Engine usage,
31595 * the unit is count of clock cycles
31597 uint64_t cce_engine_usage;
31599 * De-Compression/De-cryption Engine usage,
31600 * the unit is count of clock cycles
31602 uint64_t cdd_engine_usage;
31603 uint8_t unused_0[7];
31605 * This field is used in Output records to indicate that the output
31606 * is completely written to RAM. This field should be read as '1'
31607 * to indicate that the output has been completely written.
31608 * When writing a command completion or response to an internal processor,
31609 * the order of writes has to be such that this field is written last.
31612 } __attribute__((packed));
31614 /***************************
31615 * hwrm_stat_ctx_clr_stats *
31616 ***************************/
31619 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
31620 struct hwrm_stat_ctx_clr_stats_input {
31621 /* The HWRM command request type. */
31624 * The completion ring to send the completion event on. This should
31625 * be the NQ ID returned from the `nq_alloc` HWRM command.
31627 uint16_t cmpl_ring;
31629 * The sequence ID is used by the driver for tracking multiple
31630 * commands. This ID is treated as opaque data by the firmware and
31631 * the value is returned in the `hwrm_resp_hdr` upon completion.
31635 * The target ID of the command:
31636 * * 0x0-0xFFF8 - The function ID
31637 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31638 * * 0xFFFD - Reserved for user-space HWRM interface
31641 uint16_t target_id;
31643 * A physical address pointer pointing to a host buffer that the
31644 * command's response data will be written. This can be either a host
31645 * physical address (HPA) or a guest physical address (GPA) and must
31646 * point to a physically contiguous block of memory.
31648 uint64_t resp_addr;
31649 /* ID of the statistics context that is being queried. */
31650 uint32_t stat_ctx_id;
31651 uint8_t unused_0[4];
31652 } __attribute__((packed));
31654 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
31655 struct hwrm_stat_ctx_clr_stats_output {
31656 /* The specific error status for the command. */
31657 uint16_t error_code;
31658 /* The HWRM command request type. */
31660 /* The sequence ID from the original command. */
31662 /* The length of the response data in number of bytes. */
31664 uint8_t unused_0[7];
31666 * This field is used in Output records to indicate that the output
31667 * is completely written to RAM. This field should be read as '1'
31668 * to indicate that the output has been completely written.
31669 * When writing a command completion or response to an internal processor,
31670 * the order of writes has to be such that this field is written last.
31673 } __attribute__((packed));
31675 /********************
31676 * hwrm_pcie_qstats *
31677 ********************/
31680 /* hwrm_pcie_qstats_input (size:256b/32B) */
31681 struct hwrm_pcie_qstats_input {
31682 /* The HWRM command request type. */
31685 * The completion ring to send the completion event on. This should
31686 * be the NQ ID returned from the `nq_alloc` HWRM command.
31688 uint16_t cmpl_ring;
31690 * The sequence ID is used by the driver for tracking multiple
31691 * commands. This ID is treated as opaque data by the firmware and
31692 * the value is returned in the `hwrm_resp_hdr` upon completion.
31696 * The target ID of the command:
31697 * * 0x0-0xFFF8 - The function ID
31698 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31699 * * 0xFFFD - Reserved for user-space HWRM interface
31702 uint16_t target_id;
31704 * A physical address pointer pointing to a host buffer that the
31705 * command's response data will be written. This can be either a host
31706 * physical address (HPA) or a guest physical address (GPA) and must
31707 * point to a physically contiguous block of memory.
31709 uint64_t resp_addr;
31711 * The size of PCIe statistics block in bytes.
31712 * Firmware will DMA the PCIe statistics to
31713 * the host with this field size in the response.
31715 uint16_t pcie_stat_size;
31716 uint8_t unused_0[6];
31718 * This is the host address where
31719 * PCIe statistics will be stored
31721 uint64_t pcie_stat_host_addr;
31722 } __attribute__((packed));
31724 /* hwrm_pcie_qstats_output (size:128b/16B) */
31725 struct hwrm_pcie_qstats_output {
31726 /* The specific error status for the command. */
31727 uint16_t error_code;
31728 /* The HWRM command request type. */
31730 /* The sequence ID from the original command. */
31732 /* The length of the response data in number of bytes. */
31734 /* The size of PCIe statistics block in bytes. */
31735 uint16_t pcie_stat_size;
31736 uint8_t unused_0[5];
31738 * This field is used in Output records to indicate that the output
31739 * is completely written to RAM. This field should be read as '1'
31740 * to indicate that the output has been completely written.
31741 * When writing a command completion or response to an internal processor,
31742 * the order of writes has to be such that this field is written last.
31745 } __attribute__((packed));
31747 /* PCIe Statistics Formats */
31748 /* pcie_ctx_hw_stats (size:768b/96B) */
31749 struct pcie_ctx_hw_stats {
31750 /* Number of physical layer receiver errors */
31751 uint64_t pcie_pl_signal_integrity;
31752 /* Number of DLLP CRC errors detected by Data Link Layer */
31753 uint64_t pcie_dl_signal_integrity;
31755 * Number of TLP LCRC and sequence number errors detected
31756 * by Data Link Layer
31758 uint64_t pcie_tl_signal_integrity;
31759 /* Number of times LTSSM entered Recovery state */
31760 uint64_t pcie_link_integrity;
31761 /* Number of TLP bytes that have been trasmitted */
31762 uint64_t pcie_tx_traffic_rate;
31763 /* Number of TLP bytes that have been received */
31764 uint64_t pcie_rx_traffic_rate;
31765 /* Number of DLLP bytes that have been trasmitted */
31766 uint64_t pcie_tx_dllp_statistics;
31767 /* Number of DLLP bytes that have been received */
31768 uint64_t pcie_rx_dllp_statistics;
31770 * Number of times spent in each phase of gen3
31773 uint64_t pcie_equalization_time;
31774 /* Records the last 16 transitions of the LTSSM */
31775 uint32_t pcie_ltssm_histogram[4];
31777 * Record the last 8 reasons on why LTSSM transitioned
31780 uint64_t pcie_recovery_histogram;
31781 } __attribute__((packed));
31783 /**********************
31784 * hwrm_exec_fwd_resp *
31785 **********************/
31788 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
31789 struct hwrm_exec_fwd_resp_input {
31790 /* The HWRM command request type. */
31793 * The completion ring to send the completion event on. This should
31794 * be the NQ ID returned from the `nq_alloc` HWRM command.
31796 uint16_t cmpl_ring;
31798 * The sequence ID is used by the driver for tracking multiple
31799 * commands. This ID is treated as opaque data by the firmware and
31800 * the value is returned in the `hwrm_resp_hdr` upon completion.
31804 * The target ID of the command:
31805 * * 0x0-0xFFF8 - The function ID
31806 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31807 * * 0xFFFD - Reserved for user-space HWRM interface
31810 uint16_t target_id;
31812 * A physical address pointer pointing to a host buffer that the
31813 * command's response data will be written. This can be either a host
31814 * physical address (HPA) or a guest physical address (GPA) and must
31815 * point to a physically contiguous block of memory.
31817 uint64_t resp_addr;
31819 * This is an encapsulated request. This request should
31820 * be executed by the HWRM and the response should be
31821 * provided in the response buffer inside the encapsulated
31824 uint32_t encap_request[26];
31826 * This value indicates the target id of the response to
31827 * the encapsulated request.
31828 * 0x0 - 0xFFF8 - Used for function ids
31829 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31832 uint16_t encap_resp_target_id;
31833 uint8_t unused_0[6];
31834 } __attribute__((packed));
31836 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
31837 struct hwrm_exec_fwd_resp_output {
31838 /* The specific error status for the command. */
31839 uint16_t error_code;
31840 /* The HWRM command request type. */
31842 /* The sequence ID from the original command. */
31844 /* The length of the response data in number of bytes. */
31846 uint8_t unused_0[7];
31848 * This field is used in Output records to indicate that the output
31849 * is completely written to RAM. This field should be read as '1'
31850 * to indicate that the output has been completely written.
31851 * When writing a command completion or response to an internal processor,
31852 * the order of writes has to be such that this field is written last.
31855 } __attribute__((packed));
31857 /************************
31858 * hwrm_reject_fwd_resp *
31859 ************************/
31862 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
31863 struct hwrm_reject_fwd_resp_input {
31864 /* The HWRM command request type. */
31867 * The completion ring to send the completion event on. This should
31868 * be the NQ ID returned from the `nq_alloc` HWRM command.
31870 uint16_t cmpl_ring;
31872 * The sequence ID is used by the driver for tracking multiple
31873 * commands. This ID is treated as opaque data by the firmware and
31874 * the value is returned in the `hwrm_resp_hdr` upon completion.
31878 * The target ID of the command:
31879 * * 0x0-0xFFF8 - The function ID
31880 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31881 * * 0xFFFD - Reserved for user-space HWRM interface
31884 uint16_t target_id;
31886 * A physical address pointer pointing to a host buffer that the
31887 * command's response data will be written. This can be either a host
31888 * physical address (HPA) or a guest physical address (GPA) and must
31889 * point to a physically contiguous block of memory.
31891 uint64_t resp_addr;
31893 * This is an encapsulated request. This request should
31894 * be rejected by the HWRM and the error response should be
31895 * provided in the response buffer inside the encapsulated
31898 uint32_t encap_request[26];
31900 * This value indicates the target id of the response to
31901 * the encapsulated request.
31902 * 0x0 - 0xFFF8 - Used for function ids
31903 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31906 uint16_t encap_resp_target_id;
31907 uint8_t unused_0[6];
31908 } __attribute__((packed));
31910 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
31911 struct hwrm_reject_fwd_resp_output {
31912 /* The specific error status for the command. */
31913 uint16_t error_code;
31914 /* The HWRM command request type. */
31916 /* The sequence ID from the original command. */
31918 /* The length of the response data in number of bytes. */
31920 uint8_t unused_0[7];
31922 * This field is used in Output records to indicate that the output
31923 * is completely written to RAM. This field should be read as '1'
31924 * to indicate that the output has been completely written.
31925 * When writing a command completion or response to an internal processor,
31926 * the order of writes has to be such that this field is written last.
31929 } __attribute__((packed));
31936 /* hwrm_fwd_resp_input (size:1024b/128B) */
31937 struct hwrm_fwd_resp_input {
31938 /* The HWRM command request type. */
31941 * The completion ring to send the completion event on. This should
31942 * be the NQ ID returned from the `nq_alloc` HWRM command.
31944 uint16_t cmpl_ring;
31946 * The sequence ID is used by the driver for tracking multiple
31947 * commands. This ID is treated as opaque data by the firmware and
31948 * the value is returned in the `hwrm_resp_hdr` upon completion.
31952 * The target ID of the command:
31953 * * 0x0-0xFFF8 - The function ID
31954 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31955 * * 0xFFFD - Reserved for user-space HWRM interface
31958 uint16_t target_id;
31960 * A physical address pointer pointing to a host buffer that the
31961 * command's response data will be written. This can be either a host
31962 * physical address (HPA) or a guest physical address (GPA) and must
31963 * point to a physically contiguous block of memory.
31965 uint64_t resp_addr;
31967 * This value indicates the target id of the encapsulated
31969 * 0x0 - 0xFFF8 - Used for function ids
31970 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31973 uint16_t encap_resp_target_id;
31975 * This value indicates the completion ring the encapsulated
31976 * response will be optionally completed on. If the value is
31977 * -1, then no CR completion shall be generated for the
31978 * encapsulated response. Any other value must be a
31979 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
31980 * is provided, then a CR completion shall be generated for
31981 * the encapsulated response.
31983 uint16_t encap_resp_cmpl_ring;
31984 /* This field indicates the length of encapsulated response. */
31985 uint16_t encap_resp_len;
31989 * This is the host address where the encapsulated response
31991 * This area must be 16B aligned and must be cleared to zero
31992 * before the original request is made.
31994 uint64_t encap_resp_addr;
31995 /* This is an encapsulated response. */
31996 uint32_t encap_resp[24];
31997 } __attribute__((packed));
31999 /* hwrm_fwd_resp_output (size:128b/16B) */
32000 struct hwrm_fwd_resp_output {
32001 /* The specific error status for the command. */
32002 uint16_t error_code;
32003 /* The HWRM command request type. */
32005 /* The sequence ID from the original command. */
32007 /* The length of the response data in number of bytes. */
32009 uint8_t unused_0[7];
32011 * This field is used in Output records to indicate that the output
32012 * is completely written to RAM. This field should be read as '1'
32013 * to indicate that the output has been completely written.
32014 * When writing a command completion or response to an internal processor,
32015 * the order of writes has to be such that this field is written last.
32018 } __attribute__((packed));
32020 /*****************************
32021 * hwrm_fwd_async_event_cmpl *
32022 *****************************/
32025 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
32026 struct hwrm_fwd_async_event_cmpl_input {
32027 /* The HWRM command request type. */
32030 * The completion ring to send the completion event on. This should
32031 * be the NQ ID returned from the `nq_alloc` HWRM command.
32033 uint16_t cmpl_ring;
32035 * The sequence ID is used by the driver for tracking multiple
32036 * commands. This ID is treated as opaque data by the firmware and
32037 * the value is returned in the `hwrm_resp_hdr` upon completion.
32041 * The target ID of the command:
32042 * * 0x0-0xFFF8 - The function ID
32043 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32044 * * 0xFFFD - Reserved for user-space HWRM interface
32047 uint16_t target_id;
32049 * A physical address pointer pointing to a host buffer that the
32050 * command's response data will be written. This can be either a host
32051 * physical address (HPA) or a guest physical address (GPA) and must
32052 * point to a physically contiguous block of memory.
32054 uint64_t resp_addr;
32056 * This value indicates the target id of the encapsulated
32057 * asynchronous event.
32058 * 0x0 - 0xFFF8 - Used for function ids
32059 * 0xFFF8 - 0xFFFE - Reserved for internal processors
32060 * 0xFFFF - Broadcast to all children VFs (only applicable when
32061 * a PF is the requester)
32063 uint16_t encap_async_event_target_id;
32064 uint8_t unused_0[6];
32065 /* This is an encapsulated asynchronous event completion. */
32066 uint32_t encap_async_event_cmpl[4];
32067 } __attribute__((packed));
32069 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
32070 struct hwrm_fwd_async_event_cmpl_output {
32071 /* The specific error status for the command. */
32072 uint16_t error_code;
32073 /* The HWRM command request type. */
32075 /* The sequence ID from the original command. */
32077 /* The length of the response data in number of bytes. */
32079 uint8_t unused_0[7];
32081 * This field is used in Output records to indicate that the output
32082 * is completely written to RAM. This field should be read as '1'
32083 * to indicate that the output has been completely written.
32084 * When writing a command completion or response to an internal processor,
32085 * the order of writes has to be such that this field is written last.
32088 } __attribute__((packed));
32090 /**************************
32091 * hwrm_nvm_raw_write_blk *
32092 **************************/
32095 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
32096 struct hwrm_nvm_raw_write_blk_input {
32097 /* The HWRM command request type. */
32100 * The completion ring to send the completion event on. This should
32101 * be the NQ ID returned from the `nq_alloc` HWRM command.
32103 uint16_t cmpl_ring;
32105 * The sequence ID is used by the driver for tracking multiple
32106 * commands. This ID is treated as opaque data by the firmware and
32107 * the value is returned in the `hwrm_resp_hdr` upon completion.
32111 * The target ID of the command:
32112 * * 0x0-0xFFF8 - The function ID
32113 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32114 * * 0xFFFD - Reserved for user-space HWRM interface
32117 uint16_t target_id;
32119 * A physical address pointer pointing to a host buffer that the
32120 * command's response data will be written. This can be either a host
32121 * physical address (HPA) or a guest physical address (GPA) and must
32122 * point to a physically contiguous block of memory.
32124 uint64_t resp_addr;
32126 * 64-bit Host Source Address.
32127 * This is the loation of the source data to be written.
32129 uint64_t host_src_addr;
32131 * 32-bit Destination Address.
32132 * This is the NVRAM byte-offset where the source data will be written to.
32134 uint32_t dest_addr;
32135 /* Length of data to be written, in bytes. */
32137 } __attribute__((packed));
32139 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
32140 struct hwrm_nvm_raw_write_blk_output {
32141 /* The specific error status for the command. */
32142 uint16_t error_code;
32143 /* The HWRM command request type. */
32145 /* The sequence ID from the original command. */
32147 /* The length of the response data in number of bytes. */
32149 uint8_t unused_0[7];
32151 * This field is used in Output records to indicate that the output
32152 * is completely written to RAM. This field should be read as '1'
32153 * to indicate that the output has been completely written.
32154 * When writing a command completion or response to an internal processor,
32155 * the order of writes has to be such that this field is written last.
32158 } __attribute__((packed));
32165 /* hwrm_nvm_read_input (size:320b/40B) */
32166 struct hwrm_nvm_read_input {
32167 /* The HWRM command request type. */
32170 * The completion ring to send the completion event on. This should
32171 * be the NQ ID returned from the `nq_alloc` HWRM command.
32173 uint16_t cmpl_ring;
32175 * The sequence ID is used by the driver for tracking multiple
32176 * commands. This ID is treated as opaque data by the firmware and
32177 * the value is returned in the `hwrm_resp_hdr` upon completion.
32181 * The target ID of the command:
32182 * * 0x0-0xFFF8 - The function ID
32183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32184 * * 0xFFFD - Reserved for user-space HWRM interface
32187 uint16_t target_id;
32189 * A physical address pointer pointing to a host buffer that the
32190 * command's response data will be written. This can be either a host
32191 * physical address (HPA) or a guest physical address (GPA) and must
32192 * point to a physically contiguous block of memory.
32194 uint64_t resp_addr;
32196 * 64-bit Host Destination Address.
32197 * This is the host address where the data will be written to.
32199 uint64_t host_dest_addr;
32200 /* The 0-based index of the directory entry. */
32202 uint8_t unused_0[2];
32203 /* The NVRAM byte-offset to read from. */
32205 /* The length of the data to be read, in bytes. */
32207 uint8_t unused_1[4];
32208 } __attribute__((packed));
32210 /* hwrm_nvm_read_output (size:128b/16B) */
32211 struct hwrm_nvm_read_output {
32212 /* The specific error status for the command. */
32213 uint16_t error_code;
32214 /* The HWRM command request type. */
32216 /* The sequence ID from the original command. */
32218 /* The length of the response data in number of bytes. */
32220 uint8_t unused_0[7];
32222 * This field is used in Output records to indicate that the output
32223 * is completely written to RAM. This field should be read as '1'
32224 * to indicate that the output has been completely written.
32225 * When writing a command completion or response to an internal processor,
32226 * the order of writes has to be such that this field is written last.
32229 } __attribute__((packed));
32231 /*********************
32232 * hwrm_nvm_raw_dump *
32233 *********************/
32236 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
32237 struct hwrm_nvm_raw_dump_input {
32238 /* The HWRM command request type. */
32241 * The completion ring to send the completion event on. This should
32242 * be the NQ ID returned from the `nq_alloc` HWRM command.
32244 uint16_t cmpl_ring;
32246 * The sequence ID is used by the driver for tracking multiple
32247 * commands. This ID is treated as opaque data by the firmware and
32248 * the value is returned in the `hwrm_resp_hdr` upon completion.
32252 * The target ID of the command:
32253 * * 0x0-0xFFF8 - The function ID
32254 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32255 * * 0xFFFD - Reserved for user-space HWRM interface
32258 uint16_t target_id;
32260 * A physical address pointer pointing to a host buffer that the
32261 * command's response data will be written. This can be either a host
32262 * physical address (HPA) or a guest physical address (GPA) and must
32263 * point to a physically contiguous block of memory.
32265 uint64_t resp_addr;
32267 * 64-bit Host Destination Address.
32268 * This is the host address where the data will be written to.
32270 uint64_t host_dest_addr;
32271 /* 32-bit NVRAM byte-offset to read from. */
32273 /* Total length of NVRAM contents to be read, in bytes. */
32275 } __attribute__((packed));
32277 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
32278 struct hwrm_nvm_raw_dump_output {
32279 /* The specific error status for the command. */
32280 uint16_t error_code;
32281 /* The HWRM command request type. */
32283 /* The sequence ID from the original command. */
32285 /* The length of the response data in number of bytes. */
32287 uint8_t unused_0[7];
32289 * This field is used in Output records to indicate that the output
32290 * is completely written to RAM. This field should be read as '1'
32291 * to indicate that the output has been completely written.
32292 * When writing a command completion or response to an internal processor,
32293 * the order of writes has to be such that this field is written last.
32296 } __attribute__((packed));
32298 /****************************
32299 * hwrm_nvm_get_dir_entries *
32300 ****************************/
32303 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
32304 struct hwrm_nvm_get_dir_entries_input {
32305 /* The HWRM command request type. */
32308 * The completion ring to send the completion event on. This should
32309 * be the NQ ID returned from the `nq_alloc` HWRM command.
32311 uint16_t cmpl_ring;
32313 * The sequence ID is used by the driver for tracking multiple
32314 * commands. This ID is treated as opaque data by the firmware and
32315 * the value is returned in the `hwrm_resp_hdr` upon completion.
32319 * The target ID of the command:
32320 * * 0x0-0xFFF8 - The function ID
32321 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32322 * * 0xFFFD - Reserved for user-space HWRM interface
32325 uint16_t target_id;
32327 * A physical address pointer pointing to a host buffer that the
32328 * command's response data will be written. This can be either a host
32329 * physical address (HPA) or a guest physical address (GPA) and must
32330 * point to a physically contiguous block of memory.
32332 uint64_t resp_addr;
32334 * 64-bit Host Destination Address.
32335 * This is the host address where the directory will be written.
32337 uint64_t host_dest_addr;
32338 } __attribute__((packed));
32340 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
32341 struct hwrm_nvm_get_dir_entries_output {
32342 /* The specific error status for the command. */
32343 uint16_t error_code;
32344 /* The HWRM command request type. */
32346 /* The sequence ID from the original command. */
32348 /* The length of the response data in number of bytes. */
32350 uint8_t unused_0[7];
32352 * This field is used in Output records to indicate that the output
32353 * is completely written to RAM. This field should be read as '1'
32354 * to indicate that the output has been completely written.
32355 * When writing a command completion or response to an internal processor,
32356 * the order of writes has to be such that this field is written last.
32359 } __attribute__((packed));
32361 /*************************
32362 * hwrm_nvm_get_dir_info *
32363 *************************/
32366 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
32367 struct hwrm_nvm_get_dir_info_input {
32368 /* The HWRM command request type. */
32371 * The completion ring to send the completion event on. This should
32372 * be the NQ ID returned from the `nq_alloc` HWRM command.
32374 uint16_t cmpl_ring;
32376 * The sequence ID is used by the driver for tracking multiple
32377 * commands. This ID is treated as opaque data by the firmware and
32378 * the value is returned in the `hwrm_resp_hdr` upon completion.
32382 * The target ID of the command:
32383 * * 0x0-0xFFF8 - The function ID
32384 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32385 * * 0xFFFD - Reserved for user-space HWRM interface
32388 uint16_t target_id;
32390 * A physical address pointer pointing to a host buffer that the
32391 * command's response data will be written. This can be either a host
32392 * physical address (HPA) or a guest physical address (GPA) and must
32393 * point to a physically contiguous block of memory.
32395 uint64_t resp_addr;
32396 } __attribute__((packed));
32398 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
32399 struct hwrm_nvm_get_dir_info_output {
32400 /* The specific error status for the command. */
32401 uint16_t error_code;
32402 /* The HWRM command request type. */
32404 /* The sequence ID from the original command. */
32406 /* The length of the response data in number of bytes. */
32408 /* Number of directory entries in the directory. */
32410 /* Size of each directory entry, in bytes. */
32411 uint32_t entry_length;
32412 uint8_t unused_0[7];
32414 * This field is used in Output records to indicate that the output
32415 * is completely written to RAM. This field should be read as '1'
32416 * to indicate that the output has been completely written.
32417 * When writing a command completion or response to an internal processor,
32418 * the order of writes has to be such that this field is written last.
32421 } __attribute__((packed));
32423 /******************
32425 ******************/
32428 /* hwrm_nvm_write_input (size:384b/48B) */
32429 struct hwrm_nvm_write_input {
32430 /* The HWRM command request type. */
32433 * The completion ring to send the completion event on. This should
32434 * be the NQ ID returned from the `nq_alloc` HWRM command.
32436 uint16_t cmpl_ring;
32438 * The sequence ID is used by the driver for tracking multiple
32439 * commands. This ID is treated as opaque data by the firmware and
32440 * the value is returned in the `hwrm_resp_hdr` upon completion.
32444 * The target ID of the command:
32445 * * 0x0-0xFFF8 - The function ID
32446 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32447 * * 0xFFFD - Reserved for user-space HWRM interface
32450 uint16_t target_id;
32452 * A physical address pointer pointing to a host buffer that the
32453 * command's response data will be written. This can be either a host
32454 * physical address (HPA) or a guest physical address (GPA) and must
32455 * point to a physically contiguous block of memory.
32457 uint64_t resp_addr;
32459 * 64-bit Host Source Address.
32460 * This is where the source data is.
32462 uint64_t host_src_addr;
32463 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
32466 * Directory ordinal.
32467 * The 0-based instance of the combined Directory Entry Type and Extension.
32469 uint16_t dir_ordinal;
32470 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
32472 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
32475 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
32476 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
32478 uint32_t dir_data_length;
32483 * When this bit is '1', the original active image
32484 * will not be removed. TBD: what purpose is this?
32486 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
32489 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
32490 * If this value is less than the specified data length, it will be ignored.
32491 * The response will contain the actual allocated item length, which may be greater than the requested item length.
32492 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
32493 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
32495 uint32_t dir_item_length;
32497 } __attribute__((packed));
32499 /* hwrm_nvm_write_output (size:128b/16B) */
32500 struct hwrm_nvm_write_output {
32501 /* The specific error status for the command. */
32502 uint16_t error_code;
32503 /* The HWRM command request type. */
32505 /* The sequence ID from the original command. */
32507 /* The length of the response data in number of bytes. */
32510 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
32511 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
32513 uint32_t dir_item_length;
32514 /* The directory index of the created or modified item. */
32518 * This field is used in Output records to indicate that the output
32519 * is completely written to RAM. This field should be read as '1'
32520 * to indicate that the output has been completely written.
32521 * When writing a command completion or response to an internal processor,
32522 * the order of writes has to be such that this field is written last.
32525 } __attribute__((packed));
32527 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
32528 struct hwrm_nvm_write_cmd_err {
32530 * command specific error codes that goes to
32531 * the cmd_err field in Common HWRM Error Response.
32534 /* Unknown error */
32535 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32536 /* Unable to complete operation due to fragmentation */
32537 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
32538 /* nvm is completely full. */
32539 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
32540 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
32541 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
32542 uint8_t unused_0[7];
32543 } __attribute__((packed));
32545 /*******************
32546 * hwrm_nvm_modify *
32547 *******************/
32550 /* hwrm_nvm_modify_input (size:320b/40B) */
32551 struct hwrm_nvm_modify_input {
32552 /* The HWRM command request type. */
32555 * The completion ring to send the completion event on. This should
32556 * be the NQ ID returned from the `nq_alloc` HWRM command.
32558 uint16_t cmpl_ring;
32560 * The sequence ID is used by the driver for tracking multiple
32561 * commands. This ID is treated as opaque data by the firmware and
32562 * the value is returned in the `hwrm_resp_hdr` upon completion.
32566 * The target ID of the command:
32567 * * 0x0-0xFFF8 - The function ID
32568 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32569 * * 0xFFFD - Reserved for user-space HWRM interface
32572 uint16_t target_id;
32574 * A physical address pointer pointing to a host buffer that the
32575 * command's response data will be written. This can be either a host
32576 * physical address (HPA) or a guest physical address (GPA) and must
32577 * point to a physically contiguous block of memory.
32579 uint64_t resp_addr;
32581 * 64-bit Host Source Address.
32582 * This is where the modified data is.
32584 uint64_t host_src_addr;
32585 /* 16-bit directory entry index. */
32587 uint8_t unused_0[2];
32588 /* 32-bit NVRAM byte-offset to modify content from. */
32591 * Length of data to be modified, in bytes. The length shall
32595 uint8_t unused_1[4];
32596 } __attribute__((packed));
32598 /* hwrm_nvm_modify_output (size:128b/16B) */
32599 struct hwrm_nvm_modify_output {
32600 /* The specific error status for the command. */
32601 uint16_t error_code;
32602 /* The HWRM command request type. */
32604 /* The sequence ID from the original command. */
32606 /* The length of the response data in number of bytes. */
32608 uint8_t unused_0[7];
32610 * This field is used in Output records to indicate that the output
32611 * is completely written to RAM. This field should be read as '1'
32612 * to indicate that the output has been completely written.
32613 * When writing a command completion or response to an internal processor,
32614 * the order of writes has to be such that this field is written last.
32617 } __attribute__((packed));
32619 /***************************
32620 * hwrm_nvm_find_dir_entry *
32621 ***************************/
32624 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
32625 struct hwrm_nvm_find_dir_entry_input {
32626 /* The HWRM command request type. */
32629 * The completion ring to send the completion event on. This should
32630 * be the NQ ID returned from the `nq_alloc` HWRM command.
32632 uint16_t cmpl_ring;
32634 * The sequence ID is used by the driver for tracking multiple
32635 * commands. This ID is treated as opaque data by the firmware and
32636 * the value is returned in the `hwrm_resp_hdr` upon completion.
32640 * The target ID of the command:
32641 * * 0x0-0xFFF8 - The function ID
32642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32643 * * 0xFFFD - Reserved for user-space HWRM interface
32646 uint16_t target_id;
32648 * A physical address pointer pointing to a host buffer that the
32649 * command's response data will be written. This can be either a host
32650 * physical address (HPA) or a guest physical address (GPA) and must
32651 * point to a physically contiguous block of memory.
32653 uint64_t resp_addr;
32656 * This bit must be '1' for the dir_idx_valid field to be
32659 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
32661 /* Directory Entry Index */
32663 /* Directory Entry (Image) Type */
32666 * Directory ordinal.
32667 * The instance of this Directory Type
32669 uint16_t dir_ordinal;
32670 /* The Directory Entry Extension flags. */
32672 /* This value indicates the search option using dir_ordinal. */
32673 uint8_t opt_ordinal;
32674 /* This value indicates the search option using dir_ordinal. */
32675 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
32676 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
32677 /* Equal to specified ordinal value. */
32678 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
32679 /* Greater than or equal to specified ordinal value */
32680 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
32681 /* Greater than specified ordinal value */
32682 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
32683 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
32684 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
32685 uint8_t unused_0[3];
32686 } __attribute__((packed));
32688 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
32689 struct hwrm_nvm_find_dir_entry_output {
32690 /* The specific error status for the command. */
32691 uint16_t error_code;
32692 /* The HWRM command request type. */
32694 /* The sequence ID from the original command. */
32696 /* The length of the response data in number of bytes. */
32698 /* Allocated NVRAM for this directory entry, in bytes. */
32699 uint32_t dir_item_length;
32700 /* Size of the stored data for this directory entry, in bytes. */
32701 uint32_t dir_data_length;
32703 * Firmware version.
32704 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
32707 /* Directory ordinal. */
32708 uint16_t dir_ordinal;
32709 /* Directory Entry Index */
32711 uint8_t unused_0[7];
32713 * This field is used in Output records to indicate that the output
32714 * is completely written to RAM. This field should be read as '1'
32715 * to indicate that the output has been completely written.
32716 * When writing a command completion or response to an internal processor,
32717 * the order of writes has to be such that this field is written last.
32720 } __attribute__((packed));
32722 /****************************
32723 * hwrm_nvm_erase_dir_entry *
32724 ****************************/
32727 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
32728 struct hwrm_nvm_erase_dir_entry_input {
32729 /* The HWRM command request type. */
32732 * The completion ring to send the completion event on. This should
32733 * be the NQ ID returned from the `nq_alloc` HWRM command.
32735 uint16_t cmpl_ring;
32737 * The sequence ID is used by the driver for tracking multiple
32738 * commands. This ID is treated as opaque data by the firmware and
32739 * the value is returned in the `hwrm_resp_hdr` upon completion.
32743 * The target ID of the command:
32744 * * 0x0-0xFFF8 - The function ID
32745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32746 * * 0xFFFD - Reserved for user-space HWRM interface
32749 uint16_t target_id;
32751 * A physical address pointer pointing to a host buffer that the
32752 * command's response data will be written. This can be either a host
32753 * physical address (HPA) or a guest physical address (GPA) and must
32754 * point to a physically contiguous block of memory.
32756 uint64_t resp_addr;
32757 /* Directory Entry Index */
32759 uint8_t unused_0[6];
32760 } __attribute__((packed));
32762 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
32763 struct hwrm_nvm_erase_dir_entry_output {
32764 /* The specific error status for the command. */
32765 uint16_t error_code;
32766 /* The HWRM command request type. */
32768 /* The sequence ID from the original command. */
32770 /* The length of the response data in number of bytes. */
32772 uint8_t unused_0[7];
32774 * This field is used in Output records to indicate that the output
32775 * is completely written to RAM. This field should be read as '1'
32776 * to indicate that the output has been completely written.
32777 * When writing a command completion or response to an internal processor,
32778 * the order of writes has to be such that this field is written last.
32781 } __attribute__((packed));
32783 /*************************
32784 * hwrm_nvm_get_dev_info *
32785 *************************/
32788 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
32789 struct hwrm_nvm_get_dev_info_input {
32790 /* The HWRM command request type. */
32793 * The completion ring to send the completion event on. This should
32794 * be the NQ ID returned from the `nq_alloc` HWRM command.
32796 uint16_t cmpl_ring;
32798 * The sequence ID is used by the driver for tracking multiple
32799 * commands. This ID is treated as opaque data by the firmware and
32800 * the value is returned in the `hwrm_resp_hdr` upon completion.
32804 * The target ID of the command:
32805 * * 0x0-0xFFF8 - The function ID
32806 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32807 * * 0xFFFD - Reserved for user-space HWRM interface
32810 uint16_t target_id;
32812 * A physical address pointer pointing to a host buffer that the
32813 * command's response data will be written. This can be either a host
32814 * physical address (HPA) or a guest physical address (GPA) and must
32815 * point to a physically contiguous block of memory.
32817 uint64_t resp_addr;
32818 } __attribute__((packed));
32820 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
32821 struct hwrm_nvm_get_dev_info_output {
32822 /* The specific error status for the command. */
32823 uint16_t error_code;
32824 /* The HWRM command request type. */
32826 /* The sequence ID from the original command. */
32828 /* The length of the response data in number of bytes. */
32830 /* Manufacturer ID. */
32831 uint16_t manufacturer_id;
32833 uint16_t device_id;
32834 /* Sector size of the NVRAM device. */
32835 uint32_t sector_size;
32836 /* Total size, in bytes of the NVRAM device. */
32837 uint32_t nvram_size;
32838 uint32_t reserved_size;
32839 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
32840 uint32_t available_size;
32841 /* This field represents the major version of NVM cfg */
32842 uint8_t nvm_cfg_ver_maj;
32843 /* This field represents the minor version of NVM cfg */
32844 uint8_t nvm_cfg_ver_min;
32845 /* This field represents the update version of NVM cfg */
32846 uint8_t nvm_cfg_ver_upd;
32848 * This field is used in Output records to indicate that the output
32849 * is completely written to RAM. This field should be read as '1'
32850 * to indicate that the output has been completely written.
32851 * When writing a command completion or response to an internal processor,
32852 * the order of writes has to be such that this field is written last.
32855 } __attribute__((packed));
32857 /**************************
32858 * hwrm_nvm_mod_dir_entry *
32859 **************************/
32862 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
32863 struct hwrm_nvm_mod_dir_entry_input {
32864 /* The HWRM command request type. */
32867 * The completion ring to send the completion event on. This should
32868 * be the NQ ID returned from the `nq_alloc` HWRM command.
32870 uint16_t cmpl_ring;
32872 * The sequence ID is used by the driver for tracking multiple
32873 * commands. This ID is treated as opaque data by the firmware and
32874 * the value is returned in the `hwrm_resp_hdr` upon completion.
32878 * The target ID of the command:
32879 * * 0x0-0xFFF8 - The function ID
32880 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32881 * * 0xFFFD - Reserved for user-space HWRM interface
32884 uint16_t target_id;
32886 * A physical address pointer pointing to a host buffer that the
32887 * command's response data will be written. This can be either a host
32888 * physical address (HPA) or a guest physical address (GPA) and must
32889 * point to a physically contiguous block of memory.
32891 uint64_t resp_addr;
32894 * This bit must be '1' for the checksum field to be
32897 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
32898 /* Directory Entry Index */
32901 * Directory ordinal.
32902 * The (0-based) instance of this Directory Type.
32904 uint16_t dir_ordinal;
32905 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
32907 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
32910 * If valid, then this field updates the checksum
32911 * value of the content in the directory entry.
32914 } __attribute__((packed));
32916 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
32917 struct hwrm_nvm_mod_dir_entry_output {
32918 /* The specific error status for the command. */
32919 uint16_t error_code;
32920 /* The HWRM command request type. */
32922 /* The sequence ID from the original command. */
32924 /* The length of the response data in number of bytes. */
32926 uint8_t unused_0[7];
32928 * This field is used in Output records to indicate that the output
32929 * is completely written to RAM. This field should be read as '1'
32930 * to indicate that the output has been completely written.
32931 * When writing a command completion or response to an internal processor,
32932 * the order of writes has to be such that this field is written last.
32935 } __attribute__((packed));
32937 /**************************
32938 * hwrm_nvm_verify_update *
32939 **************************/
32942 /* hwrm_nvm_verify_update_input (size:192b/24B) */
32943 struct hwrm_nvm_verify_update_input {
32944 /* The HWRM command request type. */
32947 * The completion ring to send the completion event on. This should
32948 * be the NQ ID returned from the `nq_alloc` HWRM command.
32950 uint16_t cmpl_ring;
32952 * The sequence ID is used by the driver for tracking multiple
32953 * commands. This ID is treated as opaque data by the firmware and
32954 * the value is returned in the `hwrm_resp_hdr` upon completion.
32958 * The target ID of the command:
32959 * * 0x0-0xFFF8 - The function ID
32960 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32961 * * 0xFFFD - Reserved for user-space HWRM interface
32964 uint16_t target_id;
32966 * A physical address pointer pointing to a host buffer that the
32967 * command's response data will be written. This can be either a host
32968 * physical address (HPA) or a guest physical address (GPA) and must
32969 * point to a physically contiguous block of memory.
32971 uint64_t resp_addr;
32972 /* Directory Entry Type, to be verified. */
32975 * Directory ordinal.
32976 * The instance of the Directory Type to be verified.
32978 uint16_t dir_ordinal;
32980 * The Directory Entry Extension flags.
32981 * The "UPDATE" extension flag must be set in this value.
32982 * A corresponding directory entry with the same type and ordinal values but *without*
32983 * the "UPDATE" extension flag must also exist. The other flags of the extension must
32984 * be identical between the active and update entries.
32987 uint8_t unused_0[2];
32988 } __attribute__((packed));
32990 /* hwrm_nvm_verify_update_output (size:128b/16B) */
32991 struct hwrm_nvm_verify_update_output {
32992 /* The specific error status for the command. */
32993 uint16_t error_code;
32994 /* The HWRM command request type. */
32996 /* The sequence ID from the original command. */
32998 /* The length of the response data in number of bytes. */
33000 uint8_t unused_0[7];
33002 * This field is used in Output records to indicate that the output
33003 * is completely written to RAM. This field should be read as '1'
33004 * to indicate that the output has been completely written.
33005 * When writing a command completion or response to an internal processor,
33006 * the order of writes has to be such that this field is written last.
33009 } __attribute__((packed));
33011 /***************************
33012 * hwrm_nvm_install_update *
33013 ***************************/
33016 /* hwrm_nvm_install_update_input (size:192b/24B) */
33017 struct hwrm_nvm_install_update_input {
33018 /* The HWRM command request type. */
33021 * The completion ring to send the completion event on. This should
33022 * be the NQ ID returned from the `nq_alloc` HWRM command.
33024 uint16_t cmpl_ring;
33026 * The sequence ID is used by the driver for tracking multiple
33027 * commands. This ID is treated as opaque data by the firmware and
33028 * the value is returned in the `hwrm_resp_hdr` upon completion.
33032 * The target ID of the command:
33033 * * 0x0-0xFFF8 - The function ID
33034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33035 * * 0xFFFD - Reserved for user-space HWRM interface
33038 uint16_t target_id;
33040 * A physical address pointer pointing to a host buffer that the
33041 * command's response data will be written. This can be either a host
33042 * physical address (HPA) or a guest physical address (GPA) and must
33043 * point to a physically contiguous block of memory.
33045 uint64_t resp_addr;
33047 * Installation type. If the value 3 through 0xffff is used,
33048 * only packaged items with that type value will be installed and
33049 * conditional installation directives for those packaged items
33050 * will be over-ridden (i.e. 'create' or 'replace' will be treated
33053 uint32_t install_type;
33055 * Perform a normal package installation. Conditional installation
33056 * directives (e.g. 'create' and 'replace') of packaged items
33057 * will be followed.
33059 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
33061 * Install all packaged items regardless of installation directive
33062 * (i.e. treat all packaged items as though they have an installation
33063 * directive of 'install').
33065 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
33066 UINT32_C(0xffffffff)
33067 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
33068 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
33070 /* If set to 1, then securely erase all unused locations in persistent storage. */
33071 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
33074 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
33075 * When combined with erase_unused_space then unspecified images will be securely erased.
33077 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
33080 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
33081 * Allow additional time for this command to complete if this bit is set to 1.
33083 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
33085 uint8_t unused_0[2];
33086 } __attribute__((packed));
33088 /* hwrm_nvm_install_update_output (size:192b/24B) */
33089 struct hwrm_nvm_install_update_output {
33090 /* The specific error status for the command. */
33091 uint16_t error_code;
33092 /* The HWRM command request type. */
33094 /* The sequence ID from the original command. */
33096 /* The length of the response data in number of bytes. */
33099 * Bit-mask of successfully installed items.
33100 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
33101 * A value of 0 indicates that no items were successfully installed.
33103 uint64_t installed_items;
33104 /* result is 8 b */
33106 /* There was no problem with the package installation. */
33107 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
33108 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
33109 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
33110 /* problem_item is 8 b */
33111 uint8_t problem_item;
33112 /* There was no problem with any packaged items. */
33113 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
33115 /* There was a problem with the NVM package itself. */
33116 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
33118 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
33119 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
33120 /* reset_required is 8 b */
33121 uint8_t reset_required;
33123 * No reset is required for installed/updated firmware or
33124 * microcode to take effect.
33126 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
33129 * A PCIe reset (e.g. system reboot) is
33130 * required for newly installed/updated firmware or
33131 * microcode to take effect.
33133 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
33136 * A controller power reset (e.g. system power-cycle) is
33137 * required for newly installed/updated firmware or
33138 * microcode to take effect. Some newly installed/updated
33139 * firmware or microcode may still take effect upon the
33142 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
33144 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
33145 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
33146 uint8_t unused_0[4];
33148 * This field is used in Output records to indicate that the output
33149 * is completely written to RAM. This field should be read as '1'
33150 * to indicate that the output has been completely written.
33151 * When writing a command completion or response to an internal processor,
33152 * the order of writes has to be such that this field is written last.
33155 } __attribute__((packed));
33157 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
33158 struct hwrm_nvm_install_update_cmd_err {
33160 * command specific error codes that goes to
33161 * the cmd_err field in Common HWRM Error Response.
33164 /* Unknown error */
33165 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33166 /* Unable to complete operation due to fragmentation */
33167 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
33168 /* nvm is completely full. */
33169 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
33170 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
33171 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
33172 uint8_t unused_0[7];
33173 } __attribute__((packed));
33175 /******************
33177 ******************/
33180 /* hwrm_nvm_flush_input (size:128b/16B) */
33181 struct hwrm_nvm_flush_input {
33182 /* The HWRM command request type. */
33185 * The completion ring to send the completion event on. This should
33186 * be the NQ ID returned from the `nq_alloc` HWRM command.
33188 uint16_t cmpl_ring;
33190 * The sequence ID is used by the driver for tracking multiple
33191 * commands. This ID is treated as opaque data by the firmware and
33192 * the value is returned in the `hwrm_resp_hdr` upon completion.
33196 * The target ID of the command:
33197 * * 0x0-0xFFF8 - The function ID
33198 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33199 * * 0xFFFD - Reserved for user-space HWRM interface
33202 uint16_t target_id;
33204 * A physical address pointer pointing to a host buffer that the
33205 * command's response data will be written. This can be either a host
33206 * physical address (HPA) or a guest physical address (GPA) and must
33207 * point to a physically contiguous block of memory.
33209 uint64_t resp_addr;
33210 } __attribute__((packed));
33212 /* hwrm_nvm_flush_output (size:128b/16B) */
33213 struct hwrm_nvm_flush_output {
33214 /* The specific error status for the command. */
33215 uint16_t error_code;
33216 /* The HWRM command request type. */
33218 /* The sequence ID from the original command. */
33220 /* The length of the response data in number of bytes. */
33222 uint8_t unused_0[7];
33224 * This field is used in Output records to indicate that the output
33225 * is completely written to RAM. This field should be read as '1'
33226 * to indicate that the output has been completely written.
33227 * When writing a command completion or response to an internal processor,
33228 * the order of writes has to be such that this field is written last.
33231 } __attribute__((packed));
33233 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
33234 struct hwrm_nvm_flush_cmd_err {
33236 * command specific error codes that goes to
33237 * the cmd_err field in Common HWRM Error Response.
33240 /* Unknown error */
33241 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33242 /* flush could not be performed */
33243 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
33244 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
33245 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
33246 uint8_t unused_0[7];
33247 } __attribute__((packed));
33249 /*************************
33250 * hwrm_nvm_get_variable *
33251 *************************/
33254 /* hwrm_nvm_get_variable_input (size:320b/40B) */
33255 struct hwrm_nvm_get_variable_input {
33256 /* The HWRM command request type. */
33259 * The completion ring to send the completion event on. This should
33260 * be the NQ ID returned from the `nq_alloc` HWRM command.
33262 uint16_t cmpl_ring;
33264 * The sequence ID is used by the driver for tracking multiple
33265 * commands. This ID is treated as opaque data by the firmware and
33266 * the value is returned in the `hwrm_resp_hdr` upon completion.
33270 * The target ID of the command:
33271 * * 0x0-0xFFF8 - The function ID
33272 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33273 * * 0xFFFD - Reserved for user-space HWRM interface
33276 uint16_t target_id;
33278 * A physical address pointer pointing to a host buffer that the
33279 * command's response data will be written. This can be either a host
33280 * physical address (HPA) or a guest physical address (GPA) and must
33281 * point to a physically contiguous block of memory.
33283 uint64_t resp_addr;
33285 * This is the host address where
33286 * nvm variable will be stored
33288 uint64_t dest_data_addr;
33289 /* size of data in bits */
33291 /* nvm cfg option number */
33292 uint16_t option_num;
33294 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33296 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
33298 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
33299 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
33301 * Number of dimensions for this nvm configuration variable.
33302 * This value indicates how many of the indexN values to use.
33303 * A value of 0 means that none of the indexN values are valid.
33304 * A value of 1 requires at index0 is valued, a value of 2
33305 * requires that index0 and index1 are valid, and so forth
33307 uint16_t dimensions;
33308 /* index for the 1st dimensions */
33310 /* index for the 2nd dimensions */
33312 /* index for the 3rd dimensions */
33314 /* index for the 4th dimensions */
33318 * When this bit is set to 1, the factory default value will be returned,
33319 * 0 returns the operational value.
33321 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
33324 } __attribute__((packed));
33326 /* hwrm_nvm_get_variable_output (size:128b/16B) */
33327 struct hwrm_nvm_get_variable_output {
33328 /* The specific error status for the command. */
33329 uint16_t error_code;
33330 /* The HWRM command request type. */
33332 /* The sequence ID from the original command. */
33334 /* The length of the response data in number of bytes. */
33336 /* size of data of the actual variable retrieved in bits */
33339 * option_num is the option number for the data retrieved. It is possible in the
33340 * future that the option number returned would be different than requested. This
33341 * condition could occur if an option is deprecated and a new option id is defined
33342 * with similar characteristics, but has a slightly different definition. This
33343 * also makes it convenient for the caller to identify the variable result with
33344 * the option id from the response.
33346 uint16_t option_num;
33348 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33350 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
33352 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
33353 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
33354 uint8_t unused_0[3];
33356 * This field is used in Output records to indicate that the output
33357 * is completely written to RAM. This field should be read as '1'
33358 * to indicate that the output has been completely written.
33359 * When writing a command completion or response to an internal processor,
33360 * the order of writes has to be such that this field is written last.
33363 } __attribute__((packed));
33365 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
33366 struct hwrm_nvm_get_variable_cmd_err {
33368 * command specific error codes that goes to
33369 * the cmd_err field in Common HWRM Error Response.
33372 /* Unknown error */
33373 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33374 /* variable does not exist */
33375 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
33376 /* configuration is corrupted and the variable cannot be saved */
33377 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
33378 /* length specified is too small */
33379 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
33380 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
33381 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
33382 uint8_t unused_0[7];
33383 } __attribute__((packed));
33385 /*************************
33386 * hwrm_nvm_set_variable *
33387 *************************/
33390 /* hwrm_nvm_set_variable_input (size:320b/40B) */
33391 struct hwrm_nvm_set_variable_input {
33392 /* The HWRM command request type. */
33395 * The completion ring to send the completion event on. This should
33396 * be the NQ ID returned from the `nq_alloc` HWRM command.
33398 uint16_t cmpl_ring;
33400 * The sequence ID is used by the driver for tracking multiple
33401 * commands. This ID is treated as opaque data by the firmware and
33402 * the value is returned in the `hwrm_resp_hdr` upon completion.
33406 * The target ID of the command:
33407 * * 0x0-0xFFF8 - The function ID
33408 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33409 * * 0xFFFD - Reserved for user-space HWRM interface
33412 uint16_t target_id;
33414 * A physical address pointer pointing to a host buffer that the
33415 * command's response data will be written. This can be either a host
33416 * physical address (HPA) or a guest physical address (GPA) and must
33417 * point to a physically contiguous block of memory.
33419 uint64_t resp_addr;
33421 * This is the host address where
33422 * nvm variable will be copied from
33424 uint64_t src_data_addr;
33425 /* size of data in bits */
33427 /* nvm cfg option number */
33428 uint16_t option_num;
33430 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
33432 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
33434 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
33435 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
33437 * Number of dimensions for this nvm configuration variable.
33438 * This value indicates how many of the indexN values to use.
33439 * A value of 0 means that none of the indexN values are valid.
33440 * A value of 1 requires at index0 is valued, a value of 2
33441 * requires that index0 and index1 are valid, and so forth
33443 uint16_t dimensions;
33444 /* index for the 1st dimensions */
33446 /* index for the 2nd dimensions */
33448 /* index for the 3rd dimensions */
33450 /* index for the 4th dimensions */
33453 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
33454 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
33456 /* encryption method */
33457 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
33459 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
33460 /* No encryption. */
33461 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
33462 (UINT32_C(0x0) << 1)
33463 /* one-way encryption. */
33464 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
33465 (UINT32_C(0x1) << 1)
33466 /* symmetric AES256 encryption. */
33467 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
33468 (UINT32_C(0x2) << 1)
33469 /* SHA1 digest appended to plaintext contents, for authentication */
33470 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
33471 (UINT32_C(0x3) << 1)
33472 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
33473 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
33474 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
33476 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
33477 /* When this bit is 1, update the factory default region */
33478 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
33481 } __attribute__((packed));
33483 /* hwrm_nvm_set_variable_output (size:128b/16B) */
33484 struct hwrm_nvm_set_variable_output {
33485 /* The specific error status for the command. */
33486 uint16_t error_code;
33487 /* The HWRM command request type. */
33489 /* The sequence ID from the original command. */
33491 /* The length of the response data in number of bytes. */
33493 uint8_t unused_0[7];
33495 * This field is used in Output records to indicate that the output
33496 * is completely written to RAM. This field should be read as '1'
33497 * to indicate that the output has been completely written.
33498 * When writing a command completion or response to an internal processor,
33499 * the order of writes has to be such that this field is written last.
33502 } __attribute__((packed));
33504 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
33505 struct hwrm_nvm_set_variable_cmd_err {
33507 * command specific error codes that goes to
33508 * the cmd_err field in Common HWRM Error Response.
33511 /* Unknown error */
33512 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33513 /* variable does not exist */
33514 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
33515 /* configuration is corrupted and the variable cannot be saved */
33516 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
33517 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
33518 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
33519 uint8_t unused_0[7];
33520 } __attribute__((packed));
33522 /****************************
33523 * hwrm_nvm_validate_option *
33524 ****************************/
33527 /* hwrm_nvm_validate_option_input (size:320b/40B) */
33528 struct hwrm_nvm_validate_option_input {
33529 /* The HWRM command request type. */
33532 * The completion ring to send the completion event on. This should
33533 * be the NQ ID returned from the `nq_alloc` HWRM command.
33535 uint16_t cmpl_ring;
33537 * The sequence ID is used by the driver for tracking multiple
33538 * commands. This ID is treated as opaque data by the firmware and
33539 * the value is returned in the `hwrm_resp_hdr` upon completion.
33543 * The target ID of the command:
33544 * * 0x0-0xFFF8 - The function ID
33545 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33546 * * 0xFFFD - Reserved for user-space HWRM interface
33549 uint16_t target_id;
33551 * A physical address pointer pointing to a host buffer that the
33552 * command's response data will be written. This can be either a host
33553 * physical address (HPA) or a guest physical address (GPA) and must
33554 * point to a physically contiguous block of memory.
33556 uint64_t resp_addr;
33558 * This is the host address where
33559 * nvm variable will be copied from
33561 uint64_t src_data_addr;
33562 /* size of data in bits */
33564 /* nvm cfg option number */
33565 uint16_t option_num;
33567 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
33570 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
33572 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
33573 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
33575 * Number of dimensions for this nvm configuration variable.
33576 * This value indicates how many of the indexN values to use.
33577 * A value of 0 means that none of the indexN values are valid.
33578 * A value of 1 requires at index0 is valued, a value of 2
33579 * requires that index0 and index1 are valid, and so forth
33581 uint16_t dimensions;
33582 /* index for the 1st dimensions */
33584 /* index for the 2nd dimensions */
33586 /* index for the 3rd dimensions */
33588 /* index for the 4th dimensions */
33590 uint8_t unused_0[2];
33591 } __attribute__((packed));
33593 /* hwrm_nvm_validate_option_output (size:128b/16B) */
33594 struct hwrm_nvm_validate_option_output {
33595 /* The specific error status for the command. */
33596 uint16_t error_code;
33597 /* The HWRM command request type. */
33599 /* The sequence ID from the original command. */
33601 /* The length of the response data in number of bytes. */
33604 /* indicates that the value provided for the option is not matching with the saved data. */
33605 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
33606 /* indicates that the value provided for the option is matching the saved data. */
33607 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
33608 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
33609 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
33610 uint8_t unused_0[6];
33612 * This field is used in Output records to indicate that the output
33613 * is completely written to RAM. This field should be read as '1'
33614 * to indicate that the output has been completely written.
33615 * When writing a command completion or response to an internal processor,
33616 * the order of writes has to be such that this field is written last.
33619 } __attribute__((packed));
33621 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
33622 struct hwrm_nvm_validate_option_cmd_err {
33624 * command specific error codes that goes to
33625 * the cmd_err field in Common HWRM Error Response.
33628 /* Unknown error */
33629 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33630 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
33631 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
33632 uint8_t unused_0[7];
33633 } __attribute__((packed));
33637 ******************/
33640 /* hwrm_fw_reset_input (size:192b/24B) */
33641 struct hwrm_fw_reset_input {
33642 /* The HWRM command request type. */
33645 * The completion ring to send the completion event on. This should
33646 * be the NQ ID returned from the `nq_alloc` HWRM command.
33648 uint16_t cmpl_ring;
33650 * The sequence ID is used by the driver for tracking multiple
33651 * commands. This ID is treated as opaque data by the firmware and
33652 * the value is returned in the `hwrm_resp_hdr` upon completion.
33656 * The target ID of the command:
33657 * * 0x0-0xFFF8 - The function ID
33658 * * 0xFFF8-0xFFFE - Reserved for internal processors
33661 uint16_t target_id;
33663 * A physical address pointer pointing to a host buffer that the
33664 * command's response data will be written. This can be either a host
33665 * physical address (HPA) or a guest physical address (GPA) and must
33666 * point to a physically contiguous block of memory.
33668 uint64_t resp_addr;
33669 /* Type of embedded processor. */
33670 uint8_t embedded_proc_type;
33671 /* Boot Processor */
33672 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
33674 /* Management Processor */
33675 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
33677 /* Network control processor */
33678 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
33680 /* RoCE control processor */
33681 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
33684 * Host (in multi-host environment): This is only valid if requester is IPC.
33685 * Reinit host hardware resources and PCIe.
33687 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
33689 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
33690 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
33692 /* Reset all blocks of the chip (including all processors) */
33693 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
33696 * Host (in multi-host environment): This is only valid if requester is IPC.
33697 * Reinit host hardware resources.
33699 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
33701 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
33702 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
33703 /* Type of self reset. */
33704 uint8_t selfrst_status;
33705 /* No Self Reset */
33706 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
33708 /* Self Reset as soon as possible to do so safely */
33709 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
33711 /* Self Reset on PCIe Reset */
33712 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
33714 /* Self Reset immediately after notification to all clients. */
33715 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
33717 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
33718 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
33720 * Indicate which host is being reset. 0 means first host.
33721 * Only valid when embedded_proc_type is host in multihost
33727 * When this bit is '1', then the core firmware initiates
33728 * the reset only after graceful shut down of all registered instances.
33729 * If not, the device will continue with the existing firmware.
33731 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
33732 uint8_t unused_0[4];
33733 } __attribute__((packed));
33735 /* hwrm_fw_reset_output (size:128b/16B) */
33736 struct hwrm_fw_reset_output {
33737 /* The specific error status for the command. */
33738 uint16_t error_code;
33739 /* The HWRM command request type. */
33741 /* The sequence ID from the original command. */
33743 /* The length of the response data in number of bytes. */
33745 /* Type of self reset. */
33746 uint8_t selfrst_status;
33747 /* No Self Reset */
33748 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
33750 /* Self Reset as soon as possible to do so safely */
33751 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
33753 /* Self Reset on PCIe Reset */
33754 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
33756 /* Self Reset immediately after notification to all clients. */
33757 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
33759 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
33760 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
33761 uint8_t unused_0[6];
33763 * This field is used in Output records to indicate that the output
33764 * is completely written to RAM. This field should be read as '1'
33765 * to indicate that the output has been completely written.
33766 * When writing a command completion or response to an internal processor,
33767 * the order of writes has to be such that this field is written last.
33770 } __attribute__((packed));
33772 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */