1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Broadcom
19 #define TF_SESSIONS_MAX 1 /** max # sessions */
20 #define TF_SESSION_ID_INVALID 0xFFFFFFFF /** Invalid Session ID define */
24 * Shared memory containing private TruFlow session information.
25 * Through this structure the session can keep track of resource
26 * allocations and (if so configured) any shadow copy of flow
29 * Memory is assigned to the Truflow instance by way of
30 * tf_open_session. Memory is allocated and owned by i.e. ULP.
32 * Access control to this shared memory is handled by the spin_lock in
36 /** TrueFlow Version. Used to control the structure layout
37 * when sharing sessions. No guarantee that a secondary
38 * process would come from the same version of an executable.
40 struct tf_session_version ver;
42 /** Device type, provided by tf_open_session().
44 enum tf_device_type device_type;
46 /** Session ID, allocated by FW on tf_open_session().
48 union tf_session_id session_id;
51 * String containing name of control channel interface to be
52 * used for this session to communicate with firmware.
54 * ctrl_chan_name will be used as part of a name for any
55 * shared memory allocation.
57 char ctrl_chan_name[TF_SESSION_NAME_MAX];
60 * Boolean controlling the use and availability of shadow
61 * copy. Shadow copy will allow the TruFlow Core to keep track
62 * of resource content on the firmware side without having to
63 * query firmware. Additional private session core_data will
64 * be allocated if this boolean is set to 'true', default
67 * Size of memory depends on the NVM Resource settings for the
73 * Session Reference Count. To keep track of functions per
74 * session the ref_count is incremented. There is also a
75 * parallel TruFlow Firmware ref_count in case the TruFlow
76 * Core goes away without informing the Firmware.
80 /** Session HW and SRAM resources */
83 /* Session HW resource pools */
85 /** RX L2 CTXT TCAM Pool */
86 BITALLOC_INST(TF_L2_CTXT_TCAM_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);
87 /** TX L2 CTXT TCAM Pool */
88 BITALLOC_INST(TF_L2_CTXT_TCAM_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);
90 /** RX Profile Func Pool */
91 BITALLOC_INST(TF_PROF_FUNC_POOL_NAME_RX, TF_NUM_PROF_FUNC);
92 /** TX Profile Func Pool */
93 BITALLOC_INST(TF_PROF_FUNC_POOL_NAME_TX, TF_NUM_PROF_FUNC);
95 /** RX Profile TCAM Pool */
96 BITALLOC_INST(TF_PROF_TCAM_POOL_NAME_RX, TF_NUM_PROF_TCAM);
97 /** TX Profile TCAM Pool */
98 BITALLOC_INST(TF_PROF_TCAM_POOL_NAME_TX, TF_NUM_PROF_TCAM);
100 /** RX EM Profile ID Pool */
101 BITALLOC_INST(TF_EM_PROF_ID_POOL_NAME_RX, TF_NUM_EM_PROF_ID);
102 /** TX EM Key Pool */
103 BITALLOC_INST(TF_EM_PROF_ID_POOL_NAME_TX, TF_NUM_EM_PROF_ID);
105 /** RX WC Profile Pool */
106 BITALLOC_INST(TF_WC_TCAM_PROF_ID_POOL_NAME_RX, TF_NUM_WC_PROF_ID);
107 /** TX WC Profile Pool */
108 BITALLOC_INST(TF_WC_TCAM_PROF_ID_POOL_NAME_TX, TF_NUM_WC_PROF_ID);
110 /* TBD, how do we want to handle EM records ?*/
111 /* EM Records are not controlled by way of a pool */
113 /** RX WC TCAM Pool */
114 BITALLOC_INST(TF_WC_TCAM_POOL_NAME_RX, TF_NUM_WC_TCAM_ROW);
115 /** TX WC TCAM Pool */
116 BITALLOC_INST(TF_WC_TCAM_POOL_NAME_TX, TF_NUM_WC_TCAM_ROW);
118 /** RX Meter Profile Pool */
119 BITALLOC_INST(TF_METER_PROF_POOL_NAME_RX, TF_NUM_METER_PROF);
120 /** TX Meter Profile Pool */
121 BITALLOC_INST(TF_METER_PROF_POOL_NAME_TX, TF_NUM_METER_PROF);
123 /** RX Meter Instance Pool */
124 BITALLOC_INST(TF_METER_INST_POOL_NAME_RX, TF_NUM_METER);
126 BITALLOC_INST(TF_METER_INST_POOL_NAME_TX, TF_NUM_METER);
128 /** RX Mirror Configuration Pool*/
129 BITALLOC_INST(TF_MIRROR_POOL_NAME_RX, TF_NUM_MIRROR);
130 /** RX Mirror Configuration Pool */
131 BITALLOC_INST(TF_MIRROR_POOL_NAME_TX, TF_NUM_MIRROR);
134 BITALLOC_INST(TF_UPAR_POOL_NAME_RX, TF_NUM_UPAR);
136 BITALLOC_INST(TF_UPAR_POOL_NAME_TX, TF_NUM_UPAR);
138 /** RX SP TCAM Pool */
139 BITALLOC_INST(TF_SP_TCAM_POOL_NAME_RX, TF_NUM_SP_TCAM);
140 /** TX SP TCAM Pool */
141 BITALLOC_INST(TF_SP_TCAM_POOL_NAME_TX, TF_NUM_SP_TCAM);
144 BITALLOC_INST(TF_FKB_POOL_NAME_RX, TF_NUM_FKB);
146 BITALLOC_INST(TF_FKB_POOL_NAME_TX, TF_NUM_FKB);
148 /** RX Table Scope Pool */
149 BITALLOC_INST(TF_TBL_SCOPE_POOL_NAME_RX, TF_NUM_TBL_SCOPE);
150 /** TX Table Scope Pool */
151 BITALLOC_INST(TF_TBL_SCOPE_POOL_NAME_TX, TF_NUM_TBL_SCOPE);
153 /** RX L2 Func Pool */
154 BITALLOC_INST(TF_L2_FUNC_POOL_NAME_RX, TF_NUM_L2_FUNC);
155 /** TX L2 Func Pool */
156 BITALLOC_INST(TF_L2_FUNC_POOL_NAME_TX, TF_NUM_L2_FUNC);
158 /** RX Epoch0 Pool */
159 BITALLOC_INST(TF_EPOCH0_POOL_NAME_RX, TF_NUM_EPOCH0);
160 /** TX Epoch0 Pool */
161 BITALLOC_INST(TF_EPOCH0_POOL_NAME_TX, TF_NUM_EPOCH0);
163 /** TX Epoch1 Pool */
164 BITALLOC_INST(TF_EPOCH1_POOL_NAME_RX, TF_NUM_EPOCH1);
165 /** TX Epoch1 Pool */
166 BITALLOC_INST(TF_EPOCH1_POOL_NAME_TX, TF_NUM_EPOCH1);
168 /** RX MetaData Profile Pool */
169 BITALLOC_INST(TF_METADATA_POOL_NAME_RX, TF_NUM_METADATA);
170 /** TX MetaData Profile Pool */
171 BITALLOC_INST(TF_METADATA_POOL_NAME_TX, TF_NUM_METADATA);
173 /** RX Connection Tracking State Pool */
174 BITALLOC_INST(TF_CT_STATE_POOL_NAME_RX, TF_NUM_CT_STATE);
175 /** TX Connection Tracking State Pool */
176 BITALLOC_INST(TF_CT_STATE_POOL_NAME_TX, TF_NUM_CT_STATE);
178 /** RX Range Profile Pool */
179 BITALLOC_INST(TF_RANGE_PROF_POOL_NAME_RX, TF_NUM_RANGE_PROF);
180 /** TX Range Profile Pool */
181 BITALLOC_INST(TF_RANGE_PROF_POOL_NAME_TX, TF_NUM_RANGE_PROF);
184 BITALLOC_INST(TF_RANGE_ENTRY_POOL_NAME_RX, TF_NUM_RANGE_ENTRY);
186 BITALLOC_INST(TF_RANGE_ENTRY_POOL_NAME_TX, TF_NUM_RANGE_ENTRY);
189 BITALLOC_INST(TF_LAG_ENTRY_POOL_NAME_RX, TF_NUM_LAG_ENTRY);
191 BITALLOC_INST(TF_LAG_ENTRY_POOL_NAME_TX, TF_NUM_LAG_ENTRY);
193 /* Session SRAM pools */
195 /** RX Full Action Record Pool */
196 BITALLOC_INST(TF_SRAM_FULL_ACTION_POOL_NAME_RX,
197 TF_RSVD_SRAM_FULL_ACTION_RX);
198 /** TX Full Action Record Pool */
199 BITALLOC_INST(TF_SRAM_FULL_ACTION_POOL_NAME_TX,
200 TF_RSVD_SRAM_FULL_ACTION_TX);
202 /** RX Multicast Group Pool, only RX is supported */
203 BITALLOC_INST(TF_SRAM_MCG_POOL_NAME_RX,
204 TF_RSVD_SRAM_MCG_RX);
206 /** RX Encap 8B Pool*/
207 BITALLOC_INST(TF_SRAM_ENCAP_8B_POOL_NAME_RX,
208 TF_RSVD_SRAM_ENCAP_8B_RX);
209 /** TX Encap 8B Pool*/
210 BITALLOC_INST(TF_SRAM_ENCAP_8B_POOL_NAME_TX,
211 TF_RSVD_SRAM_ENCAP_8B_TX);
213 /** RX Encap 16B Pool */
214 BITALLOC_INST(TF_SRAM_ENCAP_16B_POOL_NAME_RX,
215 TF_RSVD_SRAM_ENCAP_16B_RX);
216 /** TX Encap 16B Pool */
217 BITALLOC_INST(TF_SRAM_ENCAP_16B_POOL_NAME_TX,
218 TF_RSVD_SRAM_ENCAP_16B_TX);
220 /** TX Encap 64B Pool, only TX is supported */
221 BITALLOC_INST(TF_SRAM_ENCAP_64B_POOL_NAME_TX,
222 TF_RSVD_SRAM_ENCAP_64B_TX);
224 /** RX Source Properties SMAC Pool */
225 BITALLOC_INST(TF_SRAM_SP_SMAC_POOL_NAME_RX,
226 TF_RSVD_SRAM_SP_SMAC_RX);
227 /** TX Source Properties SMAC Pool */
228 BITALLOC_INST(TF_SRAM_SP_SMAC_POOL_NAME_TX,
229 TF_RSVD_SRAM_SP_SMAC_TX);
231 /** TX Source Properties SMAC IPv4 Pool, only TX is supported */
232 BITALLOC_INST(TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX,
233 TF_RSVD_SRAM_SP_SMAC_IPV4_TX);
235 /** TX Source Properties SMAC IPv6 Pool, only TX is supported */
236 BITALLOC_INST(TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX,
237 TF_RSVD_SRAM_SP_SMAC_IPV6_TX);
239 /** RX Counter 64B Pool */
240 BITALLOC_INST(TF_SRAM_STATS_64B_POOL_NAME_RX,
241 TF_RSVD_SRAM_COUNTER_64B_RX);
242 /** TX Counter 64B Pool */
243 BITALLOC_INST(TF_SRAM_STATS_64B_POOL_NAME_TX,
244 TF_RSVD_SRAM_COUNTER_64B_TX);
246 /** RX NAT Source Port Pool */
247 BITALLOC_INST(TF_SRAM_NAT_SPORT_POOL_NAME_RX,
248 TF_RSVD_SRAM_NAT_SPORT_RX);
249 /** TX NAT Source Port Pool */
250 BITALLOC_INST(TF_SRAM_NAT_SPORT_POOL_NAME_TX,
251 TF_RSVD_SRAM_NAT_SPORT_TX);
253 /** RX NAT Destination Port Pool */
254 BITALLOC_INST(TF_SRAM_NAT_DPORT_POOL_NAME_RX,
255 TF_RSVD_SRAM_NAT_DPORT_RX);
256 /** TX NAT Destination Port Pool */
257 BITALLOC_INST(TF_SRAM_NAT_DPORT_POOL_NAME_TX,
258 TF_RSVD_SRAM_NAT_DPORT_TX);
260 /** RX NAT Source IPv4 Pool */
261 BITALLOC_INST(TF_SRAM_NAT_S_IPV4_POOL_NAME_RX,
262 TF_RSVD_SRAM_NAT_S_IPV4_RX);
263 /** TX NAT Source IPv4 Pool */
264 BITALLOC_INST(TF_SRAM_NAT_S_IPV4_POOL_NAME_TX,
265 TF_RSVD_SRAM_NAT_S_IPV4_TX);
267 /** RX NAT Destination IPv4 Pool */
268 BITALLOC_INST(TF_SRAM_NAT_D_IPV4_POOL_NAME_RX,
269 TF_RSVD_SRAM_NAT_D_IPV4_RX);
270 /** TX NAT IPv4 Destination Pool */
271 BITALLOC_INST(TF_SRAM_NAT_D_IPV4_POOL_NAME_TX,
272 TF_RSVD_SRAM_NAT_D_IPV4_TX);
275 * Pools not allocated from HCAPI RM
278 /** RX L2 Ctx Remap ID Pool */
279 BITALLOC_INST(TF_L2_CTXT_REMAP_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);
280 /** TX L2 Ctx Remap ID Pool */
281 BITALLOC_INST(TF_L2_CTXT_REMAP_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);
283 /** CRC32 seed table */
284 #define TF_LKUP_SEED_MEM_SIZE 512
285 uint32_t lkup_em_seed_mem[TF_DIR_MAX][TF_LKUP_SEED_MEM_SIZE];
287 /** Lookup3 init values */
288 uint32_t lkup_lkup3_init_cfg[TF_DIR_MAX];
290 /** Table scope array */
291 struct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE];
293 /** Each external pool is associated with a single table scope
294 * For each external pool store the associated table scope in
295 * this data structure
297 uint32_t ext_pool_2_scope[TF_DIR_MAX][TF_EXT_POOL_CNT_MAX];
300 #endif /* _TF_SESSION_H_ */